blob: 0fa79e2f05c0e50de60d2793343cef4e64df1b81 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
*/
#include <dt-bindings/clock/rockchip-ddr.h>
#include <dt-bindings/memory/rk1808-dram.h>
/ {
ddr_timing: ddr_timing {
compatible = "rockchip,ddr-timing";
ddr2_speed_bin = <DDR2_DEFAULT>;
ddr3_speed_bin = <DDR3_DEFAULT>;
ddr4_speed_bin = <DDR4_DEFAULT>;
pd_idle = <0>;
sr_idle = <0>;
sr_mc_gate_idle = <0>;
srpd_lite_idle = <0>;
standby_idle = <0>;
auto_pd_dis_freq = <1066>;
auto_sr_dis_freq = <800>;
ddr2_dll_dis_freq = <300>;
ddr3_dll_dis_freq = <300>;
ddr4_dll_dis_freq = <625>;
phy_dll_dis_freq = <400>;
ddr2_odt_dis_freq = <100>;
phy_ddr2_odt_dis_freq = <100>;
ddr2_drv = <DDR2_DS_REDUCE>;
ddr2_odt = <DDR2_ODT_150ohm>;
phy_ddr2_ca_drv = <PHY_DDR3_RON_34ohm>;
phy_ddr2_ck_drv = <PHY_DDR3_RON_43ohm>;
phy_ddr2_dq_drv = <PHY_DDR3_RON_34ohm>;
phy_ddr2_odt = <PHY_DDR3_RTT_213ohm>;
ddr3_odt_dis_freq = <400>;
phy_ddr3_odt_dis_freq = <400>;
ddr3_drv = <DDR3_DS_40ohm>;
ddr3_odt = <DDR3_ODT_120ohm>;
phy_ddr3_ca_drv = <PHY_DDR3_RON_34ohm>;
phy_ddr3_ck_drv = <PHY_DDR3_RON_43ohm>;
phy_ddr3_dq_drv = <PHY_DDR3_RON_34ohm>;
phy_ddr3_odt = <PHY_DDR3_RTT_213ohm>;
phy_lpddr2_odt_dis_freq = <666>;
lpddr2_drv = <LP2_DS_40ohm>;
phy_lpddr2_ca_drv = <PHY_DDR4_LPDDR2_3_RON_34ohm>;
phy_lpddr2_ck_drv = <PHY_DDR4_LPDDR2_3_RON_42ohm>;
phy_lpddr2_dq_drv = <PHY_DDR4_LPDDR2_3_RON_34ohm>;
phy_lpddr2_odt = <PHY_DDR4_LPDDR2_3_RTT_DISABLE>;
lpddr3_odt_dis_freq = <400>;
phy_lpddr3_odt_dis_freq = <400>;
lpddr3_drv = <LP3_DS_40ohm>;
lpddr3_odt = <LP3_ODT_240ohm>;
phy_lpddr3_ca_drv = <PHY_DDR4_LPDDR2_3_RON_34ohm>;
phy_lpddr3_ck_drv = <PHY_DDR4_LPDDR2_3_RON_42ohm>;
phy_lpddr3_dq_drv = <PHY_DDR4_LPDDR2_3_RON_34ohm>;
phy_lpddr3_odt = <PHY_DDR4_LPDDR2_3_RTT_229ohm>;
lpddr4_odt_dis_freq = <800>;
phy_lpddr4_odt_dis_freq = <800>;
lpddr4_drv = <LP4_PDDS_60ohm>;
lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
phy_lpddr4_ca_drv = <PHY_DDR4_LPDDR2_3_RON_42ohm>;
phy_lpddr4_ck_cs_drv = <PHY_DDR4_LPDDR2_3_RON_75ohm>;
phy_lpddr4_dq_drv = <PHY_DDR4_LPDDR2_3_RON_75ohm>;
phy_lpddr4_odt = <PHY_DDR4_LPDDR2_3_RTT_54ohm>;
ddr4_odt_dis_freq = <666>;
phy_ddr4_odt_dis_freq = <666>;
ddr4_drv = <DDR4_DS_34ohm>;
ddr4_odt = <DDR4_RTT_NOM_240ohm>;
phy_ddr4_ca_drv = <PHY_DDR4_LPDDR2_3_RON_34ohm>;
phy_ddr4_ck_drv = <PHY_DDR4_LPDDR2_3_RON_42ohm>;
phy_ddr4_dq_drv = <PHY_DDR4_LPDDR2_3_RON_34ohm>;
phy_ddr4_odt = <PHY_DDR4_LPDDR2_3_RTT_229ohm>;
/*
* CA de-skew, one step is 15ps, range 0-31
* DDR3 CA define is different from others(DDR4/LPDDR2/LPDDR3).
*/
a0_ddr3a9_de-skew = <7>;
a1_ddr3a14_de-skew = <7>;
a2_ddr3a13_de-skew = <7>;
a3_ddr3a11_de-skew = <7>;
a4_ddr3a2_de-skew = <7>;
a5_ddr3a4_de-skew = <7>;
a6_ddr3a3_de-skew = <7>;
a7_ddr3a6_de-skew = <7>;
a8_ddr3a5_de-skew = <7>;
a9_ddr3a1_de-skew = <7>;
a10_ddr3a0_de-skew = <7>;
a11_ddr3a7_de-skew = <7>;
a12_ddr3casb_de-skew = <7>;
a13_ddr3a8_de-skew = <7>;
a14_ddr3odt0_de-skew = <7>;
a15_ddr3ba1_de-skew = <7>;
a16_ddr3rasb_de-skew = <7>;
a17_ddr3null_de-skew = <7>;
ba0_ddr3ba2_de-skew = <7>;
ba1_ddr3a12_de-skew = <7>;
bg0_ddr3ba0_de-skew = <7>;
bg1_ddr3web_de-skew = <7>;
cke_ddr3cke_de-skew = <7>;
ck_ddr3ck_de-skew = <7>;
ckb_ddr3ckb_de-skew = <7>;
csb0_ddr3a10_de-skew = <7>;
odt0_ddr3a15_de-skew = <7>;
resetn_ddr3resetn_de-skew = <7>;
actn_ddr3csb0_de-skew = <7>;
csb1_ddr3csb1_de-skew = <7>;
odt1_ddr3odt1_de-skew = <7>;
/* DATA de-skew, one step is 15ps, range 0-31 */
/* cs0_skew_a */
cs0_dm0_rx_de-skew = <7>;
cs0_dm0_tx_de-skew = <7>;
cs0_dq0_rx_de-skew = <7>;
cs0_dq0_tx_de-skew = <7>;
cs0_dq1_rx_de-skew = <7>;
cs0_dq1_tx_de-skew = <7>;
cs0_dq2_rx_de-skew = <7>;
cs0_dq2_tx_de-skew = <7>;
cs0_dq3_rx_de-skew = <7>;
cs0_dq3_tx_de-skew = <7>;
cs0_dq4_rx_de-skew = <7>;
cs0_dq4_tx_de-skew = <7>;
cs0_dq5_rx_de-skew = <7>;
cs0_dq5_tx_de-skew = <7>;
cs0_dq6_rx_de-skew = <7>;
cs0_dq6_tx_de-skew = <7>;
cs0_dq7_rx_de-skew = <7>;
cs0_dq7_tx_de-skew = <7>;
cs0_dqs0p_rx_de-skew = <14>;
cs0_dqs0p_tx_de-skew = <9>;
cs0_dqs0n_tx_de-skew = <9>;
cs0_dm1_rx_de-skew = <7>;
cs0_dm1_tx_de-skew = <7>;
cs0_dq8_rx_de-skew = <7>;
cs0_dq8_tx_de-skew = <7>;
cs0_dq9_rx_de-skew = <7>;
cs0_dq9_tx_de-skew = <7>;
cs0_dq10_rx_de-skew = <7>;
cs0_dq10_tx_de-skew = <7>;
cs0_dq11_rx_de-skew = <7>;
cs0_dq11_tx_de-skew = <7>;
cs0_dq12_rx_de-skew = <7>;
cs0_dq12_tx_de-skew = <7>;
cs0_dq13_rx_de-skew = <7>;
cs0_dq13_tx_de-skew = <7>;
cs0_dq14_rx_de-skew = <7>;
cs0_dq14_tx_de-skew = <7>;
cs0_dq15_rx_de-skew = <7>;
cs0_dq15_tx_de-skew = <7>;
cs0_dqs1p_rx_de-skew = <14>;
cs0_dqs1p_tx_de-skew = <9>;
cs0_dqs1n_tx_de-skew = <9>;
cs0_dqs0n_rx_de-skew = <14>;
cs0_dqs1n_rx_de-skew = <14>;
/* cs0_skew_b */
cs0_dm2_rx_de-skew = <7>;
cs0_dm2_tx_de-skew = <7>;
cs0_dq16_rx_de-skew = <7>;
cs0_dq16_tx_de-skew = <7>;
cs0_dq17_rx_de-skew = <7>;
cs0_dq17_tx_de-skew = <7>;
cs0_dq18_rx_de-skew = <7>;
cs0_dq18_tx_de-skew = <7>;
cs0_dq19_rx_de-skew = <7>;
cs0_dq19_tx_de-skew = <7>;
cs0_dq20_rx_de-skew = <7>;
cs0_dq20_tx_de-skew = <7>;
cs0_dq21_rx_de-skew = <7>;
cs0_dq21_tx_de-skew = <7>;
cs0_dq22_rx_de-skew = <7>;
cs0_dq22_tx_de-skew = <7>;
cs0_dq23_rx_de-skew = <7>;
cs0_dq23_tx_de-skew = <7>;
cs0_dqs2p_rx_de-skew = <14>;
cs0_dqs2p_tx_de-skew = <9>;
cs0_dqs2n_tx_de-skew = <9>;
cs0_dm3_rx_de-skew = <7>;
cs0_dm3_tx_de-skew = <7>;
cs0_dq24_rx_de-skew = <7>;
cs0_dq24_tx_de-skew = <7>;
cs0_dq25_rx_de-skew = <7>;
cs0_dq25_tx_de-skew = <7>;
cs0_dq26_rx_de-skew = <7>;
cs0_dq26_tx_de-skew = <7>;
cs0_dq27_rx_de-skew = <7>;
cs0_dq27_tx_de-skew = <7>;
cs0_dq28_rx_de-skew = <7>;
cs0_dq28_tx_de-skew = <7>;
cs0_dq29_rx_de-skew = <7>;
cs0_dq29_tx_de-skew = <7>;
cs0_dq30_rx_de-skew = <7>;
cs0_dq30_tx_de-skew = <7>;
cs0_dq31_rx_de-skew = <7>;
cs0_dq31_tx_de-skew = <7>;
cs0_dqs3p_rx_de-skew = <14>;
cs0_dqs3p_tx_de-skew = <9>;
cs0_dqs3n_tx_de-skew = <9>;
cs0_dqs2n_rx_de-skew = <14>;
cs0_dqs3n_rx_de-skew = <14>;
/* cs1_skew_a */
cs1_dm0_rx_de-skew = <7>;
cs1_dm0_tx_de-skew = <7>;
cs1_dq0_rx_de-skew = <7>;
cs1_dq0_tx_de-skew = <7>;
cs1_dq1_rx_de-skew = <7>;
cs1_dq1_tx_de-skew = <7>;
cs1_dq2_rx_de-skew = <7>;
cs1_dq2_tx_de-skew = <7>;
cs1_dq3_rx_de-skew = <7>;
cs1_dq3_tx_de-skew = <7>;
cs1_dq4_rx_de-skew = <7>;
cs1_dq4_tx_de-skew = <7>;
cs1_dq5_rx_de-skew = <7>;
cs1_dq5_tx_de-skew = <7>;
cs1_dq6_rx_de-skew = <7>;
cs1_dq6_tx_de-skew = <7>;
cs1_dq7_rx_de-skew = <7>;
cs1_dq7_tx_de-skew = <7>;
cs1_dqs0p_rx_de-skew = <14>;
cs1_dqs0p_tx_de-skew = <9>;
cs1_dqs0n_tx_de-skew = <9>;
cs1_dm1_rx_de-skew = <7>;
cs1_dm1_tx_de-skew = <7>;
cs1_dq8_rx_de-skew = <7>;
cs1_dq8_tx_de-skew = <7>;
cs1_dq9_rx_de-skew = <7>;
cs1_dq9_tx_de-skew = <7>;
cs1_dq10_rx_de-skew = <7>;
cs1_dq10_tx_de-skew = <7>;
cs1_dq11_rx_de-skew = <7>;
cs1_dq11_tx_de-skew = <7>;
cs1_dq12_rx_de-skew = <7>;
cs1_dq12_tx_de-skew = <7>;
cs1_dq13_rx_de-skew = <7>;
cs1_dq13_tx_de-skew = <7>;
cs1_dq14_rx_de-skew = <7>;
cs1_dq14_tx_de-skew = <7>;
cs1_dq15_rx_de-skew = <7>;
cs1_dq15_tx_de-skew = <7>;
cs1_dqs1p_rx_de-skew = <14>;
cs1_dqs1p_tx_de-skew = <9>;
cs1_dqs1n_tx_de-skew = <9>;
cs1_dqs0n_rx_de-skew = <14>;
cs1_dqs1n_rx_de-skew = <14>;
/* cs1_skew_b */
cs1_dm2_rx_de-skew = <7>;
cs1_dm2_tx_de-skew = <7>;
cs1_dq16_rx_de-skew = <7>;
cs1_dq16_tx_de-skew = <7>;
cs1_dq17_rx_de-skew = <7>;
cs1_dq17_tx_de-skew = <7>;
cs1_dq18_rx_de-skew = <7>;
cs1_dq18_tx_de-skew = <7>;
cs1_dq19_rx_de-skew = <7>;
cs1_dq19_tx_de-skew = <7>;
cs1_dq20_rx_de-skew = <7>;
cs1_dq20_tx_de-skew = <7>;
cs1_dq21_rx_de-skew = <7>;
cs1_dq21_tx_de-skew = <7>;
cs1_dq22_rx_de-skew = <7>;
cs1_dq22_tx_de-skew = <7>;
cs1_dq23_rx_de-skew = <7>;
cs1_dq23_tx_de-skew = <7>;
cs1_dqs2p_rx_de-skew = <14>;
cs1_dqs2p_tx_de-skew = <9>;
cs1_dqs2n_tx_de-skew = <9>;
cs1_dm3_rx_de-skew = <7>;
cs1_dm3_tx_de-skew = <7>;
cs1_dq24_rx_de-skew = <7>;
cs1_dq24_tx_de-skew = <7>;
cs1_dq25_rx_de-skew = <7>;
cs1_dq25_tx_de-skew = <7>;
cs1_dq26_rx_de-skew = <7>;
cs1_dq26_tx_de-skew = <7>;
cs1_dq27_rx_de-skew = <7>;
cs1_dq27_tx_de-skew = <7>;
cs1_dq28_rx_de-skew = <7>;
cs1_dq28_tx_de-skew = <7>;
cs1_dq29_rx_de-skew = <7>;
cs1_dq29_tx_de-skew = <7>;
cs1_dq30_rx_de-skew = <7>;
cs1_dq30_tx_de-skew = <7>;
cs1_dq31_rx_de-skew = <7>;
cs1_dq31_tx_de-skew = <7>;
cs1_dqs3p_rx_de-skew = <14>;
cs1_dqs3p_tx_de-skew = <9>;
cs1_dqs3n_tx_de-skew = <9>;
cs1_dqs2n_rx_de-skew = <14>;
cs1_dqs3n_rx_de-skew = <14>;
};
};
|
