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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
*/
/dts-v1/;
#include <dt-bindings/clock/rk618-cru.h>
#include "px30-ad-r35-mb.dtsi"
/ {
panel {
compatible = "chunghwa,claa101wh31-cw", "simple-panel";
backlight = <&backlight>;
power-supply = <&vcc3v3_lcd>;
enable-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>;
prepare-delay-ms = <120>;
enable-delay-ms = <120>;
disable-delay-ms = <120>;
unprepare-delay-ms = <120>;
bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
width-mm = <231>;
height-mm = <154>;
display-timings {
native-mode = <&timing1>;
timing1: timing1 {
clock-frequency = <72000000>;
hactive = <1280>;
vactive = <800>;
hback-porch = <60>;
hfront-porch = <60>;
vback-porch = <16>;
vfront-porch = <16>;
hsync-len = <40>;
vsync-len = <6>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
port {
panel_in_lvds: endpoint {
remote-endpoint = <&lvds_out_panel>;
};
};
};
};
&dmc {
auto-freq-en = <0>;
};
&i2c0 {
status = "okay";
rk618@50 {
compatible = "rockchip,rk618";
reg = <0x50>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1_2ch_mclk>;
clocks = <&cru SCLK_I2S1_OUT>;
clock-names = "clkin";
assigned-clocks = <&cru SCLK_I2S1_OUT>;
assigned-clock-rates = <12000000>;
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
status = "okay";
clock: cru {
compatible = "rockchip,rk618-cru";
clocks = <&cru SCLK_I2S1_OUT>, <&cru DCLK_VOPL>;
clock-names = "clkin", "lcdc0_dclkp";
assigned-clocks = <&clock SCALER_PLLIN_CLK>,
<&clock VIF_PLLIN_CLK>,
<&clock SCALER_CLK>,
<&clock VIF0_PRE_CLK>,
<&clock CODEC_CLK>,
<&clock DITHER_CLK>;
assigned-clock-parents = <&cru SCLK_I2S1_OUT>,
<&clock LCDC0_CLK>,
<&clock SCALER_PLL_CLK>,
<&clock VIF_PLL_CLK>,
<&cru SCLK_I2S1_OUT>,
<&clock VIF0_CLK>;
#clock-cells = <1>;
status = "okay";
};
lvds {
compatible = "rockchip,rk618-lvds";
clocks = <&clock LVDS_CLK>;
clock-names = "lvds";
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds_in_rgb: endpoint {
remote-endpoint = <&rgb_out_lvds>;
};
};
port@1 {
reg = <1>;
lvds_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds>;
};
};
};
};
};
};
&rgb {
status = "okay";
ports {
port@1 {
reg = <1>;
rgb_out_lvds: endpoint {
remote-endpoint = <&lvds_in_rgb>;
};
};
};
};
&rgb_in_vopb {
status = "disabled";
};
&rgb_in_vopl {
status = "okay";
};
&route_rgb {
connect = <&vopl_out_rgb>;
status = "okay";
};
|
