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Rockchip specific extensions to the Synopsys Designware MIPI DSI
================================
Required properties:
- compatible: must be one of:
"rockchip,rk3128-mipi-dsi", "snps,dw-mipi-dsi".
"rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
"rockchip,rk3366-mipi-dsi", "snps,dw-mipi-dsi".
"rockchip,rk3368-mipi-dsi", "snps,dw-mipi-dsi".
"rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
- reg: Represent the physical address range of the controller.
- interrupts: Represent the controller's interrupt to the CPU(s).
- clocks, clock-names: Phandles to the controller's APB clock(pclk) as
described in [1].
- resets : phandle to the reset of MIPI DSI APB Clock.
- reset-names : should be "apb".
- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
- #address-cells: Should be <1>.
- #size-cells: Should be <0>.
- ports: contain a port node with endpoint definitions as defined in [2].
For vopb,set the reg = <0> and set the reg = <1> for vopl.
Optional properties
- clocks, clock-names:
phandle to the SNPS-PHY config clock, name should be "phy_cfg".
phandle to the SNPS-PHY PLL reference clock, name should be "ref".
phandle to the Non-SNPS PHY high speed clock, name should be "hs_clk".
phandle to the h2p bridge clock, name should be "h2p".
- phys: phandle to Non-SNPS PHY node
- phy-names: the string "mipi_dphy" when is found in a node, along with "phys"
attribute, provides phandle to MIPI PHY node
- rockchip,dual-channel: for dual-channel panel, if not, don't configure
- rockchip,lane-rate: manually configure lane-rate, not necessary.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/media/video-interfaces.txt
[3] Documentation/devicetree/bindings/reset/reset.txt
Example:
For Rockchip RK3288:
dsi0: dsi@ff960000 {
compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0x0 0xff960000 0x0 0x4000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
clock-names = "ref", "pclk";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
rockchip,dual-channel = <&dsi1>;
rockchip,lane-rate = <900>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
dsi0_in: port {
#address-cells = <1>;
#size-cells = <0>;
dsi0_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_dsi0>;
};
dsi0_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_dsi0>;
};
};
};
panel {
compatible ="boe,tv080wum-nl0";
reg = <0>;
enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_en>;
backlight = <&backlight>;
status = "okay";
};
};
dsi1: dsi@ff964000 {
compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0x0 0xff964000 0x0 0x4000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI1>;
clock-names = "ref", "pclk";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
dsi1_in: port {
#address-cells = <1>;
#size-cells = <0>;
dsi1_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_dsi1>;
};
dsi1_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_dsi1>;
};
};
};
};
For Rockchip RK3368:
dsi: dsi@ff960000 {
compatible = "rockchip,rk3368-mipi-dsi";
clocks = <&cru PCLK_MIPI_DSI0>, <&mipi_dphy>;
clock-names = "pclk", "hs_clk";
phys = <&mipi_dphy>;
phy-names = "mipi_dphy";
resets = <&cru SRST_MIPIDSI0>;
reset-names = "apb";
...
ports {
port {
dsi_in_vop: endpoint {
remote-endpoint = <&vop_out_dsi>;
};
};
};
};
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