// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.

#include <dt-bindings/clock/rk1808-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/power/rk1808-power.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	compatible = "rockchip,rk3399pro-npu";

	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		serial2 = &uart2;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a35", "arm,armv8";
			reg = <0x0 0x0>;
			enable-method = "psci";
			clocks = <&cru ARMCLK>;
			operating-points-v2 = <&cpu0_opp_table>;
			dynamic-power-coefficient = <74>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a35", "arm,armv8";
			reg = <0x0 0x1>;
			enable-method = "psci";
			clocks = <&cru ARMCLK>;
			operating-points-v2 = <&cpu0_opp_table>;
			dynamic-power-coefficient = <74>;
		};
	};

	cpu0_opp_table: cpu0-opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		nvmem-cells = <&cpu_leakage>;
		nvmem-cell-names = "leakage";

		opp-408000000 {
			opp-hz = /bits/ 64 <408000000>;
			opp-microvolt = <750000 750000 950000>;
			clock-latency-ns = <40000>;
			opp-suspend;
		};
		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <750000 750000 950000>;
			clock-latency-ns = <40000>;
		};
		opp-816000000 {
			opp-hz = /bits/ 64 <816000000>;
			opp-microvolt = <750000 750000 950000>;
			clock-latency-ns = <40000>;
		};
		opp-1008000000 {
			opp-hz = /bits/ 64 <1008000000>;
			opp-microvolt = <750000 750000 950000>;
			clock-latency-ns = <40000>;
		};
		opp-1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt = <750000 750000 950000>;
			clock-latency-ns = <40000>;
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	cpuinfo {
		compatible = "rockchip,cpuinfo";
		nvmem-cells = <&efuse_id>, <&efuse_cpu_version>;
		nvmem-cell-names = "id", "cpu-version";
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
		arm,no-tick-in-suspend;
	};

	xin24m: xin24m {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xin24m";
		#clock-cells = <0>;
	};

	xin32k: xin32k {
		compatible = "fixed-clock";
		clock-frequency = <32768>;
		clock-output-names = "xin32k";
		#clock-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&clkin_32k>;
	};

	usbdrd3: usb {
		compatible = "rockchip,rk1808-dwc3", "rockchip,rk3399-dwc3";
		clocks = <&cru SCLK_USB3_OTG0_REF>, <&cru ACLK_USB3OTG>,
			 <&cru SCLK_USB3_OTG0_SUSPEND>;
		clock-names = "ref_clk", "bus_clk",
			      "suspend_clk";
		assigned-clocks = <&cru SCLK_USB3_OTG0_SUSPEND>;
		assigned-clock-rates = <24000000>;
		power-domains = <&power RK1808_PD_PCIE>;
		resets = <&cru SRST_USB3_OTG_A>;
		reset-names = "usb3-otg";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "disabled";

		usbdrd_dwc3: dwc3@fd000000 {
			compatible = "snps,dwc3";
			reg = <0x0 0xfd000000 0x0 0x200000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			dr_mode = "peripheral";
			phys = <&u2phy_otg>, <&combphy PHY_TYPE_USB3>;
			phy-names = "usb2-phy", "usb3-phy";
			phy_type = "utmi_wide";
			snps,dis_enblslpm_quirk;
			snps,dis-u1u2-quirk;
			snps,dis-u2-freeclk-exists-quirk;
			snps,dis_u2_susphy_quirk;
			snps,dis_u3_susphy_quirk;
			snps,dis-del-phy-power-chg-quirk;
			snps,tx-ipgap-linecheck-dis-quirk;
			snps,xhci-trb-ent-quirk;
			status = "disabled";
		};
	};

	grf: syscon@fe000000 {
		compatible = "rockchip,rk1808-grf", "syscon", "simple-mfd";
		reg = <0x0 0xfe000000 0x0 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		npu_pvtm: npu-pvtm {
			compatible = "rockchip,rk1808-npu-pvtm";
			clocks = <&cru SCLK_PVTM_NPU>;
			clock-names = "npu";
			status = "okay";
		};
	};

	usb2phy_grf: syscon@fe010000 {
		compatible = "rockchip,rk1808-usb2phy-grf", "syscon",
			     "simple-mfd";
		reg = <0x0 0xfe010000 0x0 0x8000>;
		#address-cells = <1>;
		#size-cells = <1>;

		u2phy: usb2-phy@100 {
			compatible = "rockchip,rk1808-usb2phy";
			reg = <0x100 0x10>;
			clocks = <&cru SCLK_USBPHY_REF>;
			clock-names = "phyclk";
			#clock-cells = <0>;
			assigned-clocks = <&cru USB480M>;
			assigned-clock-parents = <&u2phy>;
			clock-output-names = "usb480m_phy";
			status = "disabled";

			u2phy_host: host-port {
				#phy-cells = <0>;
				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "linestate";
				status = "disabled";
			};

			u2phy_otg: otg-port {
				#phy-cells = <0>;
				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "otg-bvalid", "otg-id",
						  "linestate";
				status = "disabled";
			};
		};
	};

	combphy_grf: syscon@fe018000 {
		compatible = "rockchip,usb3phy-grf", "syscon";
		reg = <0x0 0xfe018000 0x0 0x8000>;
	};

	pmugrf: syscon@fe020000 {
		compatible = "rockchip,rk1808-pmugrf", "syscon", "simple-mfd";
		reg = <0x0 0xfe020000 0x0 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		pmu_pvtm: pmu-pvtm {
			compatible = "rockchip,rk1808-pmu-pvtm";
			clocks = <&cru SCLK_PVTM_PMU>;
			clock-names = "pmu";
			status = "okay";
		};
	};

	usb_pcie_grf: syscon@fe040000 {
		compatible = "rockchip,usb-pcie-grf", "syscon";
		reg = <0x0 0xfe040000 0x0 0x1000>;
	};

	coregrf: syscon@fe050000 {
		compatible = "rockchip,rk1808-coregrf", "syscon", "simple-mfd";
		reg = <0x0 0xfe050000 0x0 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		pvtm: pvtm {
			compatible = "rockchip,rk1808-pvtm";
			clocks = <&cru SCLK_PVTM_CORE>;
			clock-names = "core";
			status = "okay";
		};
	};

	qos_npu: qos@fe850000 {
		compatible = "syscon";
		reg = <0x0 0xfe850000 0x0 0x20>;
	};

	qos_pcie: qos@fe880000 {
		compatible = "syscon";
		reg = <0x0 0xfe880000 0x0 0x20>;
		status = "disabled";
	};

	qos_usb2: qos@fe890000 {
		compatible = "syscon";
		reg = <0x0 0xfe890000 0x0 0x20>;
		status = "disabled";
	};

	qos_usb3: qos@fe890080 {
		compatible = "syscon";
		reg = <0x0 0xfe890080 0x0 0x20>;
		status = "disabled";
	};

	qos_isp: qos@fe8a0000 {
		compatible = "syscon";
		reg = <0x0 0xfe8a0000 0x0 0x20>;
	};

	qos_rga_rd: qos@fe8a0080 {
		compatible = "syscon";
		reg = <0x0 0xfe8a0080 0x0 0x20>;
	};

	qos_rga_wr: qos@fe8a0100 {
		compatible = "syscon";
		reg = <0x0 0xfe8a0100 0x0 0x20>;
	};

	qos_cif: qos@fe8a0180 {
		compatible = "syscon";
		reg = <0x0 0xfe8a0180 0x0 0x20>;
	};

	qos_vop_raw: qos@fe8b0000 {
		compatible = "syscon";
		reg = <0x0 0xfe8b0000 0x0 0x20>;
	};

	qos_vop_lite: qos@fe8b0080 {
		compatible = "syscon";
		reg = <0x0 0xfe8b0080 0x0 0x20>;
	};

	qos_vpu: qos@fe8c0000 {
		compatible = "syscon";
		reg = <0x0 0xfe8c0000 0x0 0x20>;
	};

	gic: interrupt-controller@ff100000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		interrupt-controller;

		reg = <0x0 0xff100000 0 0x10000>, /* GICD */
		      <0x0 0xff140000 0 0xc0000>, /* GICR */
		      <0x0 0xff300000 0 0x10000>, /* GICC */
		      <0x0 0xff310000 0 0x10000>, /* GICH */
		      <0x0 0xff320000 0 0x10000>; /* GICV */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		its: interrupt-controller@ff120000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			reg = <0x0 0xff120000 0x0 0x20000>;
		};
	};

	efuse: efuse@ff260000 {
		compatible = "rockchip,rk1808-efuse";
		reg = <0x0 0xff3b0000 0x0 0x50>;
		#address-cells = <1>;
		#size-cells = <1>;
		clocks = <&cru SCLK_EFUSE_NS>, <&cru PCLK_EFUSE>;
		clock-names = "sclk_efuse", "pclk_efuse";
		assigned-clocks = <&cru SCLK_EFUSE_NS>;
		assigned-clock-rates = <24000000>;
		rockchip,efuse-size = <0x20>;

		/* Data cells */
		efuse_id: id@7 {
			reg = <0x07 0x10>;
		};
		cpu_leakage: cpu-leakage@17 {
			reg = <0x17 0x1>;
		};
		logic_leakage: logic-leakage@18 {
			reg = <0x18 0x1>;
		};
		npu_leakage: npu-leakage@19 {
			reg = <0x19 0x1>;
		};
		efuse_cpu_version: cpu-version@1c {
			reg = <0x1c 0x1>;
			bits = <3 3>;
		};
	};

	cru: clock-controller@ff350000 {
		compatible = "rockchip,rk1808-cru";
		reg = <0x0 0xff350000 0x0 0x5000>;
		rockchip,grf = <&grf>;
		#clock-cells = <1>;
		#reset-cells = <1>;

		assigned-clocks =
			<&cru PLL_GPLL>, <&cru PLL_CPLL>,
			<&cru PLL_PPLL>, <&cru ARMCLK>,
			<&cru MSCLK_PERI>, <&cru LSCLK_PERI>,
			<&cru HSCLK_BUS_PRE>, <&cru MSCLK_BUS_PRE>,
			<&cru LSCLK_BUS_PRE>;
		assigned-clock-rates =
			<1188000000>, <1000000000>,
			<100000000>, <1200000000>,
			<200000000>, <100000000>,
			<300000000>, <200000000>,
			<100000000>;
	};

	combphy: phy@ff380000 {
		compatible = "rockchip,rk1808-combphy";
		reg = <0x0 0xff380000 0x0 0x10000>;
		#phy-cells = <1>;
		clocks = <&cru SCLK_PCIEPHY_REF>;
		clock-names = "refclk";
		assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
		assigned-clock-rates = <25000000>;
		resets = <&cru SRST_USB3_OTG_A>, <&cru SRST_PCIEPHY_POR>,
			 <&cru SRST_PCIEPHY_P>, <&cru SRST_PCIEPHY_PIPE>;
		reset-names = "otg-rst", "combphy-por",
			      "combphy-apb", "combphy-pipe";
		rockchip,combphygrf = <&combphy_grf>;
		rockchip,usbpciegrf = <&usb_pcie_grf>;
		status = "disabled";
	};

	thermal_zones: thermal-zones {
		soc_thermal: soc-thermal {
			polling-delay-passive = <20>; /* milliseconds */
			polling-delay = <1000>; /* milliseconds */
			sustainable-power = <527>; /* milliwatts */

			thermal-sensors = <&tsadc 0>;

			trips {
				threshold: trip-point-0 {
					/* millicelsius */
					temperature = <75000>;
					/* millicelsius */
					hysteresis = <2000>;
					type = "passive";
				};
				target: trip-point-1 {
					/* millicelsius */
					temperature = <85000>;
					/* millicelsius */
					hysteresis = <2000>;
					type = "passive";
				};
				soc_crit: soc-crit {
					/* millicelsius */
					temperature = <115000>;
					/* millicelsius */
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&target>;
					cooling-device =
						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
					contribution = <4096>;
				};
				map1 {
					trip = <&target>;
					cooling-device =
						<&npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
					contribution = <1024>;
				};
			};
		};
	};

	tsadc: tsadc@ff3a0000 {
		compatible = "rockchip,rk1808-tsadc";
		reg = <0x0 0xff3a0000 0x0 0x100>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		rockchip,grf = <&grf>;
		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
		clock-names = "tsadc", "apb_pclk";
		assigned-clocks = <&cru SCLK_TSADC>;
		assigned-clock-rates = <650000>;
		resets = <&cru SRST_TSADC>;
		reset-names = "tsadc-apb";
		#thermal-sensor-cells = <1>;
		rockchip,hw-tshut-temp = <120000>;
		status = "disabled";
	};

	pmu: power-management@ff3e0000 {
		compatible = "rockchip,rk1808-pmu", "syscon", "simple-mfd";
		reg = <0x0 0xff3e0000 0x0 0x1000>;

		power: power-controller {
			compatible = "rockchip,rk1808-power-controller";
			#power-domain-cells = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "okay";

			/* These power domains are grouped by VD_NPU */
			pd_npu@RK1808_VD_NPU {
				reg = <RK1808_VD_NPU>;
				clocks = <&cru SCLK_NPU>,
					 <&cru ACLK_NPU>,
					 <&cru HCLK_NPU>;
				pm_qos = <&qos_npu>;
			};

			/* These power domains are grouped by VD_LOGIC */
			pd_pcie@RK1808_PD_PCIE {
				reg = <RK1808_PD_PCIE>;
				clocks = <&cru HSCLK_PCIE>,
					 <&cru LSCLK_PCIE>,
					 <&cru ACLK_PCIE>,
					 <&cru ACLK_PCIE_MST>,
					 <&cru ACLK_PCIE_SLV>,
					 <&cru PCLK_PCIE>,
					 <&cru SCLK_PCIE_AUX>,
					 <&cru SCLK_PCIE_AUX>,
					 <&cru ACLK_USB3OTG>,
					 <&cru HCLK_HOST>,
					 <&cru HCLK_HOST_ARB>,
					 <&cru SCLK_USB3_OTG0_REF>,
					 <&cru SCLK_USB3_OTG0_SUSPEND>;
				pm_qos = <&qos_pcie>,
					 <&qos_usb2>,
					 <&qos_usb3>;
			};
			pd_vpu@RK1808_PD_VPU {
				reg = <RK1808_PD_VPU>;
				clocks = <&cru ACLK_VPU>,
					 <&cru HCLK_VPU>;
				pm_qos = <&qos_vpu>;
			};
			pd_vio@RK1808_PD_VIO {
				reg = <RK1808_PD_VIO>;
				clocks = <&cru HSCLK_VIO>,
					 <&cru LSCLK_VIO>,
					 <&cru ACLK_VOPRAW>,
					 <&cru HCLK_VOPRAW>,
					 <&cru ACLK_VOPLITE>,
					 <&cru HCLK_VOPLITE>,
					 <&cru PCLK_DSI_TX>,
					 <&cru PCLK_CSI_TX>,
					 <&cru ACLK_RGA>,
					 <&cru HCLK_RGA>,
					 <&cru ACLK_ISP>,
					 <&cru HCLK_ISP>,
					 <&cru ACLK_CIF>,
					 <&cru HCLK_CIF>,
					 <&cru PCLK_CSI2HOST>,
					 <&cru DCLK_VOPRAW>,
					 <&cru DCLK_VOPLITE>;
				pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
					 <&qos_isp>, <&qos_cif>,
					 <&qos_vop_raw>, <&qos_vop_lite>;
			};
		};
	};

	i2c0: i2c@ff410000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xff410000 0x0 0x1000>;
		clocks =  <&cru SCLK_PMU_I2C0>, <&cru PCLK_I2C0_PMU>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c0_xfer>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	dmac: dmac@ff4e0000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0x0 0xff4e0000 0x0 0x4000>;
		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_DMAC>;
		clock-names = "apb_pclk";
		#dma-cells = <1>;
		peripherals-req-type-burst;
	};

	i2c1: i2c@ff500000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xff500000 0x0 0x1000>;
		clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c1_xfer>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	uart2: serial@ff550000 {
		compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart";
		reg = <0x0 0xff550000 0x0 0x100>;
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac 4>, <&dmac 5>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart2m0_xfer>;
		status = "disabled";
	};

	rktimer: rktimer@ff700000 {
		compatible = "rockchip,rk3288-timer";
		reg = <0x0 0xff700000 0x0 0x1000>;
		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
		clock-names = "pclk", "timer";
	};

	npu: npu@ffbc0000 {
		compatible = "rockchip,npu";
		reg = <0x0 0xffbc0000 0x0 0x1000>;
		clocks =  <&cru SCLK_NPU>, <&cru ACLK_NPU>, <&cru HCLK_NPU>;
		clock-names = "sclk_npu", "aclk_npu", "hclk_npu";
		assigned-clocks = <&cru SCLK_NPU>;
		assigned-clock-rates = <800000000>;
		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&power RK1808_VD_NPU>;
		operating-points-v2 = <&npu_opp_table>;
		#cooling-cells = <2>;
		status = "disabled";

		npu_power_model: power-model {
			compatible = "simple-power-model";
			static-coefficient = <342478>;
			dynamic-coefficient = <3080>;
			ts = <32000 4700 (-80) 2>;
			thermal-zone = "soc-thermal";
		};
	};

	npu_opp_table: npu-opp-table {
		compatible = "operating-points-v2";

		rockchip,max-volt = <950000>;
		rockchip,evb-irdrop = <37500>;

		rockchip,pvtm-voltage-sel = <
			0        69000   0
			69001    74000   1
			74001    99999   2
		>;
		rockchip,pvtm-freq = <200000>;
		rockchip,pvtm-volt = <800000>;
		rockchip,pvtm-ch = <0 0>;
		rockchip,pvtm-sample-time = <1000>;
		rockchip,pvtm-number = <10>;
		rockchip,pvtm-error = <1000>;
		rockchip,pvtm-ref-temp = <25>;
		rockchip,pvtm-temp-prop = <(-20) (-26)>;
		rockchip,thermal-zone = "soc-thermal";

		nvmem-cells = <&npu_leakage>;
		nvmem-cell-names = "leakage";

		opp-200000000 {
			opp-hz = /bits/ 64 <200000000>;
			opp-microvolt = <750000 750000 950000>;
		};
		opp-297000000 {
			opp-hz = /bits/ 64 <297000000>;
			opp-microvolt = <750000 750000 950000>;
		};
		opp-400000000 {
			opp-hz = /bits/ 64 <400000000>;
			opp-microvolt = <750000 750000 950000>;
		};
		opp-594000000 {
			opp-hz = /bits/ 64 <594000000>;
			opp-microvolt = <750000 750000 950000>;
		};
		opp-792000000 {
			opp-hz = /bits/ 64 <792000000>;
			opp-microvolt = <825000 825000 950000>;
			opp-microvolt-L0 = <825000 825000 950000>;
			opp-microvolt-L1 = <800000 800000 950000>;
			opp-microvolt-L2 = <775000 775000 950000>;
		};
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rk1808-pinctrl";
		rockchip,grf = <&grf>;
		rockchip,pmu = <&pmugrf>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gpio0: gpio0@ff4c0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff4c0000 0x0 0x100>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO0_PMU>, <&cru DBCLK_PMU_GPIO0>;
			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio1@ff690000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff690000 0x0 0x100>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio2@ff6a0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff6a0000 0x0 0x100>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio3@ff6b0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff6b0000 0x0 0x100>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio4@ff6c0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff6c0000 0x0 0x100>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		pcfg_pull_down: pcfg-pull-down {
			bias-pull-down;
		};

		pcfg_pull_none: pcfg-pull-none {
			bias-disable;
		};

		pcfg_pull_up_2ma: pcfg-pull-up-2ma {
			bias-pull-up;
			drive-strength = <2>;
		};

		pcfg_pull_none_smt: pcfg-pull-none-smt {
			bias-disable;
			input-schmitt-enable;
		};

		pcfg_pull_none_2ma_smt: pcfg-pull-none-2ma-smt {
			bias-disable;
			drive-strength = <2>;
			input-schmitt-enable;
		};

		pcfg_output_high: pcfg-output-high {
			output-high;
		};

		pcfg_input_smt: pcfg-input-smt {
			input-enable;
			input-schmitt-enable;
		};

		i2c0 {
			i2c0_xfer: i2c0-xfer {
				rockchip,pins =
					/* i2c0_sda */
					<0 RK_PB1 1 &pcfg_pull_none_2ma_smt>,
					/* i2c0_scl */
					<0 RK_PB0 1 &pcfg_pull_none_2ma_smt>;
			};
		};

		i2c1 {
			i2c1_xfer: i2c1-xfer {
				rockchip,pins =
					/* i2c1_sda */
					<0 RK_PC1 1 &pcfg_pull_none_2ma_smt>,
					/* i2c1_scl */
					<0 RK_PC0 1 &pcfg_pull_none_2ma_smt>;
			};
		};

		pciusb {
			pciusb_pins: pciusb-pins {
				rockchip,pins =
					/* pciusb_debug0 */
					<4 RK_PB4 3 &pcfg_pull_none>,
					/* pciusb_debug1 */
					<4 RK_PB5 3 &pcfg_pull_none>,
					/* pciusb_debug2 */
					<4 RK_PB6 3 &pcfg_pull_none>,
					/* pciusb_debug3 */
					<4 RK_PB7 3 &pcfg_pull_none>,
					/* pciusb_debug4 */
					<4 RK_PC0 3 &pcfg_pull_none>,
					/* pciusb_debug5 */
					<4 RK_PC1 3 &pcfg_pull_none>,
					/* pciusb_debug6 */
					<4 RK_PC2 3 &pcfg_pull_none>,
					/* pciusb_debug7 */
					<4 RK_PC3 3 &pcfg_pull_none>;
			};
		};

		uart2 {
			uart2m0_xfer: uart2m0-xfer {
				rockchip,pins =
					/* uart2_rxm0 */
					<4 RK_PA3 2 &pcfg_pull_up_2ma>,
					/* uart2_txm0 */
					<4 RK_PA2 2 &pcfg_pull_up_2ma>;
			};

			uart2m1_xfer: uart2m1-xfer {
				rockchip,pins =
					/* uart2_rxm1 */
					<2 RK_PD1 2 &pcfg_pull_up_2ma>,
					/* uart2_txm1 */
					<2 RK_PD0 2 &pcfg_pull_up_2ma>;
			};

			uart2m2_xfer: uart2m2-xfer {
				rockchip,pins =
					/* uart2_rxm2 */
					<3 RK_PA4 2 &pcfg_pull_up_2ma>,
					/* uart2_txm2 */
					<3 RK_PA3 2 &pcfg_pull_up_2ma>;
			};
		};

		tsadc {
			tsadc_otp_gpio: tsadc-otp-gpio {
				rockchip,pins =
					<0 RK_PA6 0 &pcfg_pull_none>;
			};

			tsadc_otp_out: tsadc-otp-out {
				rockchip,pins =
					<0 RK_PA6 2 &pcfg_pull_none>;
			};
		};

		xin32k {
			clkin_32k: clkin-32k {
				rockchip,pins =
					<0 RK_PC2 1 &pcfg_input_smt>;
			};

			clkout_32k: clkout-32k {
				rockchip,pins =
					<0 RK_PC2 1 &pcfg_output_high>;
			};
		};
	};
};