/* * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd * * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ / { chosen: chosen { bootargs = "earlyprintk=uart8250,mmio32,0xff160000 swiotlb=1 console=ttyFIQ0 androidboot.baseband=N/A androidboot.veritymode=enforcing androidboot.hardware=rk30board androidboot.console=ttyFIQ0 init=/init kpti=0"; }; fiq-debugger { compatible = "rockchip,fiq-debugger"; rockchip,serial-id = <2>; rockchip,wake-irq = <0>; /* If enable uart uses irq instead of fiq */ rockchip,irq-mode-enable = <0>; rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&uart2m0_xfer>; status = "okay"; }; firmware { firmware_android: android {}; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; drm_logo: drm-logo@00000000 { compatible = "rockchip,drm-logo"; reg = <0x0 0x0 0x0 0x0>; }; }; ramoops_mem: ramoops_mem@110000 { reg = <0x0 0x110000 0x0 0xf0000>; reg-names = "ramoops_mem"; }; ramoops { compatible = "ramoops"; record-size = <0x0 0x20000>; console-size = <0x0 0x80000>; ftrace-size = <0x0 0x00000>; pmsg-size = <0x0 0x50000>; memory-region = <&ramoops_mem>; }; }; &cpu0_opp_table { rockchip,avs = <1>; }; &display_subsystem { status = "disabled"; ports = <&vopb_out>, <&vopl_out>; logo-memory-region = <&drm_logo>; route { route_lvds: route-lvds { status = "disabled"; logo,uboot = "logo.bmp"; logo,kernel = "logo_kernel.bmp"; logo,mode = "center"; charge_logo,mode = "center"; connect = <&vopb_out_lvds>; }; route_dsi: route-dsi { status = "disabled"; logo,uboot = "logo.bmp"; logo,kernel = "logo_kernel.bmp"; logo,mode = "center"; charge_logo,mode = "center"; connect = <&vopb_out_dsi>; }; route_rgb: route-rgb { status = "disabled"; logo,uboot = "logo.bmp"; logo,kernel = "logo_kernel.bmp"; logo,mode = "center"; charge_logo,mode = "center"; connect = <&vopb_out_rgb>; }; }; }; &video_phy { status = "okay"; };