From 8a838cde7c64c2e51c251d1c64a1913e494a1cd9 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 9 May 2018 09:48:07 +0800 Subject: clk: rockchip: Add support to configurate boost for pll clock Change-Id: I15841da7266b1b0fbc3407f0c23608c99209fb11 Signed-off-by: Finley Xiao --- drivers/clk/rockchip/clk.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/clk/rockchip/clk.c') diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 8b1f3e12eac0..f26c77c40631 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -445,7 +445,8 @@ void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx, list->con_offset, grf_lock_offset, list->lock_shift, list->mode_offset, list->mode_shift, list->rate_table, - list->flags, list->pll_flags); + list->flags, list->pll_flags, + list->boost_enabled); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, list->name); -- cgit v1.2.3