From 88a5404a227753592628f51b7db70b68e2fde2a6 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Wed, 20 Sep 2017 10:22:59 +0800 Subject: clk: rockchip: fix up the rockchip_fractional_approximation If frac clk parent rate is PLL rate, but still lower than frac rate*20, not allowed fractional div. Change-Id: I09c93e1d8f32c0a4e345057964d58505b1477204 Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers/clk/rockchip/clk.c') diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 4c3f55dcd829..7cb2f3e09269 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -181,6 +181,11 @@ void rockchip_fractional_approximation(struct clk_hw *hw, p_parent = clk_hw_get_parent(clk_hw_get_parent(hw)); p_parent_rate = clk_hw_get_rate(p_parent); *parent_rate = p_parent_rate; + if (*parent_rate < rate * 20) { + pr_err("%s parent_rate(%ld) is low than rate(%ld)*20, fractional div is not allowed\n", + clk_hw_get_name(hw), *parent_rate, rate); + return; + } } /* -- cgit v1.2.3