From 868a2dedf07484cc681c6559b0f2b8f918b3cd8e Mon Sep 17 00:00:00 2001 From: Wyon Bi Date: Mon, 26 Mar 2018 16:57:14 +0800 Subject: clk: rockchip: px30: Fix i2s out mclk Fixes: f6128506aaa9 ("clk: rockchip: px30: Fix i2s out mclk") Change-Id: I90dd4d1cdb1f3a2e9009dcb574115a5e7504fc32 Signed-off-by: Wyon Bi --- drivers/clk/rockchip/clk-px30.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk/rockchip/clk-px30.c') diff --git a/drivers/clk/rockchip/clk-px30.c b/drivers/clk/rockchip/clk-px30.c index 198737f29632..c3a0eaf57ebf 100644 --- a/drivers/clk/rockchip/clk-px30.c +++ b/drivers/clk/rockchip/clk-px30.c @@ -609,7 +609,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = { &px30_i2s1_fracmux, PX30_I2S_FRAC_MAX_PRATE), GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT, PX30_CLKGATE_CON(10), 2, GFLAGS), - COMPOSITE_NODIV(SCLK_I2S1_OUT, "clk_i2s1_out_pre", mux_i2s1_out_p, 0, + COMPOSITE_NODIV(0, "clk_i2s1_out_pre", mux_i2s1_out_p, 0, PX30_CLKSEL_CON(30), 15, 1, MFLAGS, PX30_CLKGATE_CON(10), 3, GFLAGS), GATE(SCLK_I2S1_OUT, "clk_i2s1_out", "clk_i2s1_out_pre", CLK_SET_RATE_PARENT, -- cgit v1.2.3