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path: root/drivers/clk/rockchip
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2019-04-30rk: clk: Allow clk_i2s0_frac to violate precision restriction.Christoph Muellner
The fraction approximation code for rockchip frac dividers impose the following requirement (as noted in a driver comment): fractional divider must set that denominator is 20 times larger than numerator to generate precise clock frequency. Additionally the frac driver limits the maximum input frequency to 600 MHz. This limitation can be achieved by using the integer divider (limiting to e.g. 400 MHz). Note, that both restrictions are not stated in the RK3399 TRM. The implication of these restrictions are, that the range of possible output frequencies is reduced quite drastically. This results in the problem, that clk_i2s0_frac cannot generate a clock of 24.56 MHz and thus audio on RK3399-Q7 is broken. Therefore this patch whitelists clk_i2s0_frac from the first restriction, similar to the exception for UART (in the same function). Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
2019-03-12clk: rockchip: rk3128: mark the hclk_vio_h2p as critical clkWyon Bi
Change-Id: Ib4eb985b1c3aacf6e51d593fcf71cd46e1dc0b82 Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
2019-03-08clk: rockchip: rk1808: export SCLK_32K_IOE clock idElaine Zhang
Add clk_32k_ioe to select 32k io as input or output. Change-Id: Id1d32b913e9739c4462eab6e565b3fcac370e531 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2019-03-08clk: rockchip: add a clock-type for muxes based in the pmugrfElaine Zhang
Rockchip socs often have some tiny number of muxes not controlled from the core clock controller but through bits set in the pmugrf. Use MUXPMUGRF() to cover this special clock-type. Change-Id: Iac962a27a3c88ce188d03c416cb4b3b45a462c0a Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2019-02-26clk: rockchip: rk1808: add cpll as critical clkElaine Zhang
Change-Id: Ibf02b6ed9916e774d7a82f33ac7f96e3395e4e88 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2019-01-25clk: rockchip: Modify uart frac divider ruleElaine Zhang
Because uart does not have high requirements for the clk Jitter, the fractional frequency divider does not need to meet the 20-fold relationship. (If uart clk rate < 24M,Use 24M as the fractional clock source.) Change-Id: I3f55f8a4ba5dc4c950c2742dc914c41e7b6e4ee6 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-12-26clk: rockchip: rk322x: fix wrong mmc phase shift for rk3228Chen Lei
mmc sample shift should be 1 for rk3228, or it will fail if we enable mmc tuning for rk3228. Change-Id: I301c2a7d33de8d519d7c288aef03a82531016373 Signed-off-by: Chen Lei <lei.chen@rock-chips.com>
2018-12-25clk: rockchip: rk322x: fix up the gate con description errorElaine Zhang
Change-Id: I439314c590a7144fab6e33d1fb4f325530669842 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-12-21clk: rockchip: px30: add FRAC_MAX_PRATE limit for uart0Elaine Zhang
Change-Id: Id4ec1995a8c406a1eb71da05a04699aa869f52b5 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-12-21clk: rockchip: rk3399: add FRAC_MAX_PRATE limit for spdif/uart/i2s/vop/wifiElaine Zhang
Change-Id: Ie92bf9d130ec92326df722b13de5f11e9658e3a3 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-12-21clk: rockchip: rk3368: add FRAC_MAX_PRATE limit for spdif/uart/i2sElaine Zhang
Change-Id: I24d365f5cb97da8974a0f718b5b56b6ffdaae27b Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-12-21clk: rockchip: rk3366: add FRAC_MAX_PRATE limit for spdif/uart/i2sElaine Zhang
Change-Id: I9bcc2431708398d07ba9b29a41f1c50b29fcf8e7 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-12-21clk: rockchip: rk3328: add FRAC_MAX_PRATE limit for spdif/uartElaine Zhang
Change-Id: I2728481b16f588c9d9afb3415077444a888a7f7e Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-12-21clk: rockchip: rk3288: add FRAC_MAX_PRATE limit for spdif/uart/i2sElaine Zhang
Change-Id: I7ab976f8e5187e62e470643fb68e83d8c375326c Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-12-21clk: rockchip: rk3188: add FRAC_MAX_PRATE limit for spdif/uart/i2s/hsadcElaine Zhang
Change-Id: I32d2d1868674c0067bc32ae3a2ece0de7c71fe93 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-12-21clk: rockchip: rk312x: add FRAC_MAX_PRATE limit for spdif/uart/i2sElaine Zhang
Change-Id: I39ffb7b30f1de0b051a542077296ea0141f9ad13 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-12-21clk: rockchip: rk3036: add FRAC_MAX_PRATE limit for spdif/uart/i2sElaine Zhang
Change-Id: I7a82ac645bc1ff0e277104c9441068990440533b Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-12-18clk/rockchip: rk618: add CLK_IGNORE_UNUSED for lvds_clkWyon Bi
Change-Id: I2c2f9a40ba5e09a64f059415ffc50458aa74ca5e Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
2018-12-17clk: rockchip: add clock controller for rv1108Sugar Zhang
This patch add the clock tree definition for rv1108. Change-Id: I9b55cd46c62331057fe8a404c606fe9d08f03388 Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2018-12-12clk: rockchip: rk3399: export SCLK_I2SOUT_SRC clk ID for i2sElaine Zhang
Change-Id: Ifbcea830e5f49946c1feea3f51d125e6ed566d5f Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-12-05clk: rockchip: px30: Export clk id for sclk_i2s0_tx/rx muxSugar Zhang
Change-Id: I697d20fb0c69f9dcd76aaf2d18d666db2241360d Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2018-12-05clk: rockchip: add support for pvtm clkElaine Zhang
add pvtm 32K internal clock setting and select enable. Change-Id: I60225d29e16c5b96f285623260bea475c78a026a Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-11-29Revert "clk: rockchip: fix wrong mmc phase shift for rk3328"Ziyuan Xu
This reverts commit 4ef244988993afc8a6447e990a4ccb4a223d3f20. The description for CRU_EMMC/SDMMC/SDIO_CON[0/1] is jumble on chapters, make it clear that the correct shift is 1 that from IC engineer. Change-Id: I48dce293ec6ef82a5c78db38efc083227776ea99 Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2018-11-27clk/rockchip/rk618: pll: support bypass modeWyon Bi
Change-Id: I698f73b69354d4f32f38a7c9874520b3813d0900 Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
2018-11-26clk: rockchip: clk-ddr: support DPI connectorWyon Bi
Change-Id: If78851e4908b5f4547cb93496d928d916e893eac Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
2018-11-23clk: rockchip: rk1808: fix up the mac clk settingElaine Zhang
Change-Id: I589f86a629ac8607fa24025cc90dd9bf21b414d5 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-11-16clk: rockchip: rk1808: fix SCLK_DDRCLK for dmcYouMin Chen
Change-Id: Ib43c4aa3548609d35748fac23db7b5ec589d69dd Signed-off-by: YouMin Chen <cym@rock-chips.com>
2018-11-15clk: rockchip: rk3308: Set max parent rate of dclk_vop_frac for rk3308bFinley Xiao
The max parent rate of dclk_vop_frac is improved to 800MHz on rk3308b. Change-Id: Ie36120ac7048fc4c983547539a6bce34d737529d Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-11-06clk: rockchip: rk3228: add FRAC_MAX_PRATE limit for spdif/uart/i2s/Elaine Zhang
Change-Id: Ifd0035cdb8794fefe986b88f0b0a54d73b87ed13 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-11-06clk: rockchip: rk3128: add hclk_sfcElaine Zhang
Change-Id: I20d0975156dc73bcdd02c09b7ecb815d5aca6bc6 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-10-26clk: rockchip: rk1808: add pll 100M config parametersElaine Zhang
PPLL 100M use refdiv =1 fbdiv = 150, postdiv1= 6, postdiv2=6, vco= 3.6G, is best for pcie. Change-Id: I40eb1a71c5025a68cab65ec56d2c2a7725d30c63 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-10-24clk: rockchip: rk1808: add CLK_IGNORE_UNUSED for aclk_pcie_mst/slvElaine Zhang
Change-Id: I6be0c48c68c2793528b3b480ed1afd982701266d Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-10-22clk: rockchip: rk1808: remove the apll from parents clk for npuElaine Zhang
apll is always change, not allowed apll as npu parent clk. Change-Id: Ia354b7ac533c2c7537d2d25894f956b855db9bc6 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-10-17clk: rockchip: rk1808: add aclk_imemx CLK_IGNORE_UNUSED flagElaine Zhang
Change-Id: I70ebbae78bef1b3ea15c18246460926517296a19 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-10-16clk: rockchip: rk1808: fix up the clk_pciephy_src parentElaine Zhang
Change-Id: If2a071ab19a2b8902206ae9010dfd4e4aeddae48 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-10-16clk: rockchip: rk1808: mark hsclk_imem as critical clockElaine Zhang
hsclk_imem is pd_npu and pd_imem share niu clk. Change-Id: I56e06edeb16340b2df7b1033c4fd65a61e22054e Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-10-15clk: rockchip: rk1808: fix mmc clock mux configurationZiyuan Xu
The mmc_clk has four selection for parent pll. The original configuration fix the parent to GPLL that causes the mmc_clk can't assign to a precision of 400KHz. [ 6.569962 ] mmc_host mmc2: Bus speed (slot 0) = 2320312Hz (slot req 400000Hz, actual 386718HZ div = 3) Change-Id: Ie3f74de79ac1e5f455e829b1b361200ad8b33db2 Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2018-10-15clk: rockchip: fix up the pr_err for fractional div is not allowedElaine Zhang
This pr_err print has some misunderstandings. Although fractional div is not allowed, But may be integer or half-divider can be precisely assigned to the desired frequency. Change-Id: Iec5d99edcc2b9e875c1d45b7464881ab389c356e Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-10-12clk: rockchip: fix wrong mmc phase shift for rk3328Ziyuan Xu
mmc sample shift is 0 for rk3328 refer to user manaul. So it's broken if we enable mmc tuning for rk3328. Change-Id: I863204b94be29842294597b1a1e10b3d7840e8d8 Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2018-10-11clk: rockchip: rk1808: support npu half dividerElaine Zhang
Change-Id: I78d8734b96e5982e2f0dcd08cf1747ff3d8f6e21 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-10-10clk: rockchip: rk1808: add clk ID for clk_rtc32k_fracElaine Zhang
Change-Id: Iecde141adbee536285155c64267580bde2ce5b13 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-10-09clk: rockchip: rk1808: rename SCLK_GPIO to DBCLK_GPIOElaine Zhang
Change-Id: I1ed6fe175fb2e640a7a61e1a2e799e94e76b435f Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-10-09clk: rockchip: rk1808: add FRAC_MAX_PRATE limit for vop/uart/i2s/pdmElaine Zhang
Change-Id: I444203484272e442fc0798a3daaaba0aee2dda31 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-10-08Revert "clk: rockchip: rk1808: fix PMU_CRU offset"Tao Huang
This reverts commit 3e9d3367b9300edfdd022026627510de5700e50b. PMU_CRU offset is 0x4000 Change-Id: Ibce2c7fc6b7995c128dde4809446b1b428f893aa Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-10-07clk: rockchip: rk1808: mark some clk as critical clocksElaine Zhang
mark "pclk_top_pre","pclk_ddr_grf","aclk_gic" as critical clocks Change-Id: I4daf50c36e899edcff07778cbb98571c2ed2b042 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-10-07clk: rockchip: rk1808: fix up the uart0 register description errorElaine Zhang
Change-Id: I4f11f5d0a0b46557e47346064416a9ad85cdcfbd Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-10-06clk: rockchip: rk1808: fix PMU_CRU offsetTao Huang
from 0x4000 to 0xc000 Change-Id: I32f8eb124c3c0621f5001473529bbae418789309 Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-09-26clk: rockchip: rk1808: fixup wrong id-name for HCLK_I2S1Sugar Zhang
Change-Id: I10254f5c6144443d614a34d75d2400c22c448514 Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2018-09-21clk: rockchip: rk3308: Fix spi clock's nameFinley Xiao
Change-Id: Id15d23786eed3e0105ad4f53858421a222e680d9 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-09-17clk: rockchip: rk3308: Modify parent clock of wifiFinley Xiao
Change-Id: I30022ac45c7effc2bdd3b54180e0994cf6f41b7a Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-05 08:25:05 +0000