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path: root/drivers/clk/rockchip/clk.h
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2019-03-08clk: rockchip: add a clock-type for muxes based in the pmugrfElaine Zhang
Rockchip socs often have some tiny number of muxes not controlled from the core clock controller but through bits set in the pmugrf. Use MUXPMUGRF() to cover this special clock-type. Change-Id: Iac962a27a3c88ce188d03c416cb4b3b45a462c0a Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-12-17clk: rockchip: add clock controller for rv1108Sugar Zhang
This patch add the clock tree definition for rv1108. Change-Id: I9b55cd46c62331057fe8a404c606fe9d08f03388 Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2018-10-08Revert "clk: rockchip: rk1808: fix PMU_CRU offset"Tao Huang
This reverts commit 3e9d3367b9300edfdd022026627510de5700e50b. PMU_CRU offset is 0x4000 Change-Id: Ibce2c7fc6b7995c128dde4809446b1b428f893aa Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-10-06clk: rockchip: rk1808: fix PMU_CRU offsetTao Huang
from 0x4000 to 0xc000 Change-Id: I32f8eb124c3c0621f5001473529bbae418789309 Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-08-29clk: rockchip: Add divider for backup pll when boostFinley Xiao
Cpu clock rate should be less than or equal to low rate when change pll rate in boost module. Change-Id: I53c4e66f06bba1e6a85920df0aaceb80176ab016 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-08-29clk: rockchip: Add support to get boost configure from devicetreeFinley Xiao
There are some configuration options for cpu boost, such as low frequency, higt frequency, boost backup pll, and so on. Change-Id: I35d65f05bbd5ef2a70e4a2e4637e7b4f9f67dda9 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-08-09clk: rockchip: add clock controller for rk1808Elaine Zhang
Add the clock tree definition for the new rk1808 SoC. Change-Id: I86e502b27e0695c77e9937dfd7cffa14b5711954 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-06-25clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-typeFinley Xiao
The div offset of some clocks are different from their mux offset and the COMPOSITE clock-type require that div and mux offset are the same, so add a new COMPOSITE_DIV_OFFSET clock-type to handle that. Change-Id: I7d541e29328f37d2ad806b3b6e5ab35b5513b345 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-06-15clk: rockchip: add support for half dividerElaine Zhang
The new Rockchip socs have optional half divider, so we use "branch_half_divider" + "COMPOSITE_NOMUX_HALFDIV \ DIV_HALF \ COMPOSITE_HALFDIV \ CMPOSITE_NOGATE_HALFDIV" to hook that special divider clock-type into our clock-tree. Change-Id: I79e3f0e8265ccb6a9839cd83a7a3ee0ca825a020 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-06-01soc: rockchip: opp_select: Add support to adjust power scaleFinley Xiao
Change-Id: I2358d75c2fdada7cfe385e85d2106370f9aa5ea3 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-05-11clk: rockchip: Remove pll_px30 pll typeFinley Xiao
Change-Id: I96068286edc8e79aa1150553fed16b42b446fc3f Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-05-11clk: rockchip: Separate boost address from cruFinley Xiao
Change-Id: I3e632b7f6769568ade18aad2fa000bc3f6ff8c2f Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-05-11clk: rockchip: Add support to configurate boost for pll clockFinley Xiao
Change-Id: I15841da7266b1b0fbc3407f0c23608c99209fb11 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-04-02clk: rockchip: Add supprot to limit input rate for fractional dividerFinley Xiao
From Rockchips fractional divider usage, some clocks can be generated by fractional divider, but the input clock frequency of fractional divider should be less than a specified value. Change-Id: Ifd6c5f6a24a64021f990506e8657cd925f9b96f9 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-03-16soc: rockchip: add support for adjust opp-table by board IR-DropLiang Chen
The IR-Drop is always different between different boards, so we need know the IR-Drop to adjust opp-table to guarantee stably for the board. Change-Id: I8ad05d30e15a7e62910a952cc6fa199d70129660 Signed-off-by: Liang Chen <cl@rock-chips.com>
2018-03-09clk: rockchip: Fix armclk parent errorFinley Xiao
There are two clocks between armclk and pll_apll on px30, but there may be only one clock on some Socs, so it will get a error pll clock. Change-Id: I34116a1ec824b884d3745082f3546cd9ab4c0d21 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-03-06clk: rockchip: Add clock controller for the RK3308Finley Xiao
Add the clock tree definition for the new RK3308 SoC. Change-Id: I1c0794b290207d28102e8d30cca13bbbf54ccfb8 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-02-02clk: rockchip: Adjust the order of cpu boostFinley Xiao
Change-Id: I5fe78b451f9afaff276aeb251d68daf780c1eecf Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-02-02clk: rockchip: px30: Fix boost maskFinley Xiao
Change-Id: I507efe5bf432556a9e603275f03c81a5a8ef96ed Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-01-18clk: rockchip: px30: Modify clk tree according to latest documentFinley Xiao
Change-Id: Ib8d983509792b13c1cc84c78af0f572b89053cc7 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2017-12-07clk: rockchip: Fix up the pll setting to support px30 SoC.Elaine Zhang
add px30 registers offset. add new pll type pll_px30 for px30 soc APLL. Change-Id: I321ba0d8dd45b90260cc7f22030ce905949ff762 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2017-08-29clk: rockchip: remove spin_lock in the rockchip_ddrclk_sip_set_rateYouMin Chen
Change-Id: Ia3d04aef8fbf8093c2a3a89a845f948f69c8611f Signed-off-by: YouMin Chen <cym@rock-chips.com>
2017-05-10clk: rockchip: support setting ddr clock via SIP Version 2 APIsTang Yun ping
1. Add support setting ddr clock via SIP Version 2 APIs 2. RK3288 using SIP Vision 2. Change-Id: I935e43b1885a96650dc86e3eb6d79de6795062a9 Signed-off-by: Tang Yun ping <typ@rock-chips.com>
2017-04-25clk: rockchip: Add adaptive frequency scaling for pll_rk3066Finley Xiao
Change-Id: I9c3422a45f86e8b95be0ad069ac70d5490eb5161 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2017-04-06clk: rockchip: support setting ddr clock via SCPI APIsFinley Xiao
On rk3368, let a mcu scaling ddr clock via SCPI (System Control and Power Interface) APIs. Change-Id: I95342b876caad991e6d1319c5e4ec793365c7981 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2017-01-06clk: rockchip: fix up the clock controller for rk3328Elaine Zhang
According to Heiko's advice,fix up some code style, reference the other clock drivers for indentation. remove grf clk init and use muxgrf to describe. fix up the pll parent only xin24m. fix up these *_sample error description. add mac2io and mac2phy clk id. moving the clock-ids a bit more together. Change-Id: I96273a6bf808841d0488dd9db461efdffc82a99f Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2017-01-05UPSTREAM: clk: rockchip: add a clock-type for muxes based in the grfHeiko Stuebner
Rockchip socs often have some tiny number of muxes not controlled from the core clock controller but through bits set in the general register files. Add a clock-type that can control these as well, so that we don't need to work around them being absent. BUG=None TEST=Build and boot on RK3399 Signed-off-by: Heiko Stuebner <heiko@sntech.de> (cherry picked from git.kernel.org mmind/linux-rockchip.git v4.11-clk/next commit cb1d9f6ddaa436f2dce2710740b7a3546700949c) Change-Id: I79352c8596f4d03fde519cd544c9d509d84c3a66 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2016-12-12clk: rockchip: add clock controller for rk3328Elaine Zhang
Add the clock tree definition for the new rk3328 SoC. Fix up the pll setting to support rk3328 SoC. Change-Id: Icf887625697515cf3e2cd2f7da7956a57c7e558a Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2016-08-25FROMLIST: clk: rockchip: add new clock-type for the ddrclkhuang lin
On new rockchip platform(rk3399 etc), there have dcf controller to do ddr frequency scaling, and this controller will implement in arm-trust-firmware. We add a special clock-type to handle that. Change-Id: I9e15dd9e01ab1c51a639a6a59391cd5e0de383b7 Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2016-08-18FROMLIST: clk: rockchip: add clock flag parameter when register pllHeiko Stübner
add clock flag parameter so we can pass specific clock flag (like CLK_GET_RATE_NOCACHE etc..)to pll driver. Change-Id: I1e076b3efa6b5da082b6e68e2e2a4c9dfd93e3d4 Signed-off-by: Heiko Stübner <heiko@sntech.de> Signed-off-by: Lin Huang <hl@rock-chips.com>
2016-06-22BACKPORT: clk: rockchip: add clock controller for rk3228Jeffy Chen
Add the clock tree definition for the new rk3228 SoC. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> (cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git v4.8-clk/next commit 307a2e9ac524bbec707c0e2b47ca50adaecc23f2) [zx: previouslly we miss the clock driver for rk3228, it may cause conflict with struct rockchip_clk_provider on the new CCF, let's update them directly, therefore, there are include 4 BACKPORT CLs in gerrit: https://10.10.10.29/#/c/20659/1 https://10.10.10.29/#/c/20661/1 https://10.10.10.29/#/c/20662/1 https://10.10.10.29/#/c/20663/1 ] Change-Id: I8d335e17340291f00f8e1643c8e893f88b06457c Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2016-03-18clk: rockchip: add clock controller for the RK3399Xing Zheng
Add the clock tree definition for the new RK3399 SoC. Change-Id: I1d8755eb7c89bdc56b79644a96a7d3fd8e7fbc4b Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2016-03-15UPSTREAM: clk: rockchip: add new pll-type for rk3399 and similar socsXing Zheng
The rk3399's pll and clock are similar with rk3036's, it different with base on the rk3066(rk3188, rk3288, rk3368 use it), there are different adjust foctors and control registers, so these should be independent and separate from the series of rk3066s. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> (cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-clk/next commit 95e0c473a0ac1bdac25f55678dc602eb50dae684) Change-Id: I77872b5fb33eb92402e9036b97b185ea56eb45c6 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2016-03-15UPSTREAM: clk: rockchip: fix warning reported by kernel-docShawn Lin
./scripts/kernel-doc -man -v drivers/clk/rockchip/clk.h > /dev/null drivers/clk/rockchip/clk.h:133: warning: missing initial short description on line: * struct rockchip_clk_provider: information about clock provider drivers/clk/rockchip/clk.h:133: info: Scanning doc for struct drivers/clk/rockchip/clk.h:164: warning: missing initial short description on line: * struct rockchip_pll_clock: information about pll clock drivers/clk/rockchip/clk.h:164: info: Scanning doc for struct drivers/clk/rockchip/clk.h:194: warning: No description found for parameter 'parent_names' drivers/clk/rockchip/clk.h:194: warning: No description found for parameter 'num_parents' drivers/clk/rockchip/clk.h:194: warning: Excess struct/union/enum/typedef member 'parent_name' description in 'rockchip_pll_clock' drivers/clk/rockchip/clk.h:235: warning: missing initial short description on line: * struct rockchip_cpuclk_reg_data: describes register offsets and masks of the cpuclock Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> (cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-clk/next commit 1c908b320055e1ce706e91121dbb2ce7934c788f) Change-Id: I18dbd45ebd528fe2a871c98a1561dd0c0bf41e13 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2016-03-15UPSTREAM: clk: rockchip: remove mux_core_reg from rockchip_cpuclk_reg_dataShawn Lin
mux_core_reg isn't been used anywhere, let's remove it. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> (cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-clk/next commit 72478f190fec9f2358b62f32ce5e27e6f323fa53) Change-Id: Ib6d8ee5bca61d1ada6215660862d2d728927a948 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2016-03-15UPSTREAM: clk: rockchip: Add support for multiple clock providersXing Zheng
There are need to support Multi-CRUs probability in future, but it is not supported on the current Rockchip Clock Framework. Therefore, this patch add support a provider as the parameter handler when we call the clock register functions for per CRU. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> (cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-clk/next commit d509ddf2e57c99ae760d1a289b85f1e0d729f864) Conflicts: drivers/clk/rockchip/clk-rk3036.c drivers/clk/rockchip/clk-rk3188.c drivers/clk/rockchip/clk-rk3228.c drivers/clk/rockchip/clk-rk3366.c [zx: keep calling clk_register_fixed_factor previouslly, and there is no rk3228 clock controller, add support for clk-rk3366 manually, because it is not in the upstream codes.] Change-Id: I94976f38fb6edd88f334479d6e44fef5bcdfc16a Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2016-03-15UPSTREAM: clk: rockchip: allow varying mux parameters for cpuclk pll-sourcesXing Zheng
Thers are only two parent PLLs that APLL and GPLL for core on the previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed GPLL as alternate parent when core is switching freq. Since RK3399 big.LITTLE architecture, we need to select and adapt more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> (cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-clk/next commit 0fda2be634398f4b8d53c0436311f99557e56c4e) Conflicts: drivers/clk/rockchip/clk-rk3228.c [zx: there is no rk3228 clock controller, apply this patch for clk-rk3366.] Change-Id: I48fde9facccd41585873c997b0b02a7a73972717
2016-03-15UPSTREAM: clk: rockchip: only enter pll slow-mode directly before reboots on ↵Heiko Stuebner
rk3288 As commit 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") states, switching the PLLs to slow-mode is only necessary when rebooting using the soft-reset done through the CRU. The dwc2 controllers used create really big number of interrupts in special constellations involving usb-hubs and their number is so high, it can even overwhelm the interrupt handler if the cpu-speed os to low. Right now the PLLs are put into slow-mode in a shutdown syscore_ops callback which means it happens on all reboots (not only the soft-reset ones) and even on poweroff actions. This can result in the system not powering off and getting stuck instead, so we should move the slow-mode change nearer to the actual reboot action. For this we introduce the possiblity to also set a callback that gets called from the restart-handler directly prior to restarting the system and move the shutdown-callback to this new option. With this the slow-mode switch is done only on the necessary reboots and also has a smaller possibility of causing artifacts. Fixes: 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") Signed-off-by: Heiko Stuebner <heiko.stuebner@collabora.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> (cherry picked from commit dfff24bde7fb8d57482e907d5dfb0be3a9e28119) Conflicts: drivers/clk/rockchip/clk-rk3228.c [zx: there is no rk3228 clock controller, apply for clk-rk3366] Change-Id: I2e91afd893c87eb3ab8a41db1fe81f5c43409951 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2016-03-14UPSTREAM: clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE typeXing Zheng
Because there are some frac clock mux nodes don't have a gate node on the RK3399. Change-Id: I4791b90a08faab286743a5cba30738cfb046594c Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> (cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-clk/next commit ffd9d4d39ef7ff90364d3abd6c39919e6582b605)
2016-03-01UPSTREAM: clk: rockchip: add a factor clock typeHeiko Stuebner
Add a clock type for fixed factor clocks. This allows us to define fixed factor clocks where they appear in the clock hierarchy instead of in the init function. The additional factor_gate type, finally allows us to model some last parts of the clock tree correctly. Signed-off-by: Heiko Stuebner <heiko@sntech.de> (cherry picked from commit 29a30c269aba4223e2a8b443f443d7def1e43fea) Change-Id: Ie4ec8b9d9199cdbe0be045c2ed4c270029e37949 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2016-02-18UPSTREAM: clk: rockchip: fix section mismatches with new child-clocksHeiko Stübner
To model the muxes downstream of fractional dividers we introduced the child property, allowing to describe a direct child clock. The first implementation seems to cause section warnings, as the core clock-tree is marked as initdata while the data pointed to from the child element is not. While there may be some way to also set that missing property in the inline notation I didn't find it, so to actually fix the issue for now move the sub-definitions into separate declarations that can have their own __initdata properties. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Michael Turquette <mturquette@baylibre.com> (cherry picked from commit 5b73840375e3eebeb7adf957ff64a96abdf4e1a1) Change-Id: I22c03dea33af24ba5743170325f318432cfd766f
2016-02-18UPSTREAM: clk: rockchip: handle mux dependency of fractional dividersHeiko Stuebner
The fractional dividers of Rockchip SoCs contain an "auto-gating-feature" that requires the downstream mux to actually point to the fractional divider and the fractional divider gate to be enabled, for it to really accept changes to the divider ratio. The downstream muxes themselfs are not generic enough to include them directly into the fractional divider, as they have varying sources of parent clocks including not only clocks related to the fractional dividers but other clocks as well. To solve this, allow our clock branches to specify direct child clock- branches in the new child property, let the fractional divider register its downstream mux through this and add a clock notifier that temporarily switches the mux setting when it notices rate changes to the fractional divider. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com> (cherry picked from commit 8ca1ca8f6039f19673fb61552f276b848539dbd6) Change-Id: Ic538fcf248f1e8a7ac87a45788167855155ca54a
2016-02-18UPSTREAM: clk: rockchip: add clock controller for rk3036Xing Zheng
Add the clock tree definition for the new rk3036 SoC. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> (cherry picked from commit 5190c08b29899131a183ea5802b9397918cca1ae) Change-Id: I0609b405ddb437e2ae9a432f386aa89ad47e7c84
2016-02-16clk: rockchip: add new pll-type for rk3366 and similar socsXiao Feng
The rk3366's pll and clock are similar with rk3036's, it different with base on the rk3066(rk3188, rk3288, rk3368 use it), there are different adjust foctors and control registers, so these should be independent and separate from the series of rk3066s. Change-Id: I49afadd1e34952356e1d6afcb2ef5f30bfa8617c Signed-off-by: Xiao Feng <xf@rock-chips.com>
2016-01-30UPSTREAM: clk: rockchip: add new pll-type for rk3036 and similar socsXing Zheng
The rk3036's pll and clock are different with base on the rk3066(rk3188, rk3288, rk3368 use it), there are different adjust foctors and control registers, so these should be independent and separate from the series of rk3066s. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> (cherry picked from commit 9c4d6e55377bc9232a33c7388accb5bd10771eba) Change-Id: I3a4aa2eb470976d69fef6b4fc2a33d9b46989817
2015-07-28clk: rockchip: Fix PLL bandwidthDouglas Anderson
In the TRM we see that BWADJ is "a 12-bit bus that selects the values 1-4096 for the bandwidth divider (NB)": NB = BWADJ[11:0] + 1 The recommended setting of NB: NB = NF / 2. So: NB = NF / 2 BWADJ[11:0] + 1 = NF / 2 BWADJ[11:0] = NF / 2 - 1 Right now, we have: { \ .rate = _rate##U, \ .nr = _nr, \ .nf = _nf, \ .no = _no, \ .bwadj = (_nf >> 1), \ } That means we set bwadj to NF / 2, not NF / 2 - 1 All of this is a bit confusing because we specify "NR" (the 1-based value), "NF" (the 1-based value), "NO" (the 1-based value), but "BWADJ" (the 0-based value) instead of "NB" (the 1-based value). Let's change to working with "NB" and fix the off by one error. This may affect PLL jitter in a small way (hopefully for the better). Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd
* cleanup-clk-h-includes: (62 commits) clk: Remove clk.h from clk-provider.h clk: h8300: Remove clk.h and clkdev.h includes clk: at91: Include clk.h and slab.h clk: ti: Switch clk-provider.h include to clk.h clk: pistachio: Include clk.h clk: ingenic: Include clk.h clk: si570: Include clk.h clk: moxart: Include clk.h clk: cdce925: Include clk.h clk: Include clk.h in clk.c clk: zynq: Include clk.h clk: ti: Include clk.h clk: sunxi: Include clk.h and remove unused clkdev.h includes clk: st: Include clk.h clk: qcom: Include clk.h clk: highbank: Include clk.h clk: bcm: Include clk.h clk: versatile: Remove clk.h and clkdev.h includes clk: ux500: Remove clk.h and clkdev.h includes clk: tegra: Properly include clk.h ...
2015-07-20clk: rockchip: Properly include clk.hStephen Boyd
Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Only include clk.h if it's actually used. Cc: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06clk: rockchip: add rk3368 clock controllerHeiko Stuebner
Describe the clock tree and software resets of the rk3368 ARM64 SoC Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06clk: rockchip: add support for phase invertersHeiko Stuebner
Most Rockchip socs have optional phase inverters connected to some clocks that move the clock-phase by 180 degrees. Signed-off-by: Heiko Stuebner <heiko@sntech.de> [sboyd@codeaurora.org: Dropped lazy part of commit text] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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