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path: root/drivers/clk/rockchip/clk.c
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2019-04-30rk: clk: Allow clk_i2s0_frac to violate precision restriction.Christoph Muellner
The fraction approximation code for rockchip frac dividers impose the following requirement (as noted in a driver comment): fractional divider must set that denominator is 20 times larger than numerator to generate precise clock frequency. Additionally the frac driver limits the maximum input frequency to 600 MHz. This limitation can be achieved by using the integer divider (limiting to e.g. 400 MHz). Note, that both restrictions are not stated in the RK3399 TRM. The implication of these restrictions are, that the range of possible output frequencies is reduced quite drastically. This results in the problem, that clk_i2s0_frac cannot generate a clock of 24.56 MHz and thus audio on RK3399-Q7 is broken. Therefore this patch whitelists clk_i2s0_frac from the first restriction, similar to the exception for UART (in the same function). Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
2019-03-08clk: rockchip: add a clock-type for muxes based in the pmugrfElaine Zhang
Rockchip socs often have some tiny number of muxes not controlled from the core clock controller but through bits set in the pmugrf. Use MUXPMUGRF() to cover this special clock-type. Change-Id: Iac962a27a3c88ce188d03c416cb4b3b45a462c0a Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2019-01-25clk: rockchip: Modify uart frac divider ruleElaine Zhang
Because uart does not have high requirements for the clk Jitter, the fractional frequency divider does not need to meet the 20-fold relationship. (If uart clk rate < 24M,Use 24M as the fractional clock source.) Change-Id: I3f55f8a4ba5dc4c950c2742dc914c41e7b6e4ee6 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-10-15clk: rockchip: fix up the pr_err for fractional div is not allowedElaine Zhang
This pr_err print has some misunderstandings. Although fractional div is not allowed, But may be integer or half-divider can be precisely assigned to the desired frequency. Change-Id: Iec5d99edcc2b9e875c1d45b7464881ab389c356e Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-08-29clk: rockchip: Add support to get boost configure from devicetreeFinley Xiao
There are some configuration options for cpu boost, such as low frequency, higt frequency, boost backup pll, and so on. Change-Id: I35d65f05bbd5ef2a70e4a2e4637e7b4f9f67dda9 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-06-25clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-typeFinley Xiao
The div offset of some clocks are different from their mux offset and the COMPOSITE clock-type require that div and mux offset are the same, so add a new COMPOSITE_DIV_OFFSET clock-type to handle that. Change-Id: I7d541e29328f37d2ad806b3b6e5ab35b5513b345 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-06-15clk: rockchip: add support for half dividerElaine Zhang
The new Rockchip socs have optional half divider, so we use "branch_half_divider" + "COMPOSITE_NOMUX_HALFDIV \ DIV_HALF \ COMPOSITE_HALFDIV \ CMPOSITE_NOGATE_HALFDIV" to hook that special divider clock-type into our clock-tree. Change-Id: I79e3f0e8265ccb6a9839cd83a7a3ee0ca825a020 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-06-05Revert "clk: rockchip: fix up the freq overshoot"Elaine Zhang
This reverts commit c64eb759a8e21c7a7c6980ee8f50e9f644c956fe. This commit make i2s clk setting error when integer divider switching integer divider. Change-Id: I927d6995d7b215fd412e147dff6a64c8fc4e2211 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-05-29clk: rockchip: fix up the frac clk get rate errorElaine Zhang
support fractional divider with only one level parent clock Change-Id: I6593f908edf4454ef03255080bf9ac1d72c6f64e Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-05-29clk: rockchip: fix up the freq overshootElaine Zhang
When integer divider switch to frac divider, High frequency burrs that may appeared, It's deadly to the system Change-Id: I483449f9a0b980671f90d4c534fad033998deaf7 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-05-11clk: rockchip: Separate boost address from cruFinley Xiao
Change-Id: I3e632b7f6769568ade18aad2fa000bc3f6ff8c2f Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-05-11clk: rockchip: Add support to configurate boost for pll clockFinley Xiao
Change-Id: I15841da7266b1b0fbc3407f0c23608c99209fb11 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-05-07UPSTREAM: clk: rockchip: Mark rockchip_fractional_approximation staticStephen Boyd
Silence the sparse warning clk/rockchip/clk.c:172:6: warning: symbol 'rockchip_fractional_approximation' was not declared. Should it be static? Cc: Elaine Zhang <zhangqing@rock-chips.com> Cc: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> (cherry picked from commit 1dfcfa721f9390ed5fd1e9c48e9fd6e8208a4963) Change-Id: I545f079ff61c6b65363442484cdedd9e01333160
2018-04-02clk: rockchip: Add supprot to limit input rate for fractional dividerFinley Xiao
From Rockchips fractional divider usage, some clocks can be generated by fractional divider, but the input clock frequency of fractional divider should be less than a specified value. Change-Id: Ifd6c5f6a24a64021f990506e8657cd925f9b96f9 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2017-09-20clk: rockchip: fix up the rockchip_fractional_approximationElaine Zhang
If frac clk parent rate is PLL rate, but still lower than frac rate*20, not allowed fractional div. Change-Id: I09c93e1d8f32c0a4e345057964d58505b1477204 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2017-08-29clk: rockchip: remove spin_lock in the rockchip_ddrclk_sip_set_rateYouMin Chen
Change-Id: Ia3d04aef8fbf8093c2a3a89a845f948f69c8611f Signed-off-by: YouMin Chen <cym@rock-chips.com>
2017-08-10clk: rockchip: add special approximation to fix up fractional clk's jitterElaine Zhang
From Rockchips fractional divider description: 3.1.9 Fractional divider usage To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by fractional divider. Generally you must set that denominator is 20 times larger than numerator to generate precise clock frequency. So the fractional divider applies only to generate low frequency clock like I2S, UART. Therefore add a special approximation function that handles this special requirement. Change-Id: I80260392539da9d8cab79a5f6e37534d003bdbd1 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2017-01-06clk: rockchip: fix up the pll-type for rk3328Elaine Zhang
fix up the pll type pll_rk3328 description and use. add the other parts handling parents,like num_parents check and the init.num_parents parameter. add ctx->grf. Change-Id: I17f1b0dc4b8286817f587e02fdea39f2d886f3d0 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2017-01-05UPSTREAM: clk: rockchip: add a clock-type for muxes based in the grfHeiko Stuebner
Rockchip socs often have some tiny number of muxes not controlled from the core clock controller but through bits set in the general register files. Add a clock-type that can control these as well, so that we don't need to work around them being absent. BUG=None TEST=Build and boot on RK3399 Signed-off-by: Heiko Stuebner <heiko@sntech.de> (cherry picked from git.kernel.org mmind/linux-rockchip.git v4.11-clk/next commit cb1d9f6ddaa436f2dce2710740b7a3546700949c) Change-Id: I79352c8596f4d03fde519cd544c9d509d84c3a66 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2016-08-25FROMLIST: clk: rockchip: add new clock-type for the ddrclkhuang lin
On new rockchip platform(rk3399 etc), there have dcf controller to do ddr frequency scaling, and this controller will implement in arm-trust-firmware. We add a special clock-type to handle that. Change-Id: I9e15dd9e01ab1c51a639a6a59391cd5e0de383b7 Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2016-08-18FROMLIST: clk: rockchip: add clock flag parameter when register pllHeiko Stübner
add clock flag parameter so we can pass specific clock flag (like CLK_GET_RATE_NOCACHE etc..)to pll driver. Change-Id: I1e076b3efa6b5da082b6e68e2e2a4c9dfd93e3d4 Signed-off-by: Heiko Stübner <heiko@sntech.de> Signed-off-by: Lin Huang <hl@rock-chips.com>
2016-05-13Merge branch 'linux-linaro-lsk-v4.4-android' of ↵Huang, Tao
git://git.linaro.org/kernel/linux-linaro-stable.git * linux-linaro-lsk-v4.4-android: (797 commits) parisc: Use generic extable search and sort routines arm64: kasan: Use actual memory node when populating the kernel image shadow arm64: mm: treat memstart_addr as a signed quantity arm64: lse: deal with clobbered IP registers after branch via PLT arm64: mm: check at build time that PAGE_OFFSET divides the VA space evenly arm64: kasan: Fix zero shadow mapping overriding kernel image shadow arm64: consistently use p?d_set_huge arm64: fix KASLR boot-time I-cache maintenance arm64: hugetlb: partial revert of 66b3923a1a0f arm64: make irq_stack_ptr more robust arm64: efi: invoke EFI_RNG_PROTOCOL to supply KASLR randomness efi: stub: use high allocation for converted command line efi: stub: add implementation of efi_random_alloc() efi: stub: implement efi_get_random_bytes() based on EFI_RNG_PROTOCOL arm64: kaslr: randomize the linear region arm64: add support for kernel ASLR arm64: add support for building vmlinux as a relocatable PIE binary arm64: switch to relative exception tables extable: add support for relative extables to search and sort routines scripts/sortextable: add support for ET_DYN binaries ... Conflicts: arch/arm64/mm/dma-mapping.c drivers/clk/rockchip/clk-rk3368.c drivers/mmc/core/core.c drivers/mmc/core/sdio.c include/linux/dcache.h Change-Id: Ibaa1e90ac735db8d9f5e542c266ef27b91616ef4
2016-05-11clk: rockchip: free memory in error cases when registering clock branchesShawn Lin
commit 2467b6745e0ae9c6cdccff24c4cceeb14b1cce3f upstream. Add free memeory if rockchip_clk_register_branch fails. Fixes: a245fecbb806 ("clk: rockchip: add basic infrastructure...") Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-05-11clk-divider: make sure read-only dividers do not write to their registerHeiko Stuebner
commit 50359819794b4a16ae35051cd80f2dab025f6019 upstream. Commit e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1") removed the special ops struct for read-only clocks and instead opted to handle them inside the regular ops. On the rk3368 this results in breakage as aclkm now gets set a value. While it is the same divider value, the A53 core still doesn't like it, which can result in the cpu ending up in a hang. The reason being that "ACLKENMasserts one clock cycle before the rising edge of ACLKM" and the clock should only be touched when STANDBYWFIL2 is asserted. To fix this, reintroduce the read-only ops but do include the round_rate callback. That way no writes that may be unsafe are done to the divider register in any case. The Rockchip use of the clk_divider_ops is adapted to this split again, as is the nxp, lpc18xx-ccu driver that was included since the original commit. On lpc18xx-ccu the divider seems to always be read-only so only uses the new ops now. Fixes: e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1") Reported-by: Zhang Qing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-03-15UPSTREAM: clk: rockchip: remove redundant checking of device_nodeShawn Lin
rockchip_clk_of_add_provider is used by sub-clk driver which already call of_iomap before calling it. If device_node does not exist, of_iomap returns NULL which will fail to init the sub-clk driver. So really it's redundant. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> (cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-clk/next commit a96edf5a5243e1bdf642492b783221aa498f1e49) Change-Id: I9a51ed269fe26742da2ae84d99cf9689f49add1b Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2016-03-15UPSTREAM: clk: rockchip: Add support for multiple clock providersXing Zheng
There are need to support Multi-CRUs probability in future, but it is not supported on the current Rockchip Clock Framework. Therefore, this patch add support a provider as the parameter handler when we call the clock register functions for per CRU. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> (cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-clk/next commit d509ddf2e57c99ae760d1a289b85f1e0d729f864) Conflicts: drivers/clk/rockchip/clk-rk3036.c drivers/clk/rockchip/clk-rk3188.c drivers/clk/rockchip/clk-rk3228.c drivers/clk/rockchip/clk-rk3366.c [zx: keep calling clk_register_fixed_factor previouslly, and there is no rk3228 clock controller, add support for clk-rk3366 manually, because it is not in the upstream codes.] Change-Id: I94976f38fb6edd88f334479d6e44fef5bcdfc16a Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2016-03-15UPSTREAM: clk: rockchip: only enter pll slow-mode directly before reboots on ↵Heiko Stuebner
rk3288 As commit 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") states, switching the PLLs to slow-mode is only necessary when rebooting using the soft-reset done through the CRU. The dwc2 controllers used create really big number of interrupts in special constellations involving usb-hubs and their number is so high, it can even overwhelm the interrupt handler if the cpu-speed os to low. Right now the PLLs are put into slow-mode in a shutdown syscore_ops callback which means it happens on all reboots (not only the soft-reset ones) and even on poweroff actions. This can result in the system not powering off and getting stuck instead, so we should move the slow-mode change nearer to the actual reboot action. For this we introduce the possiblity to also set a callback that gets called from the restart-handler directly prior to restarting the system and move the shutdown-callback to this new option. With this the slow-mode switch is done only on the necessary reboots and also has a smaller possibility of causing artifacts. Fixes: 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") Signed-off-by: Heiko Stuebner <heiko.stuebner@collabora.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> (cherry picked from commit dfff24bde7fb8d57482e907d5dfb0be3a9e28119) Conflicts: drivers/clk/rockchip/clk-rk3228.c [zx: there is no rk3228 clock controller, apply for clk-rk3366] Change-Id: I2e91afd893c87eb3ab8a41db1fe81f5c43409951 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2016-03-01UPSTREAM: clk: rockchip: add a factor clock typeHeiko Stuebner
Add a clock type for fixed factor clocks. This allows us to define fixed factor clocks where they appear in the clock hierarchy instead of in the init function. The additional factor_gate type, finally allows us to model some last parts of the clock tree correctly. Signed-off-by: Heiko Stuebner <heiko@sntech.de> (cherry picked from commit 29a30c269aba4223e2a8b443f443d7def1e43fea) Change-Id: Ie4ec8b9d9199cdbe0be045c2ed4c270029e37949 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2016-02-18UPSTREAM: clk: rockchip: handle mux dependency of fractional dividersHeiko Stuebner
The fractional dividers of Rockchip SoCs contain an "auto-gating-feature" that requires the downstream mux to actually point to the fractional divider and the fractional divider gate to be enabled, for it to really accept changes to the divider ratio. The downstream muxes themselfs are not generic enough to include them directly into the fractional divider, as they have varying sources of parent clocks including not only clocks related to the fractional dividers but other clocks as well. To solve this, allow our clock branches to specify direct child clock- branches in the new child property, let the fractional divider register its downstream mux through this and add a clock notifier that temporarily switches the mux setting when it notices rate changes to the fractional divider. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com> (cherry picked from commit 8ca1ca8f6039f19673fb61552f276b848539dbd6) Change-Id: Ic538fcf248f1e8a7ac87a45788167855155ca54a
2016-01-30UPSTREAM: clk-divider: make sure read-only dividers do not write to their ↵Heiko Stuebner
register Commit e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1") removed the special ops struct for read-only clocks and instead opted to handle them inside the regular ops. On the rk3368 this results in breakage as aclkm now gets set a value. While it is the same divider value, the A53 core still doesn't like it, which can result in the cpu ending up in a hang. The reason being that "ACLKENMasserts one clock cycle before the rising edge of ACLKM" and the clock should only be touched when STANDBYWFIL2 is asserted. To fix this, reintroduce the read-only ops but do include the round_rate callback. That way no writes that may be unsafe are done to the divider register in any case. The Rockchip use of the clk_divider_ops is adapted to this split again, as is the nxp, lpc18xx-ccu driver that was included since the original commit. On lpc18xx-ccu the divider seems to always be read-only so only uses the new ops now. Fixes: e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1") Reported-by: Zhang Qing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> (cherry picked from git.kernel.org clk/linux.git clk-next commit 50359819794b4a16ae35051cd80f2dab025f6019) Change-Id: I382323c61f94e79ee7eaec6db16f6c2a9ad387eb
2015-10-02clk: rockchip: save width in struct clk_fractional_dividerAndy Shevchenko
The ->mwidth and ->nwidth fields will be used by clk-fractional-divider when it will be switched to rational base approximation algorithm. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06clk: rockchip: add support for phase invertersHeiko Stuebner
Most Rockchip socs have optional phase inverters connected to some clocks that move the clock-phase by 180 degrees. Signed-off-by: Heiko Stuebner <heiko@sntech.de> [sboyd@codeaurora.org: Dropped lazy part of commit text] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-04clk: make several parent names constUwe Kleine-König
Since commit 2893c379461a ("clk: make strings in parent name arrays const") the name of parent clocks can be const. So add more const in several clock drivers. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-12clk: don't use __initconst for non-const arraysUwe Kleine-König
The statement static const char *name[]; defines a modifiable array of pointers to constant chars. That is *name[0] = 'f'; is forbidden, but name[0] = "f"; is not. So marking an array that is defined as above with __initconst is wrong. Either an additional const must be added such that the whole definition reads: static const char *const name[] __initconst; or where this is not possible __initdata must be used. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-28Merge tag 'v3.19-rockchip-clk2' of ↵Michael Turquette
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next - clock phase setting capability for the rk3288 mmc clocks - pll init to allow syncing to actual rate table values - some more exported clocks - fixes for some clocks (typos etc) all of them not yet used in actual drivers
2014-11-28clk: rockchip: Add support for the mmc clock phases using the frameworkAlexandru M Stan
This patch adds the 2 physical clocks for the mmc (drive and sample). They're mostly there for the phase properties, but they also show the true clock (by dividing by RK3288_MMC_CLKGEN_DIV). The drive and sample phases are generated by dividing an upstream parent clock by 2, this allows us to adjust the phase by 90 deg. There's also an option to have up to 255 delay elements (40-80 picoseconds long). This driver uses those elements (under the assumption that they're 60 ps long) to generate approximate 22.5 degrees options. 67.5 (22.5*3) might be as high as 90 deg if the delay elements are as big as 80 ps, so a finer division (smaller than 22.5) was not picked because the phase might not be monotonic anymore. Suggested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Alexandru M Stan <amstan@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-25clk: rockchip: add ability to specify pll-specific flagsHeiko Stuebner
This adds a flag parameter to plls that allows us to create special flags to tweak the behaviour of the plls if necessary. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Kever Yang <kever.yang@rock-chips.com>
2014-11-24Merge branch 'clk-fixes' into clk-nextMichael Turquette
2014-11-17clk-divider: Fix READ_ONLY when divider > 1James Hogan
Commit 79c6ab509558 (clk: divider: add CLK_DIVIDER_READ_ONLY flag) in v3.16 introduced the CLK_DIVIDER_READ_ONLY flag which caused the recalc_rate() and round_rate() clock callbacks to be omitted. However using this flag has the unfortunate side effect of causing the clock recalculation code when a clock rate change is attempted to always treat it as a pass-through clock, i.e. with a fixed divide of 1, which may not be the case. Child clock rates are then recalculated using the wrong parent rate. Therefore instead of dropping the recalc_rate() and round_rate() callbacks, alter clk_divider_bestdiv() to always report the current divider as the best divider so that it is never altered. For me the read only clock was the system clock, which divided the PLL rate by 2, from which both the UART and the SPI clocks were divided. Initial setting of the UART rate set it correctly, but when the SPI clock was set, the other child clocks were miscalculated. The UART clock was recalculated using the PLL rate as the parent rate, resulting in a UART new_rate of double what it should be, and a UART which spewed forth garbage when the rate changes were propagated. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Thomas Abraham <thomas.ab@samsung.com> Cc: Tomasz Figa <t.figa@samsung.com> Cc: Max Schwarz <max.schwarz@online.de> Cc: <stable@vger.kernel.org> # v3.16+ Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-04clk: rockchip: disable unused clocksKever Yang
The rockchip clock driver use CLK_IGNORE_UNUSED flag to make sure all the clocks are available like default power on state. We have implement the clock manage in most of rockchip drivers, it is time to remove it for power save. Instead we add CLK_IGNORE_UNUSED for some clock nodes which should be on during boot or no module driver in kernel will initialize it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-10-01clk: rockchip: add restart handlerHeiko Stübner
Add infrastructure to write the correct value to the restart register and register the restart notifier for both rk3188 (including rk3066) and rk3288. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2014-09-27clk: rockchip: add new clock-type for the cpuclkHeiko Stuebner
When changing the armclk on Rockchip SoCs it is supposed to be reparented to an alternate parent before changing the underlying pll and back after the change. Additionally there exist clocks that are very tightly bound to the armclk whose divider values are set according to the armclk rate. Add a special clock-type to handle all that. The rate table and divider values will be supplied from the soc-specific clock controllers. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org> On a rk3288-board: Tested-by: Doug Anderson <dianders@chromium.org>
2014-09-02clk: rockchip: protect critical clocks from getting disabledHeiko Stübner
The clock-tree contains clocks that should never get disabled automatically. One example are the base ACLKs, the base supplies for all peripherals. Therefore add a structure similar to the sunxi clock-tree to protect these special clocks from being disabled. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Doug Anderson <dianders@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-02clk: rockchip: make rockchip_clk_register_branch staticHeiko Stübner
It is only used locally in clk/rockchip/clk.c and thus can be static. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-02clk: rockchip: implement the fraction divider branch typeHeiko Stübner
Rockchip SoCs may provide fraction dividers for some clocks, mostly for i2s and uarts. In contrast to the other registers, these do not use the hiword-mask paradigm, but instead split the register into the upper 16 bit for the nominator and the lower 16 bit for the denominator. The common clock framework got a generic fractional divider clock type recently that can accomodate this setting easily. All currently known fraction dividers have a separate gate too, therefore implement the divider as composite using the ops-struct from fractional_divider clock and add the gate if necessary. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-13clk: rockchip: add clock type for pll clocks and pll used on rk3066Heiko Stübner
All known Rockchip SoCs down to the RK28xx (ARM9) use a similar pattern to handle their plls: |--\ xin32k ----------------|mux\ xin24m -----| pll |----|pll|--- pll output \---------------|src/ |--/ The pll output is sourced from 1 of 3 sources, the actual pll being one of them. To change the pll frequency it is imperative to remux it to another source beforehand. This is done by adding a clock-listener to the pll that handles the remuxing before and after the rate change. The output mux is implemented as a separate clock to make use of already existing common-clock features for disabling the pll if one of the other two sources is used. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-13clk: rockchip: add basic infrastructure for clock branchesHeiko Stübner
This adds infrastructure for registering clock branches. On Rockchip SoCs most clock branches are a combination of mux,divider and gate components, thus a composite clock is used when appropriate. Clock branches are supposed to be declared in an array using the COMPOSITE* or MUX, etc makros defined in the header and then registered using rockchip_clk_register_branches. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>