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Change-Id: I2728481b16f588c9d9afb3415077444a888a7f7e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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This reverts commit 4ef244988993afc8a6447e990a4ccb4a223d3f20.
The description for CRU_EMMC/SDMMC/SDIO_CON[0/1] is jumble on
chapters, make it clear that the correct shift is 1 that from
IC engineer.
Change-Id: I48dce293ec6ef82a5c78db38efc083227776ea99
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
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mmc sample shift is 0 for rk3328 refer to user manaul.
So it's broken if we enable mmc tuning for rk3328.
Change-Id: I863204b94be29842294597b1a1e10b3d7840e8d8
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
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Set I2S clk parent to CPLL.
Change-Id: I2eaa920c6ab02cbec944b11f3aea2e7fe8551659
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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Change-Id: Ic65033f4dbc5507f28b5e3fc748382e89edb3505
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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From Rockchips fractional divider usage, some clocks can be generated
by fractional divider, but the input clock frequency of fractional
divider should be less than a specified value.
Change-Id: Ifd6c5f6a24a64021f990506e8657cd925f9b96f9
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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rk3328
commit c420c1e4db22 ("clk: rockchip: Prevent calculating mmc phase if clock rate is zero")
catches some gremlins for clk-rk3328.c that the parents of MMC phase
clock should be clk_{sdmmc, sdio, emmc}, but not sclk_{sdmmc, sdio,
emmc}.
Change-Id: I714d031e33dcbed120bd5c9c514f7a1d65446c18
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
(cherry-picked from https://patchwork.kernel.org/patch/10298425/)
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Change-Id: I0ea209224880b8c51a385ed46827bb0d8f7dd219
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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Change-Id: Ie800d876644f1a7abac3f7d7f8352ba405a9537a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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Change-Id: Idec7baa6bb0bb5824270e9cd8f3c6ed38d47ecc1
Signed-off-by: Xinhuang Li <buluess.li@rock-chips.com>
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This adds the necessary data for handling dmcfreq on the rk3328
Change-Id: If4cff5cc372f80b6776a7272a1bff54abef2cf33
Signed-off-by: CanYang He <hcy@rock-chips.com>
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Change-Id: I56ef3a201fc57d8ae368a5d1448e9e85e9143703
Signed-off-by: Xinhuang Li <buluess.li@rock-chips.com>
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Add CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT
for dclk_lcdc.
Change-Id: I19a4a8e5f9e2cc5fda8b70f1b632dccd538e02a0
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
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Change-Id: I770a83ad357f18d3258755b6c1d43ef82248951e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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Change-Id: Ia07f22997875e874037cb06fea6a3f25e6ab46dc
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
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Change-Id: Ic876175272cba40093e555ee815e9261bb39d510
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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Change-Id: Ie323c8934205bf71360d779717bb3e34c36a9dc6
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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Change-Id: I6b86bd2244fda5e1eac52be4b5399230bfc9875e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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According to Heiko's advice,fix up some code style,
reference the other clock drivers for indentation.
remove grf clk init and use muxgrf to describe.
fix up the pll parent only xin24m.
fix up these *_sample error description.
add mac2io and mac2phy clk id.
moving the clock-ids a bit more together.
Change-Id: I96273a6bf808841d0488dd9db461efdffc82a99f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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Add the clock tree definition for the new rk3328 SoC.
Fix up the pll setting to support rk3328 SoC.
Change-Id: Icf887625697515cf3e2cd2f7da7956a57c7e558a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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