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path: root/drivers/clk/rockchip/clk-rk3128.c
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2019-03-12clk: rockchip: rk3128: mark the hclk_vio_h2p as critical clkWyon Bi
Change-Id: Ib4eb985b1c3aacf6e51d593fcf71cd46e1dc0b82 Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
2018-12-21clk: rockchip: rk312x: add FRAC_MAX_PRATE limit for spdif/uart/i2sElaine Zhang
Change-Id: I39ffb7b30f1de0b051a542077296ea0141f9ad13 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-11-06clk: rockchip: rk3128: add hclk_sfcElaine Zhang
Change-Id: I20d0975156dc73bcdd02c09b7ecb815d5aca6bc6 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-04-02clk: rockchip: Add supprot to limit input rate for fractional dividerFinley Xiao
From Rockchips fractional divider usage, some clocks can be generated by fractional divider, but the input clock frequency of fractional divider should be less than a specified value. Change-Id: Ifd6c5f6a24a64021f990506e8657cd925f9b96f9 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-02-10clk: rockchip: rk3128: Add sclk_hsadc_tspFinley Xiao
Change-Id: I842869a7ea79730daa6616f1cf2a8f5db7165ceb Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-02-02clk: rockchip: rk3128: Fix aclk_peri_src parentFinley Xiao
Change-Id: Id679e7235f78635233dc4d6bd59c75ce05dfc99e Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2017-12-11pmic: rk808: rk816: fix up the RK816 setting voltage drop make the system crashshengfei Xu
Before adjusting voltage, increase clk_cpu div and reduce CPU frequency Only support for RK312x chips. Change-Id: Id327da9590f7d9d383450e79acd1b309e05cd024 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: shengfei Xu <xsf@rock-chips.com>
2017-11-24clk: rockchip: rk3128: fix incorrect configurationLiang Chen
1. The first parent name of sclk_cif_out_src is wrong, it is "sclk_cif_src". 2. The MUX configuration for sclk_cif_out_src is wrong, it should be muxdiv_offset=29, mux_shift=2, mux_width=1. Change-Id: I36a0ec0791afdef398d37ac8b92b7831619fb01b Signed-off-by: Liang Chen <cl@rock-chips.com>
2017-11-07clk: rockchip: rk3128: Fix hclk_otg gateFinley Xiao
Change-Id: Ia3d4b24f388b31635018a21ed3900590f821e0f6 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2017-10-20clk: rockchip: rk3128: fix up the hclk_vio clk descriptionElaine Zhang
set hclk_vio_niu as critical clock. Change-Id: Ib9e182ac93038df34eadae502fc18df5c0854ef9 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2017-10-19clk: rockchip: rk3128: remove CLK_IGNORE_UNUSED flag from clk_mipi_24m clockWyon Bi
This flag was in place to prevent important clocks from getting gated while they had no users. Now that the driver supports clocks properly, we can drop this. Change-Id: Ied6ea7677ab38988c89100e3644d829cb5736356 Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
2017-09-05PM / devfreq: rockchip_dmc: add support for rk3128 dmcLiang Chen
This adds the necessary data for handling dmcfreq on the rk3128. Change-Id: I6aeae7103c1eaed0b4515d8d11863c4b190b6918 Signed-off-by: Liang Chen <cl@rock-chips.com>
2017-08-31clk: rockchip: rk3126: add sclk_timer5 as critical clockElaine Zhang
sclk_timer5 is for arm arch counter, so need always on. but no dts node to handle this clk, so make it as critical clock Change-Id: I2533d98a767fd2b296f2737ca8f03a73690820df Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2017-08-31clk: rockchip: rk3128: fix up pvtm gate regs description errorElaine Zhang
Change-Id: Id2aee42b00871fc90467c09bab53abc7b6c23e41 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2017-08-31clk: rockchip: rk3128: add pclk_pmu as critical clockElaine Zhang
pclk_pmu need always on, and no dts node to handle this clk, so make it as critical clock Change-Id: If95d7c45f8935883a335846b42f526cd2f36f131 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2017-08-24clk: rockchip: rk3128: add clk gate for PCLK_MIPIPHYSandy Huang
Change-Id: Icf55c315edc9514a23d00433ffe56c864ad7f3d8 Signed-off-by: Sandy Huang <hjc@rock-chips.com>
2017-08-01clk: rockchip: rk3128: modify rk3128 clk driver to support rk3126Elaine Zhang
rk3128 and rk3126 have some gate registers describe differences. So need to make some distinctions. The RK3126 and RK3128 Same clock description we move it to the common clock branches. And the different clks description use the own clock branches. Change-Id: If9571da0a86067d814c225629a6b6f07f0270f14 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2017-06-05UPSTREAM: clk: rockchip: add clock controller for rk3128Elaine Zhang
Add the clock tree definition for the new rk3128 SoC. And it also applies to the RK3126 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> (cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next commit f6022e88faca1a6a21cbd0f009b477bc530b9cc7) Change-Id: Ib933e398bc8e40d8659bc1cdc419116f48f6ae30 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-23 08:26:30 +0000