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path: root/drivers/clk/rockchip/clk-pll.c
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2018-08-29clk: rockchip: Add divider for backup pll when boostFinley Xiao
Cpu clock rate should be less than or equal to low rate when change pll rate in boost module. Change-Id: I53c4e66f06bba1e6a85920df0aaceb80176ab016 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-08-29clk: rockchip: Add support to get boost configure from devicetreeFinley Xiao
There are some configuration options for cpu boost, such as low frequency, higt frequency, boost backup pll, and so on. Change-Id: I35d65f05bbd5ef2a70e4a2e4637e7b4f9f67dda9 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-06-20clk: rockchip: Fix rk3036 pll rate overflow calculation on 32-bitFinley Xiao
Change-Id: I4e367893e97828b01b3e6ec457714c722d2c0af6 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-06-01soc: rockchip: opp_select: Add support to adjust power scaleFinley Xiao
Change-Id: I2358d75c2fdada7cfe385e85d2106370f9aa5ea3 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-05-24clk: rockchip: pll: Fix compile error when !DEBUG_FSTao Huang
Change-Id: I49be8f1772e28ab7f3cc343b0a81f258d739fdfb Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-05-11clk: rockchip: Add a boost summary tree in debugfsFinley Xiao
Change-Id: I19544927e4535f8d6e6fe9cfbfa75c2dbb95cf03 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-05-11clk: rockchip: Remove pll_px30 pll typeFinley Xiao
Change-Id: I96068286edc8e79aa1150553fed16b42b446fc3f Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-05-11clk: rockchip: Separate boost address from cruFinley Xiao
Change-Id: I3e632b7f6769568ade18aad2fa000bc3f6ff8c2f Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-05-11clk: rockchip: Add support to configurate boost for pll clockFinley Xiao
Change-Id: I15841da7266b1b0fbc3407f0c23608c99209fb11 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-03-16soc: rockchip: add support for adjust opp-table by board IR-DropLiang Chen
The IR-Drop is always different between different boards, so we need know the IR-Drop to adjust opp-table to guarantee stably for the board. Change-Id: I8ad05d30e15a7e62910a952cc6fa199d70129660 Signed-off-by: Liang Chen <cl@rock-chips.com>
2018-03-09clk: rockchip: Fix armclk parent errorFinley Xiao
There are two clocks between armclk and pll_apll on px30, but there may be only one clock on some Socs, so it will get a error pll clock. Change-Id: I34116a1ec824b884d3745082f3546cd9ab4c0d21 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-02-25clk: rockchip: Add adaptive frequency scaling for pll_rk3036Liang Chen
Change-Id: Ifd035967afc1852df81daa2b15afea764c5b851d Signed-off-by: Liang Chen <cl@rock-chips.com>
2018-02-02clk: rockchip: Adjust the order of cpu boostFinley Xiao
Change-Id: I5fe78b451f9afaff276aeb251d68daf780c1eecf Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-02-02clk: rockchip: px30: Fix wait boost recovery idleFinley Xiao
Change-Id: If407926c5fedd1e91b1223a3926f3bb98f4cb17c Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2017-12-07clk: rockchip: Fix up the pll setting to support px30 SoC.Elaine Zhang
add px30 registers offset. add new pll type pll_px30 for px30 soc APLL. Change-Id: I321ba0d8dd45b90260cc7f22030ce905949ff762 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2017-07-13clk: rockchip: Add adaptive frequency scaling for pll_rk3399Finley Xiao
Change-Id: Id7be0fd4045f273052d69f49df1272922fb8f8dc Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2017-04-25clk: rockchip: Add adaptive frequency scaling for pll_rk3066Finley Xiao
Change-Id: I9c3422a45f86e8b95be0ad069ac70d5490eb5161 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2017-03-14clk: rockchip: fix up the rockchip_rk3066_pll_clk_set_by_auto funcElaine Zhang
Change-Id: Id7c561a50a16918c2943f79701ab72c6eaccdc41 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2017-02-22clk: rockchip: add pll_wait_lock for pll_enableElaine Zhang
if pll is power down,when power up pll need wait pll lock. Change-Id: I2e795a682a0c9712b41e00ddf054065dde4a5c7c Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2017-01-22clk: rockchip: rk3399: fix up the pr_err for debugElaine Zhang
Change-Id: I16eeacaf0307146ebf8db745621ef57e5ab16fec Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2017-01-06clk: rockchip: fix up the pll-type for rk3328Elaine Zhang
fix up the pll type pll_rk3328 description and use. add the other parts handling parents,like num_parents check and the init.num_parents parameter. add ctx->grf. Change-Id: I17f1b0dc4b8286817f587e02fdea39f2d886f3d0 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2016-12-12clk: rockchip: add clock controller for rk3328Elaine Zhang
Add the clock tree definition for the new rk3328 SoC. Fix up the pll setting to support rk3328 SoC. Change-Id: Icf887625697515cf3e2cd2f7da7956a57c7e558a Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2016-08-18FROMLIST: clk: rockchip: add clock flag parameter when register pllHeiko Stübner
add clock flag parameter so we can pass specific clock flag (like CLK_GET_RATE_NOCACHE etc..)to pll driver. Change-Id: I1e076b3efa6b5da082b6e68e2e2a4c9dfd93e3d4 Signed-off-by: Heiko Stübner <heiko@sntech.de> Signed-off-by: Lin Huang <hl@rock-chips.com>
2016-07-27clk: rockchip: rk3399: fix up the make warningElaine Zhang
fix up the warning: Line 246: rate_table->nf = nf_out; drivers/clk/rockchip/clk-pll.c:246:19: warning: 'nf_out' may be used uninitialized in this function [-Wmaybe-uninitialized] Change-Id: I6c11bf91a280f324c21214cb7839e36f9ffa0da3 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2016-07-26clk: rockchip: rk3399: add pll up and down when change pll freqElaine Zhang
set pll sequence: ->set pll to slow mode or other plls ->set pll down ->set pll params ->set pll up ->wait pll lock status ->set pll to normal mode To slove the system error: rockchip_rk3399_wait_pll_lock: timeout waiting for pll to lock rockchip_rk3399_pll_set_params: pll update unsucessful, trying to restore old params Change-Id: I62aecd9f292de5a3c7bcd8a87231785bf115159d Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2016-07-26clk: rockchip: rk3399: support pll setting by autoElaine Zhang
If setting freq is not support in rockchip_pll_rate_table rk3399_pll_rates[], It can set pll params by auto. Change-Id: I5016cece64dca4c2efec18d552ee6be426f6b95a Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2016-03-15UPSTREAM: clk: rockchip: add new pll-type for rk3399 and similar socsXing Zheng
The rk3399's pll and clock are similar with rk3036's, it different with base on the rk3066(rk3188, rk3288, rk3368 use it), there are different adjust foctors and control registers, so these should be independent and separate from the series of rk3066s. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> (cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-clk/next commit 95e0c473a0ac1bdac25f55678dc602eb50dae684) Change-Id: I77872b5fb33eb92402e9036b97b185ea56eb45c6 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2016-03-15UPSTREAM: clk: rockchip: Add support for multiple clock providersXing Zheng
There are need to support Multi-CRUs probability in future, but it is not supported on the current Rockchip Clock Framework. Therefore, this patch add support a provider as the parameter handler when we call the clock register functions for per CRU. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> (cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-clk/next commit d509ddf2e57c99ae760d1a289b85f1e0d729f864) Conflicts: drivers/clk/rockchip/clk-rk3036.c drivers/clk/rockchip/clk-rk3188.c drivers/clk/rockchip/clk-rk3228.c drivers/clk/rockchip/clk-rk3366.c [zx: keep calling clk_register_fixed_factor previouslly, and there is no rk3228 clock controller, add support for clk-rk3366 manually, because it is not in the upstream codes.] Change-Id: I94976f38fb6edd88f334479d6e44fef5bcdfc16a Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2016-02-16clk: rockchip: add new pll-type for rk3366 and similar socsXiao Feng
The rk3366's pll and clock are similar with rk3036's, it different with base on the rk3066(rk3188, rk3288, rk3368 use it), there are different adjust foctors and control registers, so these should be independent and separate from the series of rk3066s. Change-Id: I49afadd1e34952356e1d6afcb2ef5f30bfa8617c Signed-off-by: Xiao Feng <xf@rock-chips.com>
2016-01-30UPSTREAM: clk: rockchip: add new pll-type for rk3036 and similar socsXing Zheng
The rk3036's pll and clock are different with base on the rk3066(rk3188, rk3288, rk3368 use it), there are different adjust foctors and control registers, so these should be independent and separate from the series of rk3066s. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> (cherry picked from commit 9c4d6e55377bc9232a33c7388accb5bd10771eba) Change-Id: I3a4aa2eb470976d69fef6b4fc2a33d9b46989817
2015-10-01clk: rockchip: don't use clk_ APIs in the pll init-callbackHeiko Stübner
Separate the update of pll registers from the actual set_rate function so that the init callback does not need to access clk-API functions. As we now have separated the getting and setting of the pll parameters we can also directly use these new functions in other places too. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24clk: rockchip: register pll mux before pll itselfHeiko Stuebner
The structure is xin24m -> pll -> pll-mux (xin24m,pll,xin32k). The pll does have an init callback to make sure the boot-selected frequency is using the expected pll settings and resets the same frequency using the values provided in the driver if necessary. The setting itself also involves remuxing the pll-mux temporarily to the xin24m source to let the new pll rate settle. Until now this worked flawlessly, even when it had the flaw of accessing the mux settings before the mux actually got registered. With the recent clock-core conversions this flaw became apparent in null pointer dereference in [<c03fc400>] (clk_hw_get_num_parents) from [<c0400df0>] (clk_mux_get_parent+0x14/0xc8) [<c0400ddc>] (clk_mux_get_parent) from [<c040246c>] (rockchip_rk3066_pll_set_rate+0xd8/0x320) So to fix that, simply register the pll-mux before the pll, so that it will be fully initialized when the pll clock executes its init- callback and possibly touches the pll-mux clock. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-08-24clk: rockchip: Convert to clk_hw based provider APIsStephen Boyd
We're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28clk: rockchip: Fix PLL bandwidthDouglas Anderson
In the TRM we see that BWADJ is "a 12-bit bus that selects the values 1-4096 for the bandwidth divider (NB)": NB = BWADJ[11:0] + 1 The recommended setting of NB: NB = NF / 2. So: NB = NF / 2 BWADJ[11:0] + 1 = NF / 2 BWADJ[11:0] = NF / 2 - 1 Right now, we have: { \ .rate = _rate##U, \ .nr = _nr, \ .nf = _nf, \ .no = _no, \ .bwadj = (_nf >> 1), \ } That means we set bwadj to NF / 2, not NF / 2 - 1 All of this is a bit confusing because we specify "NR" (the 1-based value), "NF" (the 1-based value), "NO" (the 1-based value), but "BWADJ" (the 0-based value) instead of "NB" (the 1-based value). Let's change to working with "NB" and fix the off by one error. This may affect PLL jitter in a small way (hopefully for the better). Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-20clk: rockchip: Properly include clk.hStephen Boyd
Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Only include clk.h if it's actually used. Cc: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-04clk: make several parent names constUwe Kleine-König
Since commit 2893c379461a ("clk: make strings in parent name arrays const") the name of parent clocks can be const. So add more const in several clock drivers. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-11-25clk: rockchip: add optional sync to pll rate parametersHeiko Stuebner
In some cases firmware brings up plls with different parameters than the ones noted in the rate table for the specific frequency. These firmware-selected parameters are worse than the tested ones in the pll rate tables but cannot be changed by a simple clk_set_rate call when the rate stays the same. Therefore add a ROCKCHIP_PLL_SYNC_RATE flag and implement an init callback that checks the runtime-parameters against the matching rate table entry and adjusts them to the table-ones if necessary. If no rate table is set or the current rate does not match any rate-table entry no changes are made. Being able to limit this adjustment to specific plls is necessary to not touch the ones supplying core components like the apll and dpll supplying the armcores and dram. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Kever Yang <kever.yang@rock-chips.com>
2014-11-25clk: rockchip: setup pll_mux data earlierHeiko Stuebner
In some cases we might need to access the data of the pll mux before the actual mux gets registered - like in the following patch adding an init-callback. Therefore populate pll_mux before registering the core pll-clock. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Kever Yang <kever.yang@rock-chips.com>
2014-11-25clk: rockchip: add ability to specify pll-specific flagsHeiko Stuebner
This adds a flag parameter to plls that allows us to create special flags to tweak the behaviour of the plls if necessary. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Kever Yang <kever.yang@rock-chips.com>
2014-09-27clk: rockchip: change pll rate without a clk-notifierDoug Anderson
The Rockchip PLL code switches into slow mode (AKA bypass more AKA 24MHz mode) before actually changing the PLL. This keeps anyone from using the PLL while it's changing. However, in all known Rockchip SoCs nobody should ever see the 24MHz when changing the PLL supplying the armclk because we should reparent children to an alternate (faster than 24MHz) PLL. One problem is that the code to switch to an alternate parent was running in PRE_RATE_CHANGE. ...and the code to switch to slow mode was _also_ running in PRE_RATE_CHANGE. That meant there was no real guarantee that we would switch to an alternate parent before switching to 24MHz mode. Let's move the switch to "slow mode" straight into rockchip_rk3066_pll_set_rate(). That means we're guaranteed that the 24MHz is really a last-resort. Note that without this change on real systems we were the code to switch to an alternate parent at 24MHz. In some older versions of that code we'd appy a (temporary) / 5 to the 24MHz causing us to run at 4.8MHz. That wasn't enough to service USB interrupts in some cases and could lead to a system hang. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-07-13clk: rockchip: add clock type for pll clocks and pll used on rk3066Heiko Stübner
All known Rockchip SoCs down to the RK28xx (ARM9) use a similar pattern to handle their plls: |--\ xin32k ----------------|mux\ xin24m -----| pll |----|pll|--- pll output \---------------|src/ |--/ The pll output is sourced from 1 of 3 sources, the actual pll being one of them. To change the pll frequency it is imperative to remux it to another source beforehand. This is done by adding a clock-listener to the pll that handles the remuxing before and after the rate change. The output mux is implemented as a separate clock to make use of already existing common-clock features for disabling the pll if one of the other two sources is used. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-04 11:37:59 +0000