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2019-04-30arm64: dts: rockchip: set powerdomain for spi5 on rk3399Klaus Goger
Access to the spi5 peripheral when powered down halts the system rendering it unresponsive. Define the powerdomain in the rk3399.dtsi to prevent a shutdown when the peripheral is used. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2019-01-04arm64: dts: rockchip: add xhci trb ent quirk for rockchip SoCsWilliam Wu
This patch adds "snps,xhci-trb-ent-quirk" for DWC3 controllers in RK1808/RK3328/RK3399/RK3399pro-npu. Change-Id: I708f62747150316d66459f02b399d7c9b2667636 Signed-off-by: William Wu <william.wu@rock-chips.com>
2018-12-29thermal: rockchip: add pinctrl controlElaine Zhang
Based on the TSADC Tshut mode to select pinctrl, instead of setting pinctrl based on architecture (Not depends on pinctrl setting by "init" or "default"). And it requires setting the tshut polarity before select pinctrl. Change-Id: Iac9ca05073b0181ee13b0048d0c2a54204f82bca Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-12-27arm64: dts: rockchip: rk3399: Add specification serial number for cpuFinley Xiao
Change-Id: Ie48b09944ae3b294e3c7666bd9aa68706bdd4ba5 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-12-26arm64: dts: rockchip: rk3399: don't enable edp_hpd pin by default on soc dtsiNickey Yang
Not all the rk3399 boards use gpio4_c7 pin for edp_hpd. So this pin should be specified in the board dts. Without this patch we see below pin conflict when hdmi-cec and edp enabled. [ 0.969331] rockchip-pinctrl pinctrl: pin gpio4-23 already requested by ff940000.hdmi; cannot claim for ff970000.edp [ 0.969350] rockchip-pinctrl pinctrl: pin-151 (ff970000.edp) status -22 [ 0.969361] rockchip-pinctrl pinctrl: could not request pin 151 (gpio4-23) from group edp-hpd on device rockchip-pinctrl Change-Id: I324f28ea9f995ee4b84869ac369ab63e0c141cfa Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
2018-12-14arm64: dts: rockchip: rk3399: add interrupt name for rkispHu Kejun
Change-Id: If942773bb18b55463cdd2137493f6573ce747893 Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
2018-12-05arm64: dts: rockchip: add reset properties for i2sSugar Zhang
Change-Id: I1bdc5a417b412d484ba0caccc9e57da6a928de54 Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2018-11-23arm64: dts: rockchip: rk3399: add gpio drive strength 10maWeixin Zhou
Change-Id: Iff6303af2e87425b0509fd962b9e6b2fca8eb896 Signed-off-by: Weixin Zhou <zwx@rock-chips.com>
2018-11-06arm64: dts: rockchip: rk3399 fix uart3 cts and rts pinctl configHuibin Hong
Change-Id: I2549e2a2e1913e9d9430087b9fc0009ec28a4c8f Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2018-09-25arm64: dts: rockchip: rk3399 fix node unit name coding styleJianqun Xu
Fix node unit name coding style, such as unit name vs reg, or unit name vs format. Change-Id: I8a3e28cc1949acc23622a4a1a20e4ab1479bf512 Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2018-08-21arm64: dts: rockchip: rk3399: don't enable hdmi_cec pin by default at soc dtsiWyon Bi
Fix pin conflicts when gpio4c7 is used for hdmi_cec and edp_hpd. CEC is an optional function for HDMI. Thus the hdmi_cec pin should be specified in the board .dts. Without this patch we see below pin conflict when both hdmi and edp enabled. [ 0.969331] rockchip-pinctrl pinctrl: pin gpio4-23 already requested by ff940000.hdmi; cannot claim for ff970000.edp [ 0.969350] rockchip-pinctrl pinctrl: pin-151 (ff970000.edp) status -22 [ 0.969361] rockchip-pinctrl pinctrl: could not request pin 151 (gpio4-23) from group edp-hpd on device rockchip-pinctrl [ 0.969371] rockchip-dp ff970000.edp: Error applying setting, reverse things back Change-Id: Id3e9d7fadb6a4cfd65827be9c4b55336406995f7 Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
2018-07-31UPSTREAM: arm64: dts: rockchip: add rk3399 dw-mmc resetsHeiko Stuebner
dw-mmc got its reset-properties specified, so add the softresets for it on the rk3399. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> (Cherry-picked from 04dc7f62037b0d3aead0dc62231efad89affa9f3) Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Conflicts: arch/arm64/boot/dts/rockchip/rk3399.dtsi Change-Id: I69b8cfeef113a259b930308965e33b915026a3d7
2018-07-30UPSTREAM: arm64: dts: rockchip: assign clock rate for cpll child clocks on ↵Lin Huang
rk3399 These clocks do not assign default clock frequency, and use the default cru register value to get frequency, so if cpll increase frequency, these clocks also increase their frequency, that may exceed their signed off frequency. So assign default clock for them to avoid it. NOTE: on none of the boards currently in mainline do we expect CPLL to be anything other than 800 MHz, but some future boards might have it. It's still good to be explicit about the clock rates to make diffing against future boards easier and also to rely less on BIOS muxing. Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> (cherry picked from commit e702e13f0b4ffbe3178a39bb878b37121cbd05e2) Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Change-Id: If6a2341e2797f3c35f90fe1c621b1df13632694e
2018-07-30UPSTREAM: arm64: dts: rockchip: assign clock rate for ACLK_VIO on rk3399Shunqian Zheng
The ACLK_VIO is a parent clock used by a several children, its suggested clock rate is 400MHz. Right now it gets 400MHz because it sources from CPLL(800M) and divides by 2 after reset. It's good not to rely on default values like this, so let's explicitly set it. NOTE: it's expected that at least one board may override cru node and set the CPLL to 1.6 GHz. On that board it will be very important to be explicit about aclk-vio being 400 MHz. Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> (cherry picked from commit 3f7f3b0fb4563947424673d9b6786f46111462d9) Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Conflicts: arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi Change-Id: Iadd22356e399e8d9b3a1f2bec981f2b41d813f3c
2018-07-30UPSTREAM: arm64: dts: rockchip: set to CCI clock of RK3399 to 600MShunqian Zheng
Per testing, this can reduce the memory latency and d8 gets better scores. Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> (cherry picked from commit bb4b6201d21653c99e41d1e57b3b26524be0e87e) Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Change-Id: I6f305e0bc60a91f18f606fb7a8012d80fcd378b5
2018-07-30UPSTREAM: arm64: dts: rockchip: replace to "max-frequency" instead of ↵Jaehoon Chung
"clock-freq-min-max" In drivers/mmc/core/host.c, there is "max-freqeuncy" property. It should be same behavior, So Use the "max-frequency" instead of "clock-freq-min-max". Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> (cherry picked from commit c49590691f3819bb6be3f77938ef39038eb76643) Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Conflicts: arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts Change-Id: I92f321b167cf4af9bb91e4814e797f0429ad80af
2018-07-26ARM64: rockchip: rk3399 reorder codes in rk3399-cdn-dpJianqun Xu
Sync with upstream codes. Change-Id: Ic5306bdf16125e46892b5a85339afec67ad85482 Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2018-07-26ARM64: dts: rockchip: rk3399 reorder nodesJianqun Xu
Sync with upstream Change-Id: I24aa7e127c21d1b4f2516a70b6d2c27339da0bbc Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2018-07-26UPSTREAM: arm64: dts: rockchip: Arch counter doesn't tick in system suspendBrian Norris
The "arm,no-tick-in-suspend" property was introduced to note implementations where the system counter does not quite follow the ARM specification that it "must be implemented in an always-on power domain". Particularly, RK3399's counter stops ticking when we switch from the 24MHz clock to the 32KHz clock in low-power suspend, so let's mark it as such. Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> (cherry picked from commit e6186820a74546ac201a6669ebbee42399583b8b) Change-Id: Ib1d54426c985235ba0a383012a6e4437a9fae80c Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2018-07-26UPSTREAM: arm64: dts: drop "arm,amba-bus" in favor of "simple-bus" part 2Masahiro Yamada
Tree-wide replacement was done by commit 2ef7d5f342c1 (ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus"), but we have some new users of "arm,amba-bus" at Linux 4.7-rc1. Eliminate them now. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Chanho Min <chanho.min@lge.com> Signed-off-by: Olof Johansson <olof@lixom.net> (cherry picked from commit 15b7cc78f0951e418c940d8b3b6a7a3b962b7748) Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Conflicts: arch/arm64/boot/dts/lg/lg1312.dtsi Change-Id: I249c73ade56946fa0548b9f36889abaa7e77d3df
2018-07-26ARM64: dts: rockchip: rk3399 sync codes with upstreamJianqun Xu
Change-Id: Idcefe76d4b823593a7f316e0e24d740ead46c7a0 Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2018-07-26ARM64: dts: rockchip: rk3399 efuse node sync with upstreamJianqun Xu
Modify "efuse_id" to "cpu_id" Change-Id: Iac229325d611c2db86b075eb47d6fe84dbbc0020 Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2018-07-26UPSTREAM: arm64: dts: rockchip: update dynamic-power-coefficient for rk3399Caesar Wang
This patch updates the dynamic-power-coefficient for big cluster on rk3399 SoCs. The dynamic power consumption of the CPU is proportional to the square of the Voltage (V) and the clock frequency (f). The coefficient is used to calculate the dynamic power as below - Pdyn = dynamic-power-coefficient * V^2 * f Where Voltage is in uV, frequency is in MHz. As the following is the tested data on rk3399's big cluster. frequency(MHz) Voltage(V) Current(mA) Dynamic-power-coefficient 24 0.8 15 48 0.8 23 ~417 96 0.8 40 ~443 216 0.8 82 ~438 312 0.8 115 ~430 408 0.8 150 ~455 So the dynamic-power-coefficient average value is about 436. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Conflicts: arch/arm64/boot/dts/rockchip/rk3399.dtsi Change-Id: I05a573eb7e0a74301f35fdeb2517f7fe3be9b8fb
2018-07-26UPSTREAM: arm64: dts: rockchip: set rk3399 dynamic CPU power coefficientsBrian Norris
Provide the dynamic power coefficient of the big and little CPU clusters. These numbers are currently in use on the Samsung Chromebook Plus ("Kevin"). The power allocator thermal governor doesn't know how to do anything if it doesn't get power parameters from its cooling devices (in this case, CPUfreq). So this effectively enables the power-allocator governor. Signed-off-by: Brian Norris <briannorris@chromium.org> [set the property in each core node] Signed-off-by: Heiko Stuebner <heiko@sntech.de> (Cherry-picked from f4697bd7021f17ed540c16abafee72be73577826) Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Conflicts: arch/arm64/boot/dts/rockchip/rk3399.dtsi Change-Id: I8899a2224fe6cbf6e6f874006bf115eee62b7041
2018-07-26ARM64: dts: rockchip: reorder some codesJianqun Xu
Patch reorder some codes to sync with upstream codes Change-Id: Iba1971dcee9b5cfb25b62e8bfa2135f0576398e9 Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2018-07-19arm64: dts: rockchip: add usic node for rk3399William Wu
Add usic node for rk3399 USB 2.0 EHCI controller with usic phy. Change-Id: Ibb4179ff1479816daa3b8455b0229f8a7a05bbdf Signed-off-by: William Wu <william.wu@rock-chips.com>
2018-07-05arm64: dts: rockchip: add mipi_dphy_tx1rx1 and modify rkisp1_1 for rk3399Hu Kejun
Change-Id: I94d01c6963dc5f2f9b61159df1b13fc0bb32a0f1 Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
2018-06-21ARM64: dts: rockchip: fix rk3399 device aliasesRandy Li
Enable the alias for ethernet in rk3399 and order the items in alphabetical order. Change-Id: I7862593ad99028eba75102fb684987cec8762d1c Signed-off-by: Randy Li <randy.li@rock-chips.com>
2018-06-04arm: dts: rockchip: thermal: update soc's sw/hw over temperature power off ↵Rocky Hao
degree to cope with Wide Temperature Range test, we maxamize soc's sw/hw over temperature power off degree. fow now, 115 degree Celsius is set to trigger sw powering off. if sw function does not work and temperature is continuing to grow up, and till 120 degree Celsius, hw powering off/reset is triggered. Change-Id: I751e9ea754f434bc20df39fdbdb40216a1582c39 Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
2018-05-11arm64: dts: rockchip: modify 'gpu_power_model' for Midgard DDK r18 on rk3399Zhen Chen
The values of the coefficients are the ones in px30.dtsi, according to Rocky Hao. Change-Id: I1843b999a3b93fd5791e556db8733596c75ef8ac Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
2018-05-07dts: rockchip: Set pwm pin pull down when used for negative pwm regulatorDavid Wu
As a second global reset, the GRF is not reset, the iomux and pull of PWM pin is still keeping, but PWM controller is reset, PWM pin goes into input mode. However, the pull is still none changed in kernel, which can cause voltage problems, so should always keep the PWM pin pull down mode, with 0~50 μA power increase. Change-Id: Ibbb9465f7c550d49d416bc3438c5199434df6eba Signed-off-by: David Wu <david.wu@rock-chips.com>
2018-04-26arm64: dts: rockchip: increase mcu frequency to 97mhz for rk3399CanYang He
mcu run at 97MHz to reduce lpddr4 scale frequency elapsed time Change-Id: Ie2805eaf0d902c9531819217d05a86775d85f809 Signed-off-by: CanYang He <hcy@rock-chips.com>
2018-04-24arm64: dts: rockchip: add hdmi hdcp2 node for rk3399Huicong Xu
Change-Id: Ie78fbdc226d856a20c2da40e4166e7b23ed27aba Signed-off-by: Huicong Xu <xhc@rock-chips.com>
2018-04-13arm64: dts: rockchip: Add rkisp1 for rk3399Hu Kejun
Change-Id: Ie0eb7088d08f9c0cbd0443b6f9c635ade9b4cc8f Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
2018-03-28arm64: dts: rockchip: fix dtc warnings of rk3399Tao Huang
Change-Id: I31fbab7d90e35ae47bbc6d54aad5e82b8902af7f Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-03-19pwm: rockchip: Make pwm pinctrl setting after pwm enabledDavid Wu
If the PWM pinctrl uses default state, the iomux setting will be done at probe, the PWM may not be enabled at this moment. It will make PWM into an intermediate state, destroy the default hardware state, the PWM is not ready for work yet. So it is better for doing PWM pinctrl setting after PWM enabled. Change-Id: Iea34a7baf6a4d7df0c631f7f4fdab5b9d61bbd5f Signed-off-by: David Wu <david.wu@rock-chips.com>
2018-01-30arm64: dts: rockchip: rk3399: correct vop1_pwm_pin defineSandy Huang
vop1_pwm_pin iomux with pwm0, not pwm1 Change-Id: I7eac8f57f953e774e4ec0792e7de03e0e8806f85 Signed-off-by: Sandy Huang <hjc@rock-chips.com>
2018-01-23ARM64: dts: rk3399: add dmc config for VOPRocky Hao
Change-Id: I1b07ca19c5f6529361630ac49ba8922ba0e32db2 Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
2018-01-04arm64: dts: rockchip: fix interrupts property of rk3399Tao Huang
Change-Id: Ifed5ba59ba2ca7d527e1747ccfa962b353062c0d Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2017-12-29arm64: dts: rockchip: add HDMI cec support for rk3399Algea Cao
Change-Id: Ib27fa6c0475b060a4af5d79cc0e158070efbeceb Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2017-11-27UPSTREAM: arm64: dts: rockchip: extent IORESOURCE_MEM_64 of PCIe for rk3399Shawn Lin
Make full use of 32 regions and increase IORESOURCE_MEM_64 so that we could have more chance to support PCIe switch with more endpoints attached to our RC. Change-Id: I1da5ad041bbcc71807eda8f72320c83ba7dbcefc Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> (cherry picked from 81f66606498cb510a9158805392b8c6d9b5ed51e)
2017-11-27UPSTREAM: arm64: dts: rockchip: extent bus-ranges of PCIe for rk3399Shawn Lin
In order to support multiple hierarchy of PCIe buses, or instance, PCIe switch, we need to extent bus-ranges to as max as possible. We have 32 regions and could support up to 31 buses except bus 0 for our root bridge. Change-Id: Iccca42642442a73b1828b17110b11891f1ee5feb Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> (cherry picked from d633becc583e13b38c4aea53b97a197acd61a521)
2017-11-21arm64: dts: rockchip: rk3399: Add nocp device nodeFinley Xiao
Change-Id: I9ef68b69a263720aea3d51e854375b51027c94a2 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2017-09-22arm64: dts: rockchip: split i2s mclk pinctrl from i2s busSugar Zhang
because currently mclk is handled by codec side, so the associated pinctrl should be handled by codec too. Change-Id: I55db6e9a0181cae0cb414b9dcacae7ff0214b50c Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2017-08-18arm64: dts: rockchip: rk3399: add pvtm resetsFinley Xiao
Change-Id: I1250a5193bd44b164d62d918401e60c7c4d31c59 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2017-08-17arm64: dts: rockchip: add dmc default config for rk3399wlq
Change-Id: Iaeacb92a560743ff6dcf1f3977449004fa256992 Signed-off-by: Wu Liangqing <wlq@rock-chips.com>
2017-08-04arm64: dts: rk3399: change rga node for v4l2 rgaJacob Chen
remove some unnecessary prop Change-Id: I37c841b6048fcacaa7442cfc23872e2ccaf92e6c Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
2017-08-04arm64: dts: rockchip: rk3399: Correct DPHY PLL clockWeiYong Bi
clk_24m --> Gate --> clk_mipidphy_ref --> Gate --> clk_dphy_pll Change-Id: Icb5283c0854a475a5f2fc436e7d4448393b5ac95 Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
2017-08-02arm64: dts: rockchip: rk3399: Correct reset-names for dsiWeiYong Bi
Change-Id: Icf9b7e6dd7e1f660ca109dae4d13a9b0c6192ae3 Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
2017-08-02arm64: dts: rockchip: rk3399: add dsi1 nodeWeiYong Bi
Change-Id: I964f047b0cf9f6355d61630d03181f229fdd8c15 Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
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