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To improve the performance of dual USB transmission.
Change-Id: Ie20d17029e54d299cddadc7a286d9bf6c96b0fbb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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clk_uart4_src default parent is 24M,does not satisfy the
fractional divider must set that denominator is 20 times
larger than numerator.
Change-Id: I21fd9866794e052414a6fdf1d64840ac2a0bb8f2
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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to fix up the display error when no uboot logo show.
Change-Id: I6227391a3c0d015a5fa6ae916d849659d5957077
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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keep aclk_vop hclk_vop freq the same as uboot,
to slove shaking for uboot logo to kernel show.
Change-Id: Id0b86fc583024482f16f40b2f1ec6f9189eac160
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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set npll init freq 600M
set gpll init freq 800M
Change-Id: I110cc4b4051504dd875712bce9e473f74d8578b4
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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1.reparent vop's parent to vpll which vop is for hdmi.
2.reparent the other vop to cpll.
3.reparent others clk and set clk rate,
to slove some clks is dummy.
attention:
if the vopb is for hdmi,the vopb parent clk must be vpll
and the vopl parent clk is cpll or others plls.
if the vopl is for hdmi,the vopl parent clk must be vpll
and the vopb parent clk is cpll or other plls.
Change-Id: Ibfd05172c93f885f66deea9cec64d64e22174078
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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