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Change-Id: I0934141d4a943f9bd21f74652c78a4e2eefc1e57
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
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degree
to cope with Wide Temperature Range test, we maxamize
soc's sw/hw over temperature power off degree.
fow now, 115 degree Celsius is set to trigger sw powering off.
if sw function does not work and temperature is continuing to
grow up, and till 120 degree Celsius, hw powering off/reset
is triggered.
Change-Id: I751e9ea754f434bc20df39fdbdb40216a1582c39
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
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Change-Id: Ia9e0af6242a20c62e4042afe4d99dedcfbeb753b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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As a second global reset, the GRF is not reset, the iomux and
pull of PWM pin is still keeping, but PWM controller is reset,
PWM pin goes into input mode. However, the pull is still none
changed in kernel, which can cause voltage problems, so should
always keep the PWM pin pull down mode, with 0~50 μA power
increase.
Change-Id: Ibbb9465f7c550d49d416bc3438c5199434df6eba
Signed-off-by: David Wu <david.wu@rock-chips.com>
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The vcc_sd is used for IO voltage for sdmmc interface on rk3399
platform have a limitation that it can't be larger than 3.0v, otherwise
it has a potential risk for the chip. Correct all of them.
Change-Id: I8d4ee2202fb32d30734c98a3b514c315e62859b4
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
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invert the pwm polarity for new pwm interface
Change-Id: I8dfde14fbc4fd4aa907722f260ce72fdb4d7d3bb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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Except dts of VR.
The md5sum is identical after rename, so this commit is safe.
Change-Id: I9ec324355ae67bbe2bb626090402ae797de13d92
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
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Afer the "PM / AVS: rockchip-io: make io-domains a child of the GRF",
the pmu-io-domains should be a sub-node of the pmugrf simple-mfd.
Change-Id: Iebfe9041a604580ce3e5b028d7a143fcdbbdff25
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
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Afer the "PM / AVS: rockchip-io: make io-domains a child of the GRF",
the io-domains should be a sub-node of the grf simple-mfd.
Change-Id: Ic2a40726bccee8b795b5249e07f2537fd30b3f7b
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
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Add a new dtsi file - rk3399-opp.dtsi, to configure opp-tables
for cpu, gpu and dmc.
Add rk3399-early-opp.dtsi for board with ES1, which need limit
frequency for cpu, gpu and dmc.
Change-Id: Ib57761fd5f405b0e79039d7a01e6e023d6f5dc2c
Reviewed-by: Finley Xiao <finley.xiao@rock-chips.com>
Reviewed-by: Huang, Tao <huangtao@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
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We may miss clock-latency-ns when disable some opps, then cpufreq
will fallback to performance governor, so add clock-latency-ns for
each opp to make disable opp easy.
code as below:
drivers/cpufreq/cpufreq.c:2010
if (policy->governor->max_transition_latency &&
policy->cpuinfo.transition_latency >
policy->governor->max_transition_latency) {
if (!gov)
return -EINVAL;
else {
pr_warn("%s governor failed, too long transition latency of HW,
fallback to %s governor\n",
policy->governor->name, gov->name);
policy->governor = gov;
}
}
Change-Id: I93cff667deb487baa0115b7af0206f0803010d37
Signed-off-by: Chen Liang <cl@rock-chips.com>
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Change-Id: I047c50b984229e8bcea8726d5808504f00620092
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
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Change-Id: Ib10c6a923e3b6f62a083339ccd8807461ff8f26f
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
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