| Age | Commit message (Collapse) | Author |
|---|
|
The RK3399-Q7 (Puma) requires 33 Ohm drive strength to ensure signal
integrity at HS-400 (200MHz clock, DDR signalling).
A repeated EMC testing run validates that this increase does not
negatively impact EMC compliance (emissions have ample distance to
the regulatory limits).
Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
|
|
Extending the operating point list of the DMC to include
frequencies of up to 800 MHz.
This increases bandwidth and fixes issues observed
with RKISP1 (PIC_SIZE_ERRORs when performing memory
intensive tasks in parallel).
Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
|
|
This patch is required because the name of the "efuse_id" node has been
changed to "cpu_id" in the rk3399.dtsi by the following commit:
commit 1eefebf4c678d63d1051a38f6ffd06eb1bd66fe0
Author: Jianqun Xu <jay.xu@rock-chips.com>
Date: Tue Jul 24 15:56:18 2018 +0800
Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
|
|
CRC errors (code -84 EILSEQ) have been observed for some SanDisk
Ultra A1 cards when running at 50MHz.
Waveform analysis suggest that the level shifters that are used on the
RK3399-Q7 module for voltage translation between 3.0 and 3.3V don't
handle clock rates at or above 48MHz properly. Back off to 40MHz for
some safety margin.
Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
|
|
DDR memory frequency scaling is called DMC (dynamic memory controller)
in the RK3399 SoC.
Enable it in the DTS and in the defconfig.
To improve the reaction time of the rockchip_dmc governor, CONFIG_HZ_PERIODIC
is enabled, at the cost of a 3% idle power increase. I see worst case reaction
times of tens of seconds without it, because devfreq_dmc_ondemand_func does not
get to run.
The upthreshold and downdifferential values in the DTS are more aggressive than
what rockchip uses. This improves U-Boot make -j6 compile time by 8%.
Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
|
|
The SD-Card IO rail on the RK3399 should not be operated higher than
3.15V. We reduce it to 3.0V. Note that the I/Os on the Qseven edge
connector will still be 3.3V as expected.
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
|
|
The RK3399-Q7 (Puma) is a system-on-module featuring the Rockchip
RK3399 in a Qseven-compatible form-factor.
RK3399-Q7 features:
* CPU: ARMv8 64bit Big-Little architecture,
* Big: dual-core Cortex-A72
* Little: quad-core Cortex-A53
* IRAM: 200KB
* DRAM: 4GB-128MB dual-channel
* eMMC: onboard eMMC
* SD/MMC
* GbE (onboard Micrel KSZ9031) Gigabit ethernet PHY
* USB:
* USB3.0 dual role port
* 2x USB3.0 host, 1x USB2.0 host via onboard USB3.0 hub
* Display: HDMI/eDP/MIPI
* Camera: 2x CSI (one on the edge connector, one on the Q7 specified CSI ZIF)
* NOR Flash: onboard SPI NOR
* Companion Controller: onboard additional Cortex-M0 microcontroller
* RTC
* fan controller
* CAN
This dts describes includes all required peripherals for booting and
basic functionality including eMMC, NOR, USB, Ethernet, HDMI output
(with audio), I2C buses (including the RTC and fan controller features
provided by the default companion controller firmware) and LED
definitions.
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
|
