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path: root/arch/arm64/boot/dts/rockchip/rk3399-box.dtsi
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2019-03-05arm64: dts: rockchip: disable uart2 for rk3399 boardTao Huang
Change-Id: I0934141d4a943f9bd21f74652c78a4e2eefc1e57 Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com> Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2019-02-28arm64: dts: rockchip: rk3399-box: Fix RC pinctrl errorZhangbin Tong
The commit e38aa951c83b ("pwm: rockchip: Make pwm pinctrl setting after pwm enabled") modified the pinctrl-names to "active". Change-Id: I931707d194d7a5aa0c3e652933e8fae3ada20132 Signed-off-by: Zhangbin Tong <zebulun.tong@rock-chips.com>
2018-10-29arm64: dts: rockchip: rk3399: separate android firmwareGuochun Huang
- Split DT source files to separate out android firmware specific DT bindings - Add an alias for firmware_android in rk3399-android.dtsi Change-Id: If3ae952c61ff01903ea990c6430255af27f5a432 Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
2018-08-21arm64: dts: rockchip: rk3399-box: Add cec pinctrlAlgea Cao
Only box enable cec function by default. Change-Id: Iec1c67a3570b123feb60ba12fdcee6336e791357 Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2018-06-04arm: dts: rockchip: thermal: update soc's sw/hw over temperature power off ↵Rocky Hao
degree to cope with Wide Temperature Range test, we maxamize soc's sw/hw over temperature power off degree. fow now, 115 degree Celsius is set to trigger sw powering off. if sw function does not work and temperature is continuing to grow up, and till 120 degree Celsius, hw powering off/reset is triggered. Change-Id: I751e9ea754f434bc20df39fdbdb40216a1582c39 Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
2018-05-21ARM64: dts: rockchip: rk3399: mark xin32k clk as fixed clkElaine Zhang
Change-Id: Ia9e0af6242a20c62e4042afe4d99dedcfbeb753b Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-05-07dts: rockchip: Set pwm pin pull down when used for negative pwm regulatorDavid Wu
As a second global reset, the GRF is not reset, the iomux and pull of PWM pin is still keeping, but PWM controller is reset, PWM pin goes into input mode. However, the pull is still none changed in kernel, which can cause voltage problems, so should always keep the PWM pin pull down mode, with 0~50 μA power increase. Change-Id: Ibbb9465f7c550d49d416bc3438c5199434df6eba Signed-off-by: David Wu <david.wu@rock-chips.com>
2017-10-17arm64: dts: rockchip: correct vqmmc voltage for rk3399 platformsShawn Lin
The vcc_sd is used for IO voltage for sdmmc interface on rk3399 platform have a limitation that it can't be larger than 3.0v, otherwise it has a potential risk for the chip. Correct all of them. Change-Id: I8d4ee2202fb32d30734c98a3b514c315e62859b4 Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-08-17arm64: dts: rockchip: rk3399-box: enable remote_support_psciZhangbin Tong
Change-Id: Icd60b10ebb65f1f181bc8ff916051c9e863809b9 Signed-off-by: Zhangbin Tong <zebulun.tong@rock-chips.com>
2017-03-25arm64: dts: rk3399-box: fix dp and hdmi dclk parentsMark Yao
Change-Id: Iebe0bfe248bf4ca6f61dafe1eb86a34dc6346e6f Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
2017-03-09ARM64: dts: rk3399 box: enable hdmi_dp_soundSugar Zhang
Change-Id: I04bdec75510b3e47a62a5093fdbd6ec66926e282 Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2017-03-08arm64: dts: rockchip: rk3399: set ir irq handle on cpu1Huang zhibao
Change-Id: I89f75184af810a050f6ca09daeba17774af4465e Signed-off-by: Huang zhibao <hzb@rock-chips.com>
2017-03-06ARM64: dts: rockchip: rk3399: invert the pwm polarityElaine Zhang
invert the pwm polarity for new pwm interface Change-Id: I8dfde14fbc4fd4aa907722f260ce72fdb4d7d3bb Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2017-02-27arm64: dts: rockchip: cleanup rk3399-android.dtsiHuang, Tao
default enable rkvdec and vpu. rga is default on, remove duplicate configuration. Change-Id: I8375b2202a81977238e8120e1c2d60f2130844b5 Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
2017-02-20arm64: dts: rk3399: rename android-next to androidHuang, Tao
The md5sum is identical after rename, so this commit is safe. Change-Id: I97cb5faecebaad9d2e9c39f67f19f662642cc5e8 Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
2017-02-20arm64: dts: rk3399: rename android to android-6.0Huang, Tao
Except dts of VR. The md5sum is identical after rename, so this commit is safe. Change-Id: I9ec324355ae67bbe2bb626090402ae797de13d92 Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
2017-02-10ARM64: dts: rk3399-box: Add a new infrared remote control buttonZhangbin Tong
Change-Id: Idd384a9c8635772f3c53a0a1f60739998db1704a Signed-off-by: Zhangbin Tong <zebulun.tong@rock-chips.com>
2017-02-10ARM64: dts: rk3399: enable rockchip-suspend for boxZhangbin Tong
Change-Id: Ibfaee3b898dc77673b806e6a46570320918b9a5e Signed-off-by: Zhangbin Tong <zebulun.tong@rock-chips.com>
2017-01-11arm64: dts: rockchip: clean up emmc_phyShawn Lin
freq-sel, dr-sel and opdelay are obsolete now, so we should remove them from the DT files to prevent the spread of unused code. Change-Id: Ibfa4fa225231a004913aa31aac475eb252e329c6 Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
2016-12-29ARM64: dts: rk3399-box: Use gpio control for enable/disable of syr82x buckZhangbin Tong
Change-Id: I9e03084c93ffff5d8ea79ed037656ce8d6615226 Signed-off-by: Zhangbin Tong <zebulun.tong@rock-chips.com>
2016-12-21arm64: dts: rockchip: keep vbus always on for usb2.0 host of rk3399Frank Wang
One basic condition of usb remote wakeup is vbus on, so we add regulator-always-on property for vcc5v0_host regulator in this adds. In the previous codes, ehci/ohci-platform did not power off vcc5v0_host regulator due to some oddish codes, and we have fixed it at commit b5a0a9e8794d. Change-Id: I95c225c9c3aeec6e346d62e61fdcde5e5e02d143 Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
2016-12-13ARM64: dts: rockchip: move rk3399 pmu-io-domain nodes to the pmugrfJianqun Xu
Afer the "PM / AVS: rockchip-io: make io-domains a child of the GRF", the pmu-io-domains should be a sub-node of the pmugrf simple-mfd. Change-Id: Iebfe9041a604580ce3e5b028d7a143fcdbbdff25 Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2016-12-13ARM64: dts: rockchip: move rk3399 io-domain nodes to the grfJianqun Xu
Afer the "PM / AVS: rockchip-io: make io-domains a child of the GRF", the io-domains should be a sub-node of the grf simple-mfd. Change-Id: Ic2a40726bccee8b795b5249e07f2537fd30b3f7b Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2016-11-30ARM64: dts: rk3399: move opp tables to rk3399-opp.dtsiJianqun Xu
Add a new dtsi file - rk3399-opp.dtsi, to configure opp-tables for cpu, gpu and dmc. Add rk3399-early-opp.dtsi for board with ES1, which need limit frequency for cpu, gpu and dmc. Change-Id: Ib57761fd5f405b0e79039d7a01e6e023d6f5dc2c Reviewed-by: Finley Xiao <finley.xiao@rock-chips.com> Reviewed-by: Huang, Tao <huangtao@rock-chips.com> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2016-11-24ARM64: dts: rk3399: add clock-latency-ns for each oppChen Liang
We may miss clock-latency-ns when disable some opps, then cpufreq will fallback to performance governor, so add clock-latency-ns for each opp to make disable opp easy. code as below: drivers/cpufreq/cpufreq.c:2010 if (policy->governor->max_transition_latency && policy->cpuinfo.transition_latency > policy->governor->max_transition_latency) { if (!gov) return -EINVAL; else { pr_warn("%s governor failed, too long transition latency of HW, fallback to %s governor\n", policy->governor->name, gov->name); policy->governor = gov; } } Change-Id: I93cff667deb487baa0115b7af0206f0803010d37 Signed-off-by: Chen Liang <cl@rock-chips.com>
2016-11-11arm64: dts: rockchip: add pvtm node for rk3399Finley Xiao
Change-Id: Ic7becefeb7e7a1000b259c21fedda76794b7115c Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2016-10-28arm64: dts: rk3399-box: adjust hdmi phy_table for physical signal testxuhuicong
Change-Id: I4184d26dd26ccfa786d1147ec73caae006e32343 Signed-off-by: xuhuicong <xhc@rock-chips.com>
2016-10-28arm64: dts: rk3399-box: dp: select vopl for dp as vop0 for hdmixuhuicong
Change-Id: I8ee8a2d7e5f441e765c7d3f6c805c5a0e3666e59 Signed-off-by: xuhuicong <xhc@rock-chips.com>
2016-10-14arm64: dts: rk3399: workaround: remove sd-uhs-sdr104 for sd cardsxiaoyao
Change-Id: Ic9d1f6f0e1ff81025b8b8d8d04f98026301c900f Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>
2016-10-13arm64: dts: rockchip: add USB3 an DP child nodes for tcphyWu Liang feng
Since the commit a2be4bc ('FIXUP: UPSTREAM: phy: Add USB Type-C PHY driver for rk3399') has created 2 PHY devices separately for tcphy USB3 and DisplyPort, and registered them under the child node, we should also add the USB3 and DP child nodes to dts. Change-Id: Iffe5dc961dc96b2b41476b1db2949e95c275e19f Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
2016-10-11ARM64: dts: rk3399: add regulator-ramp-delay for dcdcElaine Zhang
used to calculate the delay time for change dcdc voltage. Change-Id: I6bb462ef087b9ce6aa98991a1b961ed5f57bb3c8 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2016-10-10ARM64: dts: rk3399-box: add card-detect-delay propertyxiaoyao
Practice shows : The sd cards are easier to be identified after increase delay Change-Id: I48912e2d184902fab8b27edba70281f0bf19b9ab Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>
2016-10-08arm64: dts: rockchip: set dwc3 dr_mode as otg for rk3399-boxWu Liang feng
rk3399-box Type-C0 USB needs to support peripheral mode and host mode, so we set dr_mode as otg. Change-Id: If94cdca3ec1d018c3f9aad14bb2c1e15e10e9c51 Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
2016-09-12arm64: dts: rockchip: pull down rst-gpio of gmac-phy at suspend for rk3399-boxDavid Wu
Some phys would not enter low power mode by writing 'power down' bit into phy common register0 such as RTL8211E. And pulling down reset gpio is also a common way to make phy get low consumption, if the supplied regulator of phy could not be disabled at suspend. Change-Id: Ib01f48ec8c0bdec633868bb79e4155561ca6c471 Signed-off-by: David Wu <david.wu@rock-chips.com>
2016-09-12arm64: dts: rockchip: enable Type-C1 phy for rk3399 box USB3 HostMeng Dongyang
There is an USB3 Standard-A receptacle on the rk3399 box platform with Type-C1 phy, this patch enalbe Type-C1 phy for the USB3 port. Change-Id: I77074823e713b8a4c5e4ff693746d1bd2c3c139c Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com> Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
2016-09-07arm64: dts: rk3399-box: adjust cpul opp tableHans Yang
Adjust voltage of 1512M to 1.125v Change-Id: I7da47f0df8b45cb769e5f273d334ce9056347235 Signed-off-by: Hans Yang <yhx@rock-chips.com>
2016-09-02ARM64: dts: rk3399: enable cdn_dp_fb for boxxuhuicong
Change-Id: Idf28d25381b20e1a92193a3a825405a6ef41dfa5 Signed-off-by: xuhuicong <xhc@rock-chips.com>
2016-09-01arm64: dts: rk3399-box: vdd_gpu force PWM mode via regulator modeZhangbin Tong
Change-Id: I20552fb4896cc6de20b7729a6ec42447c447c01c Signed-off-by: Zhangbin Tong <zebulun.tong@rock-chips.com>
2016-08-19arm64: dts: rk3399-box: add test-powerJianhong Chen
Change-Id: Id06771f84b07c3b943362369269274a41cabb279 Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>
2016-08-18arm64: dts: rk3399-box: and 32.768K clk node for BTxxh
Change-Id: I7288d8e7a20aba17dca9cdb699da24af745e5567 Signed-off-by: Xu Xuehui <xxh@rock-chips.com>
2016-08-17arm64: dts: rockchip: use extcon for usb2/usb3 on rk3399 evb/boxWu Liang feng
Change-Id: I582381af1dfc5c7bb06736d3a92d2636b1523863 Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
2016-08-17arm64: dts: rockchip: enable Type-C phy for rk3399 evb/boxWu Liang feng
Change-Id: Idb2f919e008c37aa030c114c9a11df2d69126e99 Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
2016-08-09ARM64: dts: rk3399: support fusb302 for box rev1/2Meng Dongyang
Change-Id: Iea3f9e673a08bc959b3f57d169fff738ce746645 Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
2016-08-09ARM64: dts: rk3399: adjust box temperature patametersbuluess.li
Change-Id: I24982ee8ccb0fc9cbc92f357661d3b07ca275920 Signed-off-by: buluess.li <buluess.li@rock-chips.com>
2016-08-03arm64: dts: rockchip: modify sd minimum frequency for rk3399-boxxiaoyao
The host can issue continuous clock in the frequency range of 100KHz-400KHz for card identification mode. Change-Id: I4e6a96a5ec49ee102a3b24c3f7f9b74d6bc8fd5f Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>
2016-08-03ARM64: dts: rk3399-box: adjust gpu opp tableHans Yang
Adjust voltage of 500M to 0.9v Change-Id: I21ac14f27cc7aaddfea6280e76decc28c8b1182a Signed-off-by: Hans Yang <yhx@rock-chips.com>
2016-07-29ARM64: dts: rk3399-box: ajust gpu opp tableJianqun Xu
Ajust voltage of 800M to 1v, and remove 700M. Change-Id: Iabcdcee4f84693c9db53fbaf885e946bc8ca4212 Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2016-07-29arm64: dts: rockchip: enable both of otg usb2 phys for rk3399Wu Liang feng
Enable both OTG1 PHY and OTG2 USB2 PHY for rk3399 board. With this patch, we can support usb battery charger detect and hold wake lock in OTG peripheral mode. Change-Id: Icae1924d8a2427c297f28032588f178532acc560 Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
2016-07-27FROMLIST: arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCsCaesar Wang
Add the interrupts cells value for 4, and the 4th cell is zero. Due to the doc[0] said:" the system requires describing PPI affinity, then the value must be at least 4" The 4th cell is a phandle to a node describing a set of CPUs this interrupt is affine to. The interrupt must be a PPI, and the node pointed must be a subnode of the "ppi-partitions" subnode. For interrupt types other than PPI or PPIs that are not partitionned, this cell must be zero. See the "ppi-partitions" node description below. [0]: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt Change-Id: I80d459b746aea40027a7eacfcc7aa764a57fdc9f Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> (am https://patchwork.kernel.org/patch/9215659/) (Note: fixes some no sync upstream node)
2016-07-27ARM64: dts: rk3399-box: rename files for box-rev1Jianqun Xu
Make dts files in order as follows: rk3399.dtsi rk3399-box.dtsi rk3399-box-rev1.dts rk3399-box-rev2.dts ... Change-Id: I93d1fb4380d0c84a14fc3476b7435b1abe4989d2 Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
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