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Based on the TSADC Tshut mode to select pinctrl,
instead of setting pinctrl based on architecture
(Not depends on pinctrl setting by "init" or "default").
And it requires setting the tshut polarity before select pinctrl.
Change-Id: Iac9ca05073b0181ee13b0048d0c2a54204f82bca
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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Change-Id: I1bdc5a417b412d484ba0caccc9e57da6a928de54
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
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degree
to cope with Wide Temperature Range test, we maxamize
soc's sw/hw over temperature power off degree.
fow now, 115 degree Celsius is set to trigger sw powering off.
if sw function does not work and temperature is continuing to
grow up, and till 120 degree Celsius, hw powering off/reset
is triggered.
Change-Id: I751e9ea754f434bc20df39fdbdb40216a1582c39
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
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Single entry is for target voltage and three entries are for
<target min max> voltages. Change cpu opp-microvolt form one entry to
three entries and set maximum acceptable voltage to a high value so that
regulator device can supply multiple consumers at the same time.
Change-Id: I3a0dc4e161bae33e36b232c36a0a05a3102359ef
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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According to the dwc2 programmer's guide v3.10a, in '2.1.3.2 Dedicated
FIFO Mode with No Thresholding', it suggested that:
Device RxFIFO =
- Scatter/Gather DMA mode:
(4 * number of control endpoints + 6) + ((largest USB packet used / 4) +
1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK
on rockchip platforms:
(4 * 1 + 6) + ((1024 / 4) + 1) + (2 * 6) + 1 = 280
- Slave or Buffer DMA mode:
(5 * number of control endpoints + 8) + ((largest USB packet used / 4) +
1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK
on rockchip platforms:
(5 * 1 + 8) + ((1024 / 4) + 1) + (2 * 6) + 1 = 283
Device IN Endpoint TxFIFO =
The TxFIFO must equal at least one MaxPacketSize (MPS).
In addition to RxFIFO and TxFIFOs, refer to dwc2 databook v3.10a,
'Figure 2-13 Device Mode FIFO Address Mapping and AHB FIFO Access Mapping
(Dedicated FIFO)', it required that when the device is operating in non
Scatter Gather Internal DMA mode, the last locations of the SPRAM are used
to store the DMAADDR values for each Endpoint (1 location per endpoint).
When the device is operating in Scatter Gather mode, then the last locations
of the SPRAM store the Base Descriptor address, Current Descriptor address,
Current Buffer address, and status quadlet information for each endpoint
direction (4 locations per Endpoint). If an Endpoint is bidirectional , then
4 locations will be used for IN, and another 4 for OUT).
Considering that the total FIFO size of dwc2 otg is 0x3cc (972),
and we must reserve (4 * 13) = 52 locations for all Endpoints.
So reconfig dwc2 device fifo size as follows:
Device RxFIFO = 280
Device IN Endpoint TxFIFO
- FIFO #0 = (64 / 4) = 16 (Assuming this is used for EP0)
- FIFO #1 = (1024/4) = 256 (Assuming this is used for Isochronous)
- FIFO #2 = (512/4) = 128
- FIFO #3 = (512/4) = 128
- FIFO #4 = (256/4) = 64
- FIFO #5 = (128/4) = 32
- FIFO #6 = (64/4) = 16
After reconfig the dwc2 device fifo size, test mtp write on rockchip
platform (PC -> rockchip platform) on rk312x/rk3326/px30/rk3288 evb,
when mask the 'vfs_write' in f_mtp.c, the writing data rate can be
increased from 16MBps ~ 20MBps to 30MBps ~ 36MBps on different kinds
of rockchip evbs.
Change-Id: I52c64a279523c811f706e69e427b0a6e8c45683b
Signed-off-by: William Wu <william.wu@rock-chips.com>
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Change-Id: I94be72168765327346587357f2a46515861f6e05
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
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If the PWM pinctrl uses default state, the iomux setting will
be done at probe, the PWM may not be enabled at this moment.
It will make PWM into an intermediate state, destroy the default
hardware state, the PWM is not ready for work yet. So it is better
for doing PWM pinctrl setting after PWM enabled.
Change-Id: Iea34a7baf6a4d7df0c631f7f4fdab5b9d61bbd5f
Signed-off-by: David Wu <david.wu@rock-chips.com>
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Change-Id: I07b01df67c006d14d19bc2277dc90d0e947793dd
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
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when pd power on/off, the qos regs need to save and restore.
Change-Id: I55739fb8f2b452702bdbdc974bd588bbc05848d7
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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Change-Id: I832fe95e886b5c33cc618edb24fffc2bfbb3b25f
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
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Change-Id: If986025b4e097d2d79a136cabe2ff62dd51ad39f
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
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When import dma_buf to rga driver, dma_map_sg will always do
cpu cache sync, it cause low performance.
Actually we don't want to do cpu cache sync on this context,
So set rga device with dma-coherent to skip cpu cache sync.
Change-Id: Ie256db6a072481953befafb5b8003b9c1e713436
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
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Change-Id: I581242c5b04cfbd3d6c124455d075d8152598942
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
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So we can define reg offset according to TRM, otherwise it will make
us confused.
Change-Id: I1687542fcaf7ac4e6e78d863e8940f6604794407
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
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1) Add cluster sleep mode in cpu idle_states for RK3366 SoCs.
2) Modify cpu idle parameter.
Change-Id: I538c0bead8642c3642448edfe9971a3b09e919e0
Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
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Change-Id: I99a4c252f877ff36a16f991ee2e94bb110401e47
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
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Select rktimer0 as broadcast timer.
Change-Id: I1f9d80d920b063135c3b220b4df995eb5fcefa44
Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
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Change-Id: I0e8afc5e7bc6b8e4f37b7d34e9126e931df68347
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
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Change-Id: I5c4e48f29fd9aaab72e74c0de3aa840f9990b8e2
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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Change-Id: I99b95a9fd3e70c70b6066729dd4213f8beb33e19
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
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Change-Id: I677f4554bdc0d6df9cfdffa86eebe0fa4e1759dd
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
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Change-Id: I798a6518a2a74fe07ae2bb82abaca2da501ae07b
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
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Change-Id: I5e546ecbf5e1d8cc0a36d8ebd439663e1658f23b
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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to rk3366-android-6.0.dtsi
Change-Id: I98cafab3739f322e1b3826e597b7191ddd0e49c3
Signed-off-by: David Wu <david.wu@rock-chips.com>
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Change-Id: I3ecadd51e34545af61a1bfcc54ee0d6f045c40fa
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
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Compiling the DT file with W=1, DTC warns like follows:
Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
unit name, but no reg property
Fix this by replacing '@' with '-' as the OPP nodes will never have a
"reg" property.
Change-Id: I5748be7888db149633c3980c3f5e9715cd256a52
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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Change-Id: I86dd02761a4156768af018c0c90a61afb0ff74a6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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Change-Id: I7d984bf44e04d205c243eb2012cd06ba7c7fe548
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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Same as upstream.
Change-Id: Id9042d288bdbac2fede7da4aee13cc7a32609d6d
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
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Same as upstream.
Change-Id: Ic1887e5cf808ebf214168b51683dec25880f0dac
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
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Add a efuse node in the device tree for the ARM64 rk3366 SoC.
Change-Id: I163003e7e181645579a2af53003892ba46646706
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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Change-Id: Ic90466538671e69aaea82b0b20afdcb39ecf7006
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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This adds support usb2.0 phy-phandle for ohci controller on rk3366.
Change-Id: I9b5e27636e7574669ba01e4302c741d8895c68ff
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
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We found that the system on rk3366-sdk will crash at the first time
after updating the whole firmware, the root cause is the 480m clock
from usb-phy has some issues.
Since the new usb-phy driver have taken over the 480m clock's
maintenance, the clock tree have a bit changes, so related
reference clock for usb-controler also need to correct.
Change-Id: I54dcc6f416adf61c34df2b9b897e5b58f3b6fed8
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
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It would be better to name OPP nodes as opp@<opp-hz> as that will ensure
that multiple DT nodes don't contain the same frequency. Of course we
expect the writer to name the node with its opp-hz frequency and not any
other frequency.
And that will let the compile error out if multiple nodes are using the
same opp-hz frequency.
Change-Id: Icefba93f7a95752e344b5a092a83931bf4d1e682
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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Change-Id: I3379360efc32ba455f1934760af8b968c8748984
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
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As the 750MHz cpll can't produce accurate frequancy for i2s,
for example 11289600Hz, so assign their parents to the 576MHz gpll.
Change-Id: I430bce21ae69b47e561a95e691276d0c921a702c
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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Rk3366 support single and burst mode, and flushp instruction.
But burst mode improve transfer efficiency.
Please refer to:
Commit 8e770f371cc2
"dmaengine: pl330: add burst mode according to dts config"
Change-Id: I5e3fef4684f324dda015c0afd73535c062952fc1
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
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Change-Id: I0f4b09a41d249997f4c881238101a94a48fd737d
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
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according to our testing results, added the ipa parameters for both cpu
and gpu.
for now,the gpu thermal zone is used only to get the gpu's temperature.
Change-Id: I14274c0b2d7645d08f37d918ddb415ac49ed0d9e
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
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Gpu's 480MHz need to select usbphy_480m as parent.
The jitter will be lower, if sclk_wifidsp is supplied by pll_wifi.
Change-Id: I13e5077d55ab80e5224bac36b469e39d556bd347
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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Change-Id: Ib1e43d4df5735c2364138423d9622fd906ff5349
Signed-off-by: Xubilv <xbl@rock-chips.com>
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This patch like below:
----
commit 3860aa1ccfe01adb6c3fd09e880d812ceb408e5c
Author: Heiko Stuebner <heiko@sntech.de>
Date: Sat Jan 9 03:18:51 2016 +0100
ARM: dts: rockchip: swap i2s clock ordering on rk3036
For sound setups using the simple-card mechanism, the main clock
(sysclk) is expected to be the first element. For the i2s-driver
itself it doesn't matter, as it uses named clocks, so we can just
swap them.
----
If we set HCLK_I2Sx at first, rockchip_i2s_set_sysclk will set the
HCLK_I2S freq (from example is 100MHz) to set the i2s_div, it is
incorrect.
Change-Id: Iab69d541c47d1293a784ebffc23f6c1ceaf9c0b1
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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Change-Id: Ia5a0bf96609092c22f3bdb327cdfde6f505163c6
Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
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Change-Id: I1c3ccc7b896b4fe95f834a957a4ebe2aef482806
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
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Change-Id: Id0d722d90672f78941073a4ad7e45615893b1e90
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
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Change-Id: I05bb54c00019310fb57a0bc3fb0bd365aaed10dd
Signed-off-by: xubilv <xbl@rock-chips.com>
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Assign rates for aclk_bus and aclk_peri according to our original design.
Change-Id: Iab4961d485421151be5dbdacf6929800150ab342
Signed-off-by: Feng Xiao <xf@rock-chips.com>
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Change-Id: I1742823658aa46226e3112969d3eabc695921fb5
Signed-off-by: Feng Xiao <xf@rock-chips.com>
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For sheep board, we have decided to assign vop full for
use with HDMI. And we can also change it in the board
dts in the further.
Change-Id: Id966615c84cef50f0e8d849e3840434ba7f7b7ec
Signed-off-by: Feng Xiao <xf@rock-chips.com>
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