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path: root/arch/arm64/boot/dts/rockchip/rk3328.dtsi
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2019-02-20arm64: dts: rockchip: miss RK3328 WDT clockSimon Xue
Change-Id: I4df6373a3323ebf0fed74dddabc387164cd0aa5c Signed-off-by: Simon Xue <xxm@rock-chips.com>
2019-01-04arm64: dts: rockchip: add xhci trb ent quirk for rockchip SoCsWilliam Wu
This patch adds "snps,xhci-trb-ent-quirk" for DWC3 controllers in RK1808/RK3328/RK3399/RK3399pro-npu. Change-Id: I708f62747150316d66459f02b399d7c9b2667636 Signed-off-by: William Wu <william.wu@rock-chips.com>
2018-12-29arm64: dts: rockchip: Fix typo and remove deprecated property for rk3328Tony
clock-freq-min-max is deprecated, replacing with max-frequency. changing "ciu-drv" to "ciu-drive", appears to be a typo. Change-Id: I40218e6ea800aa983f22007e23e04e6364635dbe Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2018-12-29thermal: rockchip: add pinctrl controlElaine Zhang
Based on the TSADC Tshut mode to select pinctrl, instead of setting pinctrl based on architecture (Not depends on pinctrl setting by "init" or "default"). And it requires setting the tshut polarity before select pinctrl. Change-Id: Iac9ca05073b0181ee13b0048d0c2a54204f82bca Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-12-05arm64: dts: rockchip: add reset properties for i2sSugar Zhang
Change-Id: I1bdc5a417b412d484ba0caccc9e57da6a928de54 Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2018-11-23arm64: dts: rockchip: rk3328: initialize sleep_mode_configXiaoDong Huang
Change-Id: I7e54b5b4ba55a85f967a03bc990640c5d3bdf2e1 Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
2018-08-03ARM64: dts: rockchip: rk3328: assign dclk parents for vopAlgea Cao
Change-Id: Ie3a5d9dc9aad105deb2f7ac1d1d15494512d42f3 Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2018-08-02arm64: dts: rockchip: remove unused #dma-cells for rk3328Huibin Hong
Change-Id: I936f240665b5c905e0af41a3e9dd97e0b7379473 Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2018-07-06arm64: dts: rockchip: corrected clock-names for uart1 of rk3328Huibin Hong
Change-Id: I4f2f1265ba517b5effce0c1b4130d0eb10eae9e5 Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2018-06-21arm64: dts: rockchip: re-order the rk3328 aliaseRandy Li
Making those items in alphabetical order. Change-Id: I9d2cc45d814107a2bc9e15465b99b88109f23243 Signed-off-by: Randy Li <randy.li@rock-chips.com>
2018-06-06arm64: dts: rockchip: adjust opp-table by leakage for rk3328 SoCsLiang Chen
Change-Id: Ic827fe9f868a71e6f7a69f91df43d5f7a23bc5d3 Signed-off-by: Liang Chen <cl@rock-chips.com>
2018-06-04arm: dts: rockchip: thermal: update soc's sw/hw over temperature power off ↵Rocky Hao
degree to cope with Wide Temperature Range test, we maxamize soc's sw/hw over temperature power off degree. fow now, 115 degree Celsius is set to trigger sw powering off. if sw function does not work and temperature is continuing to grow up, and till 120 degree Celsius, hw powering off/reset is triggered. Change-Id: I751e9ea754f434bc20df39fdbdb40216a1582c39 Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
2018-05-21ARM64: dts: rockchip: rk3328: add the pwm0 and pwm1 pull up pinctrl interfaceHuang jianzhi
Change-Id: I2e21318a5863a020f104872c803ff2250b84fd7d Signed-off-by: Huang jianzhi <jesse.huang@rock-chips.com>
2018-04-27arm: dts: rockchip: Change cpu opp-microvolt form one entry to threeFinley Xiao
Single entry is for target voltage and three entries are for <target min max> voltages. Change cpu opp-microvolt form one entry to three entries and set maximum acceptable voltage to a high value so that regulator device can supply multiple consumers at the same time. Change-Id: I3a0dc4e161bae33e36b232c36a0a05a3102359ef Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-04-04arm64: dts: rockchip: reconfig dwc2 device fifo sizeWilliam Wu
According to the dwc2 programmer's guide v3.10a, in '2.1.3.2 Dedicated FIFO Mode with No Thresholding', it suggested that: Device RxFIFO = - Scatter/Gather DMA mode: (4 * number of control endpoints + 6) + ((largest USB packet used / 4) + 1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK on rockchip platforms: (4 * 1 + 6) + ((1024 / 4) + 1) + (2 * 6) + 1 = 280 - Slave or Buffer DMA mode: (5 * number of control endpoints + 8) + ((largest USB packet used / 4) + 1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK on rockchip platforms: (5 * 1 + 8) + ((1024 / 4) + 1) + (2 * 6) + 1 = 283 Device IN Endpoint TxFIFO = The TxFIFO must equal at least one MaxPacketSize (MPS). In addition to RxFIFO and TxFIFOs, refer to dwc2 databook v3.10a, 'Figure 2-13 Device Mode FIFO Address Mapping and AHB FIFO Access Mapping (Dedicated FIFO)', it required that when the device is operating in non Scatter Gather Internal DMA mode, the last locations of the SPRAM are used to store the DMAADDR values for each Endpoint (1 location per endpoint). When the device is operating in Scatter Gather mode, then the last locations of the SPRAM store the Base Descriptor address, Current Descriptor address, Current Buffer address, and status quadlet information for each endpoint direction (4 locations per Endpoint). If an Endpoint is bidirectional , then 4 locations will be used for IN, and another 4 for OUT). Considering that the total FIFO size of dwc2 otg is 0x3cc (972), and we must reserve (4 * 13) = 52 locations for all Endpoints. So reconfig dwc2 device fifo size as follows: Device RxFIFO = 280 Device IN Endpoint TxFIFO - FIFO #0 = (64 / 4) = 16 (Assuming this is used for EP0) - FIFO #1 = (1024/4) = 256 (Assuming this is used for Isochronous) - FIFO #2 = (512/4) = 128 - FIFO #3 = (512/4) = 128 - FIFO #4 = (256/4) = 64 - FIFO #5 = (128/4) = 32 - FIFO #6 = (64/4) = 16 After reconfig the dwc2 device fifo size, test mtp write on rockchip platform (PC -> rockchip platform) on rk312x/rk3326/px30/rk3288 evb, when mask the 'vfs_write' in f_mtp.c, the writing data rate can be increased from 16MBps ~ 20MBps to 30MBps ~ 36MBps on different kinds of rockchip evbs. Change-Id: I52c64a279523c811f706e69e427b0a6e8c45683b Signed-off-by: William Wu <william.wu@rock-chips.com>
2018-03-28arm64: dts: rockchip: fix dtc warnings of rk3328Tao Huang
Change-Id: I946c38d7dafe695b9ba1f73758e2ea8b07787610 Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-03-21arm64: dts: rockchip: add tsp support for rk3328Jerry Xu
Change-Id: I981d8fb53b44d79bc1a425b93699a30de6982dff Signed-off-by: Jerry Xu <xbl@rock-chips.com>
2018-03-19pwm: rockchip: Make pwm pinctrl setting after pwm enabledDavid Wu
If the PWM pinctrl uses default state, the iomux setting will be done at probe, the PWM may not be enabled at this moment. It will make PWM into an intermediate state, destroy the default hardware state, the PWM is not ready for work yet. So it is better for doing PWM pinctrl setting after PWM enabled. Change-Id: Iea34a7baf6a4d7df0c631f7f4fdab5b9d61bbd5f Signed-off-by: David Wu <david.wu@rock-chips.com>
2018-03-08arm64: dts: rockchip: rk3328: Disable 400MHz and 600MHz for dmcLiang Chen
400MHz and 600MHz aren't supported at present. This had submitted in commit a8c497e79d66 ("arm64: dts: rockchip: rk3328: Disable 400MHz and 600MHz for dmc") but was modified in commit 59af91b563d0 ("arm64: dts: rockchip: auto select opp-table by leakage for rk3328") by mistake. Change-Id: I864453d16596798e063a2c3569b260fd1a95c209 Signed-off-by: Liang Chen <cl@rock-chips.com>
2018-03-01arm64: dts: rockchip: rk3328: add clk define for vop iommuSandy Huang
Change-Id: I1f6a2ad41455046e3de90be3a6026ac0afa2490d Signed-off-by: Sandy Huang <hjc@rock-chips.com>
2018-02-28arm64: dts: rockchip: add sample/drv clk for sdmmc/ext for rk3328 chipXiao Yao
Change-Id: I2c00f2e461e283abbc18b426f5298490dee4bdfe Signed-off-by: Xiao Yao <xiaoyao@rock-chips.com>
2018-02-28arm64: dts: rockchip: fix clock name for sdmmc_ext for rk3328 chipXiao Yao
Change-Id: I915aed1122b41c3f766968ea8d74d98aa8bb22ed Signed-off-by: Xiao Yao <xiaoyao@rock-chips.com>
2018-02-28arm64: dts: rockchip: rk3328: add aclk&hclk for h265e_mmuXinhuang Li
Change-Id: I46bd3817219f80fddd097ec37e10a3a29209e21f Signed-off-by: Xinhuang Li <buluess.li@rock-chips.com>
2018-02-26arm64: dts: rockchip: rk3328: add sample/drv clock for hs200 modeXiao Yao
Change-Id: I8522515920b37cbfb9ec24ba7e65aee4f276e4a7 Signed-off-by: Xiao Yao <xiaoyao@rock-chips.com>
2018-02-24arm64: dts: rockchip: rk3328: Avoid showing blurred screenFinley Xiao
If show logo in uboot, can't change vop clocks. Change-Id: Ia149b452e16dedcafaa15bfa5d5dc989b06737ff Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-01-18arm64: dts: rockchip: rk3328: Add devfreq property for rkvdecFinley Xiao
Change-Id: I819a2c950b8b0a31207f85029c61c5efb5afe622 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-01-16arm64: dts: rockchip: rk3328: Add clocks for pd_vpu and pd_videoFinley Xiao
Change-Id: Ib90efd922c77da14e61a4ebd093fe0a173264cef Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-01-16arm64: dts: rk3328: add rockchip-suspend nodeXiaoDong Huang
Change-Id: Ie0758bf8d3a25696980edba5ba34ddd1e1034d95 Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
2018-01-12arm64: dts: rockchip: rk3328: add mclk for internal codecSugar Zhang
Change-Id: I3a29c25af0fa58f97f5dd8345b91df48f4f087ff Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2018-01-12arm64: dts: rockchip: rk3328: Add rkvdec and vpu qos nodeFinley Xiao
The rkvdec and vpu qos registers need to save and restore when reset. Change-Id: If0fbee0aed9227cfd795c5f439cfb8c3b2f0ccaf Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-01-10arm64: dts: rockchip: rk3328: add vpu_combo and enable itXinhuang Li
add vpu_combo consist of avsd and vdpu Change-Id: Ib49238d6a187dd7d621ad40ee0635b74825931f8 Signed-off-by: Xinhuang Li <buluess.li@rock-chips.com>
2018-01-09arm64: dts: rockchip: auto select opp-table by leakage for rk3328Liang Chen
Change-Id: I5807d47085291efcd8eea61e59e931615b283ba5 Signed-off-by: Liang Chen <cl@rock-chips.com>
2018-01-08arm64: dts: rockchip: rk3328: Disable 400MHz and 600MHz for dmcFinley Xiao
400MHz and 600MHz aren't supported at present. Change-Id: I2420866243bcf389c1f4ae68f322639986d3e41d Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-01-05arm64: dts: rockchip: add HDMI cec support for rk3328Algea Cao
Change-Id: I28a77d09a6cd21aff9099247594323b8bff595dc Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2018-01-05arm64: dts: rockchip: rk3328: add thermal control for dmcRocky Hao
add power model for dmc and add dmc as a cooling device in thermal control Change-Id: I175e503b671be27e777693745a127a7830c6e829 Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
2018-01-05arm64: dts: rockchip: rk3328: add thermal control for rkvdecRocky Hao
add power model for rkvdec and add rkvdec as a cooling device in thermal control Change-Id: I4560f9b2a6b395d565652549a8f0dbcc1903da6f Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
2018-01-04arm64: dts: rockchip: fix interrupts property of rk3328Tao Huang
Change-Id: I456a74303595c33ec66e9c2aa19af1f9b68155b2 Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-01-04arm64: dts: rockchip: rk3328: rename reset clock of rkvdecJung Zhao
Change-Id: Ie9ad47027f474b0b07f7c3979b5a83184ac5091a Signed-off-by: Jung Zhao <jung.zhao@rock-chips.com>
2018-01-02arm64: dts: rockchip: rk3328: Add 200M for rkvdecFinley Xiao
Add an intermediate opp so that rkvdec clock rate can be set to an intermediate rate when temperature is above the trip point. Change-Id: Ia94910185c708a501072c5da8aaebfcb206ad76b Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2017-12-28arm64: dts: rockchip: rk3328: Rename opp tableFinley Xiao
Change-Id: I0dbd1b71e2d57aa6c25fb6897253e0aae9d5966b Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2017-12-28arm64: dts: rockchip: add rk3328 ddr relate nodeHecanyang
except add note to existing dts file, also add ddr timing and de-skew's dts file. Change-Id: I92b7e9c2c6572babd4be00beadbbb75aae431707 Signed-off-by: CanYang He <hcy@rock-chips.com>
2017-12-26arm64: dts: rk3328: Add rkvdec_opp_tableFinley Xiao
Change-Id: I096e337f1c62f7ed18e760ea2ea93860199bfbc6 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2017-12-26arm64: dts: rockchip: rk3328: modify rkvdec compatibleJung Zhao
Change-Id: Icdaeb0d05e546c34e43a000aaa8a51f5e2e6a9fe Signed-off-by: Jung Zhao <jung.zhao@rock-chips.com>
2017-12-22arm64: dts: rockchip: rk3328: add iep and iep_mmu nodeXinhuang Li
Change-Id: I503c8e1e24240b20bc47a3e14591a27a756b950e Signed-off-by: Xinhuang Li <buluess.li@rock-chips.com>
2017-12-12arm64: dts: rk3328: fix string error for sdio 3.0xxh
Change-Id: Id2d63cf4c3edb645985265d06930bbc56f7bf66c Signed-off-by: Xu Xuehui <xxh@rock-chips.com>
2017-12-11arm64: dts: rockchip: rk3328: fix vepu clk define errorXinhuang Li
1.vepu aclk is ACLK_H264 and hclk is HCLK_H264 2.vepu need clk_core clk define 3.add h264&h265 power domain Change-Id: I419e544cf86d90b2b8d88dd13dfed49d31a24991 Signed-off-by: Xinhuang Li <buluess.li@rock-chips.com>
2017-12-07ARM64: dts: rockchip: add rga node for rk3328lihuang
Change-Id: I8bd8674e1ff43148daef60a296ae729da7480dad Signed-off-by: Putin Lee <putin.li@rock-chips.com>
2017-11-30arm64: dts: rockchip: rk3328: add firmware and optee nodeZhang Zhijie
Add optee node to supply OP-TEE required properties. /optee node is supposed to be below /firmware node. Change-Id: I5a55a8e62c741726b9c5c7cf33ca832d3cbae86b Signed-off-by: Zhang Zhijie <zhangzj@rock-chips.com>
2017-11-30arm64: dts: rockchip: rk3328: rename rksdmmc to dwmmcXinhuang Li
Change-Id: Ie70356eeff9c0064a7d1ef7b2d5dd092ee206ac5 Signed-off-by: Xinhuang Li <buluess.li@rock-chips.com>
2017-09-01ARM64: dts: rockchip: Add gmac2phy node support for rk3328David Wu
The gmac2phy controller of rk3328 is connected to integrated phy directly inside, add the node for the integrated phy support. Change-Id: Id96d65d838d17ae4912cf8fd80d0a1f2a2aa3bf7 Signed-off-by: David Wu <david.wu@rock-chips.com>
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