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path: root/arch/arm64/boot/dts/rockchip/rk1808.dtsi
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2019-03-20arm64: dts: rockchip: rk1808: Correct the drive strength for rgmii/rmiiDavid Wu
According to the hardware test, change the tx pin drive strength to 4ma, and mdc/mdio 2ma. Change-Id: Ia5ab1728c9e9ecbfa7207217649588f600070ae4 Signed-off-by: David Wu <david.wu@rock-chips.com>
2019-03-08arm64: dts: rockchip: modify io driver strength for rk1808Jianqun Xu
For rk1808 SoCs, set EMMC 4ma, SDMMC 8ma, SDIO 4ma. Change-Id: I217d10b16f901c257069829315b79f86ce54dab1 Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2019-03-08arm64: dts: rockchip: rk1808: assigned-clock-parents for clk_32k_ioeElaine Zhang
set 32k as input mode: assigned-clocks = <&cru SCLK_32K_IOE>; assigned-clock-parents = <&xin32k>; set 32k as output mode: assigned-clocks = <&cru SCLK_32K_IOE>; assigned-clock-parents = <&cru SCLK_RTC32K_PMU>; Change-Id: Iaebd0a8b8b882c42b800dd3fba9ff5a597c966ae Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2019-03-08soc: rockchip: Change the parameter of power model for cpu and npuFinley Xiao
Change-Id: I73724946fce82311d29de4538b8446e87d67dc92 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2019-02-25arm64: dts: rockchip: add soc_bus support for rk1808XiaoDong Huang
Change-Id: Ia7c4ac877f2758ca3da4d41603d6e47c68a164e6 Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
2019-02-15arm64: dts: rockchip: adjust opp-table for rk1808 SoCsLiang Chen
Auto select opp-table level by pvtm value. Change-Id: I6043bd768452c84290715428500e4f72068eac0d Signed-off-by: Liang Chen <cl@rock-chips.com>
2019-02-12arm64: dts: rockchip: rk1808: support cpu idleXiaoDong Huang
Change-Id: Ic72e2f01e81c0e8853b90158675092595973b94a Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
2019-01-21arm64: dts: rockchip: rk1808: add csi tx reset configSandy Huang
Change-Id: I99d390a24ad2f4c92789025e2a3abe5133c0d278 Signed-off-by: Sandy Huang <hjc@rock-chips.com>
2019-01-18arm64: dts: rockchip: rk1808 add csi host interruptWenlong Zhuang
Change-Id: Ic56e5052e244ffaa27456be6b8c5564fdbdb945b Signed-off-by: Wenlong Zhuang <daisen.zhuang@rock-chips.com>
2019-01-18arm64: dts: rockchip: rk1808: config RKPM_SLP_PMIC_LPXiaoDong Huang
Change-Id: I8797d4259d948cb684ac346ea8c9dd8b94fe7a70 Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
2019-01-11arm64: dts: rockchip: add efuse node and info for RK1808 SoCsLiang Chen
Change-Id: I5ab0c408e7db0cb12c002c3e52fd3ac57bcb5c21 Signed-off-by: Liang Chen <cl@rock-chips.com>
2019-01-04arm64: dts: rockchip: add xhci trb ent quirk for rockchip SoCsWilliam Wu
This patch adds "snps,xhci-trb-ent-quirk" for DWC3 controllers in RK1808/RK3328/RK3399/RK3399pro-npu. Change-Id: I708f62747150316d66459f02b399d7c9b2667636 Signed-off-by: William Wu <william.wu@rock-chips.com>
2018-12-24arm64: dts: rockchip: rk1808: add power-domains reference for PCIeSimon Xue
RK1808 PCIe share pd with others, add pd reference in case being turned off by others Change-Id: I899eb7524ae9aaada3cc161a63434113a3a1768e Signed-off-by: Simon Xue <xxm@rock-chips.com>
2018-12-19arm64: dts: rockchip: rk1808 add sfc nodeJianqun Xu
Change-Id: I123947fe6247837f080bcc0487484f66e4906de4 Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2018-12-14arm64: dts: rockchip: rk1808: add mi/mipi irq settingHu Kejun
Change-Id: I2025e6de06f0aec1e18289bf0eec8445d5a11820 Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
2018-12-14arm64: dts: rockchip: rk1808: Add missing inbound/outbound win numsSimon Xue
Change-Id: Ibd85ca71f7d6c87d0461eff2ba6dada6b0862040 Signed-off-by: Simon Xue <xxm@rock-chips.com>
2018-12-10arm64: dts: rockchip: Change the dr_mode from peripheral to otg for rk1808David.Wu
Use the driver to auto switch the host/peripheral mode for rk1808, so the dr_mode must be otg. Change-Id: I9b05e06bacd141d5fbd00a9751f2a12a4e4385c8 Signed-off-by: David.Wu <david.wu@rock-chips.com>
2018-12-10arm64: dts: rockchip: Add usbdrd3's compatible "rockchip,rk3399-dwc3" for rk1808David Wu
We will use the dwc3-rockchip driver for rk1808, this patch is prepared for it. Change-Id: I7ca8baefd26ea6c67140b757c47e14625cfed609 Signed-off-by: David Wu <david.wu@rock-chips.com>
2018-12-05arm64: dts: rockchip: Add 'rockchip,grf' property for i2s-tdmSugar Zhang
Change-Id: I42f461651f272c2c17ad08599b2b4d16e55b5ce5 Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2018-12-05arm64: dts: rockchip: add reset properties for i2sSugar Zhang
Change-Id: I1bdc5a417b412d484ba0caccc9e57da6a928de54 Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2018-11-30arm64: dts: rockchip: rk1808: add rockchip-suspend nodeXiaoDong Huang
Change-Id: I03281e58c2ebd2cc7af39dd204aa333e27d15520 Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
2018-11-21arm64: dts: rockchip: rk1808: Add pmugrf to pcie0 nodeSimon Xue
To avoid PRSTN being drived when PCIe is working,switch to PCIe_PRSTNm0 as a workaround. Change-Id: I094be7a873d0bff301792edea6929e1199cc52a2 Signed-off-by: Simon Xue <xxm@rock-chips.com>
2018-11-19arm64: dts: rockchip: sdmmc clk pin driver strength to 4mA for rk1808Jianqun Xu
According to signal test result, sdmmc 0/1 clk pin driver strength need to be 4mA. Change-Id: Ifbd0515bcebe19423c4b110392c8ff8307431a23 Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2018-11-16arm64: dts: rockchip: add rk1808 ddr relate nodeYouMin Chen
Change-Id: I06c40f6c5e2832f79626c3438bed74fbb0551c86 Signed-off-by: YouMin Chen <cym@rock-chips.com>
2018-11-15arm64: dts: rockchip: rk1808: add cif iomux and grf to ispCai YiWei
Change-Id: I95f68b5151c76579a88d0ea743e97e55efad29af Signed-off-by: Cai YiWei <cyw@rock-chips.com>
2018-11-13arm64: dts: rockchip: Add thermal thermal zone node for rk1808Finley Xiao
Change-Id: Ie42fcef7d94829aeb056ac1ead3d5885fc1a30f8 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-11-13arm64: dts: rockchip: rk1808: Add #cooling-cells to npu nodeFinley Xiao
Change-Id: Ia6fa02863f93d460c0c7d29e7601e97f3bd5dfea Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-11-13arm64: dts: rockchip: rk1808: Add power-model for npuFinley Xiao
Change-Id: I1dfca356a128b43a7790efebb34d731ce443326b Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-11-13arm64: dts: rockchip: rk1808: Add #cooling-cells to CPU nodeFinley Xiao
Change-Id: I75e6312f7da7d6dbded29430f7479bdd6a790bfc Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-11-13arm64: dts: rockchip: rk1808: Add dynamic-power-coefficient for cpuFinley Xiao
The average value of dynamic-power-coefficient is about 74. Change-Id: I71906da6bd024022b4b64c4dd4fb9f03182fd4e8 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-11-12arm64: dts: rockchip: rk1808: Add missing num-lanesShawn Lin
Change-Id: I2eb37320c964fb031a6809f4bae30c69d356d4bc Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
2018-11-12arm64: dts: rockchip: rk1808: Add usb_pcie_grf to pcie0 nodeShawn Lin
The PCIe driver need configure some bits after passing link trainning, which belongs to the controller driver part but can not make use of PHY API. Change-Id: I8c3d5f8a25de6184bee572c7c954c9f3d9df20c2 Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
2018-11-07arm64: dts: rockchip: rk1808: fix up the pd_pcie qos nodeElaine Zhang
add usb2 and usb3 qos node, set qos_pcie\qos_usb2\qos_usb3 status = "disabled" by default. Change-Id: I307be4138c04c3bea5ae779ed85a9a4d2420ad0a Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-11-07arm64: dts: rockchip: rk1808: Add PCIe supportShawn Lin
This patch adds PCIe support for rk1808 Soc in EP mode. Change-Id: I5305d7b5ba7a2f087f64df8102c95926e73a7940 Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
2018-11-02arm64: dts: rockchip: add cif device node for rk1808Wenlong Zhuang
Change-Id: I7d6201f7fa68e6228ec25bb4a11378cbe9a25f08 Signed-off-by: Wenlong Zhuang <daisen.zhuang@rock-chips.com>
2018-11-02arm64: dts: rockchip: rk1808: add dts of rkisp1Hu Kejun
Change-Id: Ida396c224318e1ad223782ef5becc830521d86be Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
2018-11-01arm64: dts: rockchip: Change the drive strength of spi pins to 2ma for rk1808David Wu
Change-Id: Ide1e6aa0fcd18e7927c1a3adaf4da17e827b526f Signed-off-by: David Wu <david.wu@rock-chips.com>
2018-10-31arm64: dts: rockchip: rk1808: Change tsadc clock rate to 650KHzFinley Xiao
The clock frequency should be between 500KHz and 800KHz, 650KHz is a typical value. Change-Id: Id8a81f667350747576f803ce5259b4e09076be89 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-10-31arm64: dts: rockchip: parse usb_pcie_grf for combphy driver for rk1808Shawn Lin
Innosilicon combphy need release link reset grant when finishing PLL lock, so we need the driver to control usb_pcie_grf. Change-Id: If429629b39d1f68a0fdcb24c6b639f84d513aee5 Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
2018-10-30arm64: dts: rockchip: rk1808: Add opp table for npuFinley Xiao
Change-Id: I6e4df5f1591d988ebba6a8181c60b60acb50e254 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-10-30arm64: dts: rockchip: set npu frequency to 800MHz for RK1808Fei Zeng
Change-Id: Icadb6bc3e26b3b5a5b1453a9927b7c71ac9edad8 Signed-off-by: Fei Zeng <felix.zeng@rock-chips.com>
2018-10-26arm64: dts: rockchip: rk1808: modify ppll init freq to 100MElaine Zhang
Change-Id: I95f4281ad36538dc260fd06010d5e373e0064f89 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-10-26arm64: dts: rockchip: rk1808: set 2ma drive-strength for i2s, pdmSugar Zhang
Change-Id: I1ba20c8d996ba596161e6c359db255a8b0ba24d5 Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2018-10-26arm64: dts: rockchip: Change the drive strength of pwm pins to 2ma for rk1808David Wu
Change-Id: I3caf418c8edcfdf03ea8c1e042276eb4f6f75816 Signed-off-by: David Wu <david.wu@rock-chips.com>
2018-10-26arm64: dts: rockchip: Change the drive strength of i2c pins to 2ma for rk1808David Wu
Change-Id: I6dc59e0262b0306b0f3fb1629ef77d02fa831524 Signed-off-by: David Wu <david.wu@rock-chips.com>
2018-10-23arm64: dts: rockchip: add dis-u1u2-quirk for rk1808 dwc3William Wu
Change-Id: I61460bccc63e6d8cecabe4f4e6259096f069aa23 Signed-off-by: William Wu <william.wu@rock-chips.com>
2018-10-23arm64: dts: rockchip: enable power domain for rk1808 dwc3William Wu
Change-Id: Ia18a03b3c68b560ee4c5e47a4a82f11b786c8964 Signed-off-by: William Wu <william.wu@rock-chips.com>
2018-10-22arm64: dts: rockchip: add snps,dis_u3_susphy_quirk for rk1808 dwc3William Wu
Add a quirk to avoid USB 3.0 PHY enter suspend mode when the dwc3 controller suspend conditions are valid, it can help to fix the dwc3 initialization error issue with the following log: dwc3 fd000000.dwc3: failed to enable ep0out Change-Id: Iedcb9fa6c2c7fe923839362e35267fedb55889a7 Signed-off-by: William Wu <william.wu@rock-chips.com>
2018-10-22arm64: dts: rockchip: support usb3 phy for rk1808 dwc3William Wu
The combphy which supports PCIe/USB3.0 on rk1808 has been enabled, so we can used it as usb3-phy for DWC3 controller by default. Change-Id: I106885eb79621b40214bc2ebac43d8f87ac63687 Signed-off-by: William Wu <william.wu@rock-chips.com>
2018-10-22arm64: dts: rockchip: set usb3 suspend_clk to 24MHz for rk1808William Wu
The default clock frequency of usb3 suspend_clk is 32KHz, this patch sets the clock frequency to 24MHz which from the xin24m parent. Change-Id: Ia516a0d7b6c69b87a1ad6c69c421504477e18742 Signed-off-by: William Wu <william.wu@rock-chips.com>
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