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path: root/arch/arm64/boot/dts/rockchip/px30.dtsi
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2019-03-12arm64: dts: rockchip: px30: add reset properties for watchdogZiyuan Xu
Change-Id: I83a7762c23a4caaa5d3d3cd5e8e79b288f8662b4 Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2019-03-04arm64: dts: rockchip: px30: Add the I2C clock signal strengthWu Jingchen
Change-Id: I80553627d258e54739af328f01fbacf550da8e5e Signed-off-by: Wu Jingchen <oven.wu@rock-chips.com>
2019-01-18arm64: dts: rockchip: px30: add wide temperature configWeixin Zhou
Change-Id: I99af054eb795ac396f024595c83783669bef101d Signed-off-by: Weixin Zhou <zwx@rock-chips.com> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-12-29arm64: dts: rockchip: px30: Add support for video phyWyon Bi
Change-Id: Icfc90340972646a58b0ff6137a63d474d1171191 Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
2018-12-14arm64: dts: rockchip: px30: add mi/mipi irq settingHu Kejun
Change-Id: I2146d37c18d8418b32cf13736ecccb0510a851d9 Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
2018-12-05arm64: dts: rockchip: Add 'rockchip,grf' property for i2s-tdmSugar Zhang
Change-Id: I42f461651f272c2c17ad08599b2b4d16e55b5ce5 Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2018-12-05arm64: dts: rockchip: add reset properties for i2sSugar Zhang
Change-Id: I1bdc5a417b412d484ba0caccc9e57da6a928de54 Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2018-11-23arm64: dts: rockchip: px30: add grf for rkisp1Hu Kejun
when connect to dvp camera, we need grf to config cif data width Change-Id: I798d841149e1fd9f7c3fb58bd39d1706bf85ee5d Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
2018-09-26arm64: dts: rockchip: px30: drop incompatible name for i2s0_8chSugar Zhang
Change-Id: Iee0ef921389a8cddf908896785370fd75f138ec8 Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2018-08-29arm64: dts: rockchip: px30: Add boost configFinley Xiao
Change-Id: I2f82059b0b67eaa17aa94fbfc1b318d480228138 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-08-22arm64: dts: rockchip: Remove initial rate of npll for px30Finley Xiao
As npll rate may be changed when enable vopl in uboot, so we can't change npll rate in kernel on px30. Change-Id: If62da5bb77cdd411a550b2dc6250d654134474e3 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-08-08arm64: dts: rockchip: adjust opp-table by pvtm for px30/rk3326Liang Chen
Change-Id: If01552784deb6e3a2d51146fe6e05216e316c132 Signed-off-by: Liang Chen <cl@rock-chips.com>
2018-08-02arm64: dts: rockchip: remove unused #dma-cells for px30Huibin Hong
Change-Id: Ibb85ffe525246285e54bb034b8acbf66025516ba Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2018-07-31arm64: dts: rockchip: Assign nandc, emmc, sdio and sdmmc clock to DIV50 for px30Finley Xiao
Change-Id: Iebfe0235c01f0b4c7093f1c9ef3aafe2fc2a2041 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-07-23ARM64: dts: rockchip: add a new cif node for px30Cai YiWei
Change-Id: Ibfe9412ebaaede23168c1afe0104fad32a9d7882 Signed-off-by: Cai YiWei <cyw@rock-chips.com>
2018-07-06soc: rockchip: opp_select: Use 'rockchip,thermal-zone' property for pvtmFinley Xiao
Make the property more general. Change-Id: Ieacbaccdc008ff8cee51ebfafc203b3200a1c5af Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-06-25arm64: dts: rockchip: px30: Change armclk rate to 600MHzFinley Xiao
The initial voltage may be too low for 816MHz and it is enough for 600MHz. And as the alternate pll clock of armclk is created when pmucru driver initialize, so move ARMCLK to pmucru node. Change-Id: I1f443d55c74e5212a19e42e08b54ec946b4692d6 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-06-21ARM64: dts: rockchip: re-order the px30 aliasesRandy Li
Making those items in alphabetical order. Change-Id: I2abb29eaed4b5fc970f46dc382e0e82fbf6062d6 Signed-off-by: Randy Li <randy.li@rock-chips.com>
2018-06-13arm64: dts: rockchip: px30: Add resets property for otpFinley Xiao
Change-Id: Iaba6d95674ae461e9ade4521e955869ff1dcc5c8 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-06-04arm: dts: rockchip: thermal: update soc's sw/hw over temperature power off ↵Rocky Hao
degree to cope with Wide Temperature Range test, we maxamize soc's sw/hw over temperature power off degree. fow now, 115 degree Celsius is set to trigger sw powering off. if sw function does not work and temperature is continuing to grow up, and till 120 degree Celsius, hw powering off/reset is triggered. Change-Id: I751e9ea754f434bc20df39fdbdb40216a1582c39 Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
2018-06-01soc: rockchip: opp_select: Add support to adjust power scaleFinley Xiao
Change-Id: I2358d75c2fdada7cfe385e85d2106370f9aa5ea3 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-06-01arm64: dts: rockchip: px30: disable bus0 auto divXiaoDong Huang
Change-Id: Ie96ad61d3069c8045b26c08f336e63c2d4f68fef Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
2018-06-01Revert "arm64: dts: rockchip: px30: disable cpu CLUSTER_SLEEP"XiaoDong Huang
This reverts commit 3a13a2ae5203244fd688a0e6fdf8c31a0a0ca513. Change-Id: I2e02f350ffb9b1b39cd21786b3683622729b2ec8 Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
2018-05-31arm64: dts: rockchip: px30: Add bus_apll device nodeFinley Xiao
Change-Id: I6f2ea99e58069962bd04461b959d208c8453f42b Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-05-23arm64: dts: rockchip: px30: add cpuinfoBinyuan Lan
Change-Id: Ib9819736fb67ca6f8de31c847f13c660f6bcba96 Signed-off-by: Binyuan Lan <lby@rock-chips.com>
2018-05-22arm64: dts: rockchip: adjust opp-table by pvtm for px30/rk3326Liang Chen
Change-Id: I0d72c313a484611ca20c0b39b21ce6d3ed85d7d4 Signed-off-by: Liang Chen <cl@rock-chips.com>
2018-05-14arm64: dts: rockchip: px30: add reset control for i2s0_8chSugar Zhang
Change-Id: I6fb0224f36ade0701c3c0561b996cfdf99379030 Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2018-05-11arm64: dts: rockchip: px30: add reset control for pdmSugar Zhang
Change-Id: I7381a0436f0946efd8662218b1ef795bac3b048c Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2018-05-11arm64: dts: rockchip: px30: Add cpu boost device nodeFinley Xiao
Change-Id: I3b7e37238fad55e7d300f47db937d20a177fe894 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-05-09arm64: dts: rockchip: px30: Assign sclk_gpu to 200MHzFinley Xiao
Change-Id: If6c6ef0a739e681564e7702f327f563c0745c89a Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-05-04arm64: dts: rockchip: px30: fixup i2s0 nodeSugar Zhang
Change-Id: Ibf4f59d2f85dad9e7343d9d02c723891a5b7adbd Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2018-05-03arm64: dts: rockchip: px30: disable cpu CLUSTER_SLEEPXiaoDong Huang
Change-Id: I240d47f2c8f665af9d2b4c0cc87bf70ecd420bc4 Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
2018-05-03arm64: dts: rockchip: add soc_bus support for px30.Tony Xie
Change-Id: I22c0865b2624c43e2b338dd055c266b4562c8213 Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
2018-04-28arm64: dts: rockchip: px30: dmc set SYS_STATUS_ISPWu Liangqing
Change-Id: Ib0c9b3ac6ec85aa7e05c1c7389e644d0bca4ffc8 Signed-off-by: Wu Liangqing <wlq@rock-chips.com>
2018-04-27arm: dts: rockchip: Change cpu opp-microvolt form one entry to threeFinley Xiao
Single entry is for target voltage and three entries are for <target min max> voltages. Change cpu opp-microvolt form one entry to three entries and set maximum acceptable voltage to a high value so that regulator device can supply multiple consumers at the same time. Change-Id: I3a0dc4e161bae33e36b232c36a0a05a3102359ef Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-04-26arm64: dts: rockchip: px30: modify voltage for gpu 200MHz and 300MhzFinley Xiao
Change-Id: Ifbd3117d3999b322951df458a12cfe488954803d Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-04-26arm64: dts: rockchip: Enable dmc for px30/rk3326Liang Chen
Change-Id: I47c08b9fcd12c21c3cc4731617ebfe4331a0ac72 Signed-off-by: Liang Chen <cl@rock-chips.com> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-04-26arm64: dts: rockchip: support complete_irq in dmc node for px30.Tony Xie
Change-Id: I99e474f323cf57a15e1ed7431bafe3514aedc603 Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
2018-04-19arm: dts: rockchip: add grf reference for vopSandy Huang
add grf reference for rk3288,rk3368,px30 vop Change-Id: I89b620b2df45f83bdfc36dd64168107beee9b9fb Signed-off-by: Sandy Huang <hjc@rock-chips.com>
2018-04-19arm64: dts: rockchip: update pinctrl for px30Rocky Hao
1 move pinctrl into board level dts file. 2 remove pinctrl for sleep state. in sleep state we do not change pin control and keep the pin control in otp state, which is used by atf as a flag to control pmic's state. Change-Id: Ib68b20d4f4ba79d99255f1deb509ff8a741deef2 Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
2018-04-11arm64: dts: rockchip: add dts of rkisp1 for rk3326Hu Kejun
Change-Id: I0e6fe49d8560aee7404e9685f9356978b7148c7a Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
2018-04-04arm64: dts: rockchip: reconfig dwc2 device fifo sizeWilliam Wu
According to the dwc2 programmer's guide v3.10a, in '2.1.3.2 Dedicated FIFO Mode with No Thresholding', it suggested that: Device RxFIFO = - Scatter/Gather DMA mode: (4 * number of control endpoints + 6) + ((largest USB packet used / 4) + 1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK on rockchip platforms: (4 * 1 + 6) + ((1024 / 4) + 1) + (2 * 6) + 1 = 280 - Slave or Buffer DMA mode: (5 * number of control endpoints + 8) + ((largest USB packet used / 4) + 1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK on rockchip platforms: (5 * 1 + 8) + ((1024 / 4) + 1) + (2 * 6) + 1 = 283 Device IN Endpoint TxFIFO = The TxFIFO must equal at least one MaxPacketSize (MPS). In addition to RxFIFO and TxFIFOs, refer to dwc2 databook v3.10a, 'Figure 2-13 Device Mode FIFO Address Mapping and AHB FIFO Access Mapping (Dedicated FIFO)', it required that when the device is operating in non Scatter Gather Internal DMA mode, the last locations of the SPRAM are used to store the DMAADDR values for each Endpoint (1 location per endpoint). When the device is operating in Scatter Gather mode, then the last locations of the SPRAM store the Base Descriptor address, Current Descriptor address, Current Buffer address, and status quadlet information for each endpoint direction (4 locations per Endpoint). If an Endpoint is bidirectional , then 4 locations will be used for IN, and another 4 for OUT). Considering that the total FIFO size of dwc2 otg is 0x3cc (972), and we must reserve (4 * 13) = 52 locations for all Endpoints. So reconfig dwc2 device fifo size as follows: Device RxFIFO = 280 Device IN Endpoint TxFIFO - FIFO #0 = (64 / 4) = 16 (Assuming this is used for EP0) - FIFO #1 = (1024/4) = 256 (Assuming this is used for Isochronous) - FIFO #2 = (512/4) = 128 - FIFO #3 = (512/4) = 128 - FIFO #4 = (256/4) = 64 - FIFO #5 = (128/4) = 32 - FIFO #6 = (64/4) = 16 After reconfig the dwc2 device fifo size, test mtp write on rockchip platform (PC -> rockchip platform) on rk312x/rk3326/px30/rk3288 evb, when mask the 'vfs_write' in f_mtp.c, the writing data rate can be increased from 16MBps ~ 20MBps to 30MBps ~ 36MBps on different kinds of rockchip evbs. Change-Id: I52c64a279523c811f706e69e427b0a6e8c45683b Signed-off-by: William Wu <william.wu@rock-chips.com>
2018-04-03arm64: dts: rockchip: adjust dmc opp-table for px30Tony Xie
Change-Id: I3c51f94fbb5bac52553e38c699b4355d5f8f7518 Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
2018-04-02arm64: dts: rockchip: px30: Add SYS_STATUS_BOOST status for dmcFinley Xiao
Change-Id: Id7096f0b558697101fd1ed6bcf72fec92c9ce7f2 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-03-28arm64: dts: rockchip: fix dtc warnings of px30Tao Huang
Change-Id: Ie01bb2c17ec9ab4310278ace31ad25830847a74b Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-03-24arm64: dts: rockchip: fix rktimer irq for px30Tao Huang
Fixes: fd769fde5b4c ("arm64: dts: px30: support cpu/cluster idle") Change-Id: I1e95e21fa0304fe87ef7adba238e41294c5429cb Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-03-23arm64: dts: px30: support cpu/cluster idleXiaoDong Huang
Change-Id: I41b08eb568471dcf1537cb7afa637bdf6a7df2c8 Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
2018-03-22arm64: dts: rockchip: add spi aliase for px30Huibin Hong
Change-Id: I9b833d7d6a91d18a422bd2682bfc4ec4c4a9457c Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2018-03-22arm64: dts: rockchip: px30: add rgb nodeWyon Bi
Change-Id: I3bc1bd408bd97dcd18293efc258635d1f68766b3 Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
2018-03-20arm64: dts: rockchip: adjust opp-table and IR-Drop for px30/rk3326Liang Chen
Change-Id: I266078b219edc60b27cea547462cad886e3af1bb Signed-off-by: Liang Chen <cl@rock-chips.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-03 12:57:07 +0000