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path: root/arch/arm64/boot/dts/rockchip/px30.dtsi
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2018-04-27arm: dts: rockchip: Change cpu opp-microvolt form one entry to threeFinley Xiao
Single entry is for target voltage and three entries are for <target min max> voltages. Change cpu opp-microvolt form one entry to three entries and set maximum acceptable voltage to a high value so that regulator device can supply multiple consumers at the same time. Change-Id: I3a0dc4e161bae33e36b232c36a0a05a3102359ef Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-04-26arm64: dts: rockchip: px30: modify voltage for gpu 200MHz and 300MhzFinley Xiao
Change-Id: Ifbd3117d3999b322951df458a12cfe488954803d Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-04-26arm64: dts: rockchip: Enable dmc for px30/rk3326Liang Chen
Change-Id: I47c08b9fcd12c21c3cc4731617ebfe4331a0ac72 Signed-off-by: Liang Chen <cl@rock-chips.com> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-04-26arm64: dts: rockchip: support complete_irq in dmc node for px30.Tony Xie
Change-Id: I99e474f323cf57a15e1ed7431bafe3514aedc603 Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
2018-04-19arm: dts: rockchip: add grf reference for vopSandy Huang
add grf reference for rk3288,rk3368,px30 vop Change-Id: I89b620b2df45f83bdfc36dd64168107beee9b9fb Signed-off-by: Sandy Huang <hjc@rock-chips.com>
2018-04-19arm64: dts: rockchip: update pinctrl for px30Rocky Hao
1 move pinctrl into board level dts file. 2 remove pinctrl for sleep state. in sleep state we do not change pin control and keep the pin control in otp state, which is used by atf as a flag to control pmic's state. Change-Id: Ib68b20d4f4ba79d99255f1deb509ff8a741deef2 Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
2018-04-11arm64: dts: rockchip: add dts of rkisp1 for rk3326Hu Kejun
Change-Id: I0e6fe49d8560aee7404e9685f9356978b7148c7a Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
2018-04-04arm64: dts: rockchip: reconfig dwc2 device fifo sizeWilliam Wu
According to the dwc2 programmer's guide v3.10a, in '2.1.3.2 Dedicated FIFO Mode with No Thresholding', it suggested that: Device RxFIFO = - Scatter/Gather DMA mode: (4 * number of control endpoints + 6) + ((largest USB packet used / 4) + 1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK on rockchip platforms: (4 * 1 + 6) + ((1024 / 4) + 1) + (2 * 6) + 1 = 280 - Slave or Buffer DMA mode: (5 * number of control endpoints + 8) + ((largest USB packet used / 4) + 1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK on rockchip platforms: (5 * 1 + 8) + ((1024 / 4) + 1) + (2 * 6) + 1 = 283 Device IN Endpoint TxFIFO = The TxFIFO must equal at least one MaxPacketSize (MPS). In addition to RxFIFO and TxFIFOs, refer to dwc2 databook v3.10a, 'Figure 2-13 Device Mode FIFO Address Mapping and AHB FIFO Access Mapping (Dedicated FIFO)', it required that when the device is operating in non Scatter Gather Internal DMA mode, the last locations of the SPRAM are used to store the DMAADDR values for each Endpoint (1 location per endpoint). When the device is operating in Scatter Gather mode, then the last locations of the SPRAM store the Base Descriptor address, Current Descriptor address, Current Buffer address, and status quadlet information for each endpoint direction (4 locations per Endpoint). If an Endpoint is bidirectional , then 4 locations will be used for IN, and another 4 for OUT). Considering that the total FIFO size of dwc2 otg is 0x3cc (972), and we must reserve (4 * 13) = 52 locations for all Endpoints. So reconfig dwc2 device fifo size as follows: Device RxFIFO = 280 Device IN Endpoint TxFIFO - FIFO #0 = (64 / 4) = 16 (Assuming this is used for EP0) - FIFO #1 = (1024/4) = 256 (Assuming this is used for Isochronous) - FIFO #2 = (512/4) = 128 - FIFO #3 = (512/4) = 128 - FIFO #4 = (256/4) = 64 - FIFO #5 = (128/4) = 32 - FIFO #6 = (64/4) = 16 After reconfig the dwc2 device fifo size, test mtp write on rockchip platform (PC -> rockchip platform) on rk312x/rk3326/px30/rk3288 evb, when mask the 'vfs_write' in f_mtp.c, the writing data rate can be increased from 16MBps ~ 20MBps to 30MBps ~ 36MBps on different kinds of rockchip evbs. Change-Id: I52c64a279523c811f706e69e427b0a6e8c45683b Signed-off-by: William Wu <william.wu@rock-chips.com>
2018-04-03arm64: dts: rockchip: adjust dmc opp-table for px30Tony Xie
Change-Id: I3c51f94fbb5bac52553e38c699b4355d5f8f7518 Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
2018-04-02arm64: dts: rockchip: px30: Add SYS_STATUS_BOOST status for dmcFinley Xiao
Change-Id: Id7096f0b558697101fd1ed6bcf72fec92c9ce7f2 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-03-28arm64: dts: rockchip: fix dtc warnings of px30Tao Huang
Change-Id: Ie01bb2c17ec9ab4310278ace31ad25830847a74b Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-03-24arm64: dts: rockchip: fix rktimer irq for px30Tao Huang
Fixes: fd769fde5b4c ("arm64: dts: px30: support cpu/cluster idle") Change-Id: I1e95e21fa0304fe87ef7adba238e41294c5429cb Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-03-23arm64: dts: px30: support cpu/cluster idleXiaoDong Huang
Change-Id: I41b08eb568471dcf1537cb7afa637bdf6a7df2c8 Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
2018-03-22arm64: dts: rockchip: add spi aliase for px30Huibin Hong
Change-Id: I9b833d7d6a91d18a422bd2682bfc4ec4c4a9457c Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2018-03-22arm64: dts: rockchip: px30: add rgb nodeWyon Bi
Change-Id: I3bc1bd408bd97dcd18293efc258635d1f68766b3 Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
2018-03-20arm64: dts: rockchip: adjust opp-table and IR-Drop for px30/rk3326Liang Chen
Change-Id: I266078b219edc60b27cea547462cad886e3af1bb Signed-off-by: Liang Chen <cl@rock-chips.com>
2018-03-19pwm: rockchip: Make pwm pinctrl setting after pwm enabledDavid Wu
If the PWM pinctrl uses default state, the iomux setting will be done at probe, the PWM may not be enabled at this moment. It will make PWM into an intermediate state, destroy the default hardware state, the PWM is not ready for work yet. So it is better for doing PWM pinctrl setting after PWM enabled. Change-Id: Iea34a7baf6a4d7df0c631f7f4fdab5b9d61bbd5f Signed-off-by: David Wu <david.wu@rock-chips.com>
2018-03-19arm64: dts: rockchip: add cif data pin combinations for px30Zhang Yunlong
Change-Id: Ia1d81e1e6450cfc9c13c775ac6ed5d70613ee90e Signed-off-by: Zhang Yunlong <dalon.zhang@rock-chips.com>
2018-03-12arm64: dts: rockchip: px30: add rockchip-suspend nodeXiaoDong Huang
Change-Id: Iac7fdbcf6ede75d8a987c8c618bce4ebc4f536cc Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
2018-03-09arm64: dts: rockchip: px30: set default driver strength for lcdc pinsWyon Bi
Change-Id: I9b2b158576d43f4674922555ce7426bd6f3a82fd Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
2018-03-08arm64: dts: rockchip: px30: Add 12ma strength for rmii mac_refclk pinDavid Wu
If the mac_refclk is provided from mac controller, the pin of mac_refclk needs to setup 12ma strength, or the signal is not good. If the mac_refclk is provided from phy, the pin of mac_refclk needs not to setup 12ma strength, the phy would do it. Change-Id: I4f6e6d081b4616363d10358c9e36d71cacbdb134 Signed-off-by: David Wu <david.wu@rock-chips.com>
2018-03-07arm64: dts: rockchip: px30: Enable pvtmFinley Xiao
Change-Id: Ib2a0fe5bc2a9e80ea48d35fe526a9efe5df586e7 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-03-05arm64: dts: rockchip: px30: modify error of EHCI and OHCI DTMeng Dongyang
Modify the clock name of EHCI and OHCI controllers, add property of "status" for OHCI. Change-Id: I444a906bc26e26989f5f6011de949b816266b9c6 Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
2018-03-05arm64: dts: rockchip: Assign SCLK_UART1_SRC to USB480M fox px30Finley Xiao
Change-Id: Iab1c8af4289cf0767910d6301689ea52a4195067 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-03-05arm64: dts: rockchip: spi pinctrl-1 with 8ma driver strength for px30Huibin Hong
Change-Id: I8e8298e5f37e56585815a29fc0bf46f3a31ff334 Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2018-02-27arm64: rockchip: px30: Remove the initial value of PLL_CPLL and BOOSTFinley Xiao
If show logo in uboot, can't change vop clocks. Change-Id: I84fc1138b54b1c7b3c798f1bc4fb7d0f332e6895 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-02-26arm64: dts: rockchip: adjust cpu and gpu opp table for px30Liang Chen
Change-Id: I8951348731463a7614ac6f320af16222cd7fe212 Signed-off-by: Liang Chen <cl@rock-chips.com>
2018-02-26arm64: dts: rockchip: Enable SD/SDIO 3.0 for PX30/RK3326 boardsShawn Lin
This patch enables SD(IO) 3.0 for all boards by adding correct vccq and vcc power supplies, as well as properities required by UHS-I mode. Change-Id: Iec11e1d1abe7ef9fc17ba08eece3440d7dcaea0b Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
2018-02-26arm64: dts: rockchip: px30: Add nvmem-cells property for cpuFinley Xiao
Change-Id: I0f23f780fb6fc42b7599d38e1d1213e1ab116210 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-02-26arm64: dts: rockchip: px30: Add otp nodeFinley Xiao
Change-Id: I5a1ed87e9fef7346e2f268fc9a2a33cd6d192c69 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-02-24arm64: dts: rockchip: add cpu's and gpu's thermal config for px30Rocky Hao
add power model for gpu and also add cpu thermal config Change-Id: Iab5ef69b50c792b35c9ae5ffa863cc106d2c4292 Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
2018-02-24arm64: dts: rockchip: enable uart rx pull up for px30Huibin Hong
Change-Id: I533b18babbc1c153b1b61afdbbcd510eb9286dc1 Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2018-02-24arm64: dts: rockchip: Add gmac_clkin fixed clock for gmac usage for px30David Wu
Change-Id: Ibb155666235c609603e0a89316398c3aeb303805 Signed-off-by: David Wu <david.wu@rock-chips.com>
2018-02-13arm64: dts: rockchip: px30: xin32k use the fixed clkFinley Xiao
If xin32k use the rk808_clkout1, rk808 init is too late, xin32k enable count and prepare count is not match with it's child clk. Change-Id: Iec5d1f91b2289b18f41b4d915e6859154a5b7635 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-02-13arm64: dts: rockchip: px30: Change clock id for gpuFinley Xiao
Change-Id: I04ccacc3f60c7a1e4b0fa854680564963ec110fd Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-02-11arm64: dts: rockchip: px30: fixup pdm pinctrlSugar Zhang
Change-Id: I5a3978a486c63dae718b46be142eed263788e5f3 Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2018-02-10arm64: dts: rockchip: px30: modify isp mipiphy count from 0 to 1Zhong Yichong
Change-Id: I878c8b6ee15885662c215b52143cd73474dd8cbf Signed-off-by: Zhong Yichong <zyc@rock-chips.com>
2018-02-10arm64: dts: rockchip: px30: modify the isp reg rangeZhong Yichong
Change-Id: I3326908e0445c1230b73169b9d9b34a31658d0b2 Signed-off-by: Zhong Yichong <zyc@rock-chips.com>
2018-02-09arm64: dts: rockchip: add uart aliases, modify uart1 clk for px30Huibin Hong
Change-Id: Ia1accabbb76c1f1e4deb11aae055bec328ec5a61 Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2018-02-09arm64: dts: rockchip: add spi1 cs1 for px30Huibin Hong
Change-Id: I933b76ed4b312a713e390c130ef6b5c090e3779c Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2018-02-09arm64: dts: rockchip: Change the pinctrl name sdmmc0 to sdmmc for px30David Wu
Change-Id: I57a4d732337fcf4356234e58658dd82655e53751 Signed-off-by: David Wu <david.wu@rock-chips.com>
2018-02-09arm64: dts: rockchip: px30: Add sdmmc iomuxZhou weixin
Change-Id: I3debec6ca7010d2e15f1302d3403852a951da768 Signed-off-by: Weixin Zhou <zwx@rock-chips.com>
2018-02-09arm64: dts: rockchip: Remove unused sdmmc1 pinctrl for px30David Wu
1. remove sdmmc1 pinctrl 2. move sdio pinctrl to sdmmc together Change-Id: Ibcde69298cfdfdd99228de941082cde6be6dfa6b Signed-off-by: David Wu <david.wu@rock-chips.com>
2018-02-09arm64: dts: rockchip: px30: Change bus and peri to sign off frequencyFinley Xiao
Change-Id: Ie40eb2610b277b1f7e257fdd6e8f578373b0294e Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-02-08arm64: dts: rockchip: remove HCLK_HOST_ARB from usb host for px30William Wu
The HCLK_HOST_ARB is enabled with CLK_IGNORE_UNUSED flag, so we don't need to control this clk in usb host EHCI and OHCI controller driver. Change-Id: I25201170977b30f904611bbcfdcb1eb6230195fe Signed-off-by: William Wu <william.wu@rock-chips.com>
2018-02-08arm64: dts: rockchip: px30: add SCLK_RGA_CORE for rk_rga.Putin Lee
Change-Id: Ib183606bbd1a4ac2c9669100a6634aca45bcfb5e Signed-off-by: Putin Lee <putin.li@rock-chips.com>
2018-02-08arm64: dts: rockchip: add px30 ddr relate nodeYouMin Chen
Change-Id: I33119ba0250c6c9fe78d124bf92a94a52f9442bf Signed-off-by: YouMin Chen <cym@rock-chips.com>
2018-02-08arm64: dts: rockchip: px30: add vip iommu node reference to vip nodeZhong Yichong
Change-Id: Ic2772881a47aeb25ff68e2a39f3895e40db70a42 Signed-off-by: Zhong Yichong <zyc@rock-chips.com>
2018-02-08arm64: dts: rockchip: px30: add default pinctrl for i2s, pdmSugar Zhang
Change-Id: I5cf7436e65c04a30cc3ef4c89ee49e1e76ef0527 Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2018-02-08arm64: dts: rockchip: px30: Correct sdio irq number and add iomuxZhou weixin
Change-Id: Id61aece26f7c9e612a332ed8d0342693a4cc3b6a Signed-off-by: Weixin Zhou <zwx@rock-chips.com>
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