diff options
Diffstat (limited to 'include')
281 files changed, 32316 insertions, 1425 deletions
diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index ad0a5ff3d4cd..5de415bdfa56 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -392,13 +392,13 @@ struct acpi_data_node { static inline bool is_acpi_node(struct fwnode_handle *fwnode) { - return fwnode && (fwnode->type == FWNODE_ACPI + return !IS_ERR_OR_NULL(fwnode) && (fwnode->type == FWNODE_ACPI || fwnode->type == FWNODE_ACPI_DATA); } static inline bool is_acpi_device_node(struct fwnode_handle *fwnode) { - return fwnode && fwnode->type == FWNODE_ACPI; + return !IS_ERR_OR_NULL(fwnode) && fwnode->type == FWNODE_ACPI; } static inline struct acpi_device *to_acpi_device_node(struct fwnode_handle *fwnode) @@ -418,6 +418,13 @@ static inline struct acpi_data_node *to_acpi_data_node(struct fwnode_handle *fwn container_of(fwnode, struct acpi_data_node, fwnode) : NULL; } +static inline bool acpi_data_node_match(struct fwnode_handle *fwnode, + const char *name) +{ + return is_acpi_data_node(fwnode) ? + (!strcmp(to_acpi_data_node(fwnode)->name, name)) : false; +} + static inline struct fwnode_handle *acpi_fwnode_handle(struct acpi_device *adev) { return &adev->fwnode; diff --git a/include/asm-generic/preempt.h b/include/asm-generic/preempt.h index 5d8ffa3e6f8c..c1cde3577551 100644 --- a/include/asm-generic/preempt.h +++ b/include/asm-generic/preempt.h @@ -7,10 +7,10 @@ static __always_inline int preempt_count(void) { - return current_thread_info()->preempt_count; + return READ_ONCE(current_thread_info()->preempt_count); } -static __always_inline int *preempt_count_ptr(void) +static __always_inline volatile int *preempt_count_ptr(void) { return ¤t_thread_info()->preempt_count; } diff --git a/include/crypto/md5.h b/include/crypto/md5.h index 146af825eedb..327deac963c0 100644 --- a/include/crypto/md5.h +++ b/include/crypto/md5.h @@ -13,6 +13,8 @@ #define MD5_H2 0x98badcfeUL #define MD5_H3 0x10325476UL +extern const u8 md5_zero_message_hash[MD5_DIGEST_SIZE]; + struct md5_state { u32 hash[MD5_HASH_WORDS]; u32 block[MD5_BLOCK_WORDS]; diff --git a/include/crypto/sha.h b/include/crypto/sha.h index dd7905a3c22e..c94d3eb1cefd 100644 --- a/include/crypto/sha.h +++ b/include/crypto/sha.h @@ -64,6 +64,12 @@ #define SHA512_H6 0x1f83d9abfb41bd6bULL #define SHA512_H7 0x5be0cd19137e2179ULL +extern const u8 sha1_zero_message_hash[SHA1_DIGEST_SIZE]; + +extern const u8 sha224_zero_message_hash[SHA224_DIGEST_SIZE]; + +extern const u8 sha256_zero_message_hash[SHA256_DIGEST_SIZE]; + struct sha1_state { u32 state[SHA1_DIGEST_SIZE / 4]; u64 count; diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h new file mode 100644 index 000000000000..d51a694eb9ee --- /dev/null +++ b/include/drm/bridge/analogix_dp.h @@ -0,0 +1,49 @@ +/* + * Analogix DP (Display Port) Core interface driver. + * + * Copyright (C) 2015 Rockchip Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#ifndef _ANALOGIX_DP_H_ +#define _ANALOGIX_DP_H_ + +#include <drm/drm_crtc.h> + +enum analogix_dp_devtype { + EXYNOS_DP, + ROCKCHIP_DP, +}; + +enum analogix_dp_sub_devtype { + RK3288_DP, + RK3368_EDP, + RK3399_EDP, +}; + +struct analogix_dp_plat_data { + enum analogix_dp_devtype dev_type; + enum analogix_dp_sub_devtype subdev_type; + struct drm_panel *panel; + struct drm_encoder *encoder; + struct drm_connector *connector; + + int (*power_on)(struct analogix_dp_plat_data *); + int (*power_off)(struct analogix_dp_plat_data *); + int (*attach)(struct analogix_dp_plat_data *, struct drm_bridge *, + struct drm_connector *); + int (*get_modes)(struct analogix_dp_plat_data *, + struct drm_connector *); +}; + +int analogix_dp_resume(struct device *dev); +int analogix_dp_suspend(struct device *dev); + +int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev, + struct analogix_dp_plat_data *plat_data); +void analogix_dp_unbind(struct device *dev, struct device *master, void *data); + +#endif /* _ANALOGIX_DP_H_ */ diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h index bae79f3c4d28..8119bb98f257 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -14,6 +14,67 @@ struct dw_hdmi; +/** + * DOC: Supported input formats and encodings + * + * Depending on the Hardware configuration of the Controller IP, it supports + * a subset of the following input formats and encodings on its internal + * 48bit bus. + * + * +----------------------+----------------------------------+------------------------------+ + * + Format Name + Format Code + Encodings + + * +----------------------+----------------------------------+------------------------------+ + * + RGB 4:4:4 8bit + ``MEDIA_BUS_FMT_RGB888_1X24`` + ``V4L2_YCBCR_ENC_DEFAULT`` + + * +----------------------+----------------------------------+------------------------------+ + * + RGB 4:4:4 10bits + ``MEDIA_BUS_FMT_RGB101010_1X30`` + ``V4L2_YCBCR_ENC_DEFAULT`` + + * +----------------------+----------------------------------+------------------------------+ + * + RGB 4:4:4 12bits + ``MEDIA_BUS_FMT_RGB121212_1X36`` + ``V4L2_YCBCR_ENC_DEFAULT`` + + * +----------------------+----------------------------------+------------------------------+ + * + RGB 4:4:4 16bits + ``MEDIA_BUS_FMT_RGB161616_1X48`` + ``V4L2_YCBCR_ENC_DEFAULT`` + + * +----------------------+----------------------------------+------------------------------+ + * + YCbCr 4:4:4 8bit + ``MEDIA_BUS_FMT_YUV8_1X24`` + ``V4L2_YCBCR_ENC_601`` + + * + + + or ``V4L2_YCBCR_ENC_709`` + + * + + + or ``V4L2_YCBCR_ENC_XV601`` + + * + + + or ``V4L2_YCBCR_ENC_XV709`` + + * +----------------------+----------------------------------+------------------------------+ + * + YCbCr 4:4:4 10bits + ``MEDIA_BUS_FMT_YUV10_1X30`` + ``V4L2_YCBCR_ENC_601`` + + * + + + or ``V4L2_YCBCR_ENC_709`` + + * + + + or ``V4L2_YCBCR_ENC_XV601`` + + * + + + or ``V4L2_YCBCR_ENC_XV709`` + + * +----------------------+----------------------------------+------------------------------+ + * + YCbCr 4:4:4 12bits + ``MEDIA_BUS_FMT_YUV12_1X36`` + ``V4L2_YCBCR_ENC_601`` + + * + + + or ``V4L2_YCBCR_ENC_709`` + + * + + + or ``V4L2_YCBCR_ENC_XV601`` + + * + + + or ``V4L2_YCBCR_ENC_XV709`` + + * +----------------------+----------------------------------+------------------------------+ + * + YCbCr 4:4:4 16bits + ``MEDIA_BUS_FMT_YUV16_1X48`` + ``V4L2_YCBCR_ENC_601`` + + * + + + or ``V4L2_YCBCR_ENC_709`` + + * + + + or ``V4L2_YCBCR_ENC_XV601`` + + * + + + or ``V4L2_YCBCR_ENC_XV709`` + + * +----------------------+----------------------------------+------------------------------+ + * + YCbCr 4:2:2 8bit + ``MEDIA_BUS_FMT_UYVY8_1X16`` + ``V4L2_YCBCR_ENC_601`` + + * + + + or ``V4L2_YCBCR_ENC_709`` + + * +----------------------+----------------------------------+------------------------------+ + * + YCbCr 4:2:2 10bits + ``MEDIA_BUS_FMT_UYVY10_1X20`` + ``V4L2_YCBCR_ENC_601`` + + * + + + or ``V4L2_YCBCR_ENC_709`` + + * +----------------------+----------------------------------+------------------------------+ + * + YCbCr 4:2:2 12bits + ``MEDIA_BUS_FMT_UYVY12_1X24`` + ``V4L2_YCBCR_ENC_601`` + + * + + + or ``V4L2_YCBCR_ENC_709`` + + * +----------------------+----------------------------------+------------------------------+ + * + YCbCr 4:2:0 8bit + ``MEDIA_BUS_FMT_UYYVYY8_0_5X24`` + ``V4L2_YCBCR_ENC_601`` + + * + + + or ``V4L2_YCBCR_ENC_709`` + + * +----------------------+----------------------------------+------------------------------+ + * + YCbCr 4:2:0 10bits + ``MEDIA_BUS_FMT_UYYVYY10_0_5X30``+ ``V4L2_YCBCR_ENC_601`` + + * + + + or ``V4L2_YCBCR_ENC_709`` + + * +----------------------+----------------------------------+------------------------------+ + * + YCbCr 4:2:0 12bits + ``MEDIA_BUS_FMT_UYYVYY12_0_5X36``+ ``V4L2_YCBCR_ENC_601`` + + * + + + or ``V4L2_YCBCR_ENC_709`` + + * +----------------------+----------------------------------+------------------------------+ + * + YCbCr 4:2:0 16bits + ``MEDIA_BUS_FMT_UYYVYY16_0_5X48``+ ``V4L2_YCBCR_ENC_601`` + + * + + + or ``V4L2_YCBCR_ENC_709`` + + * +----------------------+----------------------------------+------------------------------+ + */ + enum { DW_HDMI_RES_8, DW_HDMI_RES_10, @@ -24,7 +85,29 @@ enum { enum dw_hdmi_devtype { IMX6Q_HDMI, IMX6DL_HDMI, + RK3228_HDMI, RK3288_HDMI, + RK3328_HDMI, + RK3366_HDMI, + RK3368_HDMI, + RK3399_HDMI, +}; + +struct dw_hdmi_audio_tmds_n { + unsigned long tmds; + unsigned int n_32k; + unsigned int n_44k1; + unsigned int n_48k; +}; + +enum dw_hdmi_phy_type { + DW_HDMI_PHY_DWC_HDMI_TX_PHY = 0x00, + DW_HDMI_PHY_DWC_MHL_PHY_HEAC = 0xb2, + DW_HDMI_PHY_DWC_MHL_PHY = 0xc2, + DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC = 0xe2, + DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY = 0xf2, + DW_HDMI_PHY_DWC_HDMI20_TX_PHY = 0xf3, + DW_HDMI_PHY_VENDOR_PHY = 0xfe, }; struct dw_hdmi_mpll_config { @@ -47,13 +130,60 @@ struct dw_hdmi_phy_config { u16 vlev_ctr; /* voltage level control */ }; +struct dw_hdmi_phy_ops { + int (*init)(struct dw_hdmi *hdmi, void *data, + struct drm_display_mode *mode); + void (*disable)(struct dw_hdmi *hdmi, void *data); + enum drm_connector_status (*read_hpd)(struct dw_hdmi *hdmi, void *data); +}; + +struct dw_hdmi_property_ops { + void (*attatch_properties)(struct drm_connector *connector, + unsigned int color, int version, + void *data); + void (*destroy_properties)(struct drm_connector *connector, + void *data); + int (*set_property)(struct drm_connector *connector, + struct drm_connector_state *state, + struct drm_property *property, + u64 val, + void *data); + int (*get_property)(struct drm_connector *connector, + const struct drm_connector_state *state, + struct drm_property *property, + u64 *val, + void *data); +}; + struct dw_hdmi_plat_data { enum dw_hdmi_devtype dev_type; + const struct dw_hdmi_audio_tmds_n *tmds_n_table; + enum drm_mode_status (*mode_valid)(struct drm_connector *connector, + struct drm_display_mode *mode); + unsigned long input_bus_format; + unsigned long input_bus_encoding; + + /* Vendor PHY support */ + const struct dw_hdmi_phy_ops *phy_ops; + const char *phy_name; + void *phy_data; + + /* Synopsys PHY support */ const struct dw_hdmi_mpll_config *mpll_cfg; + const struct dw_hdmi_mpll_config *mpll_cfg_420; const struct dw_hdmi_curr_ctrl *cur_ctr; const struct dw_hdmi_phy_config *phy_config; - enum drm_mode_status (*mode_valid)(struct drm_connector *connector, - struct drm_display_mode *mode); + int (*configure_phy)(struct dw_hdmi *hdmi, + const struct dw_hdmi_plat_data *pdata, + unsigned long mpixelclock); + + unsigned long (*get_input_bus_format)(void *data); + unsigned long (*get_output_bus_format)(void *data); + unsigned long (*get_enc_in_encoding)(void *data); + unsigned long (*get_enc_out_encoding)(void *data); + + /* Vendor Property support */ + const struct dw_hdmi_property_ops *property_ops; }; void dw_hdmi_unbind(struct device *dev, struct device *master, void *data); @@ -61,9 +191,17 @@ int dw_hdmi_bind(struct device *dev, struct device *master, void *data, struct drm_encoder *encoder, struct resource *iores, int irq, const struct dw_hdmi_plat_data *plat_data); - +void dw_hdmi_suspend(struct device *dev); +void dw_hdmi_resume(struct device *dev); +enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, + void *data); void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate); void dw_hdmi_audio_enable(struct dw_hdmi *hdmi); void dw_hdmi_audio_disable(struct dw_hdmi *hdmi); +void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi); + +/* PHY configuration */ +void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, + unsigned char addr); #endif /* __IMX_HDMI_H__ */ diff --git a/include/drm/drmP.h b/include/drm/drmP.h index a5d506b93daf..04edcd32b409 100644 --- a/include/drm/drmP.h +++ b/include/drm/drmP.h @@ -123,6 +123,7 @@ struct dma_buf_attachment; * run-time by echoing the debug value in its sysfs node: * # echo 0xf > /sys/module/drm/parameters/debug */ +#define DRM_UT_NONE 0x00 #define DRM_UT_CORE 0x01 #define DRM_UT_DRIVER 0x02 #define DRM_UT_KMS 0x04 @@ -130,11 +131,15 @@ struct dma_buf_attachment; #define DRM_UT_ATOMIC 0x10 #define DRM_UT_VBL 0x20 -extern __printf(2, 3) -void drm_ut_debug_printk(const char *function_name, - const char *format, ...); -extern __printf(1, 2) -void drm_err(const char *format, ...); +extern __printf(6, 7) +void drm_dev_printk(const struct device *dev, const char *level, + unsigned int category, const char *function_name, + const char *prefix, const char *format, ...); + +extern __printf(5, 6) +void drm_printk(const char *level, unsigned int category, + const char *function_name, const char *prefix, + const char *format, ...); /***********************************************************************/ /** \name DRM template customization defaults */ @@ -184,8 +189,12 @@ void drm_err(const char *format, ...); * \param fmt printf() like format string. * \param arg arguments */ -#define DRM_ERROR(fmt, ...) \ - drm_err(fmt, ##__VA_ARGS__) +#define DRM_DEV_ERROR(dev, fmt, ...) \ + drm_dev_printk(dev, KERN_ERR, DRM_UT_NONE, __func__, " *ERROR*",\ + fmt, ##__VA_ARGS__) +#define DRM_ERROR(fmt, ...) \ + drm_printk(KERN_ERR, DRM_UT_NONE, __func__, " *ERROR*", fmt, \ + ##__VA_ARGS__) /** * Rate limited error output. Like DRM_ERROR() but won't flood the log. @@ -193,14 +202,29 @@ void drm_err(const char *format, ...); * \param fmt printf() like format string. * \param arg arguments */ -#define DRM_ERROR_RATELIMITED(fmt, ...) \ +#define DRM_DEV_ERROR_RATELIMITED(dev, fmt, ...) \ ({ \ static DEFINE_RATELIMIT_STATE(_rs, \ DEFAULT_RATELIMIT_INTERVAL, \ DEFAULT_RATELIMIT_BURST); \ \ if (__ratelimit(&_rs)) \ - drm_err(fmt, ##__VA_ARGS__); \ + DRM_DEV_ERROR(dev, fmt, ##__VA_ARGS__); \ +}) +#define DRM_ERROR_RATELIMITED(fmt, ...) \ + DRM_DEV_ERROR_RATELIMITED(NULL, fmt, ##__VA_ARGS__) + +#define DRM_DEV_INFO(dev, fmt, ...) \ + drm_dev_printk(dev, KERN_INFO, DRM_UT_NONE, __func__, "", fmt, \ + ##__VA_ARGS__) + +#define DRM_DEV_INFO_ONCE(dev, fmt, ...) \ +({ \ + static bool __print_once __read_mostly; \ + if (!__print_once) { \ + __print_once = true; \ + DRM_DEV_INFO(dev, fmt, ##__VA_ARGS__); \ + } \ }) /** @@ -209,37 +233,74 @@ void drm_err(const char *format, ...); * \param fmt printf() like format string. * \param arg arguments */ +#define DRM_DEV_DEBUG(dev, fmt, args...) \ + drm_dev_printk(dev, KERN_DEBUG, DRM_UT_CORE, __func__, "", fmt, \ + ##args) #define DRM_DEBUG(fmt, args...) \ - do { \ - if (unlikely(drm_debug & DRM_UT_CORE)) \ - drm_ut_debug_printk(__func__, fmt, ##args); \ - } while (0) + drm_printk(KERN_DEBUG, DRM_UT_CORE, __func__, "", fmt, ##args) +#define DRM_DEV_DEBUG_DRIVER(dev, fmt, args...) \ + drm_dev_printk(dev, KERN_DEBUG, DRM_UT_DRIVER, __func__, "", \ + fmt, ##args) #define DRM_DEBUG_DRIVER(fmt, args...) \ - do { \ - if (unlikely(drm_debug & DRM_UT_DRIVER)) \ - drm_ut_debug_printk(__func__, fmt, ##args); \ - } while (0) + drm_printk(KERN_DEBUG, DRM_UT_DRIVER, __func__, "", fmt, ##args) + +#define DRM_DEV_DEBUG_KMS(dev, fmt, args...) \ + drm_dev_printk(dev, KERN_DEBUG, DRM_UT_KMS, __func__, "", fmt, \ + ##args) #define DRM_DEBUG_KMS(fmt, args...) \ - do { \ - if (unlikely(drm_debug & DRM_UT_KMS)) \ - drm_ut_debug_printk(__func__, fmt, ##args); \ - } while (0) + drm_printk(KERN_DEBUG, DRM_UT_KMS, __func__, "", fmt, ##args) + +#define DRM_DEV_DEBUG_PRIME(dev, fmt, args...) \ + drm_dev_printk(dev, KERN_DEBUG, DRM_UT_PRIME, __func__, "", \ + fmt, ##args) #define DRM_DEBUG_PRIME(fmt, args...) \ - do { \ - if (unlikely(drm_debug & DRM_UT_PRIME)) \ - drm_ut_debug_printk(__func__, fmt, ##args); \ - } while (0) + drm_printk(KERN_DEBUG, DRM_UT_PRIME, __func__, "", fmt, ##args) + +#define DRM_DEV_DEBUG_ATOMIC(dev, fmt, args...) \ + drm_dev_printk(dev, KERN_DEBUG, DRM_UT_ATOMIC, __func__, "", \ + fmt, ##args) #define DRM_DEBUG_ATOMIC(fmt, args...) \ - do { \ - if (unlikely(drm_debug & DRM_UT_ATOMIC)) \ - drm_ut_debug_printk(__func__, fmt, ##args); \ - } while (0) + drm_printk(KERN_DEBUG, DRM_UT_ATOMIC, __func__, "", fmt, ##args) + +#define DRM_DEV_DEBUG_VBL(dev, fmt, args...) \ + drm_dev_printk(dev, KERN_DEBUG, DRM_UT_VBL, __func__, "", fmt, \ + ##args) #define DRM_DEBUG_VBL(fmt, args...) \ - do { \ - if (unlikely(drm_debug & DRM_UT_VBL)) \ - drm_ut_debug_printk(__func__, fmt, ##args); \ - } while (0) + drm_printk(KERN_DEBUG, DRM_UT_VBL, __func__, "", fmt, ##args) + +#define _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, level, fmt, args...) \ +({ \ + static DEFINE_RATELIMIT_STATE(_rs, \ + DEFAULT_RATELIMIT_INTERVAL, \ + DEFAULT_RATELIMIT_BURST); \ + if (__ratelimit(&_rs)) \ + drm_dev_printk(dev, KERN_DEBUG, DRM_UT_ ## level, \ + __func__, "", fmt, ##args); \ +}) + +/** + * Rate limited debug output. Like DRM_DEBUG() but won't flood the log. + * + * \param fmt printf() like format string. + * \param arg arguments + */ +#define DRM_DEV_DEBUG_RATELIMITED(dev, fmt, args...) \ + DEV__DRM_DEFINE_DEBUG_RATELIMITED(dev, CORE, fmt, ##args) +#define DRM_DEBUG_RATELIMITED(fmt, args...) \ + DRM_DEV_DEBUG_RATELIMITED(NULL, fmt, ##args) +#define DRM_DEV_DEBUG_DRIVER_RATELIMITED(dev, fmt, args...) \ + _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, DRIVER, fmt, ##args) +#define DRM_DEBUG_DRIVER_RATELIMITED(fmt, args...) \ + DRM_DEV_DEBUG_DRIVER_RATELIMITED(NULL, fmt, ##args) +#define DRM_DEV_DEBUG_KMS_RATELIMITED(dev, fmt, args...) \ + _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, KMS, fmt, ##args) +#define DRM_DEBUG_KMS_RATELIMITED(fmt, args...) \ + DRM_DEV_DEBUG_KMS_RATELIMITED(NULL, fmt, ##args) +#define DRM_DEV_DEBUG_PRIME_RATELIMITED(dev, fmt, args...) \ + _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, PRIME, fmt, ##args) +#define DRM_DEBUG_PRIME_RATELIMITED(fmt, args...) \ + DRM_DEV_DEBUG_PRIME_RATELIMITED(NULL, fmt, ##args) /*@}*/ @@ -295,6 +356,7 @@ struct drm_ioctl_desc { /* Event queued up for userspace to read */ struct drm_pending_event { + struct completion *completion; struct drm_event *event; struct list_head link; struct drm_file *file_priv; @@ -324,6 +386,11 @@ struct drm_file { /* true if client understands atomic properties */ unsigned atomic:1; /* + * true if client understands share planes and + * hardware support share planes. + */ + unsigned share_planes:1; + /* * This client is allowed to gain master privileges for @master. * Protected by struct drm_device::master_mutex. */ @@ -626,6 +693,12 @@ struct drm_driver { void (*gem_prime_vunmap)(struct drm_gem_object *obj, void *vaddr); int (*gem_prime_mmap)(struct drm_gem_object *obj, struct vm_area_struct *vma); + int (*gem_prime_begin_cpu_access)(struct drm_gem_object *obj, + size_t, size_t, + enum dma_data_direction); + void (*gem_prime_end_cpu_access)(struct drm_gem_object *obj, + size_t, size_t, + enum dma_data_direction); /* vga arb irq handler */ void (*vgaarb_irq)(struct drm_device *dev, bool state); @@ -933,6 +1006,14 @@ extern int drm_new_set_master(struct drm_device *dev, struct drm_file *fpriv); /* Mapping support (drm_vm.h) */ extern unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait); +int drm_event_reserve_init(struct drm_device *dev, + struct drm_file *file_priv, + struct drm_pending_event *p, + struct drm_event *e); +void drm_event_cancel_free(struct drm_device *dev, + struct drm_pending_event *p); +void drm_send_event_locked(struct drm_device *dev, struct drm_pending_event *e); +void drm_send_event(struct drm_device *dev, struct drm_pending_event *e); /* Misc. IOCTL support (drm_ioctl.c) */ int drm_noop(struct drm_device *dev, void *data, @@ -1078,6 +1159,14 @@ int drm_dev_set_unique(struct drm_device *dev, const char *fmt, ...); struct drm_minor *drm_minor_acquire(unsigned int minor_id); void drm_minor_release(struct drm_minor *minor); +#ifdef CONFIG_DRM +struct drm_device *drm_device_get_by_name(const char *name); +#else +static inline struct drm_device *drm_device_get_by_name(const char *name) +{ + return NULL; +} +#endif /*@}*/ diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h index 4b74c97d297a..13567ba4310d 100644 --- a/include/drm/drm_atomic.h +++ b/include/drm/drm_atomic.h @@ -30,6 +30,12 @@ #include <drm/drm_crtc.h> +void drm_crtc_commit_put(struct drm_crtc_commit *commit); +static inline void drm_crtc_commit_get(struct drm_crtc_commit *commit) +{ + kref_get(&commit->ref); +} + struct drm_atomic_state * __must_check drm_atomic_state_alloc(struct drm_device *dev); void drm_atomic_state_clear(struct drm_atomic_state *state); @@ -109,6 +115,11 @@ drm_atomic_get_existing_connector_state(struct drm_atomic_state *state, return state->connector_states[index]; } +int drm_atomic_replace_property_blob_from_id(struct drm_device *dev, + struct drm_property_blob **blob, + uint64_t blob_id, + ssize_t expected_size, + bool *replaced); int __must_check drm_atomic_set_mode_for_crtc(struct drm_crtc_state *state, struct drm_display_mode *mode); diff --git a/include/drm/drm_atomic_helper.h b/include/drm/drm_atomic_helper.h index 8cba54a2a0a0..8e3efa70f446 100644 --- a/include/drm/drm_atomic_helper.h +++ b/include/drm/drm_atomic_helper.h @@ -42,6 +42,10 @@ int drm_atomic_helper_commit(struct drm_device *dev, struct drm_atomic_state *state, bool async); +bool drm_atomic_helper_framebuffer_changed(struct drm_device *dev, + struct drm_atomic_state *old_state, + struct drm_crtc *crtc); + void drm_atomic_helper_wait_for_vblanks(struct drm_device *dev, struct drm_atomic_state *old_state); @@ -66,6 +70,13 @@ void drm_atomic_helper_commit_planes_on_crtc(struct drm_crtc_state *old_crtc_sta void drm_atomic_helper_swap_state(struct drm_device *dev, struct drm_atomic_state *state); +/* nonblocking commit helpers */ +int drm_atomic_helper_setup_commit(struct drm_atomic_state *state, + bool nonblock); +void drm_atomic_helper_wait_for_dependencies(struct drm_atomic_state *state); +void drm_atomic_helper_commit_hw_done(struct drm_atomic_state *state); +void drm_atomic_helper_commit_cleanup_done(struct drm_atomic_state *state); + /* implementations for legacy interfaces */ int drm_atomic_helper_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, @@ -81,6 +92,12 @@ int drm_atomic_helper_set_config(struct drm_mode_set *set); int __drm_atomic_helper_set_config(struct drm_mode_set *set, struct drm_atomic_state *state); +int drm_atomic_helper_disable_all(struct drm_device *dev, + struct drm_modeset_acquire_ctx *ctx); +struct drm_atomic_state *drm_atomic_helper_suspend(struct drm_device *dev); +int drm_atomic_helper_resume(struct drm_device *dev, + struct drm_atomic_state *state); + int drm_atomic_helper_crtc_set_property(struct drm_crtc *crtc, struct drm_property *property, uint64_t val); @@ -96,6 +113,8 @@ int drm_atomic_helper_page_flip(struct drm_crtc *crtc, uint32_t flags); int drm_atomic_helper_connector_dpms(struct drm_connector *connector, int mode); +struct drm_encoder * +drm_atomic_helper_best_encoder(struct drm_connector *connector); /* default implementations for state handling */ void drm_atomic_helper_crtc_reset(struct drm_crtc *crtc); @@ -132,6 +151,9 @@ __drm_atomic_helper_connector_destroy_state(struct drm_connector *connector, struct drm_connector_state *state); void drm_atomic_helper_connector_destroy_state(struct drm_connector *connector, struct drm_connector_state *state); +void drm_atomic_helper_legacy_gamma_set(struct drm_crtc *crtc, + u16 *red, u16 *green, u16 *blue, + uint32_t start, uint32_t size); /** * drm_atomic_crtc_for_each_plane - iterate over planes currently attached to CRTC diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 3f0c6909dda1..9b2d4b6766a9 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -117,11 +117,87 @@ enum subpixel_order { SubPixelVerticalRGB, SubPixelVerticalBGR, SubPixelNone, + +}; + +/** + * struct drm_scrambling: sink's scrambling support. + */ +struct drm_scrambling { + /** + * @supported: scrambling supported for rates > 340 Mhz. + */ + bool supported; + /** + * @low_rates: scrambling supported for rates <= 340 Mhz. + */ + bool low_rates; +}; + +/* + * struct drm_scdc - Information about scdc capabilities of a HDMI 2.0 sink + * + * Provides SCDC register support and capabilities related information on a + * HDMI 2.0 sink. In case of a HDMI 1.4 sink, all parameter must be 0. + */ +struct drm_scdc { + /** + * @supported: status control & data channel present. + */ + bool supported; + /** + * @read_request: sink is capable of generating scdc read request. + */ + bool read_request; + /** + * @scrambling: sink's scrambling capabilities + */ + struct drm_scrambling scrambling; +}; + + +/** + * struct drm_hdmi_info - runtime information about the connected HDMI sink + * + * Describes if a given display supports advanced HDMI 2.0 features. + * This information is available in CEA-861-F extension blocks (like HF-VSDB). + */ +struct drm_hdmi_info { + struct drm_scdc scdc; + + /** + * @y420_vdb_modes: bitmap of modes which can support ycbcr420 + * output only (not normal RGB/YCBCR444/422 outputs). There are total + * 107 VICs defined by CEA-861-F spec, so the size is 128 bits to map + * upto 128 VICs; + */ + unsigned long y420_vdb_modes[BITS_TO_LONGS(128)]; + + /** + * @y420_cmdb_modes: bitmap of modes which can support ycbcr420 + * output also, along with normal HDMI outputs. There are total 107 + * VICs defined by CEA-861-F spec, so the size is 128 bits to map upto + * 128 VICs; + */ + unsigned long y420_cmdb_modes[BITS_TO_LONGS(128)]; + + /** @y420_cmdb_map: bitmap of SVD index, to extraxt vcb modes */ + u64 y420_cmdb_map; + + /** @y420_dc_modes: bitmap of deep color support index */ + u8 y420_dc_modes; + + /* Colorimerty info from EDID */ + u32 colorimetry; + + /* HDR metdata */ + struct hdr_static_metadata hdr_panel_metadata; }; #define DRM_COLOR_FORMAT_RGB444 (1<<0) #define DRM_COLOR_FORMAT_YCRCB444 (1<<1) #define DRM_COLOR_FORMAT_YCRCB422 (1<<2) +#define DRM_COLOR_FORMAT_YCRCB420 (1<<3) /* * Describes a given display (e.g. CRT or flat panel) and its limitations. */ @@ -144,10 +220,26 @@ struct drm_display_info { const u32 *bus_formats; unsigned int num_bus_formats; + /** + * @max_tmds_clock: Maximum TMDS clock rate supported by the + * sink in kHz. 0 means undefined. + */ + int max_tmds_clock; + + /** + * @dvi_dual: Dual-link DVI sink? + */ + bool dvi_dual; + /* Mask of supported hdmi deep color modes */ u8 edid_hdmi_dc_modes; u8 cea_rev; + + /** + * @hdmi: advance features of a HDMI sink. + */ + struct drm_hdmi_info hdmi; }; /* data corresponds to displayid vend/prod/serial */ @@ -259,11 +351,18 @@ struct drm_atomic_state; * @mode_changed: crtc_state->mode or crtc_state->enable has been changed * @active_changed: crtc_state->active has been toggled. * @connectors_changed: connectors to this crtc have been updated + * @color_mgmt_changed: color management properties have changed (degamma or + * gamma LUT or CSC matrix) * @plane_mask: bitmask of (1 << drm_plane_index(plane)) of attached planes * @last_vblank_count: for helpers and drivers to capture the vblank of the * update to ensure framebuffer cleanup isn't done too early * @adjusted_mode: for use by helpers and drivers to compute adjusted mode timings * @mode: current mode timings + * @degamma_lut: Lookup table for converting framebuffer pixel data + * before apply the conversion matrix + * @ctm: Transformation matrix + * @gamma_lut: Lookup table for converting pixel data after the + * conversion matrix * @event: optional pointer to a DRM event to signal upon completion of the * state update * @state: backpointer to global drm_atomic_state @@ -285,6 +384,7 @@ struct drm_crtc_state { bool mode_changed : 1; bool active_changed : 1; bool connectors_changed : 1; + bool color_mgmt_changed : 1; /* attached planes bitmask: * WARNING: transitional helpers do not maintain plane_mask so @@ -304,9 +404,15 @@ struct drm_crtc_state { /* blob property to expose current mode to atomic userspace */ struct drm_property_blob *mode_blob; + /* blob property to expose color management to userspace */ + struct drm_property_blob *degamma_lut; + struct drm_property_blob *ctm; + struct drm_property_blob *gamma_lut; + struct drm_pending_vblank_event *event; struct drm_atomic_state *state; + struct drm_crtc_commit *commit; }; /** @@ -391,8 +497,59 @@ struct drm_crtc_funcs { const struct drm_crtc_state *state, struct drm_property *property, uint64_t *val); + + /** + * @late_register: + * + * This optional hook can be used to register additional userspace + * interfaces attached to the crtc like debugfs interfaces. + * It is called late in the driver load sequence from drm_dev_register(). + * Everything added from this callback should be unregistered in + * the early_unregister callback. + * + * Returns: + * + * 0 on success, or a negative error code on failure. + */ + int (*late_register)(struct drm_crtc *crtc); + + /** + * @early_unregister: + * + * This optional hook should be used to unregister the additional + * userspace interfaces attached to the crtc from + * late_unregister(). It is called from drm_dev_unregister(), + * early in the driver unload sequence to disable userspace access + * before data structures are torndown. + */ + void (*early_unregister)(struct drm_crtc *crtc); }; +#if defined(CONFIG_ROCKCHIP_DRM_DEBUG) +struct vop_dump_info { + int win_id; + int area_id; + unsigned int pitches; + unsigned int height; + u32 pixel_format; + bool AFBC_flag; + bool yuv_format; + unsigned long offset; + unsigned long num_pages; + struct page **pages; +}; + +struct vop_dump_list { + struct list_head entry; + struct vop_dump_info dump_info; +}; + +enum vop_dump_status { + DUMP_DISABLE = 0, + DUMP_KEEP +}; +#endif + /** * struct drm_crtc - central CRTC control structure * @dev: parent DRM device @@ -414,9 +571,6 @@ struct drm_crtc_funcs { * @gamma_store: gamma ramp values * @helper_private: mid-layer private data * @properties: property tracking for this CRTC - * @state: current atomic state for this CRTC - * @acquire_ctx: per-CRTC implicit acquire context used by atomic drivers for - * legacy ioctls * * Each CRTC may have one or more connectors associated with it. This structure * allows the CRTC to be controlled. @@ -458,7 +612,7 @@ struct drm_crtc { int x, y; const struct drm_crtc_funcs *funcs; - /* CRTC gamma size for reporting to userspace */ + /* Legacy FB CRTC gamma size for reporting to userspace */ uint32_t gamma_size; uint16_t *gamma_store; @@ -467,13 +621,83 @@ struct drm_crtc { struct drm_object_properties properties; + /** + * @state: + * + * Current atomic state for this CRTC. + */ struct drm_crtc_state *state; - /* - * For legacy crtc ioctls so that atomic drivers can get at the locking - * acquire context. + /** + * @commit_list: + * + * List of &drm_crtc_commit structures tracking pending commits. + * Protected by @commit_lock. This list doesn't hold its own full + * reference, but burrows it from the ongoing commit. Commit entries + * must be removed from this list once the commit is fully completed, + * but before it's correspoding &drm_atomic_state gets destroyed. + */ + struct list_head commit_list; + + /** + * @commit_lock: + * + * Spinlock to protect @commit_list. + */ + spinlock_t commit_lock; + + /** + * @acquire_ctx: + * + * Per-CRTC implicit acquire context used by atomic drivers for legacy + * IOCTLs, so that atomic drivers can get at the locking acquire + * context. */ struct drm_modeset_acquire_ctx *acquire_ctx; + +#if defined(CONFIG_ROCKCHIP_DRM_DEBUG) + /** + * @vop_dump_status the status of vop dump control + * @vop_dump_list_head the list head of vop dump list + * @vop_dump_list_init_flag init once + * @vop_dump_times control the dump times + * @frme_count the frame of dump buf + */ + enum vop_dump_status vop_dump_status; + struct list_head vop_dump_list_head; + bool vop_dump_list_init_flag; + int vop_dump_times; + int frame_count; +#endif +}; + +/** + * struct drm_tv_connector_state - TV connector related states + * @subconnector: selected subconnector + * @margins: left/right/top/bottom margins + * @mode: TV mode + * @brightness: brightness in percent + * @contrast: contrast in percent + * @flicker_reduction: flicker reduction in percent + * @overscan: overscan in percent + * @saturation: saturation in percent + * @hue: hue in percent + */ +struct drm_tv_connector_state { + enum drm_mode_subconnector subconnector; + struct { + unsigned int left; + unsigned int right; + unsigned int top; + unsigned int bottom; + } margins; + unsigned int mode; + unsigned int brightness; + unsigned int contrast; + unsigned int flicker_reduction; + unsigned int overscan; + unsigned int saturation; + unsigned int hue; }; /** @@ -491,6 +715,22 @@ struct drm_connector_state { struct drm_encoder *best_encoder; struct drm_atomic_state *state; + + /** + * @content_protection: Connector property to request content + * protection. This is most commonly used for HDCP. + */ + unsigned int content_protection; + + struct drm_tv_connector_state tv; + + /** + * @metadata_blob_ptr: + * DRM blob property for HDR metadata + */ + struct drm_property_blob *hdr_source_metadata_blob_ptr; + bool hdr_metadata_changed : 1; + uint64_t blob_id; }; /** @@ -532,6 +772,34 @@ struct drm_connector_funcs { int (*fill_modes)(struct drm_connector *connector, uint32_t max_width, uint32_t max_height); int (*set_property)(struct drm_connector *connector, struct drm_property *property, uint64_t val); + + /** + * @late_register: + * + * This optional hook can be used to register additional userspace + * interfaces attached to the connector, light backlight control, i2c, + * DP aux or similar interfaces. It is called late in the driver load + * sequence from drm_connector_register() when registering all the + * core drm connector interfaces. Everything added from this callback + * should be unregistered in the early_unregister callback. + * + * Returns: + * + * 0 on success, or a negative error code on failure. + */ + int (*late_register)(struct drm_connector *connector); + + /** + * @early_unregister: + * + * This optional hook should be used to unregister the additional + * userspace interfaces attached to the connector from + * late_unregister(). It is called from drm_connector_unregister(), + * early in the driver unload sequence to disable userspace access + * before data structures are torndown. + */ + void (*early_unregister)(struct drm_connector *connector); + void (*destroy)(struct drm_connector *connector); void (*force)(struct drm_connector *connector); @@ -559,6 +827,32 @@ struct drm_connector_funcs { struct drm_encoder_funcs { void (*reset)(struct drm_encoder *encoder); void (*destroy)(struct drm_encoder *encoder); + + /** + * @late_register: + * + * This optional hook can be used to register additional userspace + * interfaces attached to the encoder like debugfs interfaces. + * It is called late in the driver load sequence from drm_dev_register(). + * Everything added from this callback should be unregistered in + * the early_unregister callback. + * + * Returns: + * + * 0 on success, or a negative error code on failure. + */ + int (*late_register)(struct drm_encoder *encoder); + + /** + * @early_unregister: + * + * This optional hook should be used to unregister the additional + * userspace interfaces attached to the encoder from + * late_unregister(). It is called from drm_dev_unregister(), + * early in the driver unload sequence to disable userspace access + * before data structures are torndown. + */ + void (*early_unregister)(struct drm_encoder *encoder); }; #define DRM_CONNECTOR_MAX_ENCODER 3 @@ -566,6 +860,7 @@ struct drm_encoder_funcs { /** * struct drm_encoder - central DRM encoder structure * @dev: parent DRM device + * @port: OF node used by find encoder by node * @head: list management * @base: base KMS object * @name: encoder name @@ -582,6 +877,7 @@ struct drm_encoder_funcs { */ struct drm_encoder { struct drm_device *dev; + struct device_node *port; struct list_head head; struct drm_mode_object base; @@ -589,6 +885,7 @@ struct drm_encoder { int encoder_type; uint32_t possible_crtcs; uint32_t possible_clones; + bool loader_protect; struct drm_crtc *crtc; struct drm_bridge *bridge; @@ -610,6 +907,7 @@ struct drm_encoder { /** * struct drm_connector - central DRM connector control structure * @dev: parent DRM device + * @port: OF node used by find connector by node. * @kdev: kernel device for sysfs attributes * @attr: sysfs attributes * @head: list management @@ -637,8 +935,6 @@ struct drm_encoder { * @encoder_ids: valid encoders for this connector * @encoder: encoder driving this connector, if any * @eld: EDID-like data, if present - * @dvi_dual: dual link DVI, if found - * @max_tmds_clock: max clock rate, if found * @latency_present: AV delay info from ELD, if found * @video_latency: video latency info from ELD, if found * @audio_latency: audio latency info from ELD, if found @@ -656,6 +952,7 @@ struct drm_encoder { * @tile_v_loc: vertical location of this tile * @tile_h_size: horizontal size of this tile. * @tile_v_size: vertical size of this tile. + * @content_protection_property: Optional property to control content protection * * Each connector may be connected to one or more CRTCs, or may be clonable by * another connector if they can share a CRTC. Each connector also has a specific @@ -664,6 +961,7 @@ struct drm_encoder { */ struct drm_connector { struct drm_device *dev; + struct device_node *port; struct device *kdev; struct device_attribute *attr; struct list_head head; @@ -676,6 +974,15 @@ struct drm_connector { bool interlace_allowed; bool doublescan_allowed; bool stereo_allowed; + + /** + * @ycbcr_420_allowed : This bool indicates if this connector is + * capable of handling YCBCR 420 output. While parsing the EDID + * blocks, its very helpful to know, if the source is capable of + * handling YCBCR 420 outputs. + */ + bool ycbcr_420_allowed; + struct list_head modes; /* list of modes on this connector */ enum drm_connector_status status; @@ -689,10 +996,18 @@ struct drm_connector { struct drm_property_blob *edid_blob_ptr; struct drm_object_properties properties; + /** + * @content_protection_property: DRM ENUM property for content + * protection + */ + struct drm_property *content_protection_property; + struct drm_property_blob *path_blob_ptr; struct drm_property_blob *tile_blob_ptr; + struct drm_property_blob *hdr_panel_blob_ptr; + uint8_t polled; /* DRM_CONNECTOR_POLL_* */ /* requested DPMS state */ @@ -706,11 +1021,10 @@ struct drm_connector { bool override_edid; uint32_t encoder_ids[DRM_CONNECTOR_MAX_ENCODER]; struct drm_encoder *encoder; /* currently active encoder */ + bool loader_protect; /* EDID bits */ uint8_t eld[MAX_ELD_BYTES]; - bool dvi_dual; - int max_tmds_clock; /* in MHz */ bool latency_present[2]; int video_latency[2]; /* [0]: progressive, [1]: interlaced */ int audio_latency[2]; @@ -734,6 +1048,7 @@ struct drm_connector { uint8_t num_h_tile, num_v_tile; uint8_t tile_h_loc, tile_v_loc; uint16_t tile_h_size, tile_v_size; + }; /** @@ -816,6 +1131,31 @@ struct drm_plane_funcs { const struct drm_plane_state *state, struct drm_property *property, uint64_t *val); + /** + * @late_register: + * + * This optional hook can be used to register additional userspace + * interfaces attached to the plane like debugfs interfaces. + * It is called late in the driver load sequence from drm_dev_register(). + * Everything added from this callback should be unregistered in + * the early_unregister callback. + * + * Returns: + * + * 0 on success, or a negative error code on failure. + */ + int (*late_register)(struct drm_plane *plane); + + /** + * @early_unregister: + * + * This optional hook should be used to unregister the additional + * userspace interfaces attached to the plane from + * late_unregister(). It is called from drm_dev_unregister(), + * early in the driver unload sequence to disable userspace access + * before data structures are torndown. + */ + void (*early_unregister)(struct drm_plane *plane); }; enum drm_plane_type { @@ -827,6 +1167,7 @@ enum drm_plane_type { /** * struct drm_plane - central DRM plane control structure * @dev: DRM device this plane belongs to + * @parent: this plane share some resources with parent plane. * @head: for list management * @base: base mode object * @possible_crtcs: pipes this plane can be bound to @@ -844,6 +1185,7 @@ enum drm_plane_type { */ struct drm_plane { struct drm_device *dev; + struct drm_plane *parent; struct list_head head; struct drm_modeset_lock mutex; @@ -886,12 +1228,79 @@ struct drm_bridge_funcs { bool (*mode_fixup)(struct drm_bridge *bridge, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode); + /** + * @disable: + * + * This callback should disable the bridge. It is called right before + * the preceding element in the display pipe is disabled. If the + * preceding element is a bridge this means it's called before that + * bridge's ->disable() function. If the preceding element is a + * &drm_encoder it's called right before the encoder's ->disable(), + * ->prepare() or ->dpms() hook from struct &drm_encoder_helper_funcs. + * + * The bridge can assume that the display pipe (i.e. clocks and timing + * signals) feeding it is still running when this callback is called. + * + * The disable callback is optional. + */ void (*disable)(struct drm_bridge *bridge); + + /** + * @post_disable: + * + * This callback should disable the bridge. It is called right after + * the preceding element in the display pipe is disabled. If the + * preceding element is a bridge this means it's called after that + * bridge's ->post_disable() function. If the preceding element is a + * &drm_encoder it's called right after the encoder's ->disable(), + * ->prepare() or ->dpms() hook from struct &drm_encoder_helper_funcs. + * + * The bridge must assume that the display pipe (i.e. clocks and timing + * singals) feeding it is no longer running when this callback is + * called. + * + * The post_disable callback is optional. + */ void (*post_disable)(struct drm_bridge *bridge); void (*mode_set)(struct drm_bridge *bridge, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode); + /** + * @pre_enable: + * + * This callback should enable the bridge. It is called right before + * the preceding element in the display pipe is enabled. If the + * preceding element is a bridge this means it's called before that + * bridge's ->pre_enable() function. If the preceding element is a + * &drm_encoder it's called right before the encoder's ->enable(), + * ->commit() or ->dpms() hook from struct &drm_encoder_helper_funcs. + * + * The display pipe (i.e. clocks and timing signals) feeding this bridge + * will not yet be running when this callback is called. The bridge must + * not enable the display link feeding the next bridge in the chain (if + * there is one) when this callback is called. + * + * The pre_enable callback is optional. + */ void (*pre_enable)(struct drm_bridge *bridge); + + /** + * @enable: + * + * This callback should enable the bridge. It is called right after + * the preceding element in the display pipe is enabled. If the + * preceding element is a bridge this means it's called after that + * bridge's ->enable() function. If the preceding element is a + * &drm_encoder it's called right after the encoder's ->enable(), + * ->commit() or ->dpms() hook from struct &drm_encoder_helper_funcs. + * + * The bridge can assume that the display pipe (i.e. clocks and timing + * signals) feeding it is running when this callback is called. This + * callback must enable the display link feeding the next bridge in the + * chain if there is one. + * + * The enable callback is optional. + */ void (*enable)(struct drm_bridge *bridge); }; @@ -919,6 +1328,111 @@ struct drm_bridge { }; /** + * struct drm_crtc_commit - track modeset commits on a CRTC + * + * This structure is used to track pending modeset changes and atomic commit on + * a per-CRTC basis. Since updating the list should never block this structure + * is reference counted to allow waiters to safely wait on an event to complete, + * without holding any locks. + * + * It has 3 different events in total to allow a fine-grained synchronization + * between outstanding updates:: + * + * atomic commit thread hardware + * + * write new state into hardware ----> ... + * signal hw_done + * switch to new state on next + * ... v/hblank + * + * wait for buffers to show up ... + * + * ... send completion irq + * irq handler signals flip_done + * cleanup old buffers + * + * signal cleanup_done + * + * wait for flip_done <---- + * clean up atomic state + * + * The important bit to know is that cleanup_done is the terminal event, but the + * ordering between flip_done and hw_done is entirely up to the specific driver + * and modeset state change. + * + * For an implementation of how to use this look at + * drm_atomic_helper_setup_commit() from the atomic helper library. + */ +struct drm_crtc_commit { + /** + * @crtc: + * + * DRM CRTC for this commit. + */ + struct drm_crtc *crtc; + + /** + * @ref: + * + * Reference count for this structure. Needed to allow blocking on + * completions without the risk of the completion disappearing + * meanwhile. + */ + struct kref ref; + + /** + * @flip_done: + * + * Will be signaled when the hardware has flipped to the new set of + * buffers. Signals at the same time as when the drm event for this + * commit is sent to userspace, or when an out-fence is singalled. Note + * that for most hardware, in most cases this happens after @hw_done is + * signalled. + */ + struct completion flip_done; + + /** + * @hw_done: + * + * Will be signalled when all hw register changes for this commit have + * been written out. Especially when disabling a pipe this can be much + * later than than @flip_done, since that can signal already when the + * screen goes black, whereas to fully shut down a pipe more register + * I/O is required. + * + * Note that this does not need to include separately reference-counted + * resources like backing storage buffer pinning, or runtime pm + * management. + */ + struct completion hw_done; + + /** + * @cleanup_done: + * + * Will be signalled after old buffers have been cleaned up by calling + * drm_atomic_helper_cleanup_planes(). Since this can only happen after + * a vblank wait completed it might be a bit later. This completion is + * useful to throttle updates and avoid hardware updates getting ahead + * of the buffer cleanup too much. + */ + struct completion cleanup_done; + + /** + * @commit_entry: + * + * Entry on the per-CRTC commit_list. Protected by crtc->commit_lock. + */ + struct list_head commit_entry; + + /** + * @event: + * + * &drm_pending_vblank_event pointer to clean up private events. + */ + struct drm_pending_vblank_event *event; +}; + +/** * struct drm_atomic_state - the global state object for atomic updates * @dev: parent DRM device * @allow_modeset: allow full modeset @@ -939,12 +1453,21 @@ struct drm_atomic_state { struct drm_plane **planes; struct drm_plane_state **plane_states; struct drm_crtc **crtcs; + struct drm_crtc_commit **crtc_commits; struct drm_crtc_state **crtc_states; int num_connector; struct drm_connector **connectors; struct drm_connector_state **connector_states; struct drm_modeset_acquire_ctx *acquire_ctx; + + /** + * @commit_work: + * + * Work item which can be used by the driver or helpers to execute the + * commit without blocking. + */ + struct work_struct commit_work; }; @@ -1038,6 +1561,15 @@ struct drm_mode_config_funcs { * @property_blob_list: list of all the blob property objects * @blob_lock: mutex for blob property allocation and management * @*_property: core property tracking + * @degamma_lut_property: LUT used to convert the framebuffer's colors to linear + * gamma + * @degamma_lut_size_property: size of the degamma LUT as supported by the + * driver (read-only) + * @ctm_property: Matrix used to convert colors after the lookup in the + * degamma LUT + * @gamma_lut_property: LUT used to convert the colors, after the CSC matrix, to + * the gamma space of the connected screen (read-only) + * @gamma_lut_size_property: size of the gamma LUT as supported by the driver * @preferred_depth: preferred RBG pixel depth, used by fb helpers * @prefer_shadow: hint to userspace to prefer shadow-fb rendering * @async_page_flip: does this device support async flips on the primary plane? @@ -1074,6 +1606,8 @@ struct drm_mode_config { */ int num_overlay_plane; int num_total_plane; + int num_share_plane; + int num_share_overlay_plane; struct list_head plane_list; int num_crtc; @@ -1094,6 +1628,10 @@ struct drm_mode_config { struct mutex blob_lock; + /* pointers to share properties */ + struct drm_property *prop_share_id; + struct drm_property *prop_share_flags; + /* pointers to standard properties */ struct list_head property_blob_list; struct drm_property *edid_property; @@ -1114,6 +1652,7 @@ struct drm_mode_config { struct drm_property *prop_crtc_id; struct drm_property *prop_active; struct drm_property *prop_mode_id; + struct drm_property *content_protection_property; /* DVI-I properties */ struct drm_property *dvi_i_subconnector_property; @@ -1139,10 +1678,23 @@ struct drm_mode_config { struct drm_property *aspect_ratio_property; struct drm_property *dirty_info_property; + /* Optional color correction properties */ + struct drm_property *degamma_lut_property; + struct drm_property *degamma_lut_size_property; + struct drm_property *ctm_property; + struct drm_property *gamma_lut_property; + struct drm_property *gamma_lut_size_property; + /* properties for virtual machine layout */ struct drm_property *suggested_x_property; struct drm_property *suggested_y_property; + /** + * hdr_metadata_property: Connector property containing hdr metatda + * This will be provided by userspace compositors based on HDR content + */ + struct drm_property *hdr_source_metadata_property; + struct drm_property *hdr_panel_metadata_property; /* dumb ioctl parameters */ uint32_t preferred_depth, prefer_shadow; @@ -1183,11 +1735,13 @@ struct drm_prop_enum_list { char *name; }; -extern int drm_crtc_init_with_planes(struct drm_device *dev, - struct drm_crtc *crtc, - struct drm_plane *primary, - struct drm_plane *cursor, - const struct drm_crtc_funcs *funcs); +extern __printf(6, 7) +int drm_crtc_init_with_planes(struct drm_device *dev, + struct drm_crtc *crtc, + struct drm_plane *primary, + struct drm_plane *cursor, + const struct drm_crtc_funcs *funcs, + const char *name, ...); extern void drm_crtc_cleanup(struct drm_crtc *crtc); extern unsigned int drm_crtc_index(struct drm_crtc *crtc); @@ -1214,8 +1768,10 @@ void drm_connector_unregister(struct drm_connector *connector); extern void drm_connector_cleanup(struct drm_connector *connector); extern unsigned int drm_connector_index(struct drm_connector *connector); -/* helper to unplug all connectors from sysfs for device */ -extern void drm_connector_unplug_all(struct drm_device *dev); + +/* helpers to {un}register all connectors from sysfs for device */ +extern int drm_connector_register_all(struct drm_device *dev); +extern void drm_connector_unregister_all(struct drm_device *dev); extern int drm_bridge_add(struct drm_bridge *bridge); extern void drm_bridge_remove(struct drm_bridge *bridge); @@ -1233,10 +1789,11 @@ void drm_bridge_mode_set(struct drm_bridge *bridge, void drm_bridge_pre_enable(struct drm_bridge *bridge); void drm_bridge_enable(struct drm_bridge *bridge); -extern int drm_encoder_init(struct drm_device *dev, - struct drm_encoder *encoder, - const struct drm_encoder_funcs *funcs, - int encoder_type); +extern __printf(5, 6) +int drm_encoder_init(struct drm_device *dev, + struct drm_encoder *encoder, + const struct drm_encoder_funcs *funcs, + int encoder_type, const char *name, ...); /** * drm_encoder_crtc_ok - can a given crtc drive a given encoder? @@ -1251,19 +1808,28 @@ static inline bool drm_encoder_crtc_ok(struct drm_encoder *encoder, return !!(encoder->possible_crtcs & drm_crtc_mask(crtc)); } -extern int drm_universal_plane_init(struct drm_device *dev, - struct drm_plane *plane, - unsigned long possible_crtcs, - const struct drm_plane_funcs *funcs, - const uint32_t *formats, - unsigned int format_count, - enum drm_plane_type type); +extern __printf(8, 9) +int drm_universal_plane_init(struct drm_device *dev, + struct drm_plane *plane, + unsigned long possible_crtcs, + const struct drm_plane_funcs *funcs, + const uint32_t *formats, + unsigned int format_count, + enum drm_plane_type type, + const char *name, ...); extern int drm_plane_init(struct drm_device *dev, struct drm_plane *plane, unsigned long possible_crtcs, const struct drm_plane_funcs *funcs, const uint32_t *formats, unsigned int format_count, bool is_primary); +extern int drm_share_plane_init(struct drm_device *dev, struct drm_plane *plane, + struct drm_plane *parent, + unsigned long possible_crtcs, + const struct drm_plane_funcs *funcs, + const uint32_t *formats, + unsigned int format_count, + enum drm_plane_type type); extern void drm_plane_cleanup(struct drm_plane *plane); extern unsigned int drm_plane_index(struct drm_plane *plane); extern struct drm_plane * drm_plane_from_index(struct drm_device *dev, int idx); @@ -1282,10 +1848,13 @@ extern void drm_encoder_cleanup(struct drm_encoder *encoder); extern const char *drm_get_connector_status_name(enum drm_connector_status status); extern const char *drm_get_subpixel_order_name(enum subpixel_order order); extern const char *drm_get_dpms_name(int val); +extern const char *drm_get_content_protection_name(int val); extern const char *drm_get_dvi_i_subconnector_name(int val); extern const char *drm_get_dvi_i_select_name(int val); extern const char *drm_get_tv_subconnector_name(int val); extern const char *drm_get_tv_select_name(int val); +extern const char *drm_get_content_protection_name(int val); +extern const char *drm_get_connector_name(int val); extern void drm_fb_release(struct drm_file *file_priv); extern void drm_property_destroy_user_blobs(struct drm_device *dev, struct drm_file *file_priv); @@ -1303,6 +1872,8 @@ extern int drm_mode_connector_set_path_property(struct drm_connector *connector, int drm_mode_connector_set_tile_property(struct drm_connector *connector); extern int drm_mode_connector_update_edid_property(struct drm_connector *connector, const struct edid *edid); +int drm_mode_connector_update_hdr_property(struct drm_connector *connector, + const struct hdr_static_metadata *data); extern int drm_display_info_set_bus_formats(struct drm_display_info *info, const u32 *formats, @@ -1380,6 +1951,8 @@ extern int drm_mode_create_tv_properties(struct drm_device *dev, unsigned int num_modes, const char * const modes[]); extern int drm_mode_create_scaling_mode_property(struct drm_device *dev); +extern int drm_connector_attach_content_protection_property( + struct drm_connector *connector); extern int drm_mode_create_aspect_ratio_property(struct drm_device *dev); extern int drm_mode_create_dirty_info_property(struct drm_device *dev); extern int drm_mode_create_suggested_offset_properties(struct drm_device *dev); @@ -1489,6 +2062,7 @@ extern int drm_mode_atomic_ioctl(struct drm_device *dev, extern void drm_fb_get_bpp_depth(uint32_t format, unsigned int *depth, int *bpp); extern int drm_format_num_planes(uint32_t format); +extern int drm_format_plane_bpp(uint32_t format, int plane); extern int drm_format_plane_cpp(uint32_t format, int plane); extern int drm_format_horz_chroma_subsampling(uint32_t format); extern int drm_format_vert_chroma_subsampling(uint32_t format); @@ -1497,6 +2071,10 @@ extern struct drm_property *drm_mode_create_rotation_property(struct drm_device unsigned int supported_rotations); extern unsigned int drm_rotation_simplify(unsigned int rotation, unsigned int supported_rotations); +struct drm_display_mode * +drm_display_mode_from_vic_index(struct drm_connector *connector, + const u8 *video_db, u8 video_len, + u8 video_index); /* Helpers */ @@ -1540,6 +2118,21 @@ static inline struct drm_property *drm_property_find(struct drm_device *dev, return mo ? obj_to_property(mo) : NULL; } +/* + * Extract a degamma/gamma LUT value provided by user and round it to the + * precision supported by the hardware. + */ +static inline uint32_t drm_color_lut_extract(uint32_t user_input, + uint32_t bit_precision) +{ + uint32_t val = user_input + (1 << (16 - bit_precision - 1)); + uint32_t max = 0xffff >> (16 - bit_precision); + + val >>= 16 - bit_precision; + + return clamp_val(val, 0, max); +} + /* Plane list iterator for legacy (overlay only) planes. */ #define drm_for_each_legacy_plane(plane, dev) \ list_for_each_entry(plane, &(dev)->mode_config.plane_list, head) \ diff --git a/include/drm/drm_crtc_helper.h b/include/drm/drm_crtc_helper.h index d842bec3d271..e72e15b72850 100644 --- a/include/drm/drm_crtc_helper.h +++ b/include/drm/drm_crtc_helper.h @@ -139,6 +139,7 @@ struct drm_crtc_helper_funcs { * @mode_set (like shared PLLs). */ struct drm_encoder_helper_funcs { + int (*loader_protect)(struct drm_encoder *encoder, bool on); void (*dpms)(struct drm_encoder *encoder, int mode); void (*save)(struct drm_encoder *encoder); void (*restore)(struct drm_encoder *encoder); @@ -167,20 +168,27 @@ struct drm_encoder_helper_funcs { /** * struct drm_connector_helper_funcs - helper operations for connectors + * @loader_protect: protect loader logo connector's power * @get_modes: get mode list for this connector * @mode_valid: is this mode valid on the given connector? (optional) * @best_encoder: return the preferred encoder for this connector * @atomic_best_encoder: atomic version of @best_encoder + * @atomic_flush: flush atomic update * * The helper operations are called by the mid-layer CRTC helper. */ struct drm_connector_helper_funcs { + int (*loader_protect)(struct drm_connector *connector, bool on); int (*get_modes)(struct drm_connector *connector); enum drm_mode_status (*mode_valid)(struct drm_connector *connector, struct drm_display_mode *mode); struct drm_encoder *(*best_encoder)(struct drm_connector *connector); struct drm_encoder *(*atomic_best_encoder)(struct drm_connector *connector, struct drm_connector_state *connector_state); + void (*atomic_begin)(struct drm_connector *connector, + struct drm_connector_state *conn_state); + void (*atomic_flush)(struct drm_connector *connector, + struct drm_connector_state *conn_state); }; extern void drm_helper_disable_unused_functions(struct drm_device *dev); @@ -189,6 +197,9 @@ extern bool drm_crtc_helper_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, int x, int y, struct drm_framebuffer *old_fb); +extern void drm_helper_crtc_enable_color_mgmt(struct drm_crtc *crtc, + int degamma_lut_size, + int gamma_lut_size); extern bool drm_helper_crtc_in_use(struct drm_crtc *crtc); extern bool drm_helper_encoder_in_use(struct drm_encoder *encoder); diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h index 623b4e98e748..c0d4df6a606f 100644 --- a/include/drm/drm_displayid.h +++ b/include/drm/drm_displayid.h @@ -73,4 +73,21 @@ struct displayid_tiled_block { u8 topology_id[8]; } __packed; +struct displayid_detailed_timings_1 { + u8 pixel_clock[3]; + u8 flags; + u8 hactive[2]; + u8 hblank[2]; + u8 hsync[2]; + u8 hsw[2]; + u8 vactive[2]; + u8 vblank[2]; + u8 vsync[2]; + u8 vsw[2]; +} __packed; + +struct displayid_detailed_timing_block { + struct displayid_block base; + struct displayid_detailed_timings_1 timings[0]; +}; #endif diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 0fb4975fae91..f30553dbac03 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -73,6 +73,7 @@ # define DP_ENHANCED_FRAME_CAP (1 << 7) #define DP_MAX_DOWNSPREAD 0x003 +# define DP_MAX_DOWNSPREAD_0_5 (1 << 0) # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) #define DP_NORP 0x004 @@ -527,6 +528,23 @@ #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0) +#define DP_AUX_HDCP_BKSV 0x68000 +#define DP_AUX_HDCP_RI_PRIME 0x68005 +#define DP_AUX_HDCP_AKSV 0x68007 +#define DP_AUX_HDCP_AN 0x6800C +#define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4) +#define DP_AUX_HDCP_BCAPS 0x68028 +# define DP_BCAPS_REPEATER_PRESENT BIT(1) +# define DP_BCAPS_HDCP_CAPABLE BIT(0) +#define DP_AUX_HDCP_BSTATUS 0x68029 +# define DP_BSTATUS_REAUTH_REQ BIT(3) +# define DP_BSTATUS_LINK_FAILURE BIT(2) +# define DP_BSTATUS_R0_PRIME_READY BIT(1) +# define DP_BSTATUS_READY BIT(0) +#define DP_AUX_HDCP_BINFO 0x6802A +#define DP_AUX_HDCP_KSV_FIFO 0x6802C +#define DP_AUX_HDCP_AINFO 0x6803B + /* DP 1.2 Sideband message defines */ /* peer device type - DP 1.2a Table 2-92 */ #define DP_PEER_DEVICE_NONE 0x0 diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index 2af97691e878..85861b63e77a 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h @@ -24,6 +24,7 @@ #define __DRM_EDID_H__ #include <linux/types.h> +#include <linux/hdmi.h> #define EDID_LENGTH 128 #define DDC_ADDR 0x50 @@ -209,6 +210,14 @@ struct detailed_timing { #define DRM_EDID_HDMI_DC_30 (1 << 4) #define DRM_EDID_HDMI_DC_Y444 (1 << 3) +/* YCBCR 420 deep color modes */ +#define DRM_EDID_YCBCR420_DC_48 (1 << 2) +#define DRM_EDID_YCBCR420_DC_36 (1 << 1) +#define DRM_EDID_YCBCR420_DC_30 (1 << 0) +#define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \ + DRM_EDID_YCBCR420_DC_36 | \ + DRM_EDID_YCBCR420_DC_30) + /* ELD Header Block */ #define DRM_ELD_HEADER_BLOCK_SIZE 4 @@ -332,7 +341,8 @@ int drm_load_edid_firmware(struct drm_connector *connector); int drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, - const struct drm_display_mode *mode); + const struct drm_display_mode *mode, + bool is_hdmi2_sink); int drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, const struct drm_display_mode *mode); @@ -346,6 +356,10 @@ static inline int drm_eld_mnl(const uint8_t *eld) return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT; } +int +drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, + void *hdr_source_metadata); + /** * drm_eld_sad - Get ELD SAD structures. * @eld: pointer to an eld memory structure with sad_count set diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h new file mode 100644 index 000000000000..43f7bd902b41 --- /dev/null +++ b/include/drm/drm_hdcp.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2017 Google, Inc. + * + * Authors: + * Sean Paul <seanpaul@chromium.org> + */ + +#ifndef _DRM_HDCP_H_INCLUDED_ +#define _DRM_HDCP_H_INCLUDED_ + +/* Period of hdcp checks (to ensure we're still authenticated) */ +#define DRM_HDCP_CHECK_PERIOD_MS (128 * 16) + +/* Shared lengths/masks between HDMI/DVI/DisplayPort */ +#define DRM_HDCP_AN_LEN 8 +#define DRM_HDCP_BSTATUS_LEN 2 +#define DRM_HDCP_KSV_LEN 5 +#define DRM_HDCP_RI_LEN 2 +#define DRM_HDCP_V_PRIME_PART_LEN 4 +#define DRM_HDCP_V_PRIME_NUM_PARTS 5 +#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x3f) + +/* Slave address for the HDCP registers in the receiver */ +#define DRM_HDCP_DDC_ADDR 0x3A + +/* HDCP register offsets for HDMI/DVI devices */ +#define DRM_HDCP_DDC_BKSV 0x00 +#define DRM_HDCP_DDC_RI_PRIME 0x08 +#define DRM_HDCP_DDC_AKSV 0x10 +#define DRM_HDCP_DDC_AN 0x18 +#define DRM_HDCP_DDC_V_PRIME(h) (0x20 + h * 4) +#define DRM_HDCP_DDC_BCAPS 0x40 +#define DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT BIT(6) +#define DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY BIT(5) +#define DRM_HDCP_DDC_BSTATUS 0x41 +#define DRM_HDCP_DDC_KSV_FIFO 0x43 + +#endif diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index f1d8d0dbb4f1..4fef19064b0f 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -96,14 +96,17 @@ struct mipi_dsi_host_ops { * struct mipi_dsi_host - DSI host device * @dev: driver model device node for this DSI host * @ops: DSI host operations + * @list: list management */ struct mipi_dsi_host { struct device *dev; const struct mipi_dsi_host_ops *ops; + struct list_head list; }; int mipi_dsi_host_register(struct mipi_dsi_host *host); void mipi_dsi_host_unregister(struct mipi_dsi_host *host); +struct mipi_dsi_host *of_find_mipi_dsi_host_by_node(struct device_node *node); /* DSI mode flags */ @@ -139,10 +142,28 @@ enum mipi_dsi_pixel_format { MIPI_DSI_FMT_RGB565, }; +#define DSI_DEV_NAME_SIZE 20 + +/** + * struct mipi_dsi_device_info - template for creating a mipi_dsi_device + * @type: DSI peripheral chip type + * @channel: DSI virtual channel assigned to peripheral + * @node: pointer to OF device node or NULL + * + * This is populated and passed to mipi_dsi_device_new to create a new + * DSI device + */ +struct mipi_dsi_device_info { + char type[DSI_DEV_NAME_SIZE]; + u32 channel; + struct device_node *node; +}; + /** * struct mipi_dsi_device - DSI peripheral device * @host: DSI host for this peripheral * @dev: driver model device node for this peripheral + * @name: DSI peripheral chip type * @channel: virtual channel assigned to the peripheral * @format: pixel format for video mode * @lanes: number of active data lanes @@ -152,20 +173,54 @@ struct mipi_dsi_device { struct mipi_dsi_host *host; struct device dev; + char name[DSI_DEV_NAME_SIZE]; unsigned int channel; unsigned int lanes; enum mipi_dsi_pixel_format format; unsigned long mode_flags; }; +#define MIPI_DSI_MODULE_PREFIX "mipi-dsi:" + static inline struct mipi_dsi_device *to_mipi_dsi_device(struct device *dev) { return container_of(dev, struct mipi_dsi_device, dev); } +/** + * mipi_dsi_pixel_format_to_bpp - obtain the number of bits per pixel for any + * given pixel format defined by the MIPI DSI + * specification + * @fmt: MIPI DSI pixel format + * + * Returns: The number of bits per pixel of the given pixel format. + */ +static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format fmt) +{ + switch (fmt) { + case MIPI_DSI_FMT_RGB888: + case MIPI_DSI_FMT_RGB666: + return 24; + + case MIPI_DSI_FMT_RGB666_PACKED: + return 18; + + case MIPI_DSI_FMT_RGB565: + return 16; + } + + return -EINVAL; +} + +struct mipi_dsi_device * +mipi_dsi_device_register_full(struct mipi_dsi_host *host, + const struct mipi_dsi_device_info *info); +void mipi_dsi_device_unregister(struct mipi_dsi_device *dsi); struct mipi_dsi_device *of_find_mipi_dsi_device_by_node(struct device_node *np); int mipi_dsi_attach(struct mipi_dsi_device *dsi); int mipi_dsi_detach(struct mipi_dsi_device *dsi); +int mipi_dsi_shutdown_peripheral(struct mipi_dsi_device *dsi); +int mipi_dsi_turn_on_peripheral(struct mipi_dsi_device *dsi); int mipi_dsi_set_maximum_return_packet_size(struct mipi_dsi_device *dsi, u16 value); @@ -214,6 +269,11 @@ int mipi_dsi_dcs_set_tear_off(struct mipi_dsi_device *dsi); int mipi_dsi_dcs_set_tear_on(struct mipi_dsi_device *dsi, enum mipi_dsi_dcs_tear_mode mode); int mipi_dsi_dcs_set_pixel_format(struct mipi_dsi_device *dsi, u8 format); +int mipi_dsi_dcs_set_tear_scanline(struct mipi_dsi_device *dsi, u16 scanline); +int mipi_dsi_dcs_set_display_brightness(struct mipi_dsi_device *dsi, + u16 brightness); +int mipi_dsi_dcs_get_display_brightness(struct mipi_dsi_device *dsi, + u16 *brightness); /** * struct mipi_dsi_driver - DSI driver diff --git a/include/drm/drm_modes.h b/include/drm/drm_modes.h index 08a8cac9e555..0309dbeb8adc 100644 --- a/include/drm/drm_modes.h +++ b/include/drm/drm_modes.h @@ -72,6 +72,7 @@ enum drm_mode_status { MODE_ONE_SIZE, /* only one resolution is supported */ MODE_NO_REDUCED, /* monitor doesn't accept reduced blanking */ MODE_NO_STEREO, /* stereo modes not supported */ + MODE_NO_420, /* ycbcr 420 modes not supported */ MODE_UNVERIFIED = -3, /* mode needs to reverified */ MODE_BAD = -2, /* unspecified reason */ MODE_ERROR = -1 /* error condition */ @@ -179,6 +180,7 @@ static inline bool drm_mode_is_stereo(const struct drm_display_mode *mode) struct drm_connector; struct drm_cmdline_mode; +struct drm_display_info; struct drm_display_mode *drm_mode_create(struct drm_device *dev); void drm_mode_destroy(struct drm_device *dev, struct drm_display_mode *mode); @@ -188,6 +190,12 @@ int drm_mode_convert_umode(struct drm_display_mode *out, const struct drm_mode_modeinfo *in); void drm_mode_probed_add(struct drm_connector *connector, struct drm_display_mode *mode); void drm_mode_debug_printmodeline(const struct drm_display_mode *mode); +bool drm_mode_is_420_only(const struct drm_display_info *display, + const struct drm_display_mode *mode); +bool drm_mode_is_420_also(const struct drm_display_info *display, + const struct drm_display_mode *mode); +bool drm_mode_is_420(const struct drm_display_info *display, + const struct drm_display_mode *mode); struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay, int vdisplay, int vrefresh, @@ -222,6 +230,8 @@ struct drm_display_mode *drm_mode_duplicate(struct drm_device *dev, const struct drm_display_mode *mode); bool drm_mode_equal(const struct drm_display_mode *mode1, const struct drm_display_mode *mode2); +bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1, + const struct drm_display_mode *mode2); bool drm_mode_equal_no_clocks_no_stereo(const struct drm_display_mode *mode1, const struct drm_display_mode *mode2); @@ -229,6 +239,9 @@ bool drm_mode_equal_no_clocks_no_stereo(const struct drm_display_mode *mode1, enum drm_mode_status drm_mode_validate_basic(const struct drm_display_mode *mode); enum drm_mode_status drm_mode_validate_size(const struct drm_display_mode *mode, int maxX, int maxY); +enum drm_mode_status +drm_mode_validate_ycbcr420(const struct drm_display_mode *mode, + struct drm_connector *connector); void drm_mode_prune_invalid(struct drm_device *dev, struct list_head *mode_list, bool verbose); void drm_mode_sort(struct list_head *mode_list); diff --git a/include/drm/drm_modeset_lock.h b/include/drm/drm_modeset_lock.h index 94938d89347c..c5576fbcb909 100644 --- a/include/drm/drm_modeset_lock.h +++ b/include/drm/drm_modeset_lock.h @@ -138,7 +138,7 @@ void drm_warn_on_modeset_not_all_locked(struct drm_device *dev); struct drm_modeset_acquire_ctx * drm_modeset_legacy_acquire_ctx(struct drm_crtc *crtc); -int drm_modeset_lock_all_crtcs(struct drm_device *dev, - struct drm_modeset_acquire_ctx *ctx); +int drm_modeset_lock_all_ctx(struct drm_device *dev, + struct drm_modeset_acquire_ctx *ctx); #endif /* DRM_MODESET_LOCK_H_ */ diff --git a/include/drm/drm_of.h b/include/drm/drm_of.h index 8544665ee4f4..74710f5e5cbf 100644 --- a/include/drm/drm_of.h +++ b/include/drm/drm_of.h @@ -1,9 +1,14 @@ #ifndef __DRM_OF_H__ #define __DRM_OF_H__ +#include <linux/of_graph.h> + struct component_master_ops; struct device; struct drm_device; +struct drm_encoder; +struct drm_panel; +struct drm_bridge; struct device_node; #ifdef CONFIG_OF @@ -12,6 +17,13 @@ extern uint32_t drm_of_find_possible_crtcs(struct drm_device *dev, extern int drm_of_component_probe(struct device *dev, int (*compare_of)(struct device *, void *), const struct component_master_ops *m_ops); +extern int drm_of_encoder_active_endpoint(struct device_node *node, + struct drm_encoder *encoder, + struct of_endpoint *endpoint); +int drm_of_find_panel_or_bridge(const struct device_node *np, + int port, int endpoint, + struct drm_panel **panel, + struct drm_bridge **bridge); #else static inline uint32_t drm_of_find_possible_crtcs(struct drm_device *dev, struct device_node *port) @@ -26,6 +38,40 @@ drm_of_component_probe(struct device *dev, { return -EINVAL; } + +static inline int drm_of_encoder_active_endpoint(struct device_node *node, + struct drm_encoder *encoder, + struct of_endpoint *endpoint) +{ + return -EINVAL; +} +static inline int drm_of_find_panel_or_bridge(const struct device_node *np, + int port, int endpoint, + struct drm_panel **panel, + struct drm_bridge **bridge) +{ + return -EINVAL; +} #endif +static inline int drm_of_encoder_active_endpoint_id(struct device_node *node, + struct drm_encoder *encoder) +{ + struct of_endpoint endpoint; + int ret = drm_of_encoder_active_endpoint(node, encoder, + &endpoint); + + return ret ?: endpoint.id; +} + +static inline int drm_of_encoder_active_port_id(struct device_node *node, + struct drm_encoder *encoder) +{ + struct of_endpoint endpoint; + int ret = drm_of_encoder_active_endpoint(node, encoder, + &endpoint); + + return ret ?: endpoint.port; +} + #endif /* __DRM_OF_H__ */ diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h index 13ff44b28893..bc4d0091979a 100644 --- a/include/drm/drm_panel.h +++ b/include/drm/drm_panel.h @@ -33,6 +33,7 @@ struct display_timing; /** * struct drm_panel_funcs - perform operations on a given panel + * @loader_protect: protect loader logo panel's power * @disable: disable panel (turn off back light, etc.) * @unprepare: turn off panel * @prepare: turn on panel and perform set up @@ -66,6 +67,7 @@ struct display_timing; * the panel. This is the job of the .unprepare() function. */ struct drm_panel_funcs { + int (*loader_protect)(struct drm_panel *panel, bool on); int (*disable)(struct drm_panel *panel); int (*unprepare)(struct drm_panel *panel); int (*prepare)(struct drm_panel *panel); @@ -101,6 +103,14 @@ static inline int drm_panel_disable(struct drm_panel *panel) return panel ? -ENOSYS : -EINVAL; } +static inline int drm_panel_loader_protect(struct drm_panel *panel, bool on) +{ + if (panel && panel->funcs && panel->funcs->loader_protect) + return panel->funcs->loader_protect(panel, on); + + return panel ? -ENOSYS : -EINVAL; +} + static inline int drm_panel_prepare(struct drm_panel *panel) { if (panel && panel->funcs && panel->funcs->prepare) @@ -133,6 +143,10 @@ void drm_panel_remove(struct drm_panel *panel); int drm_panel_attach(struct drm_panel *panel, struct drm_connector *connector); int drm_panel_detach(struct drm_panel *panel); +int rockchip_drm_crtc_send_mcu_cmd(struct drm_device *drm_dev, + struct device_node *np_crtc, + u32 type, u32 value); +struct drm_panel *drm_find_panel_by_connector(struct drm_connector *connector); #ifdef CONFIG_OF struct drm_panel *of_drm_find_panel(struct device_node *np); #else diff --git a/include/drm/drm_scdc_helper.h b/include/drm/drm_scdc_helper.h new file mode 100644 index 000000000000..dacf65a6ca18 --- /dev/null +++ b/include/drm/drm_scdc_helper.h @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2015 NVIDIA Corporation. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef DRM_SCDC_HELPER_H +#define DRM_SCDC_HELPER_H + +#include <linux/i2c.h> +#include <linux/types.h> + +#define SCDC_SINK_VERSION 0x01 +#define SCDC_SOURCE_VERSION 0x02 + +#define SCDC_UPDATE_0 0x10 +#define SCDC_READ_REQUEST_TEST (1 << 2) +#define SCDC_CED_UPDATE (1 << 1) +#define SCDC_STATUS_UPDATE (1 << 0) +#define SCDC_UPDATE_1 0x11 + +#define SCDC_TMDS_CONFIG 0x20 +#define SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 (1 << 1) +#define SCDC_TMDS_BIT_CLOCK_RATIO_BY_10 (0 << 1) +#define SCDC_SCRAMBLING_ENABLE (1 << 0) +#define SCDC_SCRAMBLER_STATUS 0x21 +#define SCDC_SCRAMBLING_STATUS (1 << 0) + +#define SCDC_CONFIG_0 0x30 +#define SCDC_READ_REQUEST_ENABLE (1 << 0) + +#define SCDC_STATUS_FLAGS_0 0x40 +#define SCDC_CH2_LOCK (1 < 3) +#define SCDC_CH1_LOCK (1 < 2) +#define SCDC_CH0_LOCK (1 < 1) +#define SCDC_CH_LOCK_MASK (SCDC_CH2_LOCK | SCDC_CH1_LOCK | SCDC_CH0_LOCK) +#define SCDC_CLOCK_DETECT (1 << 0) +#define SCDC_STATUS_FLAGS_1 0x41 + +#define SCDC_ERR_DET_0_L 0x50 +#define SCDC_ERR_DET_0_H 0x51 +#define SCDC_ERR_DET_1_L 0x52 +#define SCDC_ERR_DET_1_H 0x53 +#define SCDC_ERR_DET_2_L 0x54 +#define SCDC_ERR_DET_2_H 0x55 +#define SCDC_CHANNEL_VALID (1 << 7) +#define SCDC_ERR_DET_CHECKSUM 0x56 + +#define SCDC_TEST_CONFIG_0 0xc0 +#define SCDC_TEST_READ_REQUEST (1 << 7) +#define SCDC_TEST_READ_REQUEST_DELAY(x) ((x) & 0x7f) + +#define SCDC_MANUFACTURER_IEEE_OUI 0xd0 +#define SCDC_MANUFACTURER_IEEE_OUI_SIZE 3 +#define SCDC_DEVICE_ID 0xd3 +#define SCDC_DEVICE_ID_SIZE 8 +#define SCDC_DEVICE_HARDWARE_REVISION 0xdb +#define SCDC_DEVICE_HARDWARE_REVISION_MAJOR(x) (((x) >> 4) & 0xf) +#define SCDC_DEVICE_HARDWARE_REVISION_MINOR(x) (((x) >> 0) & 0xf) +#define SCDC_DEVICE_SOFTWARE_MAJOR_REVISION 0xdc +#define SCDC_DEVICE_SOFTWARE_MINOR_REVISION 0xdd + +#define SCDC_MANUFACTURER_SPECIFIC 0xde +#define SCDC_MANUFACTURER_SPECIFIC_SIZE 34 + +ssize_t drm_scdc_read(struct i2c_adapter *adapter, u8 offset, void *buffer, + size_t size); +ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset, + const void *buffer, size_t size); + +/** + * drm_scdc_readb - read a single byte from SCDC + * @adapter: I2C adapter + * @offset: offset of register to read + * @value: return location for the register value + * + * Reads a single byte from SCDC. This is a convenience wrapper around the + * drm_scdc_read() function. + * + * Returns: + * 0 on success or a negative error code on failure. + */ +static inline int drm_scdc_readb(struct i2c_adapter *adapter, u8 offset, + u8 *value) +{ + return drm_scdc_read(adapter, offset, value, sizeof(*value)); +} + +/** + * drm_scdc_writeb - write a single byte to SCDC + * @adapter: I2C adapter + * @offset: offset of register to read + * @value: return location for the register value + * + * Writes a single byte to SCDC. This is a convenience wrapper around the + * drm_scdc_write() function. + * + * Returns: + * 0 on success or a negative error code on failure. + */ +static inline int drm_scdc_writeb(struct i2c_adapter *adapter, u8 offset, + u8 value) +{ + return drm_scdc_write(adapter, offset, &value, sizeof(value)); +} + +/** + * drm_scdc_set_scrambling - enable scrambling + * @adapter: I2C adapter for DDC channel + * @enable: bool to indicate if scrambling is to be enabled/disabled + * + * Writes the TMDS config register over SCDC channel, and: + * enables scrambling when enable = 1 + * disables scrambling when enable = 0 + * + * Returns: + * True if scrambling is set/reset successfully, false otherwise. + */ +bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable); + +/** + * drm_scdc_set_high_tmds_clock_ratio - set TMDS clock ratio + * @adapter: I2C adapter for DDC channel + * @set: ret or reset the high clock ratio + * + * Writes to the TMDS config register over SCDC channel, and: + * sets TMDS clock ratio to 1/40 when set = 1 + * sets TMDS clock ratio to 1/10 when set = 0 + * + * Returns: + * True if write is successful, false otherwise. + */ +bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set); +#endif diff --git a/include/drm/drm_sync_helper.h b/include/drm/drm_sync_helper.h new file mode 100644 index 000000000000..a5586c674fec --- /dev/null +++ b/include/drm/drm_sync_helper.h @@ -0,0 +1,156 @@ +/* + * drm_sync_helper.h: software fence and helper functions for fences and + * reservations used for dma buffer access synchronization between drivers. + * + * Copyright 2014 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DRM_SYNC_HELPER_H_ +#define _DRM_SYNC_HELPER_H_ + +#include <linux/fence.h> +#include <linux/reservation.h> +#include <linux/atomic.h> +#include <linux/workqueue.h> + +/** + * Create software fence + * @context: execution context + * @seqno: the sequence number of this fence inside the execution context + */ +struct fence *drm_sw_fence_new(unsigned int context, + unsigned seqno); + +/** + * Signal and decrease reference count for a fence if it exists + * @fence: fence to signal + * + * Utility function called when owner access to object associated with fence is + * finished (e.g. GPU done with rendering). + */ +static inline void drm_fence_signal_and_put(struct fence **fence) +{ + if (*fence) { + fence_signal(*fence); + fence_put(*fence); + *fence = NULL; + } +} + +struct drm_reservation_cb; + +struct drm_reservation_fence_cb { + struct fence_cb base; + struct drm_reservation_cb *parent; + struct fence *fence; +}; + +/** + * Callback executed when all fences in reservation callback are signaled + * @rcb: reservation callback structure + * @context: context provided by user at init time + */ +typedef void (*drm_reservation_cb_func_t)(struct drm_reservation_cb *rcb, + void *context); + +/** + * Reservation callback structure + * @work: work context in which func is executed + * @fence_cbs: fence callbacks array + * @num_fence_cbs: number of fence callbacks + * @count: count of signaled fences, when it drops to 0 func is called + * @func: callback to execute when all fences are signaled + * @context: context provided by user during initialization + * + * It is safe and expected that func will destroy this structure before + * returning. + */ +struct drm_reservation_cb { + struct work_struct work; + struct drm_reservation_fence_cb **fence_cbs; + unsigned num_fence_cbs; + atomic_t count; + void *context; + drm_reservation_cb_func_t func; +}; + +/** + * Initialize reservation callback + * @rcb: reservation callback structure to initialize + * @func: function to call when all fences are signaled + * @context: parameter to call func with + */ +void drm_reservation_cb_init(struct drm_reservation_cb *rcb, + drm_reservation_cb_func_t func, + void *context); + +/** + * Add fences from reservation object to callback + * @rcb: reservation callback structure + * @resv: reservation object + * @exclusive: (for exclusive wait) when true add all fences, otherwise only + * exclusive fence + */ +int drm_reservation_cb_add(struct drm_reservation_cb *rcb, + struct reservation_object *resv, + bool exclusive); + +/** + * Finish adding fences + * @rcb: reservation callback structure + * + * It will trigger callback worker if all fences were signaled before. + */ +void drm_reservation_cb_done(struct drm_reservation_cb *rcb); + +/** + * Cleanup reservation callback structure + * @rcb: reservation callback structure + * + * Can be called to cancel primed reservation callback. + */ +void drm_reservation_cb_fini(struct drm_reservation_cb *rcb); + +/** + * Add reservation to array of reservations + * @resv: reservation to add + * @resvs: array of reservations + * @excl_resvs_bitmap: bitmap for exclusive reservations + * @num_resvs: number of reservations in array + * @exclusive: bool to store in excl_resvs_bitmap + */ +void +drm_add_reservation(struct reservation_object *resv, + struct reservation_object **resvs, + unsigned long *excl_resvs_bitmap, + unsigned int *num_resvs, bool exclusive); + +/** + * Acquire ww_mutex lock on all reservations in the array + * @resvs: array of reservations + * @num_resvs: number of reservations in the array + * @ctx: ww mutex context + */ +int drm_lock_reservations(struct reservation_object **resvs, + unsigned int num_resvs, struct ww_acquire_ctx *ctx); + +/** + * Release ww_mutex lock on all reservations in the array + * @resvs: array of reservations + * @num_resvs: number of reservations in the array + * @ctx: ww mutex context + */ +void drm_unlock_reservations(struct reservation_object **resvs, + unsigned int num_resvs, + struct ww_acquire_ctx *ctx); + +#endif diff --git a/include/dt-bindings/clock/px30-cru.h b/include/dt-bindings/clock/px30-cru.h new file mode 100644 index 000000000000..644d1f5d26d0 --- /dev/null +++ b/include/dt-bindings/clock/px30-cru.h @@ -0,0 +1,406 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Author: Elaine <zhangqing@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H +#define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_NPLL 4 +#define APLL_BOOST_H 5 +#define APLL_BOOST_L 6 +#define ARMCLK 7 + +/* sclk gates (special clocks) */ +#define USB480M 14 +#define SCLK_PDM 15 +#define SCLK_I2S0_TX 16 +#define SCLK_I2S0_TX_OUT 17 +#define SCLK_I2S0_RX 18 +#define SCLK_I2S0_RX_OUT 19 +#define SCLK_I2S1 20 +#define SCLK_I2S1_OUT 21 +#define SCLK_I2S2 22 +#define SCLK_I2S2_OUT 23 +#define SCLK_UART1 24 +#define SCLK_UART2 25 +#define SCLK_UART3 26 +#define SCLK_UART4 27 +#define SCLK_UART5 28 +#define SCLK_I2C0 29 +#define SCLK_I2C1 30 +#define SCLK_I2C2 31 +#define SCLK_I2C3 32 +#define SCLK_I2C4 33 +#define SCLK_PWM0 34 +#define SCLK_PWM1 35 +#define SCLK_SPI0 36 +#define SCLK_SPI1 37 +#define SCLK_TIMER0 38 +#define SCLK_TIMER1 39 +#define SCLK_TIMER2 40 +#define SCLK_TIMER3 41 +#define SCLK_TIMER4 42 +#define SCLK_TIMER5 43 +#define SCLK_TSADC 44 +#define SCLK_SARADC 45 +#define SCLK_OTP 46 +#define SCLK_OTP_USR 47 +#define SCLK_CRYPTO 48 +#define SCLK_CRYPTO_APK 49 +#define SCLK_DDRC 50 +#define SCLK_ISP 51 +#define SCLK_CIF_OUT 52 +#define SCLK_RGA_CORE 53 +#define SCLK_VOPB_PWM 54 +#define SCLK_NANDC 55 +#define SCLK_SDIO 56 +#define SCLK_EMMC 57 +#define SCLK_SFC 58 +#define SCLK_SDMMC 59 +#define SCLK_OTG_ADP 60 +#define SCLK_GMAC_SRC 61 +#define SCLK_GMAC 62 +#define SCLK_GMAC_RX_TX 63 +#define SCLK_MAC_REF 64 +#define SCLK_MAC_REFOUT 65 +#define SCLK_MAC_OUT 66 +#define SCLK_SDMMC_DRV 67 +#define SCLK_SDMMC_SAMPLE 68 +#define SCLK_SDIO_DRV 69 +#define SCLK_SDIO_SAMPLE 70 +#define SCLK_EMMC_DRV 71 +#define SCLK_EMMC_SAMPLE 72 +#define SCLK_GPU 73 +#define SCLK_PVTM 74 +#define SCLK_CORE_VPU 75 +#define SCLK_GMAC_RMII 76 +#define SCLK_UART2_SRC 77 +#define SCLK_NANDC_DIV 78 +#define SCLK_NANDC_DIV50 79 +#define SCLK_SDIO_DIV 80 +#define SCLK_SDIO_DIV50 81 +#define SCLK_EMMC_DIV 82 +#define SCLK_EMMC_DIV50 83 +#define SCLK_DDRCLK 84 +#define SCLK_UART1_SRC 85 +#define SCLK_SDMMC_DIV 86 +#define SCLK_SDMMC_DIV50 87 +#define SCLK_I2S0_TX_MUX 88 +#define SCLK_I2S0_RX_MUX 89 + +/* dclk gates */ +#define DCLK_VOPB 150 +#define DCLK_VOPL 151 + +/* aclk gates */ +#define ACLK_GPU 170 +#define ACLK_BUS_PRE 171 +#define ACLK_CRYPTO 172 +#define ACLK_VI_PRE 173 +#define ACLK_VO_PRE 174 +#define ACLK_VPU 175 +#define ACLK_PERI_PRE 176 +#define ACLK_GMAC 178 +#define ACLK_CIF 179 +#define ACLK_ISP 180 +#define ACLK_VOPB 181 +#define ACLK_VOPL 182 +#define ACLK_RGA 183 +#define ACLK_GIC 184 +#define ACLK_DCF 186 +#define ACLK_DMAC 187 +#define ACLK_BUS_SRC 188 +#define ACLK_PERI_SRC 189 + +/* hclk gates */ +#define HCLK_BUS_PRE 240 +#define HCLK_CRYPTO 241 +#define HCLK_VI_PRE 242 +#define HCLK_VO_PRE 243 +#define HCLK_VPU 244 +#define HCLK_PERI_PRE 245 +#define HCLK_MMC_NAND 246 +#define HCLK_SDMMC 247 +#define HCLK_USB 248 +#define HCLK_CIF 249 +#define HCLK_ISP 250 +#define HCLK_VOPB 251 +#define HCLK_VOPL 252 +#define HCLK_RGA 253 +#define HCLK_NANDC 254 +#define HCLK_SDIO 255 +#define HCLK_EMMC 256 +#define HCLK_SFC 257 +#define HCLK_OTG 258 +#define HCLK_HOST 259 +#define HCLK_HOST_ARB 260 +#define HCLK_PDM 261 +#define HCLK_I2S0 262 +#define HCLK_I2S1 263 +#define HCLK_I2S2 264 + +/* pclk gates */ +#define PCLK_BUS_PRE 320 +#define PCLK_DDR 321 +#define PCLK_VO_PRE 322 +#define PCLK_GMAC 323 +#define PCLK_MIPI_DSI 324 +#define PCLK_MIPIDSIPHY 325 +#define PCLK_MIPICSIPHY 326 +#define PCLK_USB_GRF 327 +#define PCLK_DCF 328 +#define PCLK_UART1 329 +#define PCLK_UART2 330 +#define PCLK_UART3 331 +#define PCLK_UART4 332 +#define PCLK_UART5 333 +#define PCLK_I2C0 334 +#define PCLK_I2C1 335 +#define PCLK_I2C2 336 +#define PCLK_I2C3 337 +#define PCLK_I2C4 338 +#define PCLK_PWM0 339 +#define PCLK_PWM1 340 +#define PCLK_SPI0 341 +#define PCLK_SPI1 342 +#define PCLK_SARADC 343 +#define PCLK_TSADC 344 +#define PCLK_TIMER 345 +#define PCLK_OTP_NS 346 +#define PCLK_WDT_NS 347 +#define PCLK_GPIO1 348 +#define PCLK_GPIO2 349 +#define PCLK_GPIO3 350 +#define PCLK_ISP 351 +#define PCLK_CIF 352 +#define PCLK_OTP_PHY 353 + +#define CLK_NR_CLKS (PCLK_OTP_PHY + 1) + +/* pmu-clocks indices */ + +#define PLL_GPLL 1 + +#define SCLK_RTC32K_PMU 4 +#define SCLK_WIFI_PMU 5 +#define SCLK_UART0_PMU 6 +#define SCLK_PVTM_PMU 7 +#define PCLK_PMU_PRE 8 +#define SCLK_REF24M_PMU 9 +#define SCLK_USBPHY_REF 10 +#define SCLK_MIPIDSIPHY_REF 11 + +#define XIN24M_DIV 12 + +#define PCLK_GPIO0_PMU 20 +#define PCLK_UART0_PMU 21 + +#define CLKPMU_NR_CLKS (PCLK_UART0_PMU + 1) + +/* soft-reset indices */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_CORE_NOC 13 +#define SRST_STRC_A 14 +#define SRST_L2C 15 + +#define SRST_DAP 16 +#define SRST_CORE_PVTM 17 +#define SRST_GPU 18 +#define SRST_GPU_NIU 19 +#define SRST_UPCTL2 20 +#define SRST_UPCTL2_A 21 +#define SRST_UPCTL2_P 22 +#define SRST_MSCH 23 +#define SRST_MSCH_P 24 +#define SRST_DDRMON_P 25 +#define SRST_DDRSTDBY_P 26 +#define SRST_DDRSTDBY 27 +#define SRST_DDRGRF_p 28 +#define SRST_AXI_SPLIT_A 29 +#define SRST_AXI_CMD_A 30 +#define SRST_AXI_CMD_P 31 + +#define SRST_DDRPHY 32 +#define SRST_DDRPHYDIV 33 +#define SRST_DDRPHY_P 34 +#define SRST_VPU_A 36 +#define SRST_VPU_NIU_A 37 +#define SRST_VPU_H 38 +#define SRST_VPU_NIU_H 39 +#define SRST_VI_NIU_A 40 +#define SRST_VI_NIU_H 41 +#define SRST_ISP_H 42 +#define SRST_ISP 43 +#define SRST_CIF_A 44 +#define SRST_CIF_H 45 +#define SRST_CIF_PCLKIN 46 +#define SRST_MIPICSIPHY_P 47 + +#define SRST_VO_NIU_A 48 +#define SRST_VO_NIU_H 49 +#define SRST_VO_NIU_P 50 +#define SRST_VOPB_A 51 +#define SRST_VOPB_H 52 +#define SRST_VOPB 53 +#define SRST_PWM_VOPB 54 +#define SRST_VOPL_A 55 +#define SRST_VOPL_H 56 +#define SRST_VOPL 57 +#define SRST_RGA_A 58 +#define SRST_RGA_H 59 +#define SRST_RGA 60 +#define SRST_MIPIDSI_HOST_P 61 +#define SRST_MIPIDSIPHY_P 62 +#define SRST_VPU_CORE 63 + +#define SRST_PERI_NIU_A 64 +#define SRST_USB_NIU_H 65 +#define SRST_USB2OTG_H 66 +#define SRST_USB2OTG 67 +#define SRST_USB2OTG_ADP 68 +#define SRST_USB2HOST_H 69 +#define SRST_USB2HOST_ARB_H 70 +#define SRST_USB2HOST_AUX_H 71 +#define SRST_USB2HOST_EHCI 72 +#define SRST_USB2HOST 73 +#define SRST_USBPHYPOR 74 +#define SRST_USBPHY_OTG_PORT 75 +#define SRST_USBPHY_HOST_PORT 76 +#define SRST_USBPHY_GRF 77 +#define SRST_CPU_BOOST_P 78 +#define SRST_CPU_BOOST 79 + +#define SRST_MMC_NAND_NIU_H 80 +#define SRST_SDIO_H 81 +#define SRST_EMMC_H 82 +#define SRST_SFC_H 83 +#define SRST_SFC 84 +#define SRST_SDCARD_NIU_H 85 +#define SRST_SDMMC_H 86 +#define SRST_NANDC_H 89 +#define SRST_NANDC 90 +#define SRST_GMAC_NIU_A 92 +#define SRST_GMAC_NIU_P 93 +#define SRST_GMAC_A 94 + +#define SRST_PMU_NIU_P 96 +#define SRST_PMU_SGRF_P 97 +#define SRST_PMU_GRF_P 98 +#define SRST_PMU 99 +#define SRST_PMU_MEM_P 100 +#define SRST_PMU_GPIO0_P 101 +#define SRST_PMU_UART0_P 102 +#define SRST_PMU_CRU_P 103 +#define SRST_PMU_PVTM 104 +#define SRST_PMU_UART 105 +#define SRST_PMU_NIU_H 106 +#define SRST_PMU_DDR_FAIL_SAVE 107 +#define SRST_PMU_CORE_PERF_A 108 +#define SRST_PMU_CORE_GRF_P 109 +#define SRST_PMU_GPU_PERF_A 110 +#define SRST_PMU_GPU_GRF_P 111 + +#define SRST_CRYPTO_NIU_A 112 +#define SRST_CRYPTO_NIU_H 113 +#define SRST_CRYPTO_A 114 +#define SRST_CRYPTO_H 115 +#define SRST_CRYPTO 116 +#define SRST_CRYPTO_APK 117 +#define SRST_BUS_NIU_H 120 +#define SRST_USB_NIU_P 121 +#define SRST_BUS_TOP_NIU_P 122 +#define SRST_INTMEM_A 123 +#define SRST_GIC_A 124 +#define SRST_ROM_H 126 +#define SRST_DCF_A 127 + +#define SRST_DCF_P 128 +#define SRST_PDM_H 129 +#define SRST_PDM 130 +#define SRST_I2S0_H 131 +#define SRST_I2S0_TX 132 +#define SRST_I2S1_H 133 +#define SRST_I2S1 134 +#define SRST_I2S2_H 135 +#define SRST_I2S2 136 +#define SRST_UART1_P 137 +#define SRST_UART1 138 +#define SRST_UART2_P 139 +#define SRST_UART2 140 +#define SRST_UART3_P 141 +#define SRST_UART3 142 +#define SRST_UART4_P 143 + +#define SRST_UART4 144 +#define SRST_UART5_P 145 +#define SRST_UART5 146 +#define SRST_I2C0_P 147 +#define SRST_I2C0 148 +#define SRST_I2C1_P 149 +#define SRST_I2C1 150 +#define SRST_I2C2_P 151 +#define SRST_I2C2 152 +#define SRST_I2C3_P 153 +#define SRST_I2C3 154 +#define SRST_PWM0_P 157 +#define SRST_PWM0 158 +#define SRST_PWM1_P 159 + +#define SRST_PWM1 160 +#define SRST_SPI0_P 161 +#define SRST_SPI0 162 +#define SRST_SPI1_P 163 +#define SRST_SPI1 164 +#define SRST_SARADC_P 165 +#define SRST_SARADC 166 +#define SRST_TSADC_P 167 +#define SRST_TSADC 168 +#define SRST_TIMER_P 169 +#define SRST_TIMER0 170 +#define SRST_TIMER1 171 +#define SRST_TIMER2 172 +#define SRST_TIMER3 173 +#define SRST_TIMER4 174 +#define SRST_TIMER5 175 + +#define SRST_OTP_NS_P 176 +#define SRST_OTP_NS_SBPI 177 +#define SRST_OTP_NS_USR 178 +#define SRST_OTP_PHY_P 179 +#define SRST_OTP_PHY 180 +#define SRST_WDT_NS_P 181 +#define SRST_GPIO1_P 182 +#define SRST_GPIO2_P 183 +#define SRST_GPIO3_P 184 +#define SRST_SGRF_P 185 +#define SRST_GRF_P 186 +#define SRST_I2S0_RX 191 + +#endif diff --git a/include/dt-bindings/clock/rk1808-cru.h b/include/dt-bindings/clock/rk1808-cru.h new file mode 100644 index 000000000000..3dd5c76d5295 --- /dev/null +++ b/include/dt-bindings/clock/rk1808-cru.h @@ -0,0 +1,472 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK1808_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK1808_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define PLL_NPLL 5 +#define PLL_PPLL 6 +#define ARMCLK 7 + +#define DCLK_VOPRAW 10 +#define DCLK_VOPLITE 11 +#define DCLK_CIF 12 +#define XIN24M_DIV 13 + +/* sclk (special clocks) */ +#define USB480M 20 +#define SCLK_PVTM_CORE 21 +#define SCLK_NPU 22 +#define SCLK_PVTM_NPU 23 +#define SCLK_DDRCLK 24 +#define SCLK_I2S0_8CH_TX_MUX 25 +#define SCLK_I2S0_8CH_RX_MUX 26 +#define SCLK_RTC32K_PMU 27 +#define SCLK_TXESC 28 +#define SCLK_RGA 29 +#define SCLK_ISP 30 +#define SCLK_CIF_OUT 31 +#define SCLK_PCIE_AUX 32 +#define SCLK_USB3_OTG0_REF 33 +#define SCLK_USB3_OTG0_SUSPEND 34 +#define SCLK_SDIO_DIV 35 +#define SCLK_SDIO_DIV50 36 +#define SCLK_SDIO 37 +#define SCLK_SDIO_DRV 38 +#define SCLK_SDIO_SAMPLE 39 +#define SCLK_EMMC_DIV 40 +#define SCLK_EMMC_DIV50 41 +#define SCLK_EMMC 42 +#define SCLK_EMMC_DRV 43 +#define SCLK_EMMC_SAMPLE 44 +#define SCLK_SDMMC_DIV 45 +#define SCLK_SDMMC_DIV50 46 +#define SCLK_SDMMC 47 +#define SCLK_SDMMC_DRV 48 +#define SCLK_SDMMC_SAMPLE 49 +#define SCLK_SFC 50 +#define SCLK_GMAC_OUT 51 +#define SCLK_GMAC_SRC 52 +#define SCLK_GMAC 53 +#define SCLK_GMAC_REF 54 +#define SCLK_GMAC_REFOUT 55 +#define SCLK_GMAC_RGMII_SPEED 56 +#define SCLK_GMAC_RMII_SPEED 57 +#define SCLK_GMAC_RX_TX 58 +#define SCLK_CRYPTO 59 +#define SCLK_CRYPTO_APK 60 +#define SCLK_UART1 61 +#define SCLK_UART2 62 +#define SCLK_UART3 63 +#define SCLK_UART4 64 +#define SCLK_UART5 65 +#define SCLK_UART6 66 +#define SCLK_UART7 67 +#define SCLK_I2C1 68 +#define SCLK_I2C2 69 +#define SCLK_I2C3 70 +#define SCLK_I2C4 71 +#define SCLK_I2C5 72 +#define SCLK_SPI0 73 +#define SCLK_SPI1 74 +#define SCLK_SPI2 75 +#define SCLK_TSADC 76 +#define SCLK_SARADC 77 +#define SCLK_EFUSE_S 78 +#define SCLK_EFUSE_NS 79 +#define DBCLK_GPIO1 80 +#define DBCLK_GPIO2 81 +#define DBCLK_GPIO3 82 +#define DBCLK_GPIO4 83 +#define SCLK_PWM0 84 +#define SCLK_PWM1 85 +#define SCLK_PWM2 86 +#define SCLK_TIMER0 87 +#define SCLK_TIMER1 88 +#define SCLK_TIMER2 89 +#define SCLK_TIMER3 90 +#define SCLK_TIMER4 91 +#define SCLK_TIMER5 92 +#define SCLK_PDM 93 +#define SCLK_I2S0_8CH_TX_SRC 94 +#define SCLK_I2S0_8CH_TX 95 +#define SCLK_I2S0_8CH_TX_OUT 96 +#define SCLK_I2S0_8CH_RX_SRC 97 +#define SCLK_I2S0_8CH_RX 98 +#define SCLK_I2S0_8CH_RX_OUT 99 +#define SCLK_I2S1_2CH_SRC 100 +#define SCLK_I2S1_2CH 101 +#define SCLK_I2S1_2CH_OUT 102 +#define SCLK_WIFI_PMU 103 +#define SCLK_UART0_PMU 104 +#define SCLK_PVTM_PMU 105 +#define SCLK_PMU_I2C0 106 +#define DBCLK_PMU_GPIO0 107 +#define SCLK_REF24M_PMU 108 +#define SCLK_USBPHY_REF 109 +#define SCLK_MIPIDSIPHY_REF 110 +#define SCLK_PCIEPHY_REF 111 +#define SCLK_RTC32K_FRAC 112 + +/* aclk gates */ +#define ACLK_GIC_PRE 145 +#define ACLK_GIC 146 +#define ACLK_VPU 147 +#define ACLK_NPU 148 +#define ACLK_IMEM_PRE 153 +#define ACLK_IMEM0 154 +#define ACLK_IMEM1 155 +#define ACLK_IMEM2 156 +#define ACLK_IMEM3 157 +#define HSCLK_VIO 158 +#define ACLK_VOPRAW 159 +#define ACLK_VOPLITE 160 +#define ACLK_RGA 161 +#define ACLK_ISP 162 +#define ACLK_CIF 163 +#define HSCLK_PCIE 164 +#define ACLK_USB3OTG 165 +#define ACLK_PCIE 166 +#define ACLK_PCIE_MST 167 +#define ACLK_PCIE_SLV 168 +#define MSCLK_PERI 169 +#define ACLK_GMAC 170 +#define HSCLK_BUS_PRE 171 +#define ACLK_CRYPTO 172 +#define ACLK_DCF 173 +#define ACLK_DMAC 174 + +/* hclk gates */ +#define HCLK_NPU 199 +#define HCLK_VPU 200 +#define LSCLK_VIO 201 +#define HCLK_VOPRAW 202 +#define HCLK_VOPLITE 203 +#define HCLK_RGA 204 +#define HCLK_ISP 205 +#define LSCLK_PCIE 206 +#define HCLK_HOST 207 +#define LSCLK_PERI 208 +#define HCLK_SDIO 209 +#define HCLK_EMMC 210 +#define HCLK_SDMMC 211 +#define HCLK_SFC 212 +#define MSCLK_BUS_PRE 213 +#define HCLK_ROM 214 +#define HCLK_CRYPTO 215 +#define HCLK_VAD 216 +#define HCLK_PDM 217 +#define HCLK_I2S0_8CH 218 +#define HCLK_I2S1_2CH 219 +#define MSCLK_CORE_NIU 220 +#define HSCLK_IMEM 221 +#define HCLK_HOST_ARB 222 +#define HCLK_CIF 223 + +/* pclk gates */ +#define PCLK_DDR 250 +#define PCLK_DSI_TX 251 +#define PCLK_CSI_TX 252 +#define PCLK_CSI2HOST 253 +#define PCLK_PCIE 254 +#define PCLK_GMAC 255 +#define LSCLK_BUS_PRE 256 +#define PCLK_DCF 257 +#define PCLK_UART1 258 +#define PCLK_UART2 259 +#define PCLK_UART3 260 +#define PCLK_UART4 261 +#define PCLK_UART5 262 +#define PCLK_UART6 263 +#define PCLK_UART7 264 +#define PCLK_I2C1 265 +#define PCLK_I2C2 266 +#define PCLK_I2C3 267 +#define PCLK_I2C4 268 +#define PCLK_I2C5 269 +#define PCLK_SPI0 270 +#define PCLK_SPI1 271 +#define PCLK_SPI2 272 +#define PCLK_TSADC 273 +#define PCLK_SARADC 274 +#define PCLK_EFUSE 275 +#define PCLK_GPIO1 276 +#define PCLK_GPIO2 277 +#define PCLK_GPIO3 278 +#define PCLK_GPIO4 279 +#define PCLK_PWM0 280 +#define PCLK_PWM1 281 +#define PCLK_PWM2 282 +#define PCLK_TIMER 283 +#define PCLK_WDT 284 +#define PCLK_MIPIDSIPHY 285 +#define PCLK_MIPICSIPHY 286 +#define PCLK_DDRMON 287 +#define PCLK_DDRC 289 +#define PCLK_MSCH 290 +#define PCLK_STDBY 291 +#define PCLK_GPIO0_PMU 292 +#define PCLK_UART0_PMU 293 +#define PCLK_I2C0_PMU 294 +#define PCLK_USB3PHY_PIPE 295 +#define PCLK_PMU_PRE 296 + +#define CLK_NR_CLKS (PCLK_PMU_PRE + 1) + +/* soft-reset indices */ + +/* cru_softrst_con0 */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE0 2 +#define SRST_CORE1 3 +#define SRST_CORE0_DBG 4 +#define SRST_CORE1_DBG 5 +#define SRST_TOPDBG 6 +#define SRST_CORE_NOC 7 +#define SRST_STRC_A 8 +#define SRST_L2C 9 +#define SRST_DAP 10 +#define SRST_CORE_MSNIU 11 +#define SRST_GIC2CORE 12 +#define SRST_CORE2GIC 13 +#define SRST_CORE_PRF_A 14 +#define SRST_CORE_GRF_P 15 + +/* cru_softrst_con1 */ +#define SRST_DDRPHY 16 +#define SRST_DDRPHY_P 18 +#define SRST_UPCTL2 20 +#define SRST_UPCTL2_A 21 +#define SRST_UPCTL2_P 22 +#define SRST_MSCH 23 +#define SRST_MSCH_P 24 +#define SRST_DDRMON_P 25 +#define SRST_DDRSTDBY_P 26 +#define SRST_DDRSTDBY 27 +#define SRST_DDRGRF_P 28 +#define SRST_AXI_SPLIT_A 29 +#define SRST_DDRDFI_CTL 30 +#define SRST_DDRDFI_CTL_P 31 + +/* cru_softrst_con2 */ +#define SRST_GIC500_NIU_A 32 +#define SRST_GIC500_A 33 +#define SRST_GIC_CORE2GIC 34 +#define SRST_GIC_GIC2CORE 35 +#define SRST_NPU_CORE 36 +#define SRST_NPU_A 37 +#define SRST_NPU_H 38 +#define SRST_NPU_NIU_A 39 +#define SRST_NPU_NIU_H 40 +#define SRST_NPU2MEM_A 41 +#define SRST_NPU_PVTM 42 +#define SRST_CORE_PVTM 43 +#define SRST_GIC_SPINLOCK_A 47 + +/* cru_softrst_con3 */ +#define SRST_PCIE_NIU_H 48 +#define SRST_PCIE_NIU_L 49 +#define SRST_PCIEGRF_P 50 +#define SRST_PCIECTL_P 51 +#define SRST_PCIECTL_POWERUP 52 +#define SRST_PCIECTL_MST_A 53 +#define SRST_PCIECTL_SLV_A 54 +#define SRST_PCIECTL_DBI_A 55 +#define SRST_PCIECTL_BUTTON 56 +#define SRST_PCIECTL_PE 57 +#define SRST_PCIECTL_CORE 58 +#define SRST_PCIECTL_NSTICKY 59 +#define SRST_PCIECTL_STICKY 60 +#define SRST_PCIECTL_PWR 61 +#define SRST_PCIE_NIU_A 62 +#define SRST_PCIE_NIU_P 63 + +/* cru_softrst_con4 */ +#define SRST_PCIEPHY_POR 64 +#define SRST_PCIEPHY_P 65 +#define SRST_PCIEPHY_PIPE 66 +#define SRST_USBPHY_POR 67 +#define SRST_USBPHY_OTG_PORT 68 +#define SRST_USBPHY_HOST_PORT 69 +#define SRST_USB3PHY_GRF_P 70 +#define SRST_USB2PHY_GRF_P 71 +#define SRST_USB3_OTG_A 72 +#define SRST_USB2HOST_H 73 +#define SRST_USB2HOST_ARB_H 74 +#define SRSTUSB2HOST_UTMI 75 + +/* cru_softrst_con5 */ +#define SRST_IMEM0_A 80 +#define SRST_IMEM1_A 81 +#define SRST_IMEM2_A 82 +#define SRST_IMEM3_A 83 +#define SRST_IMEM0_NIU_A 84 +#define SRST_IMEM1_NIU_A 85 +#define SRST_IMEM2_NIU_A 86 +#define SRST_IMEM3_NIU_A 87 +#define SRST_IMEM_NIU_H 88 +#define SRST_VPU_NIU_A 92 +#define SRST_VPU_NIU_H 93 +#define SRST_VPU_A 94 +#define SRST_VPU_H 95 + +/* cru_softrst_con6 */ +#define SRST_VIO_NIU_H 96 +#define SRST_VIO_NIU_L 97 +#define SRST_VOPRAW_A 98 +#define SRST_VOPRAW_H 99 +#define SRST_VOPRAW_D 100 +#define SRST_VOPLITE_A 101 +#define SRST_VOPLITE_H 102 +#define SRST_VOPLITE_D 103 +#define SRST_MIPIDSI_HOST_P 104 +#define SRST_CSITX_P 105 +#define SRST_CSITX_TXBYTEHS 106 +#define SRST_CSITX_TXESC 107 +#define SRST_CSITX_CAM 108 +#define SRST_CSITX_I 109 + +/* cru_softrst_con7 */ +#define SRST_RGA_A 112 +#define SRST_RGA_H 113 +#define SRST_RGA 114 +#define SRST_CSI2HOST_P 115 +#define SRST_CIF_A 116 +#define SRST_CIF_H 117 +#define SRST_CIF_I 118 +#define SRST_CIF_PCLKIN 119 +#define SRST_CIF_D 120 +#define SRST_ISP_H 121 +#define SRST_ISP 122 +#define SRST_MIPICSIPHY_P 124 +#define SRST_MIPIDSIPHY_P 125 + +/* cru_softrst_con8 */ +#define SRST_PERI_NIU_H 128 +#define SRST_PERI_NIU_L 129 +#define SRST_PDMMC_NIU_H 132 +#define SRST_SDMMC_H 133 +#define SRST_SDIO_H 134 +#define SRST_EMMC_H 135 +#define SRST_SFC_H 136 +#define SRST_SFC 137 +#define SRST_GMAC_NIU_A 140 +#define SRST_GMAC_NIU_H 141 +#define SRST_GMAC_NIU_P 142 +#define SRST_GAMC_A 143 + +/* cru_softrst_con9 */ +#define SRST_PMU_NIU_P 144 +#define SRST_PMU_SGRF_P 145 +#define SRST_PMU_GRF_P 146 +#define SRST_PMU_PMU 147 +#define SRST_PMU_MEM_P 148 +#define SRST_PMU_GPIO0_P 149 +#define SRST_PMU_UART0_P 150 +#define SRST_PMU_CRU 151 +#define SRST_PMU_PVTM 152 +#define SRST_PMU_UART0 153 +#define SRST_PMU_NIU_H 154 +#define SRST_PMU_DDR_FAIL_SAVE 155 +#define SRST_PMU_I2C0_P 156 +#define SRST_PMU_I2C0 157 +#define SRST_PMU_GPIO0_DB 158 + +/* cru_softrst_con10 */ +#define SRST_AUDIO_NIU_H 160 +#define SRST_VAD_H 161 +#define SRST_PDM_H 162 +#define SRST_PDM 163 +#define SRST_I2S0_H 164 +#define SRST_I2S0_TX 165 +#define SRST_I2S1_H 166 +#define SRST_I2S1 167 +#define SRST_I2S0_RX 168 + +/* cru_softrst_con11 */ +#define SRST_BUS_NIU_M 176 +#define SRST_BUS_NIU_L 177 +#define SRST_TOP_NIU_P 178 +#define SRST_ROM_H 179 +#define SRST_CRYPTO_A 180 +#define SRST_CRYPTO_H 181 +#define SRST_CRYPTO_CORE 182 +#define SRST_CRYPTO_APK 183 +#define SRST_DCF_A 184 +#define SRST_DCF_P 185 +#define SRST_UART1_P 186 +#define SRST_UART1 187 +#define SRST_UART2_P 188 +#define SRST_UART2 189 +#define SRST_UART3_P 190 +#define SRST_UART3 191 + +/* cru_softrst_con12 */ +#define SRST_UART4_P 192 +#define SRST_UART4 193 +#define SRST_UART5_P 194 +#define SRST_UART5 195 +#define SRST_UART6_P 196 +#define SRST_UART6 197 +#define SRST_UART7_P 198 +#define SRST_UART7 199 +#define SRST_I2C1_P 200 +#define SRST_I2C1 201 +#define SRST_I2C2_P 202 +#define SRST_I2C2 203 +#define SRST_I2C3_P 204 +#define SRST_I2C3 205 +#define SRST_PWM0_P 206 +#define SRST_PWM0 207 + +/* cru_softrst_con13 */ +#define SRST_PWM1_P 208 +#define SRST_PWM1 209 +#define SRST_PWM2_P 210 +#define SRST_PWM2 211 +#define SRST_SPI0_P 212 +#define SRST_SPI0 213 +#define SRST_SPI1_P 214 +#define SRST_SPI1 215 +#define SRST_SPI2_P 216 +#define SRST_SPI2 217 +#define SRST_BUS_SGRF_P 218 +#define SRST_BUS_GRF_P 219 +#define SRST_TIMER_P 220 +#define SRST_TIMER0 221 +#define SRST_TIMER1 222 +#define SRST_TIMER2 223 + +/* cru_softrst_con14 */ +#define SRST_TIMER3 224 +#define SRST_TIMER4 225 +#define SRST_TIMER5 226 +#define SRST_WDT_NS_P 227 +#define SRST_EFUSE_NS_P 228 +#define SRST_EFUSE_NS 229 +#define SRST_GPIO1_P 230 +#define SRST_GPIO1_DB 231 +#define SRST_GPIO2_P 232 +#define SRST_GPIO2_DB 233 +#define SRST_GPIO3_P 234 +#define SRST_GPIO3_DB 235 +#define SRST_GPIO4_P 236 +#define SRST_GPIO4_DB 237 +#define SRST_BUS_SUB_NIU_M 238 + +/* cru_softrst_con15 */ +#define SRST_I2C4_P 240 +#define SRST_I2C4 241 +#define SRST_I2C5_P 242 +#define SRST_I2C5 243 +#define SRST_SARADC 252 +#define SRST_SARADC_P 253 +#define SRST_TSADC_P 254 +#define SRST_TSADC 255 + +#endif diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h new file mode 100644 index 000000000000..658413a6feb3 --- /dev/null +++ b/include/dt-bindings/clock/rk3036-cru.h @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Xing Zheng <zhengxing@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_GPLL 3 +#define ARMCLK 4 + +/* sclk gates (special clocks) */ +#define SCLK_GPU 64 +#define SCLK_SPI 65 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_NANDC 76 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_I2S 82 +#define SCLK_SPDIF 83 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_OTGPHY0 93 +#define SCLK_LCDC 100 +#define SCLK_HDMI 109 +#define SCLK_HEVC 111 +#define SCLK_I2S_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_PVTM_CORE 123 +#define SCLK_PVTM_GPU 124 +#define SCLK_PVTM_VIDEO 125 +#define SCLK_I2S_FRAC 126 +#define SCLK_I2S_PRE 127 +#define SCLK_MAC 151 +#define SCLK_MACREF 152 +#define SCLK_MACPLL 153 +#define SCLK_SFC 160 + +/* aclk gates */ +#define ACLK_DMAC2 194 +#define ACLK_LCDC 197 +#define ACLK_VIO 203 +#define ACLK_VCODEC 208 +#define ACLK_CPU 209 +#define ACLK_PERI 210 +#define ACLK_HEVC 211 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GRF 329 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_SPI 338 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_PWM 350 +#define PCLK_TIMER 353 +#define PCLK_HDMI 360 +#define PCLK_CPU 362 +#define PCLK_PERI 363 +#define PCLK_DDRUPCTL 364 +#define PCLK_WDT 368 +#define PCLK_ACODEC 369 + +/* hclk gates */ +#define HCLK_OTG0 449 +#define HCLK_OTG1 450 +#define HCLK_NANDC 453 +#define HCLK_SFC 454 +#define HCLK_SDMMC 456 +#define HCLK_SDIO 457 +#define HCLK_EMMC 459 +#define HCLK_MAC 460 +#define HCLK_I2S 462 +#define HCLK_LCDC 465 +#define HCLK_ROM 467 +#define HCLK_VIO_BUS 472 +#define HCLK_VCODEC 476 +#define HCLK_CPU 477 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE0 0 +#define SRST_CORE1 1 +#define SRST_CORE0_DBG 4 +#define SRST_CORE1_DBG 5 +#define SRST_CORE0_POR 8 +#define SRST_CORE1_POR 9 +#define SRST_L2C 12 +#define SRST_TOPDBG 13 +#define SRST_STRC_SYS_A 14 +#define SRST_PD_CORE_NIU 15 + +#define SRST_TIMER2 16 +#define SRST_CPUSYS_H 17 +#define SRST_AHB2APB_H 19 +#define SRST_TIMER3 20 +#define SRST_INTMEM 21 +#define SRST_ROM 22 +#define SRST_PERI_NIU 23 +#define SRST_I2S 24 +#define SRST_DDR_PLL 25 +#define SRST_GPU_DLL 26 +#define SRST_TIMER0 27 +#define SRST_TIMER1 28 +#define SRST_CORE_DLL 29 +#define SRST_EFUSE_P 30 +#define SRST_ACODEC_P 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_UART0 39 +#define SRST_UART1 40 +#define SRST_UART2 41 +#define SRST_I2C0 43 +#define SRST_I2C1 44 +#define SRST_I2C2 45 +#define SRST_SFC 47 + +#define SRST_PWM0 48 +#define SRST_DAP 51 +#define SRST_DAP_SYS 52 +#define SRST_GRF 55 +#define SRST_PERIPHSYS_A 57 +#define SRST_PERIPHSYS_H 58 +#define SRST_PERIPHSYS_P 59 +#define SRST_CPU_PERI 61 +#define SRST_EMEM_PERI 62 +#define SRST_USB_PERI 63 + +#define SRST_DMA2 64 +#define SRST_MAC 66 +#define SRST_NANDC 68 +#define SRST_USBOTG0 69 +#define SRST_OTGC0 71 +#define SRST_USBOTG1 72 +#define SRST_OTGC1 74 +#define SRST_DDRMSCH 79 + +#define SRST_MMC0 81 +#define SRST_SDIO 82 +#define SRST_EMMC 83 +#define SRST_SPI0 84 +#define SRST_WDT 86 +#define SRST_DDRPHY 88 +#define SRST_DDRPHY_P 89 +#define SRST_DDRCTRL 90 +#define SRST_DDRCTRL_P 91 + +#define SRST_HDMI_P 96 +#define SRST_VIO_BUS_H 99 +#define SRST_UTMI0 103 +#define SRST_UTMI1 104 +#define SRST_USBPOR 105 + +#define SRST_VCODEC_A 112 +#define SRST_VCODEC_H 113 +#define SRST_VIO1_A 114 +#define SRST_HEVC 115 +#define SRST_VCODEC_NIU_A 116 +#define SRST_LCDC1_A 117 +#define SRST_LCDC1_H 118 +#define SRST_LCDC1_D 119 +#define SRST_GPU 120 +#define SRST_GPU_NIU_A 122 + +#define SRST_DBG_P 131 + +#endif diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h new file mode 100644 index 000000000000..7d3b5ca8a62c --- /dev/null +++ b/include/dt-bindings/clock/rk3128-cru.h @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Author: Elaine <zhangqing@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define ARMCLK 5 +#define PLL_GPLL_DIV2 6 +#define PLL_GPLL_DIV3 7 + +/* sclk gates (special clocks) */ +#define SCLK_SPI0 65 +#define SCLK_NANDC 67 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_I2S0 80 +#define SCLK_I2S1 81 +#define SCLK_SPDIF 83 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_TIMER4 89 +#define SCLK_TIMER5 90 +#define SCLK_SARADC 91 +#define SCLK_I2S_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_VOP 122 +#define SCLK_MAC_SRC 124 +#define SCLK_MAC 126 +#define SCLK_MAC_REFOUT 127 +#define SCLK_MAC_REF 128 +#define SCLK_MAC_RX 129 +#define SCLK_MAC_TX 130 +#define SCLK_HEVC_CORE 134 +#define SCLK_RGA 135 +#define SCLK_CRYPTO 138 +#define SCLK_TSP 139 +#define SCLK_OTGPHY0 142 +#define SCLK_OTGPHY1 143 +#define SCLK_DDRC 144 +#define SCLK_PVTM_FUNC 145 +#define SCLK_PVTM_CORE 146 +#define SCLK_PVTM_GPU 147 +#define SCLK_MIPI_24M 148 +#define SCLK_PVTM 149 +#define SCLK_CIF_SRC 150 +#define SCLK_CIF_OUT_SRC 151 +#define SCLK_CIF_OUT 152 +#define SCLK_SFC 153 +#define SCLK_USB480M 154 +#define SCLK_HSADC_TSP 155 + +/* dclk gates */ +#define DCLK_VOP 190 +#define DCLK_EBC 191 + +/* aclk gates */ +#define ACLK_VIO0 192 +#define ACLK_VIO1 193 +#define ACLK_DMAC 194 +#define ACLK_CPU 195 +#define ACLK_VEPU 196 +#define ACLK_VDPU 197 +#define ACLK_CIF 198 +#define ACLK_IEP 199 +#define ACLK_LCDC0 204 +#define ACLK_RGA 205 +#define ACLK_PERI 210 +#define ACLK_VOP 211 +#define ACLK_GMAC 212 +#define ACLK_GPU 213 + +/* pclk gates */ +#define PCLK_SARADC 318 +#define PCLK_WDT 319 +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GPIO3 323 +#define PCLK_VIO_H2P 324 +#define PCLK_MIPI 325 +#define PCLK_EFUSE 326 +#define PCLK_HDMI 327 +#define PCLK_ACODEC 328 +#define PCLK_GRF 329 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_I2C3 335 +#define PCLK_SPI0 338 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_TSADC 344 +#define PCLK_PWM 350 +#define PCLK_TIMER 353 +#define PCLK_CPU 354 +#define PCLK_PERI 363 +#define PCLK_GMAC 367 +#define PCLK_PMU_PRE 368 +#define PCLK_SIM_CARD 369 +#define PCLK_MIPIPHY 370 + +/* hclk gates */ +#define HCLK_SFC 439 +#define HCLK_SPDIF 440 +#define HCLK_GPS 441 +#define HCLK_USBHOST 442 +#define HCLK_I2S_8CH 443 +#define HCLK_I2S_2CH 444 +#define HCLK_VOP 452 +#define HCLK_NANDC 453 +#define HCLK_SDMMC 456 +#define HCLK_SDIO 457 +#define HCLK_EMMC 459 +#define HCLK_CPU 460 +#define HCLK_VEPU 461 +#define HCLK_VDPU 462 +#define HCLK_LCDC0 463 +#define HCLK_EBC 465 +#define HCLK_VIO 466 +#define HCLK_RGA 467 +#define HCLK_IEP 468 +#define HCLK_VIO_H2P 469 +#define HCLK_CIF 470 +#define HCLK_HOST2 473 +#define HCLK_OTG 474 +#define HCLK_TSP 475 +#define HCLK_CRYPTO 476 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_ACLK_CORE 13 +#define SRST_STRC_SYS_A 14 +#define SRST_L2C 15 + +#define SRST_CPUSYS_H 18 +#define SRST_AHB2APBSYS_H 19 +#define SRST_SPDIF 20 +#define SRST_INTMEM 21 +#define SRST_ROM 22 +#define SRST_PERI_NIU 23 +#define SRST_I2S_2CH 24 +#define SRST_I2S_8CH 25 +#define SRST_GPU_PVTM 26 +#define SRST_FUNC_PVTM 27 +#define SRST_CORE_PVTM 29 +#define SRST_EFUSE_P 30 +#define SRST_ACODEC_P 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_GPIO3 35 +#define SRST_MIPIPHY_P 36 +#define SRST_UART0 39 +#define SRST_UART1 40 +#define SRST_UART2 41 +#define SRST_I2C0 43 +#define SRST_I2C1 44 +#define SRST_I2C2 45 +#define SRST_I2C3 46 +#define SRST_SFC 47 + +#define SRST_PWM 48 +#define SRST_DAP_PO 50 +#define SRST_DAP 51 +#define SRST_DAP_SYS 52 +#define SRST_CRYPTO 53 +#define SRST_GRF 55 +#define SRST_GMAC 56 +#define SRST_PERIPH_SYS_A 57 +#define SRST_PERIPH_SYS_H 58 +#define SRST_PERIPH_SYS_P 59 +#define SRST_SMART_CARD 60 +#define SRST_CPU_PERI 61 +#define SRST_EMEM_PERI 62 +#define SRST_USB_PERI 63 + +#define SRST_DMA 64 +#define SRST_GPS 67 +#define SRST_NANDC 68 +#define SRST_USBOTG0 69 +#define SRST_OTGC0 71 +#define SRST_USBOTG1 72 +#define SRST_OTGC1 74 +#define SRST_DDRMSCH 79 + +#define SRST_SDMMC 81 +#define SRST_SDIO 82 +#define SRST_EMMC 83 +#define SRST_SPI 84 +#define SRST_WDT 86 +#define SRST_SARADC 87 +#define SRST_DDRPHY 88 +#define SRST_DDRPHY_P 89 +#define SRST_DDRCTRL 90 +#define SRST_DDRCTRL_P 91 +#define SRST_TSP 92 +#define SRST_TSP_CLKIN 93 +#define SRST_HOST0_ECHI 94 + +#define SRST_HDMI_P 96 +#define SRST_VIO_ARBI_H 97 +#define SRST_VIO0_A 98 +#define SRST_VIO_BUS_H 99 +#define SRST_VOP_A 100 +#define SRST_VOP_H 101 +#define SRST_VOP_D 102 +#define SRST_UTMI0 103 +#define SRST_UTMI1 104 +#define SRST_USBPOR 105 +#define SRST_IEP_A 106 +#define SRST_IEP_H 107 +#define SRST_RGA_A 108 +#define SRST_RGA_H 109 +#define SRST_CIF0 110 +#define SRST_PMU 111 + +#define SRST_VCODEC_A 112 +#define SRST_VCODEC_H 113 +#define SRST_VIO1_A 114 +#define SRST_HEVC_CORE 115 +#define SRST_VCODEC_NIU_A 116 +#define SRST_PMU_NIU_P 117 +#define SRST_LCDC0_S 119 +#define SRST_GPU 120 +#define SRST_GPU_NIU_A 122 +#define SRST_EBC_A 123 +#define SRST_EBC_H 124 + +#define SRST_CORE_DBG 128 +#define SRST_DBG_P 129 +#define SRST_TIMER0 130 +#define SRST_TIMER1 131 +#define SRST_TIMER2 132 +#define SRST_TIMER3 133 +#define SRST_TIMER4 134 +#define SRST_TIMER5 135 +#define SRST_VIO_H2P 136 +#define SRST_VIO_MIPI_DSI 137 + +#endif diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h index 8df77a7c030b..9d3ef39defb7 100644 --- a/include/dt-bindings/clock/rk3188-cru-common.h +++ b/include/dt-bindings/clock/rk3188-cru-common.h @@ -71,6 +71,11 @@ #define ACLK_IPP 200 #define ACLK_RGA 201 #define ACLK_CIF0 202 +#define ACLK_VEPU 203 +#define ACLK_VDPU 204 +#define ACLK_CPU 205 +#define ACLK_PERI 206 +#define ACLK_CIF1 207 /* pclk gates */ #define PCLK_GRF 320 @@ -103,6 +108,10 @@ #define PCLK_EFUSE 347 #define PCLK_TZPC 348 #define PCLK_TSADC 349 +#define PCLK_CPU 350 +#define PCLK_PERI 351 +#define PCLK_CIF0 352 +#define PCLK_CIF1 353 /* hclk gates */ #define HCLK_SDMMC 448 @@ -111,9 +120,9 @@ #define HCLK_OTG0 451 #define HCLK_EMAC 452 #define HCLK_SPDIF 453 -#define HCLK_I2S0 454 -#define HCLK_I2S1 455 -#define HCLK_I2S2 456 +#define HCLK_I2S0_2CH 454 +#define HCLK_I2S1_2CH 455 +#define HCLK_I2S_8CH 456 #define HCLK_OTG1 457 #define HCLK_HSIC 458 #define HCLK_HSADC 459 @@ -125,8 +134,14 @@ #define HCLK_IPP 465 #define HCLK_RGA 466 #define HCLK_NANDC0 467 +#define HCLK_VEPU 468 +#define HCLK_VDPU 469 +#define HCLK_CPU 470 +#define HCLK_PERI 471 +#define HCLK_CIF1 472 +#define HCLK_HDMI 473 -#define CLK_NR_CLKS (HCLK_NANDC0 + 1) +#define CLK_NR_CLKS (HCLK_HDMI + 1) /* soft-reset indices */ #define SRST_MCORE 2 diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h new file mode 100644 index 000000000000..2f22a7b1538d --- /dev/null +++ b/include/dt-bindings/clock/rk3228-cru.h @@ -0,0 +1,298 @@ +/* + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Jeffy Chen <jeffy.chen@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define ARMCLK 5 + +/* sclk gates (special clocks) */ +#define SCLK_SPI0 65 +#define SCLK_NANDC 67 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_TSADC 72 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_I2S0 80 +#define SCLK_I2S1 81 +#define SCLK_I2S2 82 +#define SCLK_SPDIF 83 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_TIMER4 89 +#define SCLK_TIMER5 90 +#define SCLK_I2S_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO_SAMPLE 119 +#define SCLK_SDIO_SRC 120 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_VOP 122 +#define SCLK_HDMI_HDCP 123 +#define SCLK_MAC_SRC 124 +#define SCLK_MAC_EXTCLK 125 +#define SCLK_MAC 126 +#define SCLK_MAC_REFOUT 127 +#define SCLK_MAC_REF 128 +#define SCLK_MAC_RX 129 +#define SCLK_MAC_TX 130 +#define SCLK_MAC_PHY 131 +#define SCLK_MAC_OUT 132 +#define SCLK_VDEC_CABAC 133 +#define SCLK_VDEC_CORE 134 +#define SCLK_RGA 135 +#define SCLK_HDCP 136 +#define SCLK_HDMI_CEC 137 +#define SCLK_CRYPTO 138 +#define SCLK_TSP 139 +#define SCLK_HSADC 140 +#define SCLK_WIFI 141 +#define SCLK_OTGPHY0 142 +#define SCLK_OTGPHY1 143 +#define SCLK_DDRC 144 + +/* dclk gates */ +#define DCLK_VOP 190 +#define DCLK_HDMI_PHY 191 +#define HDMIPHY 192 + +/* aclk gates */ +#define ACLK_DMAC 194 +#define ACLK_CPU 195 +#define ACLK_VPU_PRE 196 +#define ACLK_RKVDEC_PRE 197 +#define ACLK_RGA_PRE 198 +#define ACLK_IEP_PRE 199 +#define ACLK_HDCP_PRE 200 +#define ACLK_VOP_PRE 201 +#define ACLK_VPU 202 +#define ACLK_RKVDEC 203 +#define ACLK_IEP 204 +#define ACLK_RGA 205 +#define ACLK_HDCP 206 +#define ACLK_PERI 210 +#define ACLK_VOP 211 +#define ACLK_GMAC 212 +#define ACLK_GPU 213 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GPIO3 323 +#define PCLK_VIO_H2P 324 +#define PCLK_HDCP 325 +#define PCLK_EFUSE_1024 326 +#define PCLK_EFUSE_256 327 +#define PCLK_GRF 329 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_I2C3 335 +#define PCLK_SPI0 338 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_TSADC 344 +#define PCLK_PWM 350 +#define PCLK_TIMER 353 +#define PCLK_CPU 354 +#define PCLK_PERI 363 +#define PCLK_HDMI_CTRL 364 +#define PCLK_HDMI_PHY 365 +#define PCLK_GMAC 367 +#define PCLK_ACODECPHY 368 + +/* hclk gates */ +#define HCLK_I2S0_8CH 442 +#define HCLK_I2S1_8CH 443 +#define HCLK_I2S2_2CH 444 +#define HCLK_SPDIF_8CH 445 +#define HCLK_VOP 452 +#define HCLK_NANDC 453 +#define HCLK_SDMMC 456 +#define HCLK_SDIO 457 +#define HCLK_EMMC 459 +#define HCLK_CPU 460 +#define HCLK_VPU_PRE 461 +#define HCLK_RKVDEC_PRE 462 +#define HCLK_VIO_PRE 463 +#define HCLK_VPU 464 +#define HCLK_RKVDEC 465 +#define HCLK_VIO 466 +#define HCLK_RGA 467 +#define HCLK_IEP 468 +#define HCLK_VIO_H2P 469 +#define HCLK_HDCP_MMU 470 +#define HCLK_HOST0 471 +#define HCLK_HOST1 472 +#define HCLK_HOST2 473 +#define HCLK_OTG 474 +#define HCLK_TSP 475 +#define HCLK_M_CRYPTO 476 +#define HCLK_S_CRYPTO 477 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_ACLK_CORE 13 +#define SRST_NOC 14 +#define SRST_L2C 15 + +#define SRST_CPUSYS_H 18 +#define SRST_BUSSYS_H 19 +#define SRST_SPDIF 20 +#define SRST_INTMEM 21 +#define SRST_ROM 22 +#define SRST_OTG_ADP 23 +#define SRST_I2S0 24 +#define SRST_I2S1 25 +#define SRST_I2S2 26 +#define SRST_ACODEC_P 27 +#define SRST_DFIMON 28 +#define SRST_MSCH 29 +#define SRST_EFUSE1024 30 +#define SRST_EFUSE256 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_GPIO3 35 +#define SRST_PERIPH_NOC_A 36 +#define SRST_PERIPH_NOC_BUS_H 37 +#define SRST_PERIPH_NOC_P 38 +#define SRST_UART0 39 +#define SRST_UART1 40 +#define SRST_UART2 41 +#define SRST_PHYNOC 42 +#define SRST_I2C0 43 +#define SRST_I2C1 44 +#define SRST_I2C2 45 +#define SRST_I2C3 46 + +#define SRST_PWM 48 +#define SRST_A53_GIC 49 +#define SRST_DAP 51 +#define SRST_DAP_NOC 52 +#define SRST_CRYPTO 53 +#define SRST_SGRF 54 +#define SRST_GRF 55 +#define SRST_GMAC 56 +#define SRST_PERIPH_NOC_H 58 +#define SRST_MACPHY 63 + +#define SRST_DMA 64 +#define SRST_NANDC 68 +#define SRST_USBOTG 69 +#define SRST_OTGC 70 +#define SRST_USBHOST0 71 +#define SRST_HOST_CTRL0 72 +#define SRST_USBHOST1 73 +#define SRST_HOST_CTRL1 74 +#define SRST_USBHOST2 75 +#define SRST_HOST_CTRL2 76 +#define SRST_USBPOR0 77 +#define SRST_USBPOR1 78 +#define SRST_DDRMSCH 79 + +#define SRST_SMART_CARD 80 +#define SRST_SDMMC 81 +#define SRST_SDIO 82 +#define SRST_EMMC 83 +#define SRST_SPI 84 +#define SRST_TSP_H 85 +#define SRST_TSP 86 +#define SRST_TSADC 87 +#define SRST_DDRPHY 88 +#define SRST_DDRPHY_P 89 +#define SRST_DDRCTRL 90 +#define SRST_DDRCTRL_P 91 +#define SRST_HOST0_ECHI 92 +#define SRST_HOST1_ECHI 93 +#define SRST_HOST2_ECHI 94 +#define SRST_VOP_NOC_A 95 + +#define SRST_HDMI_P 96 +#define SRST_VIO_ARBI_H 97 +#define SRST_IEP_NOC_A 98 +#define SRST_VIO_NOC_H 99 +#define SRST_VOP_A 100 +#define SRST_VOP_H 101 +#define SRST_VOP_D 102 +#define SRST_UTMI0 103 +#define SRST_UTMI1 104 +#define SRST_UTMI2 105 +#define SRST_UTMI3 106 +#define SRST_RGA 107 +#define SRST_RGA_NOC_A 108 +#define SRST_RGA_A 109 +#define SRST_RGA_H 110 +#define SRST_HDCP_A 111 + +#define SRST_VPU_A 112 +#define SRST_VPU_H 113 +#define SRST_VPU_NOC_A 116 +#define SRST_VPU_NOC_H 117 +#define SRST_RKVDEC_A 118 +#define SRST_RKVDEC_NOC_A 119 +#define SRST_RKVDEC_H 120 +#define SRST_RKVDEC_NOC_H 121 +#define SRST_RKVDEC_CORE 122 +#define SRST_RKVDEC_CABAC 123 +#define SRST_IEP_A 124 +#define SRST_IEP_H 125 +#define SRST_GPU_A 126 +#define SRST_GPU_NOC_A 127 + +#define SRST_CORE_DBG 128 +#define SRST_DBG_P 129 +#define SRST_TIMER0 130 +#define SRST_TIMER1 131 +#define SRST_TIMER2 132 +#define SRST_TIMER3 133 +#define SRST_TIMER4 134 +#define SRST_TIMER5 135 +#define SRST_VIO_H2P 136 +#define SRST_HDMIPHY 139 +#define SRST_VDAC 140 +#define SRST_TIMER_6CH_P 141 + +#endif diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h index c719aacef14f..1f9c62f07389 100644 --- a/include/dt-bindings/clock/rk3288-cru.h +++ b/include/dt-bindings/clock/rk3288-cru.h @@ -86,7 +86,18 @@ #define SCLK_USBPHY480M_SRC 122 #define SCLK_PVTM_CORE 123 #define SCLK_PVTM_GPU 124 +#define SCLK_CRYPTO 125 +#define SCLK_MIPIDSI_24M 126 +#define SCLK_VIP_OUT 127 +#define SCLK_DDRCLK 128 +#define SCLK_I2S_SRC 129 +#define SCLK_TSPOUT 130 +#define SCLK_TSP 131 +#define SCLK_HSADC0_TSP 132 +#define SCLK_HSADC1_TSP 133 +#define SCLK_27M_TSP 134 +#define SCLK_MAC_PLL 150 #define SCLK_MAC 151 #define SCLK_MACREF_OUT 152 @@ -113,6 +124,8 @@ #define ACLK_VCODEC 208 #define ACLK_CPU 209 #define ACLK_PERI 210 +#define ACLK_VIO0 211 +#define ACLK_VIO1 212 /* pclk gates */ #define PCLK_GPIO0 320 @@ -164,6 +177,13 @@ #define PCLK_DDRUPCTL1 366 #define PCLK_PUBL1 367 #define PCLK_WDT 368 +#define PCLK_EFUSE256 369 +#define PCLK_EFUSE1024 370 +#define PCLK_ISP_IN 371 +#define PCLK_VIP 372 +#define PCLK_VIP_IN 373 +#define PCLK_PD_ALIVE 374 +#define PCLK_PD_PMU 375 /* hclk gates */ #define HCLK_GPS 448 @@ -197,8 +217,10 @@ #define HCLK_VCODEC 476 #define HCLK_CPU 477 #define HCLK_PERI 478 +#define HCLK_USB_PERI 479 +#define HCLK_VIO 480 -#define CLK_NR_CLKS (HCLK_PERI + 1) +#define CLK_NR_CLKS (HCLK_VIO + 1) /* soft-reset indices */ #define SRST_CORE0 0 diff --git a/include/dt-bindings/clock/rk3308-cru.h b/include/dt-bindings/clock/rk3308-cru.h new file mode 100644 index 000000000000..5088a0f6fb02 --- /dev/null +++ b/include/dt-bindings/clock/rk3308-cru.h @@ -0,0 +1,396 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Author: Finley Xiao <finley.xiao@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_VPLL0 3 +#define PLL_VPLL1 4 +#define ARMCLK 5 + +/* sclk (special clocks) */ +#define USB480M 14 +#define SCLK_RTC32K 15 +#define SCLK_PVTM_CORE 16 +#define SCLK_UART0 17 +#define SCLK_UART1 18 +#define SCLK_UART2 19 +#define SCLK_UART3 20 +#define SCLK_UART4 21 +#define SCLK_I2C0 22 +#define SCLK_I2C1 23 +#define SCLK_I2C2 24 +#define SCLK_I2C3 25 +#define SCLK_PWM0 26 +#define SCLK_SPI0 27 +#define SCLK_SPI1 28 +#define SCLK_SPI2 29 +#define SCLK_TIMER0 30 +#define SCLK_TIMER1 31 +#define SCLK_TIMER2 32 +#define SCLK_TIMER3 33 +#define SCLK_TIMER4 34 +#define SCLK_TIMER5 35 +#define SCLK_TSADC 36 +#define SCLK_SARADC 37 +#define SCLK_OTP 38 +#define SCLK_OTP_USR 39 +#define SCLK_CPU_BOOST 40 +#define SCLK_CRYPTO 41 +#define SCLK_CRYPTO_APK 42 +#define SCLK_NANDC_DIV 43 +#define SCLK_NANDC_DIV50 44 +#define SCLK_NANDC 45 +#define SCLK_SDMMC_DIV 46 +#define SCLK_SDMMC_DIV50 47 +#define SCLK_SDMMC 48 +#define SCLK_SDMMC_DRV 49 +#define SCLK_SDMMC_SAMPLE 50 +#define SCLK_SDIO_DIV 51 +#define SCLK_SDIO_DIV50 52 +#define SCLK_SDIO 53 +#define SCLK_SDIO_DRV 54 +#define SCLK_SDIO_SAMPLE 55 +#define SCLK_EMMC_DIV 56 +#define SCLK_EMMC_DIV50 57 +#define SCLK_EMMC 58 +#define SCLK_EMMC_DRV 59 +#define SCLK_EMMC_SAMPLE 60 +#define SCLK_SFC 61 +#define SCLK_OTG_ADP 62 +#define SCLK_MAC_SRC 63 +#define SCLK_MAC 64 +#define SCLK_MAC_REF 65 +#define SCLK_MAC_RX_TX 66 +#define SCLK_MAC_RMII 67 +#define SCLK_DDR_MON_TIMER 68 +#define SCLK_DDR_MON 69 +#define SCLK_DDRCLK 70 +#define SCLK_PMU 71 +#define SCLK_USBPHY_REF 72 +#define SCLK_WIFI 73 +#define SCLK_PVTM_PMU 74 +#define SCLK_PDM 75 +#define SCLK_I2S0_8CH_TX 76 +#define SCLK_I2S0_8CH_TX_OUT 77 +#define SCLK_I2S0_8CH_RX 78 +#define SCLK_I2S0_8CH_RX_OUT 79 +#define SCLK_I2S1_8CH_TX 80 +#define SCLK_I2S1_8CH_TX_OUT 81 +#define SCLK_I2S1_8CH_RX 82 +#define SCLK_I2S1_8CH_RX_OUT 83 +#define SCLK_I2S2_8CH_TX 84 +#define SCLK_I2S2_8CH_TX_OUT 85 +#define SCLK_I2S2_8CH_RX 86 +#define SCLK_I2S2_8CH_RX_OUT 87 +#define SCLK_I2S3_8CH_TX 88 +#define SCLK_I2S3_8CH_TX_OUT 89 +#define SCLK_I2S3_8CH_RX 90 +#define SCLK_I2S3_8CH_RX_OUT 91 +#define SCLK_I2S0_2CH 92 +#define SCLK_I2S0_2CH_OUT 93 +#define SCLK_I2S1_2CH 94 +#define SCLK_I2S1_2CH_OUT 95 +#define SCLK_SPDIF_TX_DIV 96 +#define SCLK_SPDIF_TX_DIV50 97 +#define SCLK_SPDIF_TX 98 +#define SCLK_SPDIF_RX_DIV 99 +#define SCLK_SPDIF_RX_DIV50 100 +#define SCLK_SPDIF_RX 101 +#define SCLK_I2S0_8CH_TX_MUX 102 +#define SCLK_I2S0_8CH_RX_MUX 103 +#define SCLK_I2S1_8CH_TX_MUX 104 +#define SCLK_I2S1_8CH_RX_MUX 105 +#define SCLK_I2S2_8CH_TX_MUX 106 +#define SCLK_I2S2_8CH_RX_MUX 107 +#define SCLK_I2S3_8CH_TX_MUX 108 +#define SCLK_I2S3_8CH_RX_MUX 109 +#define SCLK_I2S0_8CH_TX_SRC 110 +#define SCLK_I2S0_8CH_RX_SRC 111 +#define SCLK_I2S1_8CH_TX_SRC 112 +#define SCLK_I2S1_8CH_RX_SRC 113 +#define SCLK_I2S2_8CH_TX_SRC 114 +#define SCLK_I2S2_8CH_RX_SRC 115 +#define SCLK_I2S3_8CH_TX_SRC 116 +#define SCLK_I2S3_8CH_RX_SRC 117 +#define SCLK_I2S0_2CH_SRC 118 +#define SCLK_I2S1_2CH_SRC 119 +#define SCLK_PWM1 120 +#define SCLK_PWM2 121 +#define SCLK_OWIRE 122 + +/* dclk */ +#define DCLK_VOP 125 + +/* aclk */ +#define ACLK_BUS_SRC 130 +#define ACLK_BUS 131 +#define ACLK_PERI_SRC 132 +#define ACLK_PERI 133 +#define ACLK_MAC 134 +#define ACLK_CRYPTO 135 +#define ACLK_VOP 136 +#define ACLK_GIC 137 +#define ACLK_DMAC0 138 +#define ACLK_DMAC1 139 + +/* hclk */ +#define HCLK_BUS 150 +#define HCLK_PERI 151 +#define HCLK_AUDIO 152 +#define HCLK_NANDC 153 +#define HCLK_SDMMC 154 +#define HCLK_SDIO 155 +#define HCLK_EMMC 156 +#define HCLK_SFC 157 +#define HCLK_OTG 158 +#define HCLK_HOST 159 +#define HCLK_HOST_ARB 160 +#define HCLK_PDM 161 +#define HCLK_SPDIFTX 162 +#define HCLK_SPDIFRX 163 +#define HCLK_I2S0_8CH 164 +#define HCLK_I2S1_8CH 165 +#define HCLK_I2S2_8CH 166 +#define HCLK_I2S3_8CH 167 +#define HCLK_I2S0_2CH 168 +#define HCLK_I2S1_2CH 169 +#define HCLK_VAD 170 +#define HCLK_CRYPTO 171 +#define HCLK_VOP 172 + +/* pclk */ +#define PCLK_BUS 190 +#define PCLK_DDR 191 +#define PCLK_PERI 192 +#define PCLK_PMU 193 +#define PCLK_AUDIO 194 +#define PCLK_MAC 195 +#define PCLK_ACODEC 196 +#define PCLK_UART0 197 +#define PCLK_UART1 198 +#define PCLK_UART2 199 +#define PCLK_UART3 200 +#define PCLK_UART4 201 +#define PCLK_I2C0 202 +#define PCLK_I2C1 203 +#define PCLK_I2C2 204 +#define PCLK_I2C3 205 +#define PCLK_PWM0 206 +#define PCLK_SPI0 207 +#define PCLK_SPI1 208 +#define PCLK_SPI2 209 +#define PCLK_SARADC 210 +#define PCLK_TSADC 211 +#define PCLK_TIMER 212 +#define PCLK_OTP_NS 213 +#define PCLK_WDT 214 +#define PCLK_GPIO0 215 +#define PCLK_GPIO1 216 +#define PCLK_GPIO2 217 +#define PCLK_GPIO3 218 +#define PCLK_GPIO4 219 +#define PCLK_SGRF 220 +#define PCLK_GRF 221 +#define PCLK_USBSD_DET 222 +#define PCLK_DDR_UPCTL 223 +#define PCLK_DDR_MON 224 +#define PCLK_DDRPHY 225 +#define PCLK_DDR_STDBY 226 +#define PCLK_USB_GRF 227 +#define PCLK_CRU 228 +#define PCLK_OTP_PHY 229 +#define PCLK_CPU_BOOST 230 +#define PCLK_PWM1 231 +#define PCLK_PWM2 232 +#define PCLK_CAN 233 +#define PCLK_OWIRE 234 + +#define CLK_NR_CLKS (PCLK_OWIRE + 1) + +/* soft-reset indices */ + +/* cru_softrst_con0 */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_CORE_NOC 13 +#define SRST_STRC_A 14 +#define SRST_L2C 15 + +/* cru_softrst_con1 */ +#define SRST_DAP 16 +#define SRST_CORE_PVTM 17 +#define SRST_CORE_PRF 18 +#define SRST_CORE_GRF 19 +#define SRST_DDRUPCTL 20 +#define SRST_DDRUPCTL_P 22 +#define SRST_MSCH 23 +#define SRST_DDRMON_P 25 +#define SRST_DDRSTDBY_P 26 +#define SRST_DDRSTDBY 27 +#define SRST_DDRPHY 28 +#define SRST_DDRPHY_DIV 29 +#define SRST_DDRPHY_P 30 + +/* cru_softrst_con2 */ +#define SRST_BUS_NIU_H 32 +#define SRST_USB_NIU_P 33 +#define SRST_CRYPTO_A 34 +#define SRST_CRYPTO_H 35 +#define SRST_CRYPTO 36 +#define SRST_CRYPTO_APK 37 +#define SRST_VOP_A 38 +#define SRST_VOP_H 39 +#define SRST_VOP_D 40 +#define SRST_INTMEM_A 41 +#define SRST_ROM_H 42 +#define SRST_GIC_A 43 +#define SRST_UART0_P 44 +#define SRST_UART0 45 +#define SRST_UART1_P 46 +#define SRST_UART1 47 + +/* cru_softrst_con3 */ +#define SRST_UART2_P 48 +#define SRST_UART2 49 +#define SRST_UART3_P 50 +#define SRST_UART3 51 +#define SRST_UART4_P 52 +#define SRST_UART4 53 +#define SRST_I2C0_P 54 +#define SRST_I2C0 55 +#define SRST_I2C1_P 56 +#define SRST_I2C1 57 +#define SRST_I2C2_P 58 +#define SRST_I2C2 59 +#define SRST_I2C3_P 60 +#define SRST_I2C3 61 +#define SRST_PWM0_P 62 +#define SRST_PWM0 63 + +/* cru_softrst_con4 */ +#define SRST_SPI0_P 64 +#define SRST_SPI0 65 +#define SRST_SPI1_P 66 +#define SRST_SPI1 67 +#define SRST_SPI2_P 68 +#define SRST_SPI2 69 +#define SRST_SARADC_P 70 +#define SRST_TSADC_P 71 +#define SRST_TSADC 72 +#define SRST_TIMER0_P 73 +#define SRST_TIMER0 74 +#define SRST_TIMER1 75 +#define SRST_TIMER2 76 +#define SRST_TIMER3 77 +#define SRST_TIMER4 78 +#define SRST_TIMER5 79 + +/* cru_softrst_con5 */ +#define SRST_OTP_NS_P 80 +#define SRST_OTP_NS_SBPI 81 +#define SRST_OTP_NS_USR 82 +#define SRST_OTP_PHY_P 83 +#define SRST_OTP_PHY 84 +#define SRST_GPIO0_P 86 +#define SRST_GPIO1_P 87 +#define SRST_GPIO2_P 88 +#define SRST_GPIO3_P 89 +#define SRST_GPIO4_P 90 +#define SRST_GRF_P 91 +#define SRST_USBSD_DET_P 92 +#define SRST_PMU 93 +#define SRST_PMU_PVTM 94 +#define SRST_USB_GRF_P 95 + +/* cru_softrst_con6 */ +#define SRST_CPU_BOOST 96 +#define SRST_CPU_BOOST_P 97 +#define SRST_PWM1_P 98 +#define SRST_PWM1 99 +#define SRST_PWM2_P 100 +#define SRST_PWM2 101 +#define SRST_PERI_NIU_A 104 +#define SRST_PERI_NIU_H 105 +#define SRST_PERI_NIU_p 106 +#define SRST_USB2OTG_H 107 +#define SRST_USB2OTG 108 +#define SRST_USB2OTG_ADP 109 +#define SRST_USB2HOST_H 110 +#define SRST_USB2HOST_ARB_H 111 + +/* cru_softrst_con7 */ +#define SRST_USB2HOST_AUX_H 112 +#define SRST_USB2HOST_EHCI 113 +#define SRST_USB2HOST 114 +#define SRST_USBPHYPOR 115 +#define SRST_UTMI0 116 +#define SRST_UTMI1 117 +#define SRST_SDIO_H 118 +#define SRST_EMMC_H 119 +#define SRST_SFC_H 120 +#define SRST_SFC 121 +#define SRST_SD_H 122 +#define SRST_NANDC_H 123 +#define SRST_NANDC_N 124 +#define SRST_MAC_A 125 +#define SRST_CAN_P 126 +#define SRST_OWIRE_P 127 + +/* cru_softrst_con8 */ +#define SRST_AUDIO_NIU_H 128 +#define SRST_AUDIO_NIU_P 129 +#define SRST_PDM_H 130 +#define SRST_PDM_M 131 +#define SRST_SPDIFTX_H 132 +#define SRST_SPDIFTX_M 133 +#define SRST_SPDIFRX_H 134 +#define SRST_SPDIFRX_M 135 +#define SRST_I2S0_8CH_H 136 +#define SRST_I2S0_8CH_TX_M 137 +#define SRST_I2S0_8CH_RX_M 138 +#define SRST_I2S1_8CH_H 139 +#define SRST_I2S1_8CH_TX_M 140 +#define SRST_I2S1_8CH_RX_M 141 +#define SRST_I2S2_8CH_H 142 +#define SRST_I2S2_8CH_TX_M 143 + +/* cru_softrst_con9 */ +#define SRST_I2S2_8CH_RX_M 144 +#define SRST_I2S3_8CH_H 145 +#define SRST_I2S3_8CH_TX_M 146 +#define SRST_I2S3_8CH_RX_M 147 +#define SRST_I2S0_2CH_H 148 +#define SRST_I2S0_2CH_M 149 +#define SRST_I2S1_2CH_H 150 +#define SRST_I2S1_2CH_M 151 +#define SRST_VAD_H 152 +#define SRST_ACODEC_P 153 + +#endif diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h new file mode 100644 index 000000000000..62479fddb96b --- /dev/null +++ b/include/dt-bindings/clock/rk3328-cru.h @@ -0,0 +1,402 @@ +/* + * Copyright (c) 2016 Rockchip Electronics Co. Ltd. + * Author: Elaine <zhangqing@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define PLL_NPLL 5 +#define ARMCLK 6 + +/* sclk gates (special clocks) */ +#define SCLK_RTC32K 30 +#define SCLK_SDMMC_EXT 31 +#define SCLK_SPI 32 +#define SCLK_SDMMC 33 +#define SCLK_SDIO 34 +#define SCLK_EMMC 35 +#define SCLK_TSADC 36 +#define SCLK_SARADC 37 +#define SCLK_UART0 38 +#define SCLK_UART1 39 +#define SCLK_UART2 40 +#define SCLK_I2S0 41 +#define SCLK_I2S1 42 +#define SCLK_I2S2 43 +#define SCLK_I2S1_OUT 44 +#define SCLK_I2S2_OUT 45 +#define SCLK_SPDIF 46 +#define SCLK_TIMER0 47 +#define SCLK_TIMER1 48 +#define SCLK_TIMER2 49 +#define SCLK_TIMER3 50 +#define SCLK_TIMER4 51 +#define SCLK_TIMER5 52 +#define SCLK_WIFI 53 +#define SCLK_CIF_OUT 54 +#define SCLK_I2C0 55 +#define SCLK_I2C1 56 +#define SCLK_I2C2 57 +#define SCLK_I2C3 58 +#define SCLK_CRYPTO 59 +#define SCLK_PWM 60 +#define SCLK_PDM 61 +#define SCLK_EFUSE 62 +#define SCLK_OTP 63 +#define SCLK_DDRCLK 64 +#define SCLK_VDEC_CABAC 65 +#define SCLK_VDEC_CORE 66 +#define SCLK_VENC_DSP 67 +#define SCLK_VENC_CORE 68 +#define SCLK_RGA 69 +#define SCLK_HDMI_SFC 70 +#define SCLK_HDMI_CEC 71 +#define SCLK_USB3_REF 72 +#define SCLK_USB3_SUSPEND 73 +#define SCLK_SDMMC_DRV 74 +#define SCLK_SDIO_DRV 75 +#define SCLK_EMMC_DRV 76 +#define SCLK_SDMMC_EXT_DRV 77 +#define SCLK_SDMMC_SAMPLE 78 +#define SCLK_SDIO_SAMPLE 79 +#define SCLK_EMMC_SAMPLE 80 +#define SCLK_SDMMC_EXT_SAMPLE 81 +#define SCLK_VOP 82 +#define SCLK_MAC2PHY_RXTX 83 +#define SCLK_MAC2PHY_SRC 84 +#define SCLK_MAC2PHY_REF 85 +#define SCLK_MAC2PHY_OUT 86 +#define SCLK_MAC2IO_RX 87 +#define SCLK_MAC2IO_TX 88 +#define SCLK_MAC2IO_REFOUT 89 +#define SCLK_MAC2IO_REF 90 +#define SCLK_MAC2IO_OUT 91 +#define SCLK_TSP 92 +#define SCLK_HSADC_TSP 93 +#define SCLK_USB3PHY_REF 94 +#define SCLK_REF_USB3OTG 95 +#define SCLK_USB3OTG_REF 96 +#define SCLK_USB3OTG_SUSPEND 97 +#define SCLK_REF_USB3OTG_SRC 98 +#define SCLK_MAC2IO_SRC 99 +#define SCLK_MAC2IO 100 +#define SCLK_MAC2PHY 101 +#define SCLK_MAC2IO_EXT 102 + +/* dclk gates */ +#define DCLK_LCDC 120 +#define DCLK_HDMIPHY 121 +#define HDMIPHY 122 +#define USB480M 123 +#define DCLK_LCDC_SRC 124 + +/* aclk gates */ +#define ACLK_AXISRAM 130 +#define ACLK_VOP_PRE 131 +#define ACLK_USB3OTG 132 +#define ACLK_RGA_PRE 133 +#define ACLK_DMAC 134 +#define ACLK_GPU 135 +#define ACLK_BUS_PRE 136 +#define ACLK_PERI_PRE 137 +#define ACLK_RKVDEC_PRE 138 +#define ACLK_RKVDEC 139 +#define ACLK_RKVENC 140 +#define ACLK_VPU_PRE 141 +#define ACLK_VIO_PRE 142 +#define ACLK_VPU 143 +#define ACLK_VIO 144 +#define ACLK_VOP 145 +#define ACLK_GMAC 146 +#define ACLK_H265 147 +#define ACLK_H264 148 +#define ACLK_MAC2PHY 149 +#define ACLK_MAC2IO 150 +#define ACLK_DCF 151 +#define ACLK_TSP 152 +#define ACLK_PERI 153 +#define ACLK_RGA 154 +#define ACLK_IEP 155 +#define ACLK_CIF 156 +#define ACLK_HDCP 157 + +/* pclk gates */ +#define PCLK_GPIO0 200 +#define PCLK_GPIO1 201 +#define PCLK_GPIO2 202 +#define PCLK_GPIO3 203 +#define PCLK_GRF 204 +#define PCLK_I2C0 205 +#define PCLK_I2C1 206 +#define PCLK_I2C2 207 +#define PCLK_I2C3 208 +#define PCLK_SPI 209 +#define PCLK_UART0 210 +#define PCLK_UART1 211 +#define PCLK_UART2 212 +#define PCLK_TSADC 213 +#define PCLK_PWM 214 +#define PCLK_TIMER 215 +#define PCLK_BUS_PRE 216 +#define PCLK_PERI_PRE 217 +#define PCLK_HDMI_CTRL 218 +#define PCLK_HDMI_PHY 219 +#define PCLK_GMAC 220 +#define PCLK_H265 221 +#define PCLK_MAC2PHY 222 +#define PCLK_MAC2IO 223 +#define PCLK_USB3PHY_OTG 224 +#define PCLK_USB3PHY_PIPE 225 +#define PCLK_USB3_GRF 226 +#define PCLK_USB2_GRF 227 +#define PCLK_HDMIPHY 228 +#define PCLK_DDR 229 +#define PCLK_PERI 230 +#define PCLK_HDMI 231 +#define PCLK_HDCP 232 +#define PCLK_DCF 233 +#define PCLK_SARADC 234 +#define PCLK_ACODEC 235 + +/* hclk gates */ +#define HCLK_PERI 308 +#define HCLK_TSP 309 +#define HCLK_GMAC 310 +#define HCLK_I2S0_8CH 311 +#define HCLK_I2S1_8CH 312 +#define HCLK_I2S2_2CH 313 +#define HCLK_SPDIF_8CH 314 +#define HCLK_VOP 315 +#define HCLK_NANDC 316 +#define HCLK_SDMMC 317 +#define HCLK_SDIO 318 +#define HCLK_EMMC 319 +#define HCLK_SDMMC_EXT 320 +#define HCLK_RKVDEC_PRE 321 +#define HCLK_RKVDEC 322 +#define HCLK_RKVENC 323 +#define HCLK_VPU_PRE 324 +#define HCLK_VIO_PRE 325 +#define HCLK_VPU 326 +#define HCLK_VIO 327 +#define HCLK_BUS_PRE 328 +#define HCLK_PERI_PRE 329 +#define HCLK_H264 330 +#define HCLK_CIF 331 +#define HCLK_OTG_PMU 332 +#define HCLK_OTG 333 +#define HCLK_HOST0 334 +#define HCLK_HOST0_ARB 335 +#define HCLK_CRYPTO_MST 336 +#define HCLK_CRYPTO_SLV 337 +#define HCLK_PDM 338 +#define HCLK_IEP 339 +#define HCLK_RGA 340 +#define HCLK_HDCP 341 + +#define CLK_NR_CLKS (HCLK_HDCP + 1) + +/* soft-reset indices */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_CORE_NIU 13 +#define SRST_STRC_A 14 +#define SRST_L2C 15 + +#define SRST_A53_GIC 18 +#define SRST_DAP 19 +#define SRST_PMU_P 21 +#define SRST_EFUSE 22 +#define SRST_BUSSYS_H 23 +#define SRST_BUSSYS_P 24 +#define SRST_SPDIF 25 +#define SRST_INTMEM 26 +#define SRST_ROM 27 +#define SRST_GPIO0 28 +#define SRST_GPIO1 29 +#define SRST_GPIO2 30 +#define SRST_GPIO3 31 + +#define SRST_I2S0 32 +#define SRST_I2S1 33 +#define SRST_I2S2 34 +#define SRST_I2S0_H 35 +#define SRST_I2S1_H 36 +#define SRST_I2S2_H 37 +#define SRST_UART0 38 +#define SRST_UART1 39 +#define SRST_UART2 40 +#define SRST_UART0_P 41 +#define SRST_UART1_P 42 +#define SRST_UART2_P 43 +#define SRST_I2C0 44 +#define SRST_I2C1 45 +#define SRST_I2C2 46 +#define SRST_I2C3 47 + +#define SRST_I2C0_P 48 +#define SRST_I2C1_P 49 +#define SRST_I2C2_P 50 +#define SRST_I2C3_P 51 +#define SRST_EFUSE_SE_P 52 +#define SRST_EFUSE_NS_P 53 +#define SRST_PWM0 54 +#define SRST_PWM0_P 55 +#define SRST_DMA 56 +#define SRST_TSP_A 57 +#define SRST_TSP_H 58 +#define SRST_TSP 59 +#define SRST_TSP_HSADC 60 +#define SRST_DCF_A 61 +#define SRST_DCF_P 62 + +#define SRST_SCR 64 +#define SRST_SPI 65 +#define SRST_TSADC 66 +#define SRST_TSADC_P 67 +#define SRST_CRYPTO 68 +#define SRST_SGRF 69 +#define SRST_GRF 70 +#define SRST_USB_GRF 71 +#define SRST_TIMER_6CH_P 72 +#define SRST_TIMER0 73 +#define SRST_TIMER1 74 +#define SRST_TIMER2 75 +#define SRST_TIMER3 76 +#define SRST_TIMER4 77 +#define SRST_TIMER5 78 +#define SRST_USB3GRF 79 + +#define SRST_PHYNIU 80 +#define SRST_HDMIPHY 81 +#define SRST_VDAC 82 +#define SRST_ACODEC_p 83 +#define SRST_SARADC 85 +#define SRST_SARADC_P 86 +#define SRST_GRF_DDR 87 +#define SRST_DFIMON 88 +#define SRST_MSCH 89 +#define SRST_DDRMSCH 91 +#define SRST_DDRCTRL 92 +#define SRST_DDRCTRL_P 93 +#define SRST_DDRPHY 94 +#define SRST_DDRPHY_P 95 + +#define SRST_GMAC_NIU_A 96 +#define SRST_GMAC_NIU_P 97 +#define SRST_GMAC2PHY_A 98 +#define SRST_GMAC2IO_A 99 +#define SRST_MACPHY 100 +#define SRST_OTP_PHY 101 +#define SRST_GPU_A 102 +#define SRST_GPU_NIU_A 103 +#define SRST_SDMMCEXT 104 +#define SRST_PERIPH_NIU_A 105 +#define SRST_PERIHP_NIU_H 106 +#define SRST_PERIHP_P 107 +#define SRST_PERIPHSYS_H 108 +#define SRST_MMC0 109 +#define SRST_SDIO 110 +#define SRST_EMMC 111 + +#define SRST_USB2OTG_H 112 +#define SRST_USB2OTG 113 +#define SRST_USB2OTG_ADP 114 +#define SRST_USB2HOST_H 115 +#define SRST_USB2HOST_ARB 116 +#define SRST_USB2HOST_AUX 117 +#define SRST_USB2HOST_EHCIPHY 118 +#define SRST_USB2HOST_UTMI 119 +#define SRST_USB3OTG 120 +#define SRST_USBPOR 121 +#define SRST_USB2OTG_UTMI 122 +#define SRST_USB2HOST_PHY_UTMI 123 +#define SRST_USB3OTG_UTMI 124 +#define SRST_USB3PHY_U2 125 +#define SRST_USB3PHY_U3 126 +#define SRST_USB3PHY_PIPE 127 + +#define SRST_VIO_A 128 +#define SRST_VIO_BUS_H 129 +#define SRST_VIO_H2P_H 130 +#define SRST_VIO_ARBI_H 131 +#define SRST_VOP_NIU_A 132 +#define SRST_VOP_A 133 +#define SRST_VOP_H 134 +#define SRST_VOP_D 135 +#define SRST_RGA 136 +#define SRST_RGA_NIU_A 137 +#define SRST_RGA_A 138 +#define SRST_RGA_H 139 +#define SRST_IEP_A 140 +#define SRST_IEP_H 141 +#define SRST_HDMI 142 +#define SRST_HDMI_P 143 + +#define SRST_HDCP_A 144 +#define SRST_HDCP 145 +#define SRST_HDCP_H 146 +#define SRST_CIF_A 147 +#define SRST_CIF_H 148 +#define SRST_CIF_P 149 +#define SRST_OTP_P 150 +#define SRST_OTP_SBPI 151 +#define SRST_OTP_USER 152 +#define SRST_DDRCTRL_A 153 +#define SRST_DDRSTDY_P 154 +#define SRST_DDRSTDY 155 +#define SRST_PDM_H 156 +#define SRST_PDM 157 +#define SRST_USB3PHY_OTG_P 158 +#define SRST_USB3PHY_PIPE_P 159 + +#define SRST_VCODEC_A 160 +#define SRST_VCODEC_NIU_A 161 +#define SRST_VCODEC_H 162 +#define SRST_VCODEC_NIU_H 163 +#define SRST_VDEC_A 164 +#define SRST_VDEC_NIU_A 165 +#define SRST_VDEC_H 166 +#define SRST_VDEC_NIU_H 167 +#define SRST_VDEC_CORE 168 +#define SRST_VDEC_CABAC 169 +#define SRST_DDRPHYDIV 175 + +#define SRST_RKVENC_NIU_A 176 +#define SRST_RKVENC_NIU_H 177 +#define SRST_RKVENC_H265_A 178 +#define SRST_RKVENC_H265_P 179 +#define SRST_RKVENC_H265_CORE 180 +#define SRST_RKVENC_H265_DSP 181 +#define SRST_RKVENC_H264_A 182 +#define SRST_RKVENC_H264_H 183 +#define SRST_RKVENC_INTMEM 184 + +#endif diff --git a/include/dt-bindings/clock/rk3366-cru.h b/include/dt-bindings/clock/rk3366-cru.h new file mode 100644 index 000000000000..31ae3993b123 --- /dev/null +++ b/include/dt-bindings/clock/rk3366-cru.h @@ -0,0 +1,424 @@ +/* + * Copyright (c) 2016 Rockchip Electronics Co. Ltd. + * Author: Xiao Feng <xf@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3366_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3366_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define PLL_NPLL 5 +#define PLL_MPLL 6 +#define PLL_WPLL 7 +#define PLL_BPLL 8 +#define ARMCLK 9 + +/* sclk gates (special clocks) */ +#define SCLK_CRYPTO 64 +#define SCLK_I2S_8CH_OUT 65 +#define SCLK_I2S_8CH 66 +#define SCLK_I2S_2CH 67 +#define SCLK_SPDIF_8CH 68 +#define SCLK_RGA 69 +#define SCLK_VOP_FULL_PWM 70 +#define SCLK_ISP 71 +#define SCLK_HDMI_HDCP 72 +#define SCLK_HDMI_CEC 73 +#define SCLK_HDCP 75 +#define SCLK_PVTM_CORE 76 +#define SCLK_PVTM_GPU 77 +#define SCLK_SPI0 78 +#define SCLK_SPI1 79 +#define SCLK_SPI2 80 +#define SCLK_SDMMC 81 +#define SCLK_SDIO0 82 +#define SCLK_SDIO1 83 +#define SCLK_EMMC 84 +#define SCLK_SDMMC_DRV 85 +#define SCLK_SDMMC_SAMPLE 86 +#define SCLK_SDIO0_DRV 87 +#define SCLK_SDIO0_SAMPLE 88 +#define SCLK_SDIO1_DRV 89 +#define SCLK_SDIO1_SAMPLE 90 +#define SCLK_EMMC_DRV 91 +#define SCLK_EMMC_SAMPLE 92 +#define SCLK_OTG_PHY0 93 +#define SCLK_OTG_PHY1 94 +#define SCLK_OTG_ADP 95 +#define SCLK_USB3_REF 96 +#define SCLK_USB3_SUSPEND 97 +#define SCLK_TSADC 98 +#define SCLK_SARADC 99 +#define SCLK_NANDC0 100 +#define SCLK_SFC 101 +#define SCLK_UART0 102 +#define SCLK_UART1 103 +#define SCLK_UART2 104 +#define SCLK_UART3 105 +#define SCLK_UART4 106 +#define SCLK_MAC 107 +#define SCLK_MACREF_OUT 108 +#define SCLK_MACREF 109 +#define SCLK_MAC_RX 110 +#define SCLK_MAC_TX 111 +#define SCLK_BT_52 112 +#define SCLK_BT_M0 113 +#define SCLK_WIFIDSP 114 +#define SCLK_TIMER0 115 +#define SCLK_TIMER1 116 +#define SCLK_TIMER2 117 +#define SCLK_TIMER3 118 +#define SCLK_TIMER4 119 +#define SCLK_TIMER5 120 +#define SCLK_USBPHY480M 121 +#define SCLK_WIFI_WPLL 122 +#define SCLK_WIFI_USBPHY480M 123 +#define SCLK_MIPIDSI_24M 124 +#define SCLK_HEVC_CABAC 125 +#define SCLK_HEVC_CORE 126 +#define SCLK_VIP_SRC 127 +#define SCLK_VIP_OUT 128 +#define SCLK_PVTM_PMU 129 +#define SCLK_MPLL_SRC 130 +#define SCLK_32K_INTR 131 +#define SCLK_32K 132 +#define SCLK_I2S_8CH_SRC 133 +#define SCLK_I2S_2CH_SRC 134 +#define SCLK_SPDIF_8CH_SRC 135 + +#define DCLK_VOP_FULL 170 +#define DCLK_VOP_LITE 171 +#define DCLK_HDMIPHY 172 +#define MCLK_CRYPTO 173 + +/* aclk gates */ +#define ACLK_DMAC_BUS 194 +#define ACLK_DFC 195 +#define ACLK_GPU 196 +#define ACLK_GPU_NOC 197 +#define ACLK_USB3 198 +#define ACLK_GMAC 199 +#define ACLK_DMAC_PERI 200 +#define ACLK_VIDEO 201 +#define ACLK_RKVDEC 202 +#define ACLK_RGA 203 +#define ACLK_IEP 204 +#define ACLK_VOP_LITE 205 +#define ACLK_VOP_FULL 206 +#define ACLK_VOP_IEP 207 +#define ACLK_ISP 208 +#define ACLK_HDCP 209 +#define ACLK_BUS 210 +#define ACLK_PERI0 211 +#define ACLK_PERI1 212 + +/* pclk gates */ +#define PCLK_PMU 322 +#define PCLK_SGRF 323 +#define PCLK_PMUGRF 324 +#define PCLK_GPIO0 325 +#define PCLK_GPIO1 326 +#define PCLK_GPIO2 327 +#define PCLK_GPIO3 328 +#define PCLK_GPIO4 329 +#define PCLK_GPIO5 330 +#define PCLK_GRF 331 +#define PCLK_DPHYRX 332 +#define PCLK_DPHYTX 333 +#define PCLK_TIMER0 334 +#define PCLK_DMFIMON 335 +#define PCLK_MAILBOX 336 +#define PCLK_DFC 337 +#define PCLK_DDRUPCTL 338 +#define PCLK_DDRPHY 339 +#define PCLK_RKPWM 340 +#define PCLK_GMAC 341 +#define PCLK_SPI0 342 +#define PCLK_SPI1 343 +#define PCLK_I2C0 344 +#define PCLK_I2C1 345 +#define PCLK_I2C2 346 +#define PCLK_I2C3 347 +#define PCLK_I2C4 348 +#define PCLK_I2C5 349 +#define PCLK_UART0 350 +#define PCLK_UART2 351 +#define PCLK_UART3 352 +#define PCLK_SARADC 353 +#define PCLK_TSADC 354 +#define PCLK_SIM 355 +#define PCLK_HDCP 356 +#define PCLK_HDMI_CTRL 357 +#define PCLK_VIO_H2P 358 +#define PCLK_WDT 359 +#define PCLK_BUS 361 +#define PCLK_PERI0 362 +#define PCLK_PERI1 363 +#define PCLK_MIPI_DSI0 364 +#define PCLK_ISP 365 +#define PCLK_EFUSE_1024 366 +#define PCLK_EFUSE_256 367 + +/* hclk gates */ +#define HCLK_I2S_8CH 448 +#define HCLK_I2S_2CH 449 +#define HCLK_SPDIF 450 +#define HCLK_ROM 451 +#define HCLK_CRYPTO 452 +#define HCLK_OTG 453 +#define HCLK_HOST 454 +#define HCLK_SDMMC 455 +#define HCLK_SDIO 456 +#define HCLK_EMMC 457 +#define HCLK_NANDC0 458 +#define HCLK_SFC 459 +#define HCLK_VIDEO 460 +#define HCLK_RKVDEC 461 +#define HCLK_ISP 462 +#define HCLK_RGA 463 +#define HCLK_IEP 464 +#define HCLK_VOP_FULL 465 +#define HCLK_VOP_LITE 466 +#define HCLK_VIO_AHB_ARBITER 467 +#define HCLK_VIO_NOC 468 +#define HCLK_VIO_H2P 469 +#define HCLK_VIO_HDCPMMU 470 +#define HCLK_BUS 471 +#define HCLK_PERI0 472 +#define HCLK_PERI1 473 + +#define CLK_NR_CLKS (HCLK_PERI1 + 1) + +/* soft-reset indices */ + +/* cru_softrst0_con */ +#define SRST_CORE0 0 +#define SRST_CORE1 1 +#define SRST_CORE2 2 +#define SRST_CORE3 3 +#define SRST_CORE0_PO 4 +#define SRST_CORE1_PO 5 +#define SRST_CORE2_PO 6 +#define SRST_CORE3_PO 7 +#define SRST_SOCDBG 14 +#define SRST_CORE_DBG 15 + +/* cru_softrst1_con */ +#define SRST_DCF_AXI 16 +#define SRST_DCF_APB 17 +#define SRST_DMAC1 18 +#define SRST_INTMEM 19 +#define SRST_ROM 20 +#define SRST_SPDIF8CH 21 +#define SRST_I2S8CH 23 +#define SRST_MAILBOX 24 +#define SRST_I2S2CH 25 +#define SRST_EFUSE_256 26 +#define SRST_MCU_SYS 28 +#define SRST_MCU_PO 29 +#define SRST_MCU_NOC 30 +#define SRST_EFUSE 31 + +/* cru_softrst2_con */ +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_GPIO3 35 +#define SRST_GPIO4 36 +#define SRST_GPIO5 37 +#define SRST_PMUGRF 41 +#define SRST_I2C0 42 +#define SRST_I2C1 43 +#define SRST_I2C2 44 +#define SRST_I2C3 45 +#define SRST_I2C4 46 +#define SRST_I2C5 47 + +/* cru_softrst3_con */ +#define SRST_DWPWM 48 +#define SRST_PERIPH1_AXI 50 +#define SRST_PERIPH1_AHB 51 +#define SRST_PERIPH1_APB 52 +#define SRST_PERIPH1_NIU 53 +#define SRST_PERI_AHB_ARBI1 54 +#define SRST_GRF 55 +#define SRST_PMU 56 +#define SRST_PERIPH0_AXI 57 +#define SRST_PERIPH0_AHB 58 +#define SRST_PERIPH0_APB 59 +#define SRST_PERIPH0_NIU 60 +#define SRST_PDPERI_AHB_ARBI0 61 +#define SRST_USBHOST0_ARBI 62 + +/* cru_softrst4_con */ +#define SRST_DMAC2 64 +#define SRST_MAC 66 +#define SRST_USB3 67 +#define SRST_USB3PHY 68 +#define SRST_RKPWM 69 +#define SRST_USBHOST0 72 +#define SRST_HSADC 76 +#define SRST_NANDC0 77 +#define SRST_SFC 79 + +/* cru_softrst5_con */ +#define SRST_TZPC 80 +#define SRST_SPI0 83 +#define SRST_SPI1 84 +#define SRST_SARADC 87 +#define SRST_PDALIVE_NIU 88 +#define SRST_PDPMU_INTMEM 89 +#define SRST_PDPMU_NIU 90 +#define SRST_SGRF 91 +#define SRST_VOP1_AXI 93 +#define SRST_VOP1_AHB 94 +#define SRST_VOP1_DCLK 95 + +/* cru_softrst6_con */ +#define SRST_VIO_ARBI 96 +#define SRST_RGA_NIU 97 +#define SRST_VIO0_NIU_AXI 98 +#define SRST_VIO_NIU_AHB 99 +#define SRST_VOP0_AXI 100 +#define SRST_VOP0_AHB 101 +#define SRST_VOP0_DCLK 102 +#define SRST_HDCP_NIU 103 +#define SRST_VIP 104 +#define SRST_RGA_CORE 105 +#define SRST_IEP_AXI 106 +#define SRST_IEP_AHB 107 +#define SRST_RGA_AXI 108 +#define SRST_RGA_AHB 109 +#define SRST_ISP 110 + +/* cru_softrst7_con */ +#define SRST_VIDEO_AXI 112 +#define SRST_VIDEO_AHB 113 +#define SRST_MIPIDPHYTX 114 +#define SRST_MIPIDSI0 115 +#define SRST_MIPIDPHYRX 116 +#define SRST_MIPICSI 117 +#define SRST_LVDS_CON 119 +#define SRST_GPU 120 +#define SRST_HDMI 121 +#define SRST_RGA_H2P 122 +#define SRST_PMU_PVTM 123 +#define SRST_CORE_PVTM 124 +#define SRST_GPU_PVTM 125 +#define SRST_GPU_NOC 126 + +/* cru_softrst8_con */ +#define SRST_MMC0 128 +#define SRST_SDIO0 129 +#define SRST_EMMC 131 +#define SRST_USBOTG_AHB 132 +#define SRST_USBOTG_PHY 133 +#define SRST_USBOTG_CON 134 +#define SRST_USBHOST0_AHB 135 +#define SRST_USBHPHY1 136 +#define SRST_USBHOST0_CON 137 +#define SRST_USBOTG_UTMI 138 +#define SRST_USBHOST0_UTMI 139 +#define SRST_USB_ADP 141 +#define SRST_TSADC 142 + +/* cru_softrst9_con */ +#define SRST_CORESIGHT 144 +#define SRST_PD_CORE_AHB_NOC 145 +#define SRST_PD_CORE_APB_NOC 146 +#define SRST_RKVDEC_NIU_AHB 147 +#define SRST_GIC 148 +#define SRST_LCDC_PWM0 149 +#define SRST_RKVDEC 150 +#define SRST_RKVDEC_NIU 151 +#define SRST_RKVDEC_AHB 152 +#define SRST_RKVDEC_CABAC 154 +#define SRST_RKVDEC_CORE 155 +#define SRST_GPU_CFG_NIU 157 +#define SRST_DFIMON 158 +#define SRST_TSADC_APB 159 + +/* cru_softrst10_con */ +#define SRST_DDRPHY0 160 +#define SRST_DDRPHY0_APB 161 +#define SRST_DDRCTRL0 162 +#define SRST_DDRCTRL0_APB 163 +#define SRST_DDRPHY0_CTL 164 +#define SRST_VIDEO_NIU 165 +#define SRST_VIDEO_NIU_AHB 167 +#define SRST_DDRMSCH0 170 +#define SRST_PDBUS_AHB 173 +#define SRST_CRYPTO 174 +#define SRST_DDR_NOC 175 + +/* cru_softrst11_con */ +#define SRST_PSPVTM_TOP 176 +#define SRST_PSPVTM_CORE 177 +#define SRST_PSPVTM_GPU 178 +#define SRST_UART0 179 +#define SRST_UART1 180 +#define SRST_UART2 181 +#define SRST_UART3 182 +#define SRST_UART4 183 +#define SRST_PSPVTM_VIDEO 184 +#define SRST_PSPVTM_VIO 185 +#define SRST_SIMC 186 +#define SRST_PSPVTM_PERI 187 + +/* cru_softrst12_con */ +#define SRST_WIFI_MAC_CORE 192 +#define SRST_WIFI_MAC_WT 193 +#define SRST_WIFI_MPIF 194 +#define SRST_WIFI_EXT 195 +#define SRST_WIFI_AHB 196 +#define SRST_WIFI_DSP 197 +#define SRST_BT_FAST_AHB 198 +#define SRST_BT_SLOW_AHB 199 +#define SRST_BT_SLOW_APB 200 +#define SRST_BT_MODEM 201 +#define SRST_BT_MCU 202 +#define SRST_BT_DM 203 +#define SRST_WIFI_LP 204 +#define SRST_BT_LP 205 +#define SRST_BT_MCU_SYS 206 +#define SRST_WIFI_DSP_ORSTN 207 + +/* cru_softrst13_con */ +#define SRST_CORE0_WFI 208 +#define SRST_CORE0_PO_WFI 209 +#define SRST_CORE_L2 210 +#define SRST_PD_CORE_NIU 212 +#define SRST_PDBUS_STRSYS 213 +#define SRST_TRACE 222 + +/* cru_softrst14_con */ +#define SRST_TIMER00 224 +#define SRST_TIMER01 225 +#define SRST_TIMER02 226 +#define SRST_TIMER03 227 +#define SRST_TIMER04 228 +#define SRST_TIMER05 229 +#define SRST_TIMER10 230 +#define SRST_TIMER11 231 +#define SRST_TIMER12 232 +#define SRST_TIMER13 233 +#define SRST_TIMER14 234 +#define SRST_TIMER15 235 +#define SRST_TIMER0_APB 236 +#define SRST_TIMER1_APB 237 + +#endif diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h index 9c5dd9ba2f6c..5d3531686790 100644 --- a/include/dt-bindings/clock/rk3368-cru.h +++ b/include/dt-bindings/clock/rk3368-cru.h @@ -44,13 +44,12 @@ #define SCLK_I2S_8CH 82 #define SCLK_SPDIF_8CH 83 #define SCLK_I2S_2CH 84 -#define SCLK_TIMER0 85 -#define SCLK_TIMER1 86 -#define SCLK_TIMER2 87 -#define SCLK_TIMER3 88 -#define SCLK_TIMER4 89 -#define SCLK_TIMER5 90 -#define SCLK_TIMER6 91 +#define SCLK_TIMER00 85 +#define SCLK_TIMER01 86 +#define SCLK_TIMER02 87 +#define SCLK_TIMER03 88 +#define SCLK_TIMER04 89 +#define SCLK_TIMER05 90 #define SCLK_OTGPHY0 93 #define SCLK_OTG_ADP 96 #define SCLK_HSICPHY480M 97 @@ -82,6 +81,19 @@ #define SCLK_SFC 126 #define SCLK_MAC 127 #define SCLK_MACREF_OUT 128 +#define SCLK_MIPIDSI_24M 129 +#define SCLK_CRYPTO 130 +#define SCLK_VIP_SRC 131 +#define SCLK_VIP_OUT 132 +#define SCLK_TIMER10 133 +#define SCLK_TIMER11 134 +#define SCLK_TIMER12 135 +#define SCLK_TIMER13 136 +#define SCLK_TIMER14 137 +#define SCLK_TIMER15 138 +#define SCLK_DDRCLK 139 +#define SCLK_TSP 140 +#define SCLK_HSADC_TSP 141 #define DCLK_VOP 190 #define MCLK_CRYPTO 191 @@ -105,6 +117,7 @@ #define ACLK_VIDEO 208 #define ACLK_BUS 209 #define ACLK_PERI 210 +#define ACLK_CCI_PRE 211 /* pclk gates */ #define PCLK_GPIO0 320 @@ -151,8 +164,13 @@ #define PCLK_ISP 366 #define PCLK_VIP 367 #define PCLK_WDT 368 +#define PCLK_DPHYRX 369 +#define PCLK_DPHYTX0 370 +#define PCLK_EFUSE256 371 +#define PCLK_EFUSE1024 372 /* hclk gates */ +#define HCLK_USB_PERI 447 #define HCLK_SFC 448 #define HCLK_OTG0 449 #define HCLK_HOST0 450 diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h new file mode 100644 index 000000000000..a2aa50c8d3ab --- /dev/null +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -0,0 +1,773 @@ +/* + * Copyright (c) 2016 Rockchip Electronics Co. Ltd. + * Author: Xing Zheng <zhengxing@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H + +#define RK3399_TWO_PLL_FOR_VOP + +/* core clocks */ +#define PLL_APLLL 1 +#define PLL_APLLB 2 +#define PLL_DPLL 3 +#define PLL_CPLL 4 +#define PLL_GPLL 5 +#define PLL_NPLL 6 +#define PLL_VPLL 7 +#define ARMCLKL 8 +#define ARMCLKB 9 + +/* sclk gates (special clocks) */ +#define SCLK_I2SOUT_SRC 64 +#define SCLK_I2C1 65 +#define SCLK_I2C2 66 +#define SCLK_I2C3 67 +#define SCLK_I2C5 68 +#define SCLK_I2C6 69 +#define SCLK_I2C7 70 +#define SCLK_SPI0 71 +#define SCLK_SPI1 72 +#define SCLK_SPI2 73 +#define SCLK_SPI4 74 +#define SCLK_SPI5 75 +#define SCLK_SDMMC 76 +#define SCLK_SDIO 77 +#define SCLK_EMMC 78 +#define SCLK_TSADC 79 +#define SCLK_SARADC 80 +#define SCLK_UART0 81 +#define SCLK_UART1 82 +#define SCLK_UART2 83 +#define SCLK_UART3 84 +#define SCLK_SPDIF_8CH 85 +#define SCLK_I2S0_8CH 86 +#define SCLK_I2S1_8CH 87 +#define SCLK_I2S2_8CH 88 +#define SCLK_I2S_8CH_OUT 89 +#define SCLK_TIMER00 90 +#define SCLK_TIMER01 91 +#define SCLK_TIMER02 92 +#define SCLK_TIMER03 93 +#define SCLK_TIMER04 94 +#define SCLK_TIMER05 95 +#define SCLK_TIMER06 96 +#define SCLK_TIMER07 97 +#define SCLK_TIMER08 98 +#define SCLK_TIMER09 99 +#define SCLK_TIMER10 100 +#define SCLK_TIMER11 101 +#define SCLK_MACREF 102 +#define SCLK_MAC_RX 103 +#define SCLK_MAC_TX 104 +#define SCLK_MAC 105 +#define SCLK_MACREF_OUT 106 +#define SCLK_VOP0_PWM 107 +#define SCLK_VOP1_PWM 108 +#define SCLK_RGA_CORE 109 +#define SCLK_ISP0 110 +#define SCLK_ISP1 111 +#define SCLK_HDMI_CEC 112 +#define SCLK_HDMI_SFR 113 +#define SCLK_DP_CORE 114 +#define SCLK_PVTM_CORE_L 115 +#define SCLK_PVTM_CORE_B 116 +#define SCLK_PVTM_GPU 117 +#define SCLK_PVTM_DDR 118 +#define SCLK_MIPIDPHY_REF 119 +#define SCLK_MIPIDPHY_CFG 120 +#define SCLK_HSICPHY 121 +#define SCLK_USBPHY480M 122 +#define SCLK_USB2PHY0_REF 123 +#define SCLK_USB2PHY1_REF 124 +#define SCLK_UPHY0_TCPDPHY_REF 125 +#define SCLK_UPHY0_TCPDCORE 126 +#define SCLK_UPHY1_TCPDPHY_REF 127 +#define SCLK_UPHY1_TCPDCORE 128 +#define SCLK_USB3OTG0_REF 129 +#define SCLK_USB3OTG1_REF 130 +#define SCLK_USB3OTG0_SUSPEND 131 +#define SCLK_USB3OTG1_SUSPEND 132 +#define SCLK_CRYPTO0 133 +#define SCLK_CRYPTO1 134 +#define SCLK_CCI_TRACE 135 +#define SCLK_CS 136 +#define SCLK_CIF_OUT 137 +#define SCLK_PCIEPHY_REF 138 +#define SCLK_PCIE_CORE 139 +#define SCLK_M0_PERILP 140 +#define SCLK_M0_PERILP_DEC 141 +#define SCLK_CM0S 142 +#define SCLK_DBG_NOC 143 +#define SCLK_DBG_PD_CORE_B 144 +#define SCLK_DBG_PD_CORE_L 145 +#define SCLK_DFIMON0_TIMER 146 +#define SCLK_DFIMON1_TIMER 147 +#define SCLK_INTMEM0 148 +#define SCLK_INTMEM1 149 +#define SCLK_INTMEM2 150 +#define SCLK_INTMEM3 151 +#define SCLK_INTMEM4 152 +#define SCLK_INTMEM5 153 +#define SCLK_SDMMC_DRV 154 +#define SCLK_SDMMC_SAMPLE 155 +#define SCLK_SDIO_DRV 156 +#define SCLK_SDIO_SAMPLE 157 +#define SCLK_VDU_CORE 158 +#define SCLK_VDU_CA 159 +#define SCLK_PCIE_PM 160 +#define SCLK_SPDIF_REC_DPTX 161 +#define SCLK_DPHY_PLL 162 +#define SCLK_DPHY_TX0_CFG 163 +#define SCLK_DPHY_TX1RX1_CFG 164 +#define SCLK_DPHY_RX0_CFG 165 +#define SCLK_RMII_SRC 166 +#define SCLK_PCIEPHY_REF100M 167 +#define SCLK_USBPHY0_480M_SRC 168 +#define SCLK_USBPHY1_480M_SRC 169 +#define SCLK_DDRCLK 170 +#define SCLK_TESTCLKOUT2 171 +#define SCLK_UART0_SRC 172 +#define SCLK_UART_SRC 173 +#define SCLK_I2S0_DIV 174 +#define SCLK_I2S1_DIV 175 +#define SCLK_I2S2_DIV 176 +#define SCLK_SPDIF_DIV 177 +#define SCLK_CIF_OUT_SRC 178 +#define SCLK_TESTCLKOUT1 179 + +#define DCLK_VOP0 180 +#define DCLK_VOP1 181 +#define DCLK_VOP0_DIV 182 +#define DCLK_VOP1_DIV 183 +#define DCLK_M0_PERILP 184 +#define DCLK_VOP0_FRAC 185 +#define DCLK_VOP1_FRAC 186 + +#define FCLK_CM0S 190 + +/* aclk gates */ +#define ACLK_PERIHP 192 +#define ACLK_PERIHP_NOC 193 +#define ACLK_PERILP0 194 +#define ACLK_PERILP0_NOC 195 +#define ACLK_PERF_PCIE 196 +#define ACLK_PCIE 197 +#define ACLK_INTMEM 198 +#define ACLK_TZMA 199 +#define ACLK_DCF 200 +#define ACLK_CCI 201 +#define ACLK_CCI_NOC0 202 +#define ACLK_CCI_NOC1 203 +#define ACLK_CCI_GRF 204 +#define ACLK_CENTER 205 +#define ACLK_CENTER_MAIN_NOC 206 +#define ACLK_CENTER_PERI_NOC 207 +#define ACLK_GPU 208 +#define ACLK_PERF_GPU 209 +#define ACLK_GPU_GRF 210 +#define ACLK_DMAC0_PERILP 211 +#define ACLK_DMAC1_PERILP 212 +#define ACLK_GMAC 213 +#define ACLK_GMAC_NOC 214 +#define ACLK_PERF_GMAC 215 +#define ACLK_VOP0_NOC 216 +#define ACLK_VOP0 217 +#define ACLK_VOP1_NOC 218 +#define ACLK_VOP1 219 +#define ACLK_RGA 220 +#define ACLK_RGA_NOC 221 +#define ACLK_HDCP 222 +#define ACLK_HDCP_NOC 223 +#define ACLK_HDCP22 224 +#define ACLK_IEP 225 +#define ACLK_IEP_NOC 226 +#define ACLK_VIO 227 +#define ACLK_VIO_NOC 228 +#define ACLK_ISP0 229 +#define ACLK_ISP1 230 +#define ACLK_ISP0_NOC 231 +#define ACLK_ISP1_NOC 232 +#define ACLK_ISP0_WRAPPER 233 +#define ACLK_ISP1_WRAPPER 234 +#define ACLK_VCODEC 235 +#define ACLK_VCODEC_NOC 236 +#define ACLK_VDU 237 +#define ACLK_VDU_NOC 238 +#define ACLK_PERI 239 +#define ACLK_EMMC 240 +#define ACLK_EMMC_CORE 241 +#define ACLK_EMMC_NOC 242 +#define ACLK_EMMC_GRF 243 +#define ACLK_USB3 244 +#define ACLK_USB3_NOC 245 +#define ACLK_USB3OTG0 246 +#define ACLK_USB3OTG1 247 +#define ACLK_USB3_RKSOC_AXI_PERF 248 +#define ACLK_USB3_GRF 249 +#define ACLK_GIC 250 +#define ACLK_GIC_NOC 251 +#define ACLK_GIC_ADB400_CORE_L_2_GIC 252 +#define ACLK_GIC_ADB400_CORE_B_2_GIC 253 +#define ACLK_GIC_ADB400_GIC_2_CORE_L 254 +#define ACLK_GIC_ADB400_GIC_2_CORE_B 255 +#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256 +#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257 +#define ACLK_ADB400M_PD_CORE_L 258 +#define ACLK_ADB400M_PD_CORE_B 259 +#define ACLK_PERF_CORE_L 260 +#define ACLK_PERF_CORE_B 261 +#define ACLK_GIC_PRE 262 +#define ACLK_VOP0_PRE 263 +#define ACLK_VOP1_PRE 264 + +/* pclk gates */ +#define PCLK_PERIHP 320 +#define PCLK_PERIHP_NOC 321 +#define PCLK_PERILP0 322 +#define PCLK_PERILP1 323 +#define PCLK_PERILP1_NOC 324 +#define PCLK_PERILP_SGRF 325 +#define PCLK_PERIHP_GRF 326 +#define PCLK_PCIE 327 +#define PCLK_SGRF 328 +#define PCLK_INTR_ARB 329 +#define PCLK_CENTER_MAIN_NOC 330 +#define PCLK_CIC 331 +#define PCLK_COREDBG_B 332 +#define PCLK_COREDBG_L 333 +#define PCLK_DBG_CXCS_PD_CORE_B 334 +#define PCLK_DCF 335 +#define PCLK_GPIO2 336 +#define PCLK_GPIO3 337 +#define PCLK_GPIO4 338 +#define PCLK_GRF 339 +#define PCLK_HSICPHY 340 +#define PCLK_I2C1 341 +#define PCLK_I2C2 342 +#define PCLK_I2C3 343 +#define PCLK_I2C5 344 +#define PCLK_I2C6 345 +#define PCLK_I2C7 346 +#define PCLK_SPI0 347 +#define PCLK_SPI1 348 +#define PCLK_SPI2 349 +#define PCLK_SPI4 350 +#define PCLK_SPI5 351 +#define PCLK_UART0 352 +#define PCLK_UART1 353 +#define PCLK_UART2 354 +#define PCLK_UART3 355 +#define PCLK_TSADC 356 +#define PCLK_SARADC 357 +#define PCLK_GMAC 358 +#define PCLK_GMAC_NOC 359 +#define PCLK_TIMER0 360 +#define PCLK_TIMER1 361 +#define PCLK_EDP 362 +#define PCLK_EDP_NOC 363 +#define PCLK_EDP_CTRL 364 +#define PCLK_VIO 365 +#define PCLK_VIO_NOC 366 +#define PCLK_VIO_GRF 367 +#define PCLK_MIPI_DSI0 368 +#define PCLK_MIPI_DSI1 369 +#define PCLK_HDCP 370 +#define PCLK_HDCP_NOC 371 +#define PCLK_HDMI_CTRL 372 +#define PCLK_DP_CTRL 373 +#define PCLK_HDCP22 374 +#define PCLK_GASKET 375 +#define PCLK_DDR 376 +#define PCLK_DDR_MON 377 +#define PCLK_DDR_SGRF 378 +#define PCLK_ISP1_WRAPPER 379 +#define PCLK_WDT 380 +#define PCLK_EFUSE1024NS 381 +#define PCLK_EFUSE1024S 382 +#define PCLK_PMU_INTR_ARB 383 +#define PCLK_MAILBOX0 384 +#define PCLK_USBPHY_MUX_G 385 +#define PCLK_UPHY0_TCPHY_G 386 +#define PCLK_UPHY0_TCPD_G 387 +#define PCLK_UPHY1_TCPHY_G 388 +#define PCLK_UPHY1_TCPD_G 389 +#define PCLK_ALIVE 390 + +/* hclk gates */ +#define HCLK_PERIHP 448 +#define HCLK_PERILP0 449 +#define HCLK_PERILP1 450 +#define HCLK_PERILP0_NOC 451 +#define HCLK_PERILP1_NOC 452 +#define HCLK_M0_PERILP 453 +#define HCLK_M0_PERILP_NOC 454 +#define HCLK_AHB1TOM 455 +#define HCLK_HOST0 456 +#define HCLK_HOST0_ARB 457 +#define HCLK_HOST1 458 +#define HCLK_HOST1_ARB 459 +#define HCLK_HSIC 460 +#define HCLK_SD 461 +#define HCLK_SDMMC 462 +#define HCLK_SDMMC_NOC 463 +#define HCLK_M_CRYPTO0 464 +#define HCLK_M_CRYPTO1 465 +#define HCLK_S_CRYPTO0 466 +#define HCLK_S_CRYPTO1 467 +#define HCLK_I2S0_8CH 468 +#define HCLK_I2S1_8CH 469 +#define HCLK_I2S2_8CH 470 +#define HCLK_SPDIF 471 +#define HCLK_VOP0_NOC 472 +#define HCLK_VOP0 473 +#define HCLK_VOP1_NOC 474 +#define HCLK_VOP1 475 +#define HCLK_ROM 476 +#define HCLK_IEP 477 +#define HCLK_IEP_NOC 478 +#define HCLK_ISP0 479 +#define HCLK_ISP1 480 +#define HCLK_ISP0_NOC 481 +#define HCLK_ISP1_NOC 482 +#define HCLK_ISP0_WRAPPER 483 +#define HCLK_ISP1_WRAPPER 484 +#define HCLK_RGA 485 +#define HCLK_RGA_NOC 486 +#define HCLK_HDCP 487 +#define HCLK_HDCP_NOC 488 +#define HCLK_HDCP22 489 +#define HCLK_VCODEC 490 +#define HCLK_VCODEC_NOC 491 +#define HCLK_VDU 492 +#define HCLK_VDU_NOC 493 +#define HCLK_SDIO 494 +#define HCLK_SDIO_NOC 495 +#define HCLK_SDIOAUDIO_NOC 496 + +#define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1) + +/* pmu-clocks indices */ + +#define PLL_PPLL 1 + +#define SCLK_32K_SUSPEND_PMU 2 +#define SCLK_SPI3_PMU 3 +#define SCLK_TIMER12_PMU 4 +#define SCLK_TIMER13_PMU 5 +#define SCLK_UART4_PMU 6 +#define SCLK_PVTM_PMU 7 +#define SCLK_WIFI_PMU 8 +#define SCLK_I2C0_PMU 9 +#define SCLK_I2C4_PMU 10 +#define SCLK_I2C8_PMU 11 +#define SCLK_UART4_SRC 12 + +#define PCLK_SRC_PMU 19 +#define PCLK_PMU 20 +#define PCLK_PMUGRF_PMU 21 +#define PCLK_INTMEM1_PMU 22 +#define PCLK_GPIO0_PMU 23 +#define PCLK_GPIO1_PMU 24 +#define PCLK_SGRF_PMU 25 +#define PCLK_NOC_PMU 26 +#define PCLK_I2C0_PMU 27 +#define PCLK_I2C4_PMU 28 +#define PCLK_I2C8_PMU 29 +#define PCLK_RKPWM_PMU 30 +#define PCLK_SPI3_PMU 31 +#define PCLK_TIMER_PMU 32 +#define PCLK_MAILBOX_PMU 33 +#define PCLK_UART4_PMU 34 +#define PCLK_WDT_M0_PMU 35 + +#define FCLK_CM0S_SRC_PMU 44 +#define FCLK_CM0S_PMU 45 +#define SCLK_CM0S_PMU 46 +#define HCLK_CM0S_PMU 47 +#define DCLK_CM0S_PMU 48 +#define PCLK_INTR_ARB_PMU 49 +#define HCLK_NOC_PMU 50 + +#define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1) + +/* soft-reset indices */ + +/* cru_softrst_con0 */ +#define SRST_CORE_L0 0 +#define SRST_CORE_B0 1 +#define SRST_CORE_PO_L0 2 +#define SRST_CORE_PO_B0 3 +#define SRST_L2_L 4 +#define SRST_L2_B 5 +#define SRST_ADB_L 6 +#define SRST_ADB_B 7 +#define SRST_A_CCI 8 +#define SRST_A_CCIM0_NOC 9 +#define SRST_A_CCIM1_NOC 10 +#define SRST_DBG_NOC 11 + +/* cru_softrst_con1 */ +#define SRST_CORE_L0_T 16 +#define SRST_CORE_L1 17 +#define SRST_CORE_L2 18 +#define SRST_CORE_L3 19 +#define SRST_CORE_PO_L0_T 20 +#define SRST_CORE_PO_L1 21 +#define SRST_CORE_PO_L2 22 +#define SRST_CORE_PO_L3 23 +#define SRST_A_ADB400_GIC2COREL 24 +#define SRST_A_ADB400_COREL2GIC 25 +#define SRST_P_DBG_L 26 +#define SRST_L2_L_T 28 +#define SRST_ADB_L_T 29 +#define SRST_A_RKPERF_L 30 +#define SRST_PVTM_CORE_L 31 + +/* cru_softrst_con2 */ +#define SRST_CORE_B0_T 32 +#define SRST_CORE_B1 33 +#define SRST_CORE_PO_B0_T 36 +#define SRST_CORE_PO_B1 37 +#define SRST_A_ADB400_GIC2COREB 40 +#define SRST_A_ADB400_COREB2GIC 41 +#define SRST_P_DBG_B 42 +#define SRST_L2_B_T 44 +#define SRST_ADB_B_T 45 +#define SRST_A_RKPERF_B 46 +#define SRST_PVTM_CORE_B 47 + +/* cru_softrst_con3 */ +#define SRST_A_CCI_T 50 +#define SRST_A_CCIM0_NOC_T 51 +#define SRST_A_CCIM1_NOC_T 52 +#define SRST_A_ADB400M_PD_CORE_B_T 53 +#define SRST_A_ADB400M_PD_CORE_L_T 54 +#define SRST_DBG_NOC_T 55 +#define SRST_DBG_CXCS 56 +#define SRST_CCI_TRACE 57 +#define SRST_P_CCI_GRF 58 + +/* cru_softrst_con4 */ +#define SRST_A_CENTER_MAIN_NOC 64 +#define SRST_A_CENTER_PERI_NOC 65 +#define SRST_P_CENTER_MAIN 66 +#define SRST_P_DDRMON 67 +#define SRST_P_CIC 68 +#define SRST_P_CENTER_SGRF 69 +#define SRST_DDR0_MSCH 70 +#define SRST_DDRCFG0_MSCH 71 +#define SRST_DDR0 72 +#define SRST_DDRPHY0 73 +#define SRST_DDR1_MSCH 74 +#define SRST_DDRCFG1_MSCH 75 +#define SRST_DDR1 76 +#define SRST_DDRPHY1 77 +#define SRST_DDR_CIC 78 +#define SRST_PVTM_DDR 79 + +/* cru_softrst_con5 */ +#define SRST_A_VCODEC_NOC 80 +#define SRST_A_VCODEC 81 +#define SRST_H_VCODEC_NOC 82 +#define SRST_H_VCODEC 83 +#define SRST_A_VDU_NOC 88 +#define SRST_A_VDU 89 +#define SRST_H_VDU_NOC 90 +#define SRST_H_VDU 91 +#define SRST_VDU_CORE 92 +#define SRST_VDU_CA 93 + +/* cru_softrst_con6 */ +#define SRST_A_IEP_NOC 96 +#define SRST_A_VOP_IEP 97 +#define SRST_A_IEP 98 +#define SRST_H_IEP_NOC 99 +#define SRST_H_IEP 100 +#define SRST_A_RGA_NOC 102 +#define SRST_A_RGA 103 +#define SRST_H_RGA_NOC 104 +#define SRST_H_RGA 105 +#define SRST_RGA_CORE 106 +#define SRST_EMMC_NOC 108 +#define SRST_EMMC 109 +#define SRST_EMMC_GRF 110 + +/* cru_softrst_con7 */ +#define SRST_A_PERIHP_NOC 112 +#define SRST_P_PERIHP_GRF 113 +#define SRST_H_PERIHP_NOC 114 +#define SRST_USBHOST0 115 +#define SRST_HOSTC0_AUX 116 +#define SRST_HOST0_ARB 117 +#define SRST_USBHOST1 118 +#define SRST_HOSTC1_AUX 119 +#define SRST_HOST1_ARB 120 +#define SRST_SDIO0 121 +#define SRST_SDMMC 122 +#define SRST_HSIC 123 +#define SRST_HSIC_AUX 124 +#define SRST_AHB1TOM 125 +#define SRST_P_PERIHP_NOC 126 +#define SRST_HSICPHY 127 + +/* cru_softrst_con8 */ +#define SRST_A_PCIE 128 +#define SRST_P_PCIE 129 +#define SRST_PCIE_CORE 130 +#define SRST_PCIE_MGMT 131 +#define SRST_PCIE_MGMT_STICKY 132 +#define SRST_PCIE_PIPE 133 +#define SRST_PCIE_PM 134 +#define SRST_PCIEPHY 135 +#define SRST_A_GMAC_NOC 136 +#define SRST_A_GMAC 137 +#define SRST_P_GMAC_NOC 138 +#define SRST_P_GMAC_GRF 140 +#define SRST_HSICPHY_POR 142 +#define SRST_HSICPHY_UTMI 143 + +/* cru_softrst_con9 */ +#define SRST_USB2PHY0_POR 144 +#define SRST_USB2PHY0_UTMI_PORT0 145 +#define SRST_USB2PHY0_UTMI_PORT1 146 +#define SRST_USB2PHY0_EHCIPHY 147 +#define SRST_UPHY0_PIPE_L00 148 +#define SRST_UPHY0 149 +#define SRST_UPHY0_TCPDPWRUP 150 +#define SRST_USB2PHY1_POR 152 +#define SRST_USB2PHY1_UTMI_PORT0 153 +#define SRST_USB2PHY1_UTMI_PORT1 154 +#define SRST_USB2PHY1_EHCIPHY 155 +#define SRST_UPHY1_PIPE_L00 156 +#define SRST_UPHY1 157 +#define SRST_UPHY1_TCPDPWRUP 158 + +/* cru_softrst_con10 */ +#define SRST_A_PERILP0_NOC 160 +#define SRST_A_DCF 161 +#define SRST_GIC500 162 +#define SRST_DMAC0_PERILP0 163 +#define SRST_DMAC1_PERILP0 164 +#define SRST_TZMA 165 +#define SRST_INTMEM 166 +#define SRST_ADB400_MST0 167 +#define SRST_ADB400_MST1 168 +#define SRST_ADB400_SLV0 169 +#define SRST_ADB400_SLV1 170 +#define SRST_H_PERILP0 171 +#define SRST_H_PERILP0_NOC 172 +#define SRST_ROM 173 +#define SRST_CRYPTO_S 174 +#define SRST_CRYPTO_M 175 + +/* cru_softrst_con11 */ +#define SRST_P_DCF 176 +#define SRST_CM0S_NOC 177 +#define SRST_CM0S 178 +#define SRST_CM0S_DBG 179 +#define SRST_CM0S_PO 180 +#define SRST_CRYPTO 181 +#define SRST_P_PERILP1_SGRF 182 +#define SRST_P_PERILP1_GRF 183 +#define SRST_CRYPTO1_S 184 +#define SRST_CRYPTO1_M 185 +#define SRST_CRYPTO1 186 +#define SRST_GIC_NOC 188 +#define SRST_SD_NOC 189 +#define SRST_SDIOAUDIO_BRG 190 + +/* cru_softrst_con12 */ +#define SRST_H_PERILP1 192 +#define SRST_H_PERILP1_NOC 193 +#define SRST_H_I2S0_8CH 194 +#define SRST_H_I2S1_8CH 195 +#define SRST_H_I2S2_8CH 196 +#define SRST_H_SPDIF_8CH 197 +#define SRST_P_PERILP1_NOC 198 +#define SRST_P_EFUSE_1024 199 +#define SRST_P_EFUSE_1024S 200 +#define SRST_P_I2C0 201 +#define SRST_P_I2C1 202 +#define SRST_P_I2C2 203 +#define SRST_P_I2C3 204 +#define SRST_P_I2C4 205 +#define SRST_P_I2C5 206 +#define SRST_P_MAILBOX0 207 + +/* cru_softrst_con13 */ +#define SRST_P_UART0 208 +#define SRST_P_UART1 209 +#define SRST_P_UART2 210 +#define SRST_P_UART3 211 +#define SRST_P_SARADC 212 +#define SRST_P_TSADC 213 +#define SRST_P_SPI0 214 +#define SRST_P_SPI1 215 +#define SRST_P_SPI2 216 +#define SRST_P_SPI4 217 +#define SRST_P_SPI5 218 +#define SRST_SPI0 219 +#define SRST_SPI1 220 +#define SRST_SPI2 221 +#define SRST_SPI4 222 +#define SRST_SPI5 223 + +/* cru_softrst_con14 */ +#define SRST_I2S0_8CH 224 +#define SRST_I2S1_8CH 225 +#define SRST_I2S2_8CH 226 +#define SRST_SPDIF_8CH 227 +#define SRST_UART0 228 +#define SRST_UART1 229 +#define SRST_UART2 230 +#define SRST_UART3 231 +#define SRST_TSADC 232 +#define SRST_I2C0 233 +#define SRST_I2C1 234 +#define SRST_I2C2 235 +#define SRST_I2C3 236 +#define SRST_I2C4 237 +#define SRST_I2C5 238 +#define SRST_SDIOAUDIO_NOC 239 + +/* cru_softrst_con15 */ +#define SRST_A_VIO_NOC 240 +#define SRST_A_HDCP_NOC 241 +#define SRST_A_HDCP 242 +#define SRST_H_HDCP_NOC 243 +#define SRST_H_HDCP 244 +#define SRST_P_HDCP_NOC 245 +#define SRST_P_HDCP 246 +#define SRST_P_HDMI_CTRL 247 +#define SRST_P_DP_CTRL 248 +#define SRST_S_DP_CTRL 249 +#define SRST_C_DP_CTRL 250 +#define SRST_P_MIPI_DSI0 251 +#define SRST_P_MIPI_DSI1 252 +#define SRST_DP_CORE 253 +#define SRST_DP_I2S 254 + +/* cru_softrst_con16 */ +#define SRST_GASKET 256 +#define SRST_VIO_GRF 258 +#define SRST_DPTX_SPDIF_REC 259 +#define SRST_HDMI_CTRL 260 +#define SRST_HDCP_CTRL 261 +#define SRST_A_ISP0_NOC 262 +#define SRST_A_ISP1_NOC 263 +#define SRST_H_ISP0_NOC 266 +#define SRST_H_ISP1_NOC 267 +#define SRST_H_ISP0 268 +#define SRST_H_ISP1 269 +#define SRST_ISP0 270 +#define SRST_ISP1 271 + +/* cru_softrst_con17 */ +#define SRST_A_VOP0_NOC 272 +#define SRST_A_VOP1_NOC 273 +#define SRST_A_VOP0 274 +#define SRST_A_VOP1 275 +#define SRST_H_VOP0_NOC 276 +#define SRST_H_VOP1_NOC 277 +#define SRST_H_VOP0 278 +#define SRST_H_VOP1 279 +#define SRST_D_VOP0 280 +#define SRST_D_VOP1 281 +#define SRST_VOP0_PWM 282 +#define SRST_VOP1_PWM 283 +#define SRST_P_EDP_NOC 284 +#define SRST_P_EDP_CTRL 285 + +/* cru_softrst_con18 */ +#define SRST_A_GPU 288 +#define SRST_A_GPU_NOC 289 +#define SRST_A_GPU_GRF 290 +#define SRST_PVTM_GPU 291 +#define SRST_A_USB3_NOC 292 +#define SRST_A_USB3_OTG0 293 +#define SRST_A_USB3_OTG1 294 +#define SRST_A_USB3_GRF 295 +#define SRST_PMU 296 + +/* cru_softrst_con19 */ +#define SRST_P_TIMER0_5 304 +#define SRST_TIMER0 305 +#define SRST_TIMER1 306 +#define SRST_TIMER2 307 +#define SRST_TIMER3 308 +#define SRST_TIMER4 309 +#define SRST_TIMER5 310 +#define SRST_P_TIMER6_11 311 +#define SRST_TIMER6 312 +#define SRST_TIMER7 313 +#define SRST_TIMER8 314 +#define SRST_TIMER9 315 +#define SRST_TIMER10 316 +#define SRST_TIMER11 317 +#define SRST_P_INTR_ARB_PMU 318 +#define SRST_P_ALIVE_SGRF 319 + +/* cru_softrst_con20 */ +#define SRST_P_GPIO2 320 +#define SRST_P_GPIO3 321 +#define SRST_P_GPIO4 322 +#define SRST_P_GRF 323 +#define SRST_P_ALIVE_NOC 324 +#define SRST_P_WDT0 325 +#define SRST_P_WDT1 326 +#define SRST_P_INTR_ARB 327 +#define SRST_P_UPHY0_DPTX 328 +#define SRST_P_UPHY0_APB 330 +#define SRST_P_UPHY0_TCPHY 332 +#define SRST_P_UPHY1_TCPHY 333 +#define SRST_P_UPHY0_TCPDCTRL 334 +#define SRST_P_UPHY1_TCPDCTRL 335 + +/* pmu soft-reset indices */ + +/* pmu_cru_softrst_con0 */ +#define SRST_P_NOC 0 +#define SRST_P_INTMEM 1 +#define SRST_H_CM0S 2 +#define SRST_H_CM0S_NOC 3 +#define SRST_DBG_CM0S 4 +#define SRST_PO_CM0S 5 +#define SRST_P_SPI3 6 +#define SRST_SPI3 7 +#define SRST_P_TIMER_0_1 8 +#define SRST_P_TIMER_0 9 +#define SRST_P_TIMER_1 10 +#define SRST_P_UART4 11 +#define SRST_UART4 12 +#define SRST_P_WDT 13 + +/* pmu_cru_softrst_con1 */ +#define SRST_P_I2C6 16 +#define SRST_P_I2C7 17 +#define SRST_P_I2C8 18 +#define SRST_P_MAILBOX 19 +#define SRST_P_RKPWM 20 +#define SRST_P_PMUGRF 21 +#define SRST_P_SGRF 22 +#define SRST_P_GPIO0 23 +#define SRST_P_GPIO1 24 +#define SRST_P_CRU 25 +#define SRST_P_INTR 26 +#define SRST_PVTM 27 +#define SRST_I2C6 28 +#define SRST_I2C7 29 +#define SRST_I2C8 30 + +#endif diff --git a/include/dt-bindings/clock/rk618-cru.h b/include/dt-bindings/clock/rk618-cru.h new file mode 100644 index 000000000000..72ae0aef1378 --- /dev/null +++ b/include/dt-bindings/clock/rk618-cru.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_RK618_CRU_H +#define _DT_BINDINGS_CLK_RK618_CRU_H + +#define LCDC0_CLK 1 +#define LCDC1_CLK 2 +#define VIF_PLLIN_CLK 3 +#define SCALER_PLLIN_CLK 4 +#define VIF_PLL_CLK 5 +#define SCALER_PLL_CLK 6 +#define VIF0_CLK 7 +#define VIF1_CLK 8 +#define SCALER_IN_CLK 9 +#define SCALER_CLK 10 +#define DITHER_CLK 11 +#define HDMI_CLK 12 +#define MIPI_CLK 13 +#define LVDS_CLK 14 +#define LVTTL_CLK 15 +#define RGB_CLK 16 +#define VIF0_PRE_CLK 17 +#define VIF1_PRE_CLK 18 +#define CODEC_CLK 19 + +#endif diff --git a/include/dt-bindings/clock/rk_system_status.h b/include/dt-bindings/clock/rk_system_status.h new file mode 100644 index 000000000000..381447b4fbe0 --- /dev/null +++ b/include/dt-bindings/clock/rk_system_status.h @@ -0,0 +1,38 @@ +/* + * + * Copyright (C) 2011-2014 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ROCKCHIP_SYSTEM_STATUS_H +#define __ROCKCHIP_SYSTEM_STATUS_H + +#define SYS_STATUS_NORMAL (1<<0) +#define SYS_STATUS_SUSPEND (1<<1) +#define SYS_STATUS_IDLE (1<<2) +#define SYS_STATUS_REBOOT (1<<3) +#define SYS_STATUS_VIDEO_4K (1<<4) +#define SYS_STATUS_VIDEO_1080P (1<<5) +#define SYS_STATUS_GPU (1<<6) +#define SYS_STATUS_RGA (1<<7) +#define SYS_STATUS_CIF0 (1<<8) +#define SYS_STATUS_CIF1 (1<<9) +#define SYS_STATUS_LCDC0 (1<<10) +#define SYS_STATUS_LCDC1 (1<<11) +#define SYS_STATUS_BOOST (1<<12) +#define SYS_STATUS_PERFORMANCE (1<<13) +#define SYS_STATUS_ISP (1<<14) +#define SYS_STATUS_HDMI (1<<15) + +#define SYS_STATUS_DUALVIEW (SYS_STATUS_LCDC0|SYS_STATUS_LCDC1) + +#endif diff --git a/include/dt-bindings/clock/rockchip,rk3036.h b/include/dt-bindings/clock/rockchip,rk3036.h new file mode 100644 index 000000000000..019550c7d0c1 --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk3036.h @@ -0,0 +1,155 @@ +#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_RK3036_H +#define _DT_BINDINGS_CLOCK_ROCKCHIP_RK3036_H + +#include "rockchip.h" + +/* pll id */ +#define RK3036_APLL_ID 0 +#define RK3036_DPLL_ID 1 +#define RK3036_GPLL_ID 2 +#define RK3036_END_PLL_ID 3 + +/* reset id */ +#define RK3036_RST_CORE0 0 +#define RK3036_RST_CORE1 1 +#define RK3036_RST_0RES2 2 +#define RK3036_RST_0RES3 3 +#define RK3036_RST_CORE0_DBG 4 +#define RK3036_RST_CORE1_DBG 5 +#define RK3036_RST_0RES6 6 +#define RK3036_RST_0RES7 7 +#define RK3036_RST_CORE0_POR 8 +#define RK3036_RST_CORE1_POR 9 +#define RK3036_RST_0RES10 10 +#define RK3036_RST_0RES11 11 +#define RK3036_RST_L2C 12 +#define RK3036_RST_TOPDBG 13 +#define RK3036_RST_STRC_SYS_A 14 +#define RK3036_RST_PD_CORE_NIU 15 + +#define RK3036_RST_TIMER2 16 +#define RK3036_RST_CPUSYS_H 17 +#define RK3036_RST_1RES2 18 +#define RK3036_RST_AHB2APB_H 19 +#define RK3036_RST_TIMER3 20 +#define RK3036_RST_INTMEM 21 +#define RK3036_RST_ROM 22 +#define RK3036_RST_PERI_NIU 23 +#define RK3036_RST_I2S 24 +#define RK3036_RST_DDR_PLL 25 +#define RK3036_RST_GPU_DLL 26 +#define RK3036_RST_TIMER0 27 +#define RK3036_RST_TIMER1 28 +#define RK3036_RST_CORE_DLL 29 +#define RK3036_RST_EFUSE_P 30 +#define RK3036_RST_ACODEC_P 31 + +#define RK3036_RST_GPIO0 32 +#define RK3036_RST_GPIO1 33 +#define RK3036_RST_GPIO2 34 +#define RK3036_RST_2RES3 35 +#define RK3036_RST_2RES4 36 +#define RK3036_RST_2RES5 37 +#define RK3036_RST_2RES6 38 +#define RK3036_RST_UART0 39 +#define RK3036_RST_UART1 40 +#define RK3036_RST_UART2 41 +#define RK3036_RST_2RES10 42 +#define RK3036_RST_I2C0 43 +#define RK3036_RST_I2C1 44 +#define RK3036_RST_I2C2 45 +#define RK3036_RST_2RES14 46 +#define RK3036_RST_SFC 47 + +#define RK3036_RST_PWM0 48 +#define RK3036_RST_3RES1 49 +#define RK3036_RST_3RES2 50 +#define RK3036_RST_DAP 51 +#define RK3036_RST_DAP_SYS 52 +#define RK3036_RST_3RES5 53 +#define RK3036_RST_3RES6 54 +#define RK3036_RST_GRF 55 +#define RK3036_RST_3RES8 56 +#define RK3036_RST_PERIPHSYS_A 57 +#define RK3036_RST_PERIPHSYS_H 58 +#define RK3036_RST_PERIPHSYS_P 59 +#define RK3036_RST_3RES12 60 +#define RK3036_RST_CPU_PERI 61 +#define RK3036_RST_EMEM_PERI 62 +#define RK3036_RST_USB_PERI 63 + +#define RK3036_RST_DMA2 64 +#define RK3036_RST_4RES1 65 +#define RK3036_RST_MAC 66 +#define RK3036_RST_4RES3 67 +#define RK3036_RST_NANDC 68 +#define RK3036_RST_USBOTG0 69 +#define RK3036_RST_4RES6 70 +#define RK3036_RST_OTGC0 71 +#define RK3036_RST_USBOTG1 72 +#define RK3036_RST_4RES9 73 +#define RK3036_RST_OTGC1 74 +#define RK3036_RST_4RES11 75 +#define RK3036_RST_4RES12 76 +#define RK3036_RST_4RES13 77 +#define RK3036_RST_4RES14 78 +#define RK3036_RST_DDRMSCH 79 + +#define RK3036_RST_5RES0 80 +#define RK3036_RST_MMC0 81 +#define RK3036_RST_SDIO 82 +#define RK3036_RST_EMMC 83 +#define RK3036_RST_SPI0 84 +#define RK3036_RST_5RES5 85 +#define RK3036_RST_WDT 86 +#define RK3036_RST_5RES7 87 +#define RK3036_RST_DDRPHY 88 +#define RK3036_RST_DDRPHY_P 89 +#define RK3036_RST_DDRCTRL 90 +#define RK3036_RST_DDRCTRL_P 91 +#define RK3036_RST_5RES12 92 +#define RK3036_RST_5RES13 93 +#define RK3036_RST_5RES14 94 +#define RK3036_RST_5RES15 95 + +#define RK3036_RST_HDMI_P 96 +#define RK3036_RST_6RES1 97 +#define RK3036_RST_6RES2 98 +#define RK3036_RST_VIO_BUS_H 99 +#define RK3036_RST_6RES4 100 +#define RK3036_RST_6RES5 101 +#define RK3036_RST_6RES6 102 +#define RK3036_RST_UTMI0 103 +#define RK3036_RST_UTMI1 104 +#define RK3036_RST_USBPOR 105 +#define RK3036_RST_6RES10 106 +#define RK3036_RST_6RES11 107 +#define RK3036_RST_6RES12 108 +#define RK3036_RST_6RES13 109 +#define RK3036_RST_6RES14 110 +#define RK3036_RST_6RES15 111 + +#define RK3036_RST_VCODEC_A 112 +#define RK3036_RST_VCODEC_H 113 +#define RK3036_RST_VIO1_A 114 +#define RK3036_RST_HEVC 115 +#define RK3036_RST_VCODEC_NIU_A 116 +#define RK3036_RST_LCDC1_A 117 +#define RK3036_RST_LCDC1_H 118 +#define RK3036_RST_LCDC1_D 119 +#define RK3036_RST_GPU 120 +#define RK3036_RST_7RES9 121 +#define RK3036_RST_GPU_NIU_A 122 +#define RK3036_RST_7RES11 123 +#define RK3036_RST_7RES12 124 +#define RK3036_RST_7RES13 125 +#define RK3036_RST_7RES14 126 +#define RK3036_RST_7RES15 127 + +#define RK3036_RST_8RES0 128 +#define RK3036_RST_8RES1 129 +#define RK3036_RST_8RES2 130 +#define RK3036_RST_DBG_P 131 +/* con8[15:4] is reserved */ + +#endif /* _DT_BINDINGS_CLOCK_ROCKCHIP_RK3036_H */ diff --git a/include/dt-bindings/clock/rockchip,rk312x.h b/include/dt-bindings/clock/rockchip,rk312x.h new file mode 100755 index 000000000000..0af5abca3470 --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk312x.h @@ -0,0 +1,167 @@ +#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_RK3128_H +#define _DT_BINDINGS_CLOCK_ROCKCHIP_RK3128_H + +#include "rockchip.h" + +/* pll id */ +#define RK3128_APLL_ID 0 +#define RK3128_DPLL_ID 1 +#define RK3128_CPLL_ID 2 +#define RK3128_GPLL_ID 3 +#define RK3128_END_PLL_ID 4 + +/* reset id */ +#define RK3128_RST_CORE0_PO 0 +#define RK3128_RST_CORE1_PO 1 +#define RK3128_RST_CORE2_PO 2 +#define RK3128_RST_CORE3_PO 3 +#define RK3128_RST_CORE0 4 +#define RK3128_RST_CORE1 5 +#define RK3128_RST_CORE2 6 +#define RK3128_RST_CORE3 7 +#define RK3128_RST_CORE0_DBG 8 +#define RK3128_RST_CORE1_DBG 9 +#define RK3128_RST_CORE2_DBG 10 +#define RK3128_RST_CORE3_DBG 11 +#define RK3128_RST_TOPDBG 12 +#define RK3128_RST_ACLK_CORE 13 +#define RK3128_RST_STRC_SYS_A 14 +#define RK3128_RST_L2C 15 + +#define RK3128_RST_1RES0 16 +#define RK3128_RST_1RES1 17 +#define RK3128_RST_CPUSYS_H 18 +#define RK3128_RST_AHB2APB_H 19 +#define RK3128_RST_SPDIF 20 +#define RK3128_RST_INTMEM 21 +#define RK3128_RST_ROM 22 +#define RK3128_RST_PERI_NIU 23 +#define RK3128_RST_I2S_2CH 24 +#define RK3128_RST_I2S_8CH 25 +#define RK3128_RST_GPU_PVTM 26 +#define RK3128_RST_FUNC_PVTM 27 +#define RK3128_RST_1RES12 28 +#define RK3128_RST_CORE_PVTM 29 +#define RK3128_RST_EFUSE_P 30 +#define RK3128_RST_ACODEC_P 31 + +#define RK3128_RST_GPIO0 32 +#define RK3128_RST_GPIO1 33 +#define RK3128_RST_GPIO2 34 +#define RK3128_RST_GPIO3 35 +#define RK3128_RST_MIPIPHY 36 +#define RK3128_RST_2RES5 37 +#define RK3128_RST_2RES6 38 +#define RK3128_RST_UART0 39 +#define RK3128_RST_UART1 40 +#define RK3128_RST_UART2 41 +#define RK3128_RST_2RES10 42 +#define RK3128_RST_I2C0 43 +#define RK3128_RST_I2C1 44 +#define RK3128_RST_I2C2 45 +#define RK3128_RST_I2C3 46 +#define RK3128_RST_SFC 47 + +#define RK3128_RST_PWM0 48 +#define RK3128_RST_3RES1 49 +#define RK3128_RST_DAP_P 50 +#define RK3128_RST_DAP 51 +#define RK3128_RST_DAP_SYS 52 +#define RK3128_RST_CRYPTO 53 +#define RK3128_RST_3RES6 54 +#define RK3128_RST_GRF 55 +#define RK3128_RST_GMAC 56 +#define RK3128_RST_PERIPHSYS_A 57 +#define RK3128_RST_PERIPHSYS_H 58 +#define RK3128_RST_PERIPHSYS_P 59 +#define RK3128_RST_SMART_CARD 60 +#define RK3128_RST_CPU_PERI 61 +#define RK3128_RST_EMEM_PERI 62 +#define RK3128_RST_USB_PERI 63 + +#define RK3128_RST_DMA2 64 +#define RK3128_RST_4RES1 65 +#define RK3128_RST_4RES2 66 +#define RK3128_RST_GPS 67 +#define RK3128_RST_NANDC 68 +#define RK3128_RST_USBOTG0 69 +#define RK3128_RST_4RES6 70 +#define RK3128_RST_OTGC0 71 +#define RK3128_RST_USBOTG1 72 +#define RK3128_RST_4RES9 73 +#define RK3128_RST_OTGC1 74 +#define RK3128_RST_4RES11 75 +#define RK3128_RST_4RES12 76 +#define RK3128_RST_4RES13 77 +#define RK3128_RST_4RES14 78 +#define RK3128_RST_DDRMSCH 79 + +#define RK3128_RST_5RES0 80 +#define RK3128_RST_MMC0 81 +#define RK3128_RST_SDIO 82 +#define RK3128_RST_EMMC 83 +#define RK3128_RST_SPI0 84 +#define RK3128_RST_5RES5 85 +#define RK3128_RST_WDT 86 +#define RK3128_RST_SARADC 87 +#define RK3128_RST_DDRPHY 88 +#define RK3128_RST_DDRPHY_P 89 +#define RK3128_RST_DDRCTRL 90 +#define RK3128_RST_DDRCTRL_P 91 +#define RK3128_RST_TSP 92 +#define RK3128_RST_TSP_CLKIN0 93 +#define RK3128_RST_USBHOST0_EHCI 94 +#define RK3128_RST_5RES15 95 + +#define RK3128_RST_HDMI_P 96 +#define RK3128_RST_VIO_ARBI_H 97 +#define RK3128_RST_VIO_A 98 +#define RK3128_RST_VIO_BUS_H 99 +#define RK3128_RST_LCDC0_A 100 +#define RK3128_RST_LCDC0_H 101 +#define RK3128_RST_LCDC0_D 102 +#define RK3128_RST_UTMI0 103 +#define RK3128_RST_UTMI1 104 +#define RK3128_RST_USBPOR 105 +#define RK3128_RST_IEP_A 106 +#define RK3128_RST_IEP_H 107 +#define RK3128_RST_RGA_A 108 +#define RK3128_RST_RGA_H 109 +#define RK3128_RST_CIF0 110 +#define RK3128_RST_PMU 111 + +#define RK3128_RST_VCODEC_A 112 +#define RK3128_RST_VCODEC_H 113 +#define RK3128_RST_VIO1_A 114 +#define RK3128_RST_HEVC 115 +#define RK3128_RST_VCODEC_NIU_A 116 +#define RK3128_RST_PMU_NIU 117 +#define RK3128_RST_7RES6 118 +#define RK3128_RST_LCDC0_S 119 +#define RK3128_RST_GPU 120 +#define RK3128_RST_7RES9 121 +#define RK3128_RST_GPU_NIU_A 122 +#define RK3128_RST_EBC_A 123 +#define RK3128_RST_EBC_H 124 +#define RK3128_RST_7RES13 125 +#define RK3128_RST_7RES14 126 +#define RK3128_RST_7RES15 127 + +#define RK3128_RST_CORE_DBG 128 +#define RK3128_RST_DBG_P 129 +#define RK3128_RST_TIMER0 130 +#define RK3128_RST_TIMER1 131 +#define RK3128_RST_TIMER2 132 +#define RK3128_RST_TIMER3 133 +#define RK3128_RST_TIMER4 134 +#define RK3128_RST_TIMER5 135 +#define RK3128_RST_VIO_H2P 136 +#define RK3128_RST_VIO_MIPI_DSI 137 +#define RK3128_RST_8RES10 138 +#define RK3128_RST_8RES11 139 +#define RK3128_RST_8RES12 140 +#define RK3128_RST_8RES13 141 +#define RK3128_RST_8RES14 142 +#define RK3128_RST_8RES15 143 + +#endif /* _DT_BINDINGS_CLOCK_ROCKCHIP_RK3128_H */ diff --git a/include/dt-bindings/clock/rockchip,rk3188.h b/include/dt-bindings/clock/rockchip,rk3188.h new file mode 100644 index 000000000000..b8c57e1cfed8 --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk3188.h @@ -0,0 +1,13 @@ +#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_RK3188_H +#define _DT_BINDINGS_CLOCK_ROCKCHIP_RK3188_H + +#include "rockchip.h" + +/* pll id */ +#define RK3188_APLL_ID 0 +#define RK3188_DPLL_ID 1 +#define RK3188_CPLL_ID 2 +#define RK3188_GPLL_ID 3 +#define RK3188_END_PLL_ID 4 + +#endif /* _DT_BINDINGS_CLOCK_ROCKCHIP_RK3188_H */ diff --git a/include/dt-bindings/clock/rockchip,rk3228.h b/include/dt-bindings/clock/rockchip,rk3228.h new file mode 100644 index 000000000000..b86e44536722 --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk3228.h @@ -0,0 +1,167 @@ +#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_RK3228_H +#define _DT_BINDINGS_CLOCK_ROCKCHIP_RK3228_H + +#include "rockchip.h" + +/* pll id */ +#define RK3228_APLL_ID 0 +#define RK3228_DPLL_ID 1 +#define RK3228_CPLL_ID 2 +#define RK3228_GPLL_ID 3 +#define RK3228_END_PLL_ID 4 + +/* reset id */ +#define RK3228_RST_CORE0_PO 0 +#define RK3228_RST_CORE1_PO 1 +#define RK3228_RST_CORE2_PO 2 +#define RK3228_RST_CORE3_PO 3 +#define RK3228_RST_CORE0 4 +#define RK3228_RST_CORE1 5 +#define RK3228_RST_CORE2 6 +#define RK3228_RST_CORE3 7 +#define RK3228_RST_CORE0_DBG 8 +#define RK3228_RST_CORE1_DBG 9 +#define RK3228_RST_CORE2_DBG 10 +#define RK3228_RST_CORE3_DBG 11 +#define RK3228_RST_TOPDBG 12 +#define RK3228_RST_ACLK_CORE 13 +#define RK3228_RST_NOC_A 14 +#define RK3228_RST_L2C 15 + +#define RK3228_RST_1RES0 16 +#define RK3228_RST_1RES1 17 +#define RK3228_RST_CPUSYS_H 18 +#define RK3228_RST_BUSSYS_H 19 +#define RK3228_RST_SPDIF 20 +#define RK3228_RST_INTMEM 21 +#define RK3228_RST_ROM 22 +#define RK3228_RST_OTG_ADP 23 +#define RK3228_RST_I2S0 24 +#define RK3228_RST_I2S1 25 +#define RK3228_RST_I2S2 26 +#define RK3228_RST_ACODEC_P 27 +#define RK3228_RST_DFIMON 28 +#define RK3228_RST_MSCH 29 +#define RK3228_RST_EFUSE_1024 30 +#define RK3228_RST_EFUSE_256 31 + +#define RK3228_RST_GPIO0 32 +#define RK3228_RST_GPIO1 33 +#define RK3228_RST_GPIO2 34 +#define RK3228_RST_GPIO3 35 +#define RK3228_RST_PERIPH_NOC_A 36 +#define RK3228_RST_PERIPH_NOC_H 37 +#define RK3228_RST_PERIPH_NOC_P 38 +#define RK3228_RST_UART0 39 +#define RK3228_RST_UART1 40 +#define RK3228_RST_UART2 41 +#define RK3228_RST_PHYNOC 42 +#define RK3228_RST_I2C0 43 +#define RK3228_RST_I2C1 44 +#define RK3228_RST_I2C2 45 +#define RK3228_RST_I2C3 46 +#define RK3228_RST_2RES15 47 + +#define RK3228_RST_PWM0 48 +#define RK3228_RST_A53_GIC 49 +#define RK3228_RST_3RES2 50 +#define RK3228_RST_DAP 51 +#define RK3228_RST_DAP_NOC 52 +#define RK3228_RST_CRYPTO 53 +#define RK3228_RST_SGRF 54 +#define RK3228_RST_GRF 55 +#define RK3228_RST_GMAC 56 +#define RK3228_RST_3RES9 57 +#define RK3228_RST_PERIPHSYS_A 58 +#define RK3228_RST_3RES11 59 +#define RK3228_RST_3RES12 60 +#define RK3228_RST_3RES13 61 +#define RK3228_RST_3RES14 62 +#define RK3228_RST_MACPHY 63 + +#define RK3228_RST_4RES0 64 +#define RK3228_RST_4RES1 65 +#define RK3228_RST_4RES2 66 +#define RK3228_RST_4RES3 67 +#define RK3228_RST_NANDC 68 +#define RK3228_RST_USBOTG0 69 +#define RK3228_RST_OTGC0 70 +#define RK3228_RST_USBHOST0 71 +#define RK3228_RST_HOST_CTRL0 72 +#define RK3228_RST_USBHOST1 73 +#define RK3228_RST_HOST_CTRL1 74 +#define RK3228_RST_USBHOST2 75 +#define RK3228_RST_HOST_CTRL2 76 +#define RK3228_RST_USBPOR0 77 +#define RK3228_RST_USBPOR1 78 +#define RK3228_RST_DDRMSCH 79 + +#define RK3228_RST_SMART_CARD 80 +#define RK3228_RST_SDMMC0 81 +#define RK3228_RST_SDIO 82 +#define RK3228_RST_EMMC 83 +#define RK3228_RST_SPI0 84 +#define RK3228_RST_TSP_H 85 +#define RK3228_RST_TSP 86 +#define RK3228_RST_TSADC 87 +#define RK3228_RST_DDRPHY 88 +#define RK3228_RST_DDRPHY_P 89 +#define RK3228_RST_DDRCTRL 90 +#define RK3228_RST_DDRCTRL_P 91 +#define RK3228_RST_HOST0_ECHI 92 +#define RK3228_RST_HOST1_ECHI 93 +#define RK3228_RST_HOST2_ECHI 94 +#define RK3228_RST_VOP 95 + +#define RK3228_RST_HDMI_P 96 +#define RK3228_RST_VIO_ARBI_H 97 +#define RK3228_RST_IEP_NOC_A 98 +#define RK3228_RST_VIO_NOC_H 99 +#define RK3228_RST_VOP_A 100 +#define RK3228_RST_VOP_H 101 +#define RK3228_RST_VOP_D 102 +#define RK3228_RST_UTMI0 103 +#define RK3228_RST_UTMI1 104 +#define RK3228_RST_UTMI2 105 +#define RK3228_RST_UTMI3 106 +#define RK3228_RST_RGA 107 +#define RK3228_RST_RGA_NOC_A 108 +#define RK3228_RST_RGA_A 109 +#define RK3228_RST_RGA_H 110 +#define RK3228_RST_HDCP_A 111 + +#define RK3228_RST_VPU_A 112 +#define RK3228_RST_VPU_H 113 +#define RK3228_RST_7RES2 114 +#define RK3228_RST_7RES3 115 +#define RK3228_RST_VPU_NOC_A 116 +#define RK3228_RST_VPU_NOC_H 117 +#define RK3228_RST_RKVDEC_A 118 +#define RK3228_RST_RKVDEC_NOC_A 119 +#define RK3228_RST_RKVDEC_H 120 +#define RK3228_RST_RKVDEC_NOC_H 121 +#define RK3228_RST_RKVDEC_CORE 122 +#define RK3228_RST_RKVDEC_CABAC 123 +#define RK3228_RST_IEP_A 124 +#define RK3228_RST_IEP_H 125 +#define RK3228_RST_GPU_A 126 +#define RK3228_RST_GPU_NOC_A 127 + +#define RK3228_RST_CORE_DBG 128 +#define RK3228_RST_DBG_P 129 +#define RK3228_RST_TIMER0 130 +#define RK3228_RST_TIMER1 131 +#define RK3228_RST_TIMER2 132 +#define RK3228_RST_TIMER3 133 +#define RK3228_RST_TIMER4 134 +#define RK3228_RST_TIMER5 135 +#define RK3228_RST_VIO_H2P 136 +#define RK3228_RST_8RES9 137 +#define RK3228_RST_8RES10 138 +#define RK3228_RST_HDMIPHY 139 +#define RK3228_RST_VDAC 140 +#define RK3228_RST_TIMER_6CH 141 +#define RK3228_RST_8RES14 142 +#define RK3228_RST_8RES15 143 + +#endif /* _DT_BINDINGS_CLOCK_ROCKCHIP_RK3228_H */ diff --git a/include/dt-bindings/clock/rockchip,rk3288.h b/include/dt-bindings/clock/rockchip,rk3288.h new file mode 100644 index 000000000000..1a2803c4f168 --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk3288.h @@ -0,0 +1,220 @@ +#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_RK3288_H +#define _DT_BINDINGS_CLOCK_ROCKCHIP_RK3288_H + +#include "rockchip.h" + +/* pll id */ +#define RK3288_APLL_ID 0 +#define RK3288_DPLL_ID 1 +#define RK3288_CPLL_ID 2 +#define RK3288_GPLL_ID 3 +#define RK3288_NPLL_ID 4 +#define RK3288_END_PLL_ID 5 + +/* reset id */ +#define RK3288_SOFT_RST_CORE0 0 +#define RK3288_SOFT_RST_CORE1 1 +#define RK3288_SOFT_RST_CORE2 2 +#define RK3288_SOFT_RST_CORE3 3 +#define RK3288_SOFT_RST_CORE0_PO 4 +#define RK3288_SOFT_RST_CORE1_PO 5 +#define RK3288_SOFT_RST_CORE2_PO 6 +#define RK3288_SOFT_RST_CORE3_PO 7 +#define RK3288_SOFT_RST_PD_CORE_STR_SYS_A 8 +#define RK3288_SOFT_RST_PD_BUS_STR_SYS_A 9 +#define RK3288_SOFT_RST_L2C 10 +#define RK3288_SOFT_RST_TOPDBG 11 +#define RK3288_SOFT_RST_CORE0_DBG 12 +#define RK3288_SOFT_RST_CORE1_DBG 13 +#define RK3288_SOFT_RST_CORE2_DBG 14 +#define RK3288_SOFT_RST_CORE3_DBG 15 + +#define RK3288_SOFT_RST_PD_BUS_AHB_ARBITOR 16 +#define RK3288_SOFT_RST_EFUSE_256BIT_P 17 +#define RK3288_SOFT_RST_DMA1 18 +#define RK3288_SOFT_RST_INTMEM 19 +#define RK3288_SOFT_RST_ROM 20 +#define RK3288_SOFT_RST_SPDIF_8CH 21 +#define RK3288_SOFT_RST_TIMER_P 22 +#define RK3288_SOFT_RST_I2S 23 +#define RK3288_SOFT_RST_SPDIF 24 +#define RK3288_SOFT_RST_TIMER0 25 +#define RK3288_SOFT_RST_TIMER1 26 +#define RK3288_SOFT_RST_TIMER2 27 +#define RK3288_SOFT_RST_TIMER3 28 +#define RK3288_SOFT_RST_TIMER4 29 +#define RK3288_SOFT_RST_TIMER5 30 +#define RK3288_SOFT_RST_EFUSE_P 31 + +#define RK3288_SOFT_RST_GPIO0 32 +#define RK3288_SOFT_RST_GPIO1 33 +#define RK3288_SOFT_RST_GPIO2 34 +#define RK3288_SOFT_RST_GPIO3 35 +#define RK3288_SOFT_RST_GPIO4 36 +#define RK3288_SOFT_RST_GPIO5 37 +#define RK3288_SOFT_RST_GPIO6 38 +#define RK3288_SOFT_RST_GPIO7 39 +#define RK3288_SOFT_RST_GPIO8 40 +#define RK3288_SOFT_RST_2RES9 41 +#define RK3288_SOFT_RST_I2C0 42 +#define RK3288_SOFT_RST_I2C1 43 +#define RK3288_SOFT_RST_I2C2 44 +#define RK3288_SOFT_RST_I2C3 45 +#define RK3288_SOFT_RST_I2C4 46 +#define RK3288_SOFT_RST_I2C5 47 + +#define RK3288_SOFT_RST_DW_PWM 48 +#define RK3288_SOFT_RST_MMC_PERI 49 +#define RK3288_SOFT_RST_PERIPH_MMU 50 +#define RK3288_SOFT_RST_DAP 51 +#define RK3288_SOFT_RST_DAP_SYS 52 +#define RK3288_SOFT_RST_TPIU_AT 53 +#define RK3288_SOFT_RST_PMU_P 54 +#define RK3288_SOFT_RST_GRF 55 +#define RK3288_SOFT_RST_PMU 56 +#define RK3288_SOFT_RST_PERIPHSYS_A 57 +#define RK3288_SOFT_RST_PERIPHSYS_H 58 +#define RK3288_SOFT_RST_PERIPHSYS_P 59 +#define RK3288_SOFT_RST_PERIPH_NIU 60 +#define RK3288_SOFT_RST_PD_PERI_AHB_ARBITOR 61 +#define RK3288_SOFT_RST_EMEM_PERI 62 +#define RK3288_SOFT_RST_USB_PERI 63 + +#define RK3288_SOFT_RST_DMA2 64 +#define RK3288_SOFT_RST_4RES1 65 +#define RK3288_SOFT_RST_MAC 66 +#define RK3288_SOFT_RST_GPS 67 +#define RK3288_SOFT_RST_4RES4 68 +#define RK3288_SOFT_RST_RK_PWM 69 +#define RK3288_SOFT_RST_4RES6 70 +#define RK3288_SOFT_RST_CCP 71 +#define RK3288_SOFT_RST_USB_HOST0 72 +#define RK3288_SOFT_RST_EHCI1 73 +#define RK3288_SOFT_RST_EHCI1_AUX 74 +#define RK3288_SOFT_RST_EHCI1PHY 75 +#define RK3288_SOFT_RST_HSADC 76 +#define RK3288_SOFT_RST_NANDC0 77 +#define RK3288_SOFT_RST_NANDC1 78 +#define RK3288_SOFT_RST_4RES15 79 + +#define RK3288_SOFT_RST_TZPC 80 +#define RK3288_SOFT_RST_5RES1 81 +#define RK3288_SOFT_RST_5RES2 82 +#define RK3288_SOFT_RST_SPI0 83 +#define RK3288_SOFT_RST_SPI1 84 +#define RK3288_SOFT_RST_SPI2 85 +#define RK3288_SOFT_RST_5RES6 86 +#define RK3288_SOFT_RST_SARADC 87 +#define RK3288_SOFT_RST_PD_ALIVE_NIU_P 88 +#define RK3288_SOFT_RST_PD_PMU_INTMEM_P 89 +#define RK3288_SOFT_RST_PD_PMU_NIU_P 90 +#define RK3288_SOFT_RST_SECURITY_GRF_P 91 +#define RK3288_SOFT_RST_5RES12 92 +#define RK3288_SOFT_RST_5RES13 93 +#define RK3288_SOFT_RST_5RES14 94 +#define RK3288_SOFT_RST_5RES15 95 + +#define RK3288_SOFT_RST_VIO_ARBI_H 96 +#define RK3288_SOFT_RST_RGA_NIU_A 97 +#define RK3288_SOFT_RST_VIO0_NIU_A 98 +#define RK3288_SOFT_RST_VIO_NIU_H 99 +#define RK3288_SOFT_RST_LCDC0_A 100 +#define RK3288_SOFT_RST_LCDC0_H 101 +#define RK3288_SOFT_RST_LCDC0_D 102 +#define RK3288_SOFT_RST_VIO1_NIU_A 103 +#define RK3288_SOFT_RST_VIP 104 +#define RK3288_SOFT_RST_RGA_CORE 105 +#define RK3288_SOFT_RST_IEP_A 106 +#define RK3288_SOFT_RST_IEP_H 107 +#define RK3288_SOFT_RST_RGA_A 108 +#define RK3288_SOFT_RST_RGA_H 109 +#define RK3288_SOFT_RST_ISP 110 +#define RK3288_SOFT_RST_EDP 111 + +#define RK3288_SOFT_RST_VCODEC_A 112 +#define RK3288_SOFT_RST_VCODEC_H 113 +#define RK3288_SOFT_RST_VIO_H2P_H 114 +#define RK3288_SOFT_RST_MIPIDSI0_P 115 +#define RK3288_SOFT_RST_MIPIDSI1_P 116 +#define RK3288_SOFT_RST_MIPICSI_P 117 +#define RK3288_SOFT_RST_LVDS_PHY_P 118 +#define RK3288_SOFT_RST_LVDS_CON 119 +#define RK3288_SOFT_RST_GPU 120 +#define RK3288_SOFT_RST_HDMI 121 +#define RK3288_SOFT_RST_7RES10 122 +#define RK3288_SOFT_RST_7RES11 123 +#define RK3288_SOFT_RST_CORE_PVTM 124 +#define RK3288_SOFT_RST_GPU_PVTM 125 +#define RK3288_SOFT_RST_7RES14 126 +#define RK3288_SOFT_RST_7RES15 127 + +#define RK3288_SOFT_RST_MMC0 128 +#define RK3288_SOFT_RST_SDIO0 129 +#define RK3288_SOFT_RST_SDIO1 130 +#define RK3288_SOFT_RST_EMMC 131 +#define RK3288_SOFT_RST_USBOTG_H 132 +#define RK3288_SOFT_RST_USBOTGPHY 133 +#define RK3288_SOFT_RST_USBOTGC 134 +#define RK3288_SOFT_RST_USBHOST0_H 135 +#define RK3288_SOFT_RST_USBHOST0PHY 136 +#define RK3288_SOFT_RST_USBHOST0C 137 +#define RK3288_SOFT_RST_USBHOST1_H 138 +#define RK3288_SOFT_RST_USBHOST1PHY 139 +#define RK3288_SOFT_RST_USBHOST1C 140 +#define RK3288_SOFT_RST_USB_ADP 141 +#define RK3288_SOFT_RST_ACC_EFUSE 142 +#define RK3288_SOFT_RST_8RES15 143 + +#define RK3288_SOFT_RST_CORESIGHT 144 +#define RK3288_SOFT_RST_PD_CORE_AHB_NOC 145 +#define RK3288_SOFT_RST_PD_CORE_APB_NOC 146 +#define RK3288_SOFT_RST_PD_CORE_MP_AXI 147 +#define RK3288_SOFT_RST_GIC 148 +#define RK3288_SOFT_RST_LCDCPWM0 149 +#define RK3288_SOFT_RST_LCDCPWM1 150 +#define RK3288_SOFT_RST_VIO0_H2P_BRG 151 +#define RK3288_SOFT_RST_VIO1_H2P_BRG 152 +#define RK3288_SOFT_RST_RGA_H2P_BRG 153 +#define RK3288_SOFT_RST_HEVC 154 +#define RK3288_SOFT_RST_9RES11 155 +#define RK3288_SOFT_RST_9RES12 156 +#define RK3288_SOFT_RST_9RES13 157 +#define RK3288_SOFT_RST_9RES14 158 +#define RK3288_SOFT_RST_TSADC_P 159 + +#define RK3288_SOFT_RST_DDRPHY0 160 +#define RK3288_SOFT_RST_DDRPHY0_P 161 +#define RK3288_SOFT_RST_DDRCTRL0 162 +#define RK3288_SOFT_RST_DDRCTRL0_P 163 +#define RK3288_SOFT_RST_DDRPHY0_CTL 164 +#define RK3288_SOFT_RST_DDRPHY1 165 +#define RK3288_SOFT_RST_DDRPHY1_P 166 +#define RK3288_SOFT_RST_DDRCTRL1 167 +#define RK3288_SOFT_RST_DDRCTRL1_P 168 +#define RK3288_SOFT_RST_DDRPHY1_CTL 169 +#define RK3288_SOFT_RST_DDRMSCH0 170 +#define RK3288_SOFT_RST_DDRMSCH1 171 +#define RK3288_SOFT_RST_10RES12 172 +#define RK3288_SOFT_RST_10RES13 173 +#define RK3288_SOFT_RST_CRYPTO 174 +#define RK3288_SOFT_RST_C2C_HOST 175 + +#define RK3288_SOFT_RST_LCDC1_A 176 +#define RK3288_SOFT_RST_LCDC1_H 177 +#define RK3288_SOFT_RST_LCDC1_D 178 +#define RK3288_SOFT_RST_UART0 179 +#define RK3288_SOFT_RST_UART1 180 +#define RK3288_SOFT_RST_UART2 181 +#define RK3288_SOFT_RST_UART3 182 +#define RK3288_SOFT_RST_UART4 183 +#define RK3288_SOFT_RST_11RES8 184 +#define RK3288_SOFT_RST_11RES9 185 +#define RK3288_SOFT_RST_SIMC 186 +#define RK3288_SOFT_RST_PS2C 187 +#define RK3288_SOFT_RST_TSP 188 +#define RK3288_SOFT_RST_TSP_CLKIN0 189 +#define RK3288_SOFT_RST_TSP_CLKIN1 190 +#define RK3288_SOFT_RST_TSP_27M 191 + + +#endif /* _DT_BINDINGS_CLOCK_ROCKCHIP_RK3288_H */ diff --git a/include/dt-bindings/clock/rockchip,rk3368.h b/include/dt-bindings/clock/rockchip,rk3368.h new file mode 100644 index 000000000000..76630794b4d9 --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk3368.h @@ -0,0 +1,263 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_RK3368_H +#define _DT_BINDINGS_CLOCK_ROCKCHIP_RK3368_H + +#include "rockchip.h" + +/* reset id */ +#define RK3368_SRST_CORE_B_0_SC 0 +#define RK3368_SRST_CORE_B_1 1 +#define RK3368_SRST_CORE_B_2 2 +#define RK3368_SRST_CORE_B_3 3 +#define RK3368_SRST_CORE_B_PO0_SC 4 +#define RK3368_SRST_CORE_B_PO1 5 +#define RK3368_SRST_CORE_B_PO2 6 +#define RK3368_SRST_CORE_B_PO3 7 +#define RK3368_SRST_L2_B_SC 8 +#define RK3368_SRST_ADB_B_SC 9 +#define RK3368_SRST_PD_CORE_B_NIU 10 +#define RK3368_SRST_STRC_SYS_A_SC 11 +#define RK3368_SRST_0RES12 12 +#define RK3368_SRST_0RES13 13 +#define RK3368_SRST_SOCDBG_B 14 +#define RK3368_SRST_CORE_B_DBG 15 + +#define RK3368_SRST_1RES0 16 +#define RK3368_SRST_1RES1 17 +#define RK3368_SRST_DMA1 18 +#define RK3368_SRST_INTMEM 19 +#define RK3368_SRST_ROM 20 +#define RK3368_SRST_SPDIF_8CH 21 +#define RK3368_SRST_1RES6 22 +#define RK3368_SRST_I2S 23 +#define RK3368_SRST_MAILBOX 24 +#define RK3368_SRST_I2S_2CH 25 +#define RK3368_SRST_EFUSE_256_P 26 +#define RK3368_SRST_1RES11 27 +#define RK3368_SRST_MCU_SYS 28 +#define RK3368_SRST_MCU_PO 29 +#define RK3368_SRST_MCU_NOC_H 30 +#define RK3368_SRST_EFUSE_P 31 + +#define RK3368_SRST_GPIO0 32 +#define RK3368_SRST_GPIO1 33 +#define RK3368_SRST_GPIO2 34 +#define RK3368_SRST_GPIO3 35 +#define RK3368_SRST_GPIO4 36 +#define RK3368_SRST_2RES5 37 +#define RK3368_SRST_2RES6 38 +#define RK3368_SRST_2RES7 39 +#define RK3368_SRST_2RES8 40 +#define RK3368_SRST_PMUGRF_P 41 +#define RK3368_SRST_I2C0 42 +#define RK3368_SRST_I2C1 43 +#define RK3368_SRST_I2C2 44 +#define RK3368_SRST_I2C3 45 +#define RK3368_SRST_I2C4 46 +#define RK3368_SRST_I2C5 47 + +#define RK3368_SRST_DW_PWM 48 +#define RK3368_SRST_MMC_PERI 49 +#define RK3368_SRST_PERIPH_MMU 50 +#define RK3368_SRST_3RES3 51 +#define RK3368_SRST_3RES4 52 +#define RK3368_SRST_3RES5 53 +#define RK3368_SRST_3RES6 54 +#define RK3368_SRST_GRF 55 +#define RK3368_SRST_PMU 56 +#define RK3368_SRST_PERIPH_SYS_A 57 +#define RK3368_SRST_PERIPH_SYS_H 58 +#define RK3368_SRST_PERIPH_SYS_P 59 +#define RK3368_SRST_PERIPH_NIU 60 +#define RK3368_SRST_PD_PERI_AHB_ARBITOR 61 +#define RK3368_SRST_EMEM_PERI 62 +#define RK3368_SRST_USB_PERI 63 + +#define RK3368_SRST_DMA2 64 +#define RK3368_SRST_4RES1 65 +#define RK3368_SRST_MAC 66 +#define RK3368_SRST_GPS 67 +#define RK3368_SRST_4RES4 68 +#define RK3368_SRST_RK_PWM 69 +#define RK3368_SRST_4RES6 70 +#define RK3368_SRST_4RES7 71 +#define RK3368_SRST_HOST0_H 72 +#define RK3368_SRST_EHCI1 73 +#define RK3368_SRST_EHCI1_AUX 74 +#define RK3368_SRST_EHCI1PHY 75 +#define RK3368_SRST_HSADC_H 76 +#define RK3368_SRST_NANDC0 77 +#define RK3368_SRST_4RES14 78 +#define RK3368_SRST_SFC 79 + +#define RK3368_SRST_5RES0 80 +#define RK3368_SRST_5RES1 81 +#define RK3368_SRST_5RES2 82 +#define RK3368_SRST_SPI0 83 +#define RK3368_SRST_SPI1 84 +#define RK3368_SRST_SPI2 85 +#define RK3368_SRST_5RES6 86 +#define RK3368_SRST_SARADC 87 +#define RK3368_SRST_PD_ALIVE_NIU_P 88 +#define RK3368_SRST_PD_PMU_INTMEM_P 89 +#define RK3368_SRST_PD_PMU_NIU_P 90 +#define RK3368_SRST_SGRF_P 91 +#define RK3368_SRST_5RES12 92 +#define RK3368_SRST_5RES13 93 +#define RK3368_SRST_5RES14 94 +#define RK3368_SRST_5RES15 95 + +#define RK3368_SRST_VIO_ARBI_H 96 +#define RK3368_SRST_RGA_NIU_A 97 +#define RK3368_SRST_VIO0_NIU_A 98 +#define RK3368_SRST_VIO0_BUS_H 99 +#define RK3368_SRST_LCDC0_A 100 +#define RK3368_SRST_LCDC0_H 101 +#define RK3368_SRST_LCDC0_D 102 +#define RK3368_SRST_6RES7 103 +#define RK3368_SRST_VIP 104 +#define RK3368_SRST_RGA_CORE 105 +#define RK3368_SRST_IEP_A 106 +#define RK3368_SRST_IEP_H 107 +#define RK3368_SRST_RGA_A 108 +#define RK3368_SRST_RGA_H 109 +#define RK3368_SRST_ISP 110 +#define RK3368_SRST_EDP_24M 111 + +#define RK3368_SRST_VIDEO_A 112 +#define RK3368_SRST_VIDEO_H 113 +#define RK3368_SRST_MIPIDPHYTX_P 114 +#define RK3368_SRST_MIPIDSI0_P 115 +#define RK3368_SRST_MIPIDPHYRX_P 116 +#define RK3368_SRST_MIPICSI_P 117 +#define RK3368_SRST_7RES6 118 +#define RK3368_SRST_7RES7 119 +#define RK3368_SRST_GPU_CORE 120 +#define RK3368_SRST_HDMI 121 +#define RK3368_SRST_EDP_P 122 +#define RK3368_SRST_PMU_PVTM 123 +#define RK3368_SRST_CORE_PVTM 124 +#define RK3368_SRST_GPU_PVTM 125 +#define RK3368_SRST_GPU_SYS_A 126 +#define RK3368_SRST_GPU_MEM_NIU_A 127 + +#define RK3368_SRST_MMC0 128 +#define RK3368_SRST_SDIO0 129 +#define RK3368_SRST_8RES2 130 +#define RK3368_SRST_EMMC 131 +#define RK3368_SRST_USBOTG0_H 132 +#define RK3368_SRST_USBOTGPHY0 133 +#define RK3368_SRST_USBOTGC0 134 +#define RK3368_SRST_USBHOSTC0_H 135 +#define RK3368_SRST_USBOTGPHY1 136 +#define RK3368_SRST_USBHOSTC0 137 +#define RK3368_SRST_USBPHY0_UTMI 138 +#define RK3368_SRST_USBPHY1_UTMI 139 +#define RK3368_SRST_8RES12 140 +#define RK3368_SRST_USB_ADP 141 +#define RK3368_SRST_8RES14 142 +#define RK3368_SRST_8RES15 143 + +#define RK3368_SRST_DBG 144 +#define RK3368_SRST_PD_CORE_AHB_NOC 145 +#define RK3368_SRST_PD_CORE_APB_NOC 146 +#define RK3368_SRST_9RES3 147 +#define RK3368_SRST_GIC 148 +#define RK3368_SRST_LCDCPWM0 149 +#define RK3368_SRST_9RES6 150 +#define RK3368_SRST_9RES7 151 +#define RK3368_SRST_9RES8 152 +#define RK3368_SRST_RGA_H2P_BRG 153 +#define RK3368_SRST_VIDEO 154 +#define RK3368_SRST_9RES11 155 +#define RK3368_SRST_9RES12 156 +#define RK3368_SRST_GPU_CFG_NIU_A 157 +#define RK3368_SRST_9RES14 158 +#define RK3368_SRST_TSADC_P 159 + +#define RK3368_SRST_DDRPHY0 160 +#define RK3368_SRST_DDRPHY0_P 161 +#define RK3368_SRST_DDRCTRL0 162 +#define RK3368_SRST_DDRCTRL0_P 163 +#define RK3368_SRST_10RES4 164 +#define RK3368_SRST_VIDEO_NIU_A 165 +#define RK3368_SRST_10RES6 166 +#define RK3368_SRST_VIDEO_NIU_H 167 +#define RK3368_SRST_10RES8 168 +#define RK3368_SRST_10RES9 169 +#define RK3368_SRST_DDRMSCH0 170 +#define RK3368_SRST_10RES11 171 +#define RK3368_SRST_10RES12 172 +#define RK3368_SRST_SYS_BUS 173 +#define RK3368_SRST_CRYPTO 174 +#define RK3368_SRST_10RES15 175 + +#define RK3368_SRST_11RES0 176 +#define RK3368_SRST_11RES1 177 +#define RK3368_SRST_11RES2 178 +#define RK3368_SRST_UART0 179 +#define RK3368_SRST_UART1 180 +#define RK3368_SRST_UART2 181 +#define RK3368_SRST_UART3 182 +#define RK3368_SRST_UART4 183 +#define RK3368_SRST_11RES8 184 +#define RK3368_SRST_11RES9 185 +#define RK3368_SRST_SIMC_P 186 +#define RK3368_SRST_11RES11 187 +#define RK3368_SRST_TSP_H 188 +#define RK3368_SRST_TSP_CLKIN0 189 +#define RK3368_SRST_11RES14 190 +#define RK3368_SRST_11RES15 191 + +#define RK3368_SRST_CORE_L_0_SC 192 +#define RK3368_SRST_CORE_L_1 193 +#define RK3368_SRST_CORE_L_2 194 +#define RK3368_SRST_CORE_L_3 195 +#define RK3368_SRST_CORE_L_PO0_SC 196 +#define RK3368_SRST_CORE_L_PO1 197 +#define RK3368_SRST_CORE_L_PO2 198 +#define RK3368_SRST_CORE_L_PO3 199 +#define RK3368_SRST_L2_L_SC 200 +#define RK3368_SRST_ADB_L_SC 201 +#define RK3368_SRST_PD_CORE_L_NIU_A_SC 202 +#define RK3368_SRST_CCI400_SYS_SC 203 +#define RK3368_SRST_CCI400_DDR_SC 204 +#define RK3368_SRST_CCI400_SC 205 +#define RK3368_SRST_SOCDBG_L 206 +#define RK3368_SRST_CORE_L_DBG 207 + +#define RK3368_SRST_CORE_B_0 208 +#define RK3368_SRST_CORE_B_PO0 209 +#define RK3368_SRST_L2_B 210 +#define RK3368_SRST_ADB_B 211 +#define RK3368_SRST_PD_CORE_B_NIU_A 212 +#define RK3368_SRST_STRC_SYS_A 213 +#define RK3368_SRST_CORE_L_0 214 +#define RK3368_SRST_CORE_L_PO0 215 +#define RK3368_SRST_L2_L 216 +#define RK3368_SRST_ADB_L 217 +#define RK3368_SRST_PD_CORE_L_NIU_A 218 +#define RK3368_SRST_CCI400_SYS 219 +#define RK3368_SRST_CCI400_DDR 220 +#define RK3368_SRST_CCI400 221 +#define RK3368_SRST_TRACE 222 +#define RK3368_SRST_13RES15 223 + +#define RK3368_SRST_TIMER00 224 +#define RK3368_SRST_TIMER01 225 +#define RK3368_SRST_TIMER02 226 +#define RK3368_SRST_TIMER03 227 +#define RK3368_SRST_TIMER04 228 +#define RK3368_SRST_TIMER05 229 +#define RK3368_SRST_TIMER10 230 +#define RK3368_SRST_TIMER11 231 +#define RK3368_SRST_TIMER12 232 +#define RK3368_SRST_TIMER13 233 +#define RK3368_SRST_TIMER14 234 +#define RK3368_SRST_TIMER15 235 +#define RK3368_SRST_TIMER0_P 236 +#define RK3368_SRST_TIMER1_P 237 +#define RK3368_SRST_14RES14 238 +#define RK3368_SRST_14RES15 239 + +#endif /* _DT_BINDINGS_CLOCK_ROCKCHIP_RK3368_H */ diff --git a/include/dt-bindings/clock/rockchip-ddr.h b/include/dt-bindings/clock/rockchip-ddr.h new file mode 100644 index 000000000000..b065432e7793 --- /dev/null +++ b/include/dt-bindings/clock/rockchip-ddr.h @@ -0,0 +1,63 @@ +/* + * + * Copyright (C) 2017 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H +#define _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H + +#define DDR2_DEFAULT (0) + +#define DDR3_800D (0) /* 5-5-5 */ +#define DDR3_800E (1) /* 6-6-6 */ +#define DDR3_1066E (2) /* 6-6-6 */ +#define DDR3_1066F (3) /* 7-7-7 */ +#define DDR3_1066G (4) /* 8-8-8 */ +#define DDR3_1333F (5) /* 7-7-7 */ +#define DDR3_1333G (6) /* 8-8-8 */ +#define DDR3_1333H (7) /* 9-9-9 */ +#define DDR3_1333J (8) /* 10-10-10 */ +#define DDR3_1600G (9) /* 8-8-8 */ +#define DDR3_1600H (10) /* 9-9-9 */ +#define DDR3_1600J (11) /* 10-10-10 */ +#define DDR3_1600K (12) /* 11-11-11 */ +#define DDR3_1866J (13) /* 10-10-10 */ +#define DDR3_1866K (14) /* 11-11-11 */ +#define DDR3_1866L (15) /* 12-12-12 */ +#define DDR3_1866M (16) /* 13-13-13 */ +#define DDR3_2133K (17) /* 11-11-11 */ +#define DDR3_2133L (18) /* 12-12-12 */ +#define DDR3_2133M (19) /* 13-13-13 */ +#define DDR3_2133N (20) /* 14-14-14 */ +#define DDR3_DEFAULT (21) +#define DDR_DDR2 (22) +#define DDR_LPDDR (23) +#define DDR_LPDDR2 (24) + +#define DDR4_1600J (0) /* 10-10-10 */ +#define DDR4_1600K (1) /* 11-11-11 */ +#define DDR4_1600L (2) /* 12-12-12 */ +#define DDR4_1866L (3) /* 12-12-12 */ +#define DDR4_1866M (4) /* 13-13-13 */ +#define DDR4_1866N (5) /* 14-14-14 */ +#define DDR4_2133N (6) /* 14-14-14 */ +#define DDR4_2133P (7) /* 15-15-15 */ +#define DDR4_2133R (8) /* 16-16-16 */ +#define DDR4_2400P (9) /* 15-15-15 */ +#define DDR4_2400R (10) /* 16-16-16 */ +#define DDR4_2400U (11) /* 18-18-18 */ +#define DDR4_DEFAULT (12) + +#define PAUSE_CPU_STACK_SIZE 16 + +#endif diff --git a/include/dt-bindings/clock/rockchip.h b/include/dt-bindings/clock/rockchip.h new file mode 100644 index 000000000000..b438f7bd4083 --- /dev/null +++ b/include/dt-bindings/clock/rockchip.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_H +#define _DT_BINDINGS_CLOCK_ROCKCHIP_H + +#ifndef BIT +#define BIT(nr) (1 << (nr)) +#endif + +#define CLK_DIVIDER_PLUS_ONE (0) +#define CLK_DIVIDER_ONE_BASED BIT(0) +#define CLK_DIVIDER_POWER_OF_TWO BIT(1) +#define CLK_DIVIDER_ALLOW_ZERO BIT(2) +#define CLK_DIVIDER_HIWORD_MASK BIT(3) + +/* Rockchip special defined */ +//#define CLK_DIVIDER_FIXED BIT(6) +#define CLK_DIVIDER_USER_DEFINE BIT(7) + +/* + * flags used across common struct clk. these flags should only affect the + * top-level framework. custom flags for dealing with hardware specifics + * belong in struct clk_foo + */ +#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ +#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ +#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ +#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ +#define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ +#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ +#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ +#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ +#define CLK_SET_RATE_PARENT_IN_ORDER BIT(8) /* consider the order of re-parent + and set_div on rate change */ + + + +/* Rockchip pll flags */ +#define CLK_PLL_3188 BIT(0) +#define CLK_PLL_3188_APLL BIT(1) +#define CLK_PLL_3188PLUS BIT(2) +#define CLK_PLL_3188PLUS_APLL BIT(3) +#define CLK_PLL_3288_APLL BIT(4) +#define CLK_PLL_3188PLUS_AUTO BIT(5) +#define CLK_PLL_3036_APLL BIT(6) +#define CLK_PLL_3036PLUS_AUTO BIT(7) +#define CLK_PLL_312XPLUS BIT(8) +#define CLK_PLL_3368_APLLB BIT(9) +#define CLK_PLL_3368_APLLL BIT(10) +#define CLK_PLL_3368_LOW_JITTER BIT(11) + + +/* rate_ops index */ +#define CLKOPS_RATE_MUX_DIV 1 +#define CLKOPS_RATE_EVENDIV 2 +#define CLKOPS_RATE_MUX_EVENDIV 3 +#define CLKOPS_RATE_I2S_FRAC 4 +#define CLKOPS_RATE_FRAC 5 +#define CLKOPS_RATE_I2S 6 +#define CLKOPS_RATE_CIFOUT 7 +#define CLKOPS_RATE_UART 8 +#define CLKOPS_RATE_HSADC 9 +#define CLKOPS_RATE_MAC_REF 10 +#define CLKOPS_RATE_CORE 11 +#define CLKOPS_RATE_CORE_CHILD 12 +#define CLKOPS_RATE_DDR 13 +#define CLKOPS_RATE_RK3288_I2S 14 +#define CLKOPS_RATE_RK3288_USB480M 15 +#define CLKOPS_RATE_RK3288_DCLK_LCDC0 16 +#define CLKOPS_RATE_RK3288_DCLK_LCDC1 17 +#define CLKOPS_RATE_DDR_DIV2 18 +#define CLKOPS_RATE_DDR_DIV4 19 +#define CLKOPS_RATE_RK3368_MUX_DIV_NPLL 20 +#define CLKOPS_RATE_RK3368_DCLK_LCDC 21 +#define CLKOPS_RATE_RK3368_DDR 22 + +#define CLKOPS_TABLE_END (~0) + +/* pd id */ +#define CLK_PD_BCPU 0 +#define CLK_PD_BDSP 1 +#define CLK_PD_BUS 2 +#define CLK_PD_CPU_0 3 +#define CLK_PD_CPU_1 4 +#define CLK_PD_CPU_2 5 +#define CLK_PD_CPU_3 6 +#define CLK_PD_CS 7 +#define CLK_PD_GPU 8 +#define CLK_PD_HEVC 9 +#define CLK_PD_PERI 10 +#define CLK_PD_SCU 11 +#define CLK_PD_VIDEO 12 +#define CLK_PD_VIO 13 +#define CLK_PD_GPU_0 14 +#define CLK_PD_GPU_1 15 + +#define CLK_PD_VIRT 255 + +/* reset flag */ +#define ROCKCHIP_RESET_HIWORD_MASK BIT(0) + +#endif /* _DT_BINDINGS_CLOCK_ROCKCHIP_H */ diff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h new file mode 100644 index 000000000000..d8d0e0456dc2 --- /dev/null +++ b/include/dt-bindings/clock/rv1108-cru.h @@ -0,0 +1,362 @@ +/* + * Copyright (c) 2016 Rockchip Electronics Co. Ltd. + * Author: Shawn Lin <shawn.lin@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H + +/* pll id */ +#define PLL_APLL 0 +#define PLL_DPLL 1 +#define PLL_GPLL 2 +#define ARMCLK 3 + +/* sclk gates (special clocks) */ +#define SCLK_SPI0 65 +#define SCLK_NANDC 67 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_UART0 72 +#define SCLK_UART1 73 +#define SCLK_UART2 74 +#define SCLK_I2S0 75 +#define SCLK_I2S1 76 +#define SCLK_I2S2 77 +#define SCLK_TIMER0 78 +#define SCLK_TIMER1 79 +#define SCLK_SFC 80 +#define SCLK_SDMMC_DRV 81 +#define SCLK_SDIO_DRV 82 +#define SCLK_EMMC_DRV 83 +#define SCLK_SDMMC_SAMPLE 84 +#define SCLK_SDIO_SAMPLE 85 +#define SCLK_EMMC_SAMPLE 86 +#define SCLK_VENC_CORE 87 +#define SCLK_HEVC_CORE 88 +#define SCLK_HEVC_CABAC 89 +#define SCLK_PWM0_PMU 90 +#define SCLK_I2C0_PMU 91 +#define SCLK_WIFI 92 +#define SCLK_CIFOUT 93 +#define SCLK_MIPI_CSI_OUT 94 +#define SCLK_CIF0 95 +#define SCLK_CIF1 96 +#define SCLK_CIF2 97 +#define SCLK_CIF3 98 +#define SCLK_DSP 99 +#define SCLK_DSP_IOP 100 +#define SCLK_DSP_EPP 101 +#define SCLK_DSP_EDP 102 +#define SCLK_DSP_EDAP 103 +#define SCLK_CVBS_HOST 104 +#define SCLK_HDMI_SFR 105 +#define SCLK_HDMI_CEC 106 +#define SCLK_CRYPTO 107 +#define SCLK_SPI 108 +#define SCLK_SARADC 109 +#define SCLK_TSADC 110 +#define SCLK_MAC_PRE 111 +#define SCLK_MAC 112 +#define SCLK_MAC_RX 113 +#define SCLK_MAC_REF 114 +#define SCLK_MAC_REFOUT 115 +#define SCLK_DSP_PFM 116 +#define SCLK_RGA 117 +#define SCLK_I2C1 118 +#define SCLK_I2C2 119 +#define SCLK_I2C3 120 +#define SCLK_PWM 121 +#define SCLK_ISP 122 +#define SCLK_USBPHY 123 +#define SCLK_I2S0_SRC 124 +#define SCLK_I2S1_SRC 125 +#define SCLK_I2S2_SRC 126 +#define SCLK_UART0_SRC 127 +#define SCLK_UART1_SRC 128 +#define SCLK_UART2_SRC 129 + +#define DCLK_VOP_SRC 185 +#define DCLK_HDMIPHY 186 +#define DCLK_VOP 187 + +/* aclk gates */ +#define ACLK_DMAC 192 +#define ACLK_PRE 193 +#define ACLK_CORE 194 +#define ACLK_ENMCORE 195 +#define ACLK_RKVENC 196 +#define ACLK_RKVDEC 197 +#define ACLK_VPU 198 +#define ACLK_CIF0 199 +#define ACLK_VIO0 200 +#define ACLK_VIO1 201 +#define ACLK_VOP 202 +#define ACLK_IEP 203 +#define ACLK_RGA 204 +#define ACLK_ISP 205 +#define ACLK_CIF1 206 +#define ACLK_CIF2 207 +#define ACLK_CIF3 208 +#define ACLK_PERI 209 +#define ACLK_GMAC 210 + +/* pclk gates */ +#define PCLK_GPIO1 256 +#define PCLK_GPIO2 257 +#define PCLK_GPIO3 258 +#define PCLK_GRF 259 +#define PCLK_I2C1 260 +#define PCLK_I2C2 261 +#define PCLK_I2C3 262 +#define PCLK_SPI 263 +#define PCLK_SFC 264 +#define PCLK_UART0 265 +#define PCLK_UART1 266 +#define PCLK_UART2 267 +#define PCLK_TSADC 268 +#define PCLK_PWM 269 +#define PCLK_TIMER 270 +#define PCLK_PERI 271 +#define PCLK_GPIO0_PMU 272 +#define PCLK_I2C0_PMU 273 +#define PCLK_PWM0_PMU 274 +#define PCLK_ISP 275 +#define PCLK_VIO 276 +#define PCLK_MIPI_DSI 277 +#define PCLK_HDMI_CTRL 278 +#define PCLK_SARADC 279 +#define PCLK_DSP_CFG 280 +#define PCLK_BUS 281 +#define PCLK_EFUSE0 282 +#define PCLK_EFUSE1 283 +#define PCLK_WDT 284 +#define PCLK_GMAC 285 + +/* hclk gates */ +#define HCLK_I2S0_8CH 320 +#define HCLK_I2S1_2CH 321 +#define HCLK_I2S2_2CH 322 +#define HCLK_NANDC 323 +#define HCLK_SDMMC 324 +#define HCLK_SDIO 325 +#define HCLK_EMMC 326 +#define HCLK_PERI 327 +#define HCLK_SFC 328 +#define HCLK_RKVENC 329 +#define HCLK_RKVDEC 330 +#define HCLK_CIF0 331 +#define HCLK_VIO 332 +#define HCLK_VOP 333 +#define HCLK_IEP 334 +#define HCLK_RGA 335 +#define HCLK_ISP 336 +#define HCLK_CRYPTO_MST 337 +#define HCLK_CRYPTO_SLV 338 +#define HCLK_HOST0 339 +#define HCLK_OTG 340 +#define HCLK_CIF1 341 +#define HCLK_CIF2 342 +#define HCLK_CIF3 343 +#define HCLK_BUS 344 +#define HCLK_VPU 345 + +#define CLK_NR_CLKS (HCLK_VPU + 1) + +/* reset id */ +#define SRST_CORE_PO_AD 0 +#define SRST_CORE_AD 1 +#define SRST_L2_AD 2 +#define SRST_CPU_NIU_AD 3 +#define SRST_CORE_PO 4 +#define SRST_CORE 5 +#define SRST_L2 6 +#define SRST_CORE_DBG 8 +#define PRST_DBG 9 +#define RST_DAP 10 +#define PRST_DBG_NIU 11 +#define ARST_STRC_SYS_AD 15 + +#define SRST_DDRPHY_CLKDIV 16 +#define SRST_DDRPHY 17 +#define PRST_DDRPHY 18 +#define PRST_HDMIPHY 19 +#define PRST_VDACPHY 20 +#define PRST_VADCPHY 21 +#define PRST_MIPI_CSI_PHY 22 +#define PRST_MIPI_DSI_PHY 23 +#define PRST_ACODEC 24 +#define ARST_BUS_NIU 25 +#define PRST_TOP_NIU 26 +#define ARST_INTMEM 27 +#define HRST_ROM 28 +#define ARST_DMAC 29 +#define SRST_MSCH_NIU 30 +#define PRST_MSCH_NIU 31 + +#define PRST_DDRUPCTL 32 +#define NRST_DDRUPCTL 33 +#define PRST_DDRMON 34 +#define HRST_I2S0_8CH 35 +#define MRST_I2S0_8CH 36 +#define HRST_I2S1_2CH 37 +#define MRST_IS21_2CH 38 +#define HRST_I2S2_2CH 39 +#define MRST_I2S2_2CH 40 +#define HRST_CRYPTO 41 +#define SRST_CRYPTO 42 +#define PRST_SPI 43 +#define SRST_SPI 44 +#define PRST_UART0 45 +#define PRST_UART1 46 +#define PRST_UART2 47 + +#define SRST_UART0 48 +#define SRST_UART1 49 +#define SRST_UART2 50 +#define PRST_I2C1 51 +#define PRST_I2C2 52 +#define PRST_I2C3 53 +#define SRST_I2C1 54 +#define SRST_I2C2 55 +#define SRST_I2C3 56 +#define PRST_PWM1 58 +#define SRST_PWM1 60 +#define PRST_WDT 61 +#define PRST_GPIO1 62 +#define PRST_GPIO2 63 + +#define PRST_GPIO3 64 +#define PRST_GRF 65 +#define PRST_EFUSE 66 +#define PRST_EFUSE512 67 +#define PRST_TIMER0 68 +#define SRST_TIMER0 69 +#define SRST_TIMER1 70 +#define PRST_TSADC 71 +#define SRST_TSADC 72 +#define PRST_SARADC 73 +#define SRST_SARADC 74 +#define HRST_SYSBUS 75 +#define PRST_USBGRF 76 + +#define ARST_PERIPH_NIU 80 +#define HRST_PERIPH_NIU 81 +#define PRST_PERIPH_NIU 82 +#define HRST_PERIPH 83 +#define HRST_SDMMC 84 +#define HRST_SDIO 85 +#define HRST_EMMC 86 +#define HRST_NANDC 87 +#define NRST_NANDC 88 +#define HRST_SFC 89 +#define SRST_SFC 90 +#define ARST_GMAC 91 +#define HRST_OTG 92 +#define SRST_OTG 93 +#define SRST_OTG_ADP 94 +#define HRST_HOST0 95 + +#define HRST_HOST0_AUX 96 +#define HRST_HOST0_ARB 97 +#define SRST_HOST0_EHCIPHY 98 +#define SRST_HOST0_UTMI 99 +#define SRST_USBPOR 100 +#define SRST_UTMI0 101 +#define SRST_UTMI1 102 + +#define ARST_VIO0_NIU 102 +#define ARST_VIO1_NIU 103 +#define HRST_VIO_NIU 104 +#define PRST_VIO_NIU 105 +#define ARST_VOP 106 +#define HRST_VOP 107 +#define DRST_VOP 108 +#define ARST_IEP 109 +#define HRST_IEP 110 +#define ARST_RGA 111 +#define HRST_RGA 112 +#define SRST_RGA 113 +#define PRST_CVBS 114 +#define PRST_HDMI 115 +#define SRST_HDMI 116 +#define PRST_MIPI_DSI 117 + +#define ARST_ISP_NIU 118 +#define HRST_ISP_NIU 119 +#define HRST_ISP 120 +#define SRST_ISP 121 +#define ARST_VIP0 122 +#define HRST_VIP0 123 +#define PRST_VIP0 124 +#define ARST_VIP1 125 +#define HRST_VIP1 126 +#define PRST_VIP1 127 +#define ARST_VIP2 128 +#define HRST_VIP2 129 +#define PRST_VIP2 120 +#define ARST_VIP3 121 +#define HRST_VIP3 122 +#define PRST_VIP4 123 + +#define PRST_CIF1TO4 124 +#define SRST_CVBS_CLK 125 +#define HRST_CVBS 126 + +#define ARST_VPU_NIU 140 +#define HRST_VPU_NIU 141 +#define ARST_VPU 142 +#define HRST_VPU 143 +#define ARST_RKVDEC_NIU 144 +#define HRST_RKVDEC_NIU 145 +#define ARST_RKVDEC 146 +#define HRST_RKVDEC 147 +#define SRST_RKVDEC_CABAC 148 +#define SRST_RKVDEC_CORE 149 +#define ARST_RKVENC_NIU 150 +#define HRST_RKVENC_NIU 151 +#define ARST_RKVENC 152 +#define HRST_RKVENC 153 +#define SRST_RKVENC_CORE 154 + +#define SRST_DSP_CORE 156 +#define SRST_DSP_SYS 157 +#define SRST_DSP_GLOBAL 158 +#define SRST_DSP_OECM 159 +#define PRST_DSP_IOP_NIU 160 +#define ARST_DSP_EPP_NIU 161 +#define ARST_DSP_EDP_NIU 162 +#define PRST_DSP_DBG_NIU 163 +#define PRST_DSP_CFG_NIU 164 +#define PRST_DSP_GRF 165 +#define PRST_DSP_MAILBOX 166 +#define PRST_DSP_INTC 167 +#define PRST_DSP_PFM_MON 169 +#define SRST_DSP_PFM_MON 170 +#define ARST_DSP_EDAP_NIU 171 + +#define SRST_PMU 172 +#define SRST_PMU_I2C0 173 +#define PRST_PMU_I2C0 174 +#define PRST_PMU_GPIO0 175 +#define PRST_PMU_INTMEM 176 +#define PRST_PMU_PWM0 177 +#define SRST_PMU_PWM0 178 +#define PRST_PMU_GRF 179 +#define SRST_PMU_NIU 180 +#define SRST_PMU_PVTM 181 +#define ARST_DSP_EDP_PERF 184 +#define ARST_DSP_EPP_PERF 185 + +#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */ diff --git a/include/dt-bindings/display/drm_mipi_dsi.h b/include/dt-bindings/display/drm_mipi_dsi.h new file mode 100644 index 000000000000..bc24ce4ddd08 --- /dev/null +++ b/include/dt-bindings/display/drm_mipi_dsi.h @@ -0,0 +1,53 @@ +/* + * MIPI DSI Bus + * + * Copyright (c) Fuzhou Rockchip Electronics Co.Ltd + * Authors: + * Mark Yao <yzq@rock-chips.com> + * + * based on include/drm/drm_mipi_dsi.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _DRM_MIPI_DSI_H__ +#define _DRM_MIPI_DSI_H__ + +/* DSI mode flags */ + +/* video mode */ +#define MIPI_DSI_MODE_VIDEO (1 << 0) +/* video burst mode */ +#define MIPI_DSI_MODE_VIDEO_BURST (1 << 1) +/* video pulse mode */ +#define MIPI_DSI_MODE_VIDEO_SYNC_PULSE (1 << 2) +/* enable auto vertical count mode */ +#define MIPI_DSI_MODE_VIDEO_AUTO_VERT (1 << 3) +/* enable hsync-end packets in vsync-pulse and v-porch area */ +#define MIPI_DSI_MODE_VIDEO_HSE (1 << 4) +/* disable hfront-porch area */ +#define MIPI_DSI_MODE_VIDEO_HFP (1 << 5) +/* disable hback-porch area */ +#define MIPI_DSI_MODE_VIDEO_HBP (1 << 6) +/* disable hsync-active area */ +#define MIPI_DSI_MODE_VIDEO_HSA (1 << 7) +/* flush display FIFO on vsync pulse */ +#define MIPI_DSI_MODE_VSYNC_FLUSH (1 << 8) +/* disable EoT packets in HS mode */ +#define MIPI_DSI_MODE_EOT_PACKET (1 << 9) +/* device supports non-continuous clock behavior (DSI spec 5.6.1) */ +#define MIPI_DSI_CLOCK_NON_CONTINUOUS (1 << 10) +/* transmit data in low power */ +#define MIPI_DSI_MODE_LPM (1 << 11) + +#define MIPI_DSI_FMT_RGB888 0 +#define MIPI_DSI_FMT_RGB666 1 +#define MIPI_DSI_FMT_RGB666_PACKED 2 +#define MIPI_DSI_FMT_RGB565 3 + +#define MIPI_CSI_FMT_RAW8 0x10 +#define MIPI_CSI_FMT_RAW10 0x11 + +#endif /* __DRM_MIPI_DSI__ */ diff --git a/include/dt-bindings/display/media-bus-format.h b/include/dt-bindings/display/media-bus-format.h new file mode 100644 index 000000000000..190d491d5b13 --- /dev/null +++ b/include/dt-bindings/display/media-bus-format.h @@ -0,0 +1,137 @@ +/* + * Media Bus API header + * + * Copyright (C) 2009, Guennadi Liakhovetski <g.liakhovetski@gmx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_MEDIA_BUS_FORMAT_H +#define __LINUX_MEDIA_BUS_FORMAT_H + +/* + * These bus formats uniquely identify data formats on the data bus. Format 0 + * is reserved, MEDIA_BUS_FMT_FIXED shall be used by host-client pairs, where + * the data format is fixed. Additionally, "2X8" means that one pixel is + * transferred in two 8-bit samples, "BE" or "LE" specify in which order those + * samples are transferred over the bus: "LE" means that the least significant + * bits are transferred first, "BE" means that the most significant bits are + * transferred first, and "PADHI" and "PADLO" define which bits - low or high, + * in the incomplete high byte, are filled with padding bits. + * + * The bus formats are grouped by type, bus_width, bits per component, samples + * per pixel and order of subsamples. Numerical values are sorted using generic + * numerical sort order (8 thus comes before 10). + * + * As their value can't change when a new bus format is inserted in the + * enumeration, the bus formats are explicitly given a numerical value. The next + * free values for each category are listed below, update them when inserting + * new pixel codes. + */ + +#define MEDIA_BUS_FMT_FIXED 0x0001 + +/* RGB - next is 0x1018 */ +#define MEDIA_BUS_FMT_RGB444_1X12 0x1016 +#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001 +#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002 +#define MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE 0x1003 +#define MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE 0x1004 +#define MEDIA_BUS_FMT_RGB565_1X16 0x1017 +#define MEDIA_BUS_FMT_BGR565_2X8_BE 0x1005 +#define MEDIA_BUS_FMT_BGR565_2X8_LE 0x1006 +#define MEDIA_BUS_FMT_RGB565_2X8_BE 0x1007 +#define MEDIA_BUS_FMT_RGB565_2X8_LE 0x1008 +#define MEDIA_BUS_FMT_RGB666_1X18 0x1009 +#define MEDIA_BUS_FMT_RBG888_1X24 0x100e +#define MEDIA_BUS_FMT_RGB666_1X24_CPADHI 0x1015 +#define MEDIA_BUS_FMT_RGB666_1X7X3_SPWG 0x1010 +#define MEDIA_BUS_FMT_BGR888_1X24 0x1013 +#define MEDIA_BUS_FMT_GBR888_1X24 0x1014 +#define MEDIA_BUS_FMT_RGB888_1X24 0x100a +#define MEDIA_BUS_FMT_RGB888_2X12_BE 0x100b +#define MEDIA_BUS_FMT_RGB888_2X12_LE 0x100c +#define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG 0x1011 +#define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA 0x1012 +#define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d +#define MEDIA_BUS_FMT_RGB888_1X32_PADHI 0x100f + +/* YUV (including grey) - next is 0x2026 */ +#define MEDIA_BUS_FMT_Y8_1X8 0x2001 +#define MEDIA_BUS_FMT_UV8_1X8 0x2015 +#define MEDIA_BUS_FMT_UYVY8_1_5X8 0x2002 +#define MEDIA_BUS_FMT_VYUY8_1_5X8 0x2003 +#define MEDIA_BUS_FMT_YUYV8_1_5X8 0x2004 +#define MEDIA_BUS_FMT_YVYU8_1_5X8 0x2005 +#define MEDIA_BUS_FMT_UYVY8_2X8 0x2006 +#define MEDIA_BUS_FMT_VYUY8_2X8 0x2007 +#define MEDIA_BUS_FMT_YUYV8_2X8 0x2008 +#define MEDIA_BUS_FMT_YVYU8_2X8 0x2009 +#define MEDIA_BUS_FMT_Y10_1X10 0x200a +#define MEDIA_BUS_FMT_UYVY10_2X10 0x2018 +#define MEDIA_BUS_FMT_VYUY10_2X10 0x2019 +#define MEDIA_BUS_FMT_YUYV10_2X10 0x200b +#define MEDIA_BUS_FMT_YVYU10_2X10 0x200c +#define MEDIA_BUS_FMT_Y12_1X12 0x2013 +#define MEDIA_BUS_FMT_UYVY12_2X12 0x201c +#define MEDIA_BUS_FMT_VYUY12_2X12 0x201d +#define MEDIA_BUS_FMT_YUYV12_2X12 0x201e +#define MEDIA_BUS_FMT_YVYU12_2X12 0x201f +#define MEDIA_BUS_FMT_UYVY8_1X16 0x200f +#define MEDIA_BUS_FMT_VYUY8_1X16 0x2010 +#define MEDIA_BUS_FMT_YUYV8_1X16 0x2011 +#define MEDIA_BUS_FMT_YVYU8_1X16 0x2012 +#define MEDIA_BUS_FMT_YDYUYDYV8_1X16 0x2014 +#define MEDIA_BUS_FMT_UYVY10_1X20 0x201a +#define MEDIA_BUS_FMT_VYUY10_1X20 0x201b +#define MEDIA_BUS_FMT_YUYV10_1X20 0x200d +#define MEDIA_BUS_FMT_YVYU10_1X20 0x200e +#define MEDIA_BUS_FMT_VUY8_1X24 0x2024 +#define MEDIA_BUS_FMT_YUV8_1X24 0x2025 +#define MEDIA_BUS_FMT_UYVY12_1X24 0x2020 +#define MEDIA_BUS_FMT_VYUY12_1X24 0x2021 +#define MEDIA_BUS_FMT_YUYV12_1X24 0x2022 +#define MEDIA_BUS_FMT_YVYU12_1X24 0x2023 +#define MEDIA_BUS_FMT_YUV10_1X30 0x2016 +#define MEDIA_BUS_FMT_AYUV8_1X32 0x2017 + +/* Bayer - next is 0x3019 */ +#define MEDIA_BUS_FMT_SBGGR8_1X8 0x3001 +#define MEDIA_BUS_FMT_SGBRG8_1X8 0x3013 +#define MEDIA_BUS_FMT_SGRBG8_1X8 0x3002 +#define MEDIA_BUS_FMT_SRGGB8_1X8 0x3014 +#define MEDIA_BUS_FMT_SBGGR10_ALAW8_1X8 0x3015 +#define MEDIA_BUS_FMT_SGBRG10_ALAW8_1X8 0x3016 +#define MEDIA_BUS_FMT_SGRBG10_ALAW8_1X8 0x3017 +#define MEDIA_BUS_FMT_SRGGB10_ALAW8_1X8 0x3018 +#define MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8 0x300b +#define MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8 0x300c +#define MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8 0x3009 +#define MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8 0x300d +#define MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE 0x3003 +#define MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE 0x3004 +#define MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE 0x3005 +#define MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE 0x3006 +#define MEDIA_BUS_FMT_SBGGR10_1X10 0x3007 +#define MEDIA_BUS_FMT_SGBRG10_1X10 0x300e +#define MEDIA_BUS_FMT_SGRBG10_1X10 0x300a +#define MEDIA_BUS_FMT_SRGGB10_1X10 0x300f +#define MEDIA_BUS_FMT_SBGGR12_1X12 0x3008 +#define MEDIA_BUS_FMT_SGBRG12_1X12 0x3010 +#define MEDIA_BUS_FMT_SGRBG12_1X12 0x3011 +#define MEDIA_BUS_FMT_SRGGB12_1X12 0x3012 + +/* JPEG compressed formats - next is 0x4002 */ +#define MEDIA_BUS_FMT_JPEG_1X8 0x4001 + +/* Vendor specific formats - next is 0x5002 */ + +/* S5C73M3 sensor specific interleaved UYVY and JPEG */ +#define MEDIA_BUS_FMT_S5C_UYVY_JPEG_1X8 0x5001 + +/* HSV - next is 0x6002 */ +#define MEDIA_BUS_FMT_AHSV8888_1X32 0x6001 + +#endif /* __LINUX_MEDIA_BUS_FORMAT_H */ diff --git a/include/dt-bindings/display/mipi_dsi.h b/include/dt-bindings/display/mipi_dsi.h new file mode 100644 index 000000000000..38aeee0ed51d --- /dev/null +++ b/include/dt-bindings/display/mipi_dsi.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +drivers/video/rockchip/transmitter/mipi_dsi.h +*/ +#ifndef MIPI_DSI_H_ +#define MIPI_DSI_H_ + +#ifdef CONFIG_MIPI_DSI_FT +#include "..\..\common\config.h" +#endif + +//DSI DATA TYPE +#define DTYPE_DCS_SWRITE_0P 0x05 +#define DTYPE_DCS_SWRITE_1P 0x15 +#define DTYPE_DCS_LWRITE 0x39 +#define DTYPE_GEN_LWRITE 0x29 +#define DTYPE_GEN_SWRITE_2P 0x23 +#define DTYPE_GEN_SWRITE_1P 0x13 +#define DTYPE_GEN_SWRITE_0P 0x03 + +//command transmit mode +#define HSDT 0x00 +#define LPDT 0x01 + +//DSI DATA TYPE FLAG +#define DATA_TYPE_DCS 0x00 +#define DATA_TYPE_GEN 0x01 + +//Video Mode +#define VM_NBMWSP 0x00 //Non burst mode with sync pulses +#define VM_NBMWSE 0x01 //Non burst mode with sync events +#define VM_BM 0x02 //Burst mode + +//Video Pixel Format +#define VPF_16BPP 0x00 +#define VPF_18BPP 0x01 //packed +#define VPF_18BPPL 0x02 //loosely packed +#define VPF_24BPP 0x03 + +//Display Command Set +#define dcs_enter_idle_mode 0x39 +#define dcs_enter_invert_mode 0x21 +#define dcs_enter_normal_mode 0x13 +#define dcs_enter_partial_mode 0x12 +#define dcs_enter_sleep_mode 0x10 +#define dcs_exit_idle_mode 0x38 +#define dcs_exit_invert_mode 0x20 +#define dcs_exit_sleep_mode 0x11 +#define dcs_get_address_mode 0x0b +#define dcs_get_blue_channel 0x08 +#define dcs_get_diagnostic_result 0x0f +#define dcs_get_display_mode 0x0d +#define dcs_get_green_channel 0x07 +#define dcs_get_pixel_format 0x0c +#define dcs_get_power_mode 0x0a +#define dcs_get_red_channel 0x06 +#define dcs_get_scanline 0x45 +#define dcs_get_signal_mode 0x0e +#define dcs_nop 0x00 +#define dcs_read_DDB_continue 0xa8 +#define dcs_read_DDB_start 0xa1 +#define dcs_read_memory_continue 0x3e +#define dcs_read_memory_start 0x2e +#define dcs_set_address_mode 0x36 +#define dcs_set_column_address 0x2a +#define dcs_set_display_off 0x28 +#define dcs_set_display_on 0x29 +#define dcs_set_gamma_curve 0x26 +#define dcs_set_page_address 0x2b +#define dcs_set_partial_area 0x30 +#define dcs_set_pixel_format 0x3a +#define dcs_set_scroll_area 0x33 +#define dcs_set_scroll_start 0x37 +#define dcs_set_tear_off 0x34 +#define dcs_set_tear_on 0x35 +#define dcs_set_tear_scanline 0x44 +#define dcs_soft_reset 0x01 +#define dcs_write_LUT 0x2d +#define dcs_write_memory_continue 0x3c +#define dcs_write_memory_start 0x2c + +#ifndef MHz +#define MHz 1000000 +#endif + + +#if 0 +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long s64; +typedef unsigned long u64; +#endif + + +//iomux +#define OLD_RK_IOMUX 0 + + +#endif /* end of MIPI_DSI_H_ */ diff --git a/include/dt-bindings/display/rk_fb.h b/include/dt-bindings/display/rk_fb.h new file mode 100644 index 000000000000..0b4594b2b055 --- /dev/null +++ b/include/dt-bindings/display/rk_fb.h @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _DT_BINDINGS_RKFB_H_ +#define _DT_BINDINGS_RKFB_H_ +#define GPIO 0 +#define REGULATOR 1 + +#define PRMRY 1 /*primary display device*/ +#define EXTEND 2 /*extend display device*/ + +#define DISPLAY_SOURCE_LCDC0 0 +#define DISPLAY_SOURCE_LCDC1 1 + +#define NO_DUAL 0 +#define ONE_DUAL 1 +#define DUAL 2 +#define DUAL_LCD 3 + +#define DEFAULT_MODE 0 +#define ONE_VOP_DUAL_MIPI_HOR_SCAN 1 +#define ONE_VOP_DUAL_MIPI_VER_SCAN 2 +#define TWO_VOP_TWO_SCREEN 3 + +/******************************************************************** +** display output interface supported by rockchip ** +********************************************************************/ +#define OUT_P888 0 //24bit screen,connect to lcdc D0~D23 +#define OUT_P666 1 //18bit screen,connect to lcdc D0~D17 +#define OUT_P565 2 +#define OUT_S888x 4 +#define OUT_CCIR656 6 +#define OUT_S888 8 +#define OUT_S888DUMY 12 +#define OUT_YUV_420 14 +#define OUT_P101010 15 +#define OUT_YUV_420_10BIT 16 +#define OUT_YUV_422 12 +#define OUT_YUV_422_10BIT 17 +#define OUT_P16BPP4 24 +#define OUT_D888_P666 0x21 //18bit screen,connect to lcdc D2~D7, D10~D15, D18~D23 +#define OUT_D888_P565 0x22 + +#define SCREEN_NULL 0 +#define SCREEN_RGB 1 +#define SCREEN_LVDS 2 +#define SCREEN_DUAL_LVDS 3 +#define SCREEN_MCU 4 +#define SCREEN_TVOUT 5 +#define SCREEN_HDMI 6 +#define SCREEN_MIPI 7 +#define SCREEN_DUAL_MIPI 8 +#define SCREEN_EDP 9 +#define SCREEN_TVOUT_TEST 10 +#define SCREEN_LVDS_10BIT 11 +#define SCREEN_DUAL_LVDS_10BIT 12 +#define SCREEN_DP 13 + +#define LVDS_8BIT_1 0 +#define LVDS_8BIT_2 1 +#define LVDS_8BIT_3 2 +#define LVDS_6BIT 3 +#define LVDS_10BIT_1 4 +#define LVDS_10BIT_2 5 + +/* x y mirror or rotate mode */ +#define NO_MIRROR 0 +#define X_MIRROR 1 /* up-down flip*/ +#define Y_MIRROR 2 /* left-right flip */ +#define X_Y_MIRROR 3 /* the same as rotate 180 degrees */ +#define ROTATE_90 4 /* clockwise rotate 90 degrees */ +#define ROTATE_180 8 /* rotate 180 degrees + * It is recommended to use X_Y_MIRROR + * rather than ROTATE_180 + */ +#define ROTATE_270 12/* clockwise rotate 270 degrees */ + +#define COLOR_RGB 0 +#define COLOR_RGB_BT2020 1 +/* default colorspace is bt601 */ +#define COLOR_YCBCR 2 +#define COLOR_YCBCR_BT709 3 +#define COLOR_YCBCR_BT2020 4 + +#define IS_YUV_COLOR(x) ((x) >= COLOR_YCBCR) + +#define SCREEN_VIDEO_MODE 0 +#define SCREEN_CMD_MODE 1 + +/* fb win map */ +#define FB_DEFAULT_ORDER 0 +#define FB0_WIN2_FB1_WIN1_FB2_WIN0 12 +#define FB0_WIN1_FB1_WIN2_FB2_WIN0 21 +#define FB0_WIN2_FB1_WIN0_FB2_WIN1 102 +#define FB0_WIN0_FB1_WIN2_FB2_WIN1 120 +#define FB0_WIN0_FB1_WIN1_FB2_WIN2 210 +#define FB0_WIN1_FB1_WIN0_FB2_WIN2 201 +#define FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3 3210 +#define FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3_FB4_HWC 43210 + +#define DISPLAY_POLICY_SDK 0 +#define DISPLAY_POLICY_BOX 1 + +/* lvds connect config + * + * LVDS_8BIT_1 LVDS_8BIT_2 LVDS_8BIT_3 LVDS_6BIT +---------------------------------------------------------------------- + TX0 R0 R2 R2 R0 + TX1 R1 R3 R3 R1 + TX2 R2 R4 R4 R2 +Y TX3 R3 R5 R5 R3 +0 TX4 R4 R6 R6 R4 + TX6 R5 R7 R7 R5 + TX7 G0 G2 G2 G0 +---------------------------------------------------------------------- + TX8 G1 G3 G3 G1 + TX9 G2 G4 G4 G2 +Y TX12 G3 G5 G5 G3 +1 TX13 G4 G6 G6 G4 + TX14 G5 G7 G7 G5 + TX15 B0 B2 B2 B0 + TX18 B1 B3 B3 B1 +---------------------------------------------------------------------- + TX19 B2 B4 B4 B2 + TX20 B3 B5 B5 B3 + TX21 B4 B6 B6 B4 +Y TX22 B5 B7 B7 B5 +2 TX24 HSYNC HSYNC HSYNC HSYNC + TX25 VSYNC VSYNC VSYNC VSYNC + TX26 ENABLE ENABLE ENABLE ENABLE +---------------------------------------------------------------------- + TX27 R6 R0 GND GND + TX5 R7 R1 GND GND + TX10 G6 G0 GND GND +Y TX11 G7 G1 GND GND +3 TX16 B6 B0 GND GND + TX17 B7 B1 GND GND + TX23 RSVD RSVD RSVD RSVD +---------------------------------------------------------------------- + + * LVDS_10BIT_1 LVDS_10BIT_2 +---------------------------------------------------------------------- + TX0 R0 R4 + TX1 R1 R5 + TX2 R2 R6 +Y TX3 R3 R7 +0 TX4 R4 R8 + TX6 R5 R9 + TX7 G0 G4 +---------------------------------------------------------------------- + TX8 G1 G5 + TX9 G2 G6 +Y TX12 G3 G7 +1 TX13 G4 G8 + TX14 G5 G9 + TX15 B0 B4 + TX18 B1 B5 +---------------------------------------------------------------------- + TX19 B2 B6 + TX20 B3 B7 + TX21 B4 B8 +Y TX22 B5 B9 +2 TX24 HSYNC HSYNC + TX25 VSYNC VSYNC + TX26 ENABLE ENABLE +---------------------------------------------------------------------- + TX27 R6 R2 + TX5 R7 R3 + TX10 G6 G2 +Y TX11 G7 G3 +3 TX16 B6 B2 + TX17 B7 B3 + TX23 GND GND +---------------------------------------------------------------------- + TX27 R8 R0 + TX5 R9 R1 + TX10 G8 G0 +Y TX11 G9 G1 +4 TX16 B8 B0 + TX17 B9 B1 + TX23 GND GND +------------------------------------------------------------------------ +*/ + +#endif diff --git a/include/dt-bindings/display/screen-timing/lcd-86v-rgb1024x600.dtsi b/include/dt-bindings/display/screen-timing/lcd-86v-rgb1024x600.dtsi new file mode 100644 index 000000000000..dcca65671ffb --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-86v-rgb1024x600.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RockChip. LCD_RGB1024x600 FOR 86V + * + */ + + +disp_timings: display-timings { + native-mode = <&timing0>; + timing0: timing0 { + screen-type = <SCREEN_RGB>; + out-face = <OUT_P666>; + clock-frequency = <60000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <100>; + hfront-porch = <120>; + vback-porch = <10>; + vfront-porch = <15>; + hsync-len = <100>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-F402.dtsi b/include/dt-bindings/display/screen-timing/lcd-F402.dtsi new file mode 100644 index 000000000000..0a7a45ad935e --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-F402.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RockChip. DisplayPort screen LP097QX1 + * + */ + + +disp_timings: display-timings { + native-mode = <&timing0>; + timing0: timing0 { + screen-type = <SCREEN_EDP>; + out-face = <OUT_P666>; + clock-frequency = <205000000>; + hactive = <1536>; + vactive = <2048>; + hback-porch = <48>; + hfront-porch = <12>; + vback-porch = <8>; + vfront-porch = <8>; + hsync-len = <16>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + dsp-lut = <0x00000000 0x00010101 0x00020202 0x00030303 0x00040404 0x00050505 0x00060606 0x00070707 0x00080808 0x00090909 + 0x000a0a0a 0x000b0b0b 0x000c0c0c 0x000d0d0d 0x000e0e0e 0x000f0f0f 0x00101010 0x00111111 0x00121212 0x00131313 + 0x00141414 0x00151515 0x00161616 0x00171717 0x00181818 0x00191919 0x001a1a1a 0x001b1b1b 0x001c1c1c 0x001d1d1d + 0x001e1e1e 0x001f1f1f 0x00202020 0x00212121 0x00222222 0x00232323 0x00242424 0x00252525 0x00262626 0x00272727 + 0x00282828 0x00292929 0x002a2a2a 0x002b2b2b 0x002c2c2c 0x002d2d2d 0x002e2e2e 0x002f2f2f 0x00303030 0x00313131 + 0x00323232 0x00333333 0x00343434 0x00353535 0x00363636 0x00373737 0x00383838 0x00393939 0x003a3a3a 0x003b3b3b + 0x003c3c3c 0x003d3d3d 0x003e3e3e 0x003f3f3f 0x00404040 0x00414141 0x00424242 0x00434343 0x00444444 0x00454545 + 0x00464646 0x00474747 0x00484848 0x00494949 0x004a4a4a 0x004b4b4b 0x004c4c4c 0x004d4d4d 0x004e4e4e 0x004f4f4f + 0x00505050 0x00515151 0x00525252 0x00535353 0x00545454 0x00555555 0x00565656 0x00575757 0x00585858 0x00595959 + 0x005a5a5a 0x005b5b5b 0x005c5c5c 0x005d5d5d 0x005e5e5e 0x005f5f5f 0x00606060 0x00616161 0x00626262 0x00636363 + 0x00646464 0x00656565 0x00666666 0x00676767 0x00686868 0x00696969 0x006a6a6a 0x006b6b6b 0x006c6c6c 0x006d6d6d + 0x006e6e6e 0x006f6f6f 0x00707070 0x00717171 0x00727272 0x00737373 0x00747474 0x00757575 0x00767676 0x00777777 + 0x00787878 0x00797979 0x007a7a7a 0x007b7b7b 0x007c7c7c 0x007d7d7d 0x007e7e7e 0x007f7f7f 0x00808080 0x00818181 + 0x00828282 0x00838383 0x00848484 0x00858585 0x00868686 0x00878787 0x00888888 0x00898989 0x008a8a8a 0x008b8b8b + 0x008c8c8c 0x008d8d8d 0x008e8e8e 0x008f8f8f 0x00909090 0x00919191 0x00929292 0x00939393 0x00949494 0x00959595 + 0x00969696 0x00979797 0x00989898 0x00999999 0x009a9a9a 0x009b9b9b 0x009c9c9c 0x009d9d9d 0x009e9e9e 0x009f9f9f + 0x00a0a0a0 0x00a1a1a1 0x00a2a2a2 0x00a3a3a3 0x00a4a4a4 0x00a5a5a5 0x00a6a6a6 0x00a7a7a7 0x00a8a8a8 0x00a9a9a9 + 0x00aaaaaa 0x00ababab 0x00acacac 0x00adadad 0x00aeaeae 0x00afafaf 0x00b0b0b0 0x00b1b1b1 0x00b2b2b2 0x00b3b3b3 + 0x00b4b4b4 0x00b5b5b5 0x00b6b6b6 0x00b7b7b7 0x00b8b8b8 0x00b9b9b9 0x00bababa 0x00bbbbbb 0x00bcbcbc 0x00bdbdbd + 0x00bebebe 0x00bfbfbf 0x00c0c0c0 0x00c1c1c1 0x00c2c2c2 0x00c3c3c3 0x00c4c4c4 0x00c5c5c5 0x00c6c6c6 0x00c7c7c7 + 0x00c8c8c8 0x00c9c9c9 0x00cacaca 0x00cbcbcb 0x00cccccc 0x00cdcdcd 0x00cecece 0x00cfcfcf 0x00d0d0d0 0x00d1d1d1 + 0x00d2d2d2 0x00d3d3d3 0x00d4d4d4 0x00d5d5d5 0x00d6d6d6 0x00d7d7d7 0x00d8d8d8 0x00d9d9d9 0x00dadada 0x00dbdbdb + 0x00dcdcdc 0x00dddddd 0x00dedede 0x00dfdfdf 0x00e0e0e0 0x00e1e1e1 0x00e2e2e2 0x00e3e3e3 0x00e4e4e4 0x00e5e5e5 + 0x00e6e6e6 0x00e7e7e7 0x00e8e8e8 0x00e9e9e9 0x00eaeaea 0x00ebebeb 0x00ececec 0x00ededed 0x00eeeeee 0x00efefef + 0x00f0f0f0 0x00f1f1f1 0x00f2f2f2 0x00f3f3f3 0x00f4f4f4 0x00f5f5f5 0x00f6f6f6 0x00f7f7f7 0x00f8f8f8 0x00f9f9f9 + 0x00fafafa 0x00fbfbfb 0x00fcfcfc 0x00fdfdfd 0x00fefefe 0x00ffffff>; + cabc-lut = < + /*gamma = 2.2*/ + 0x00000383 0x00000392 0x000003a2 0x000003b2 0x000003c2 0x000003d2 0x000003e2 0x000003f3 + 0x00000403 0x00000414 0x00000425 0x00000436 0x00000447 0x00000458 0x0000046a 0x0000047b + 0x0000048d 0x0000049f 0x000004b1 0x000004c3 0x000004d5 0x000004e8 0x000004fa 0x0000050d + 0x00000520 0x00000533 0x00000546 0x0000055a 0x0000056d 0x00000581 0x00000595 0x000005a9 + 0x000005bd 0x000005d1 0x000005e5 0x000005fa 0x0000060f 0x00000624 0x00000639 0x0000064e + 0x00000663 0x00000679 0x0000068e 0x000006a4 0x000006ba 0x000006d0 0x000006e6 0x000006fd + 0x00000713 0x0000072a 0x00000741 0x00000758 0x0000076f 0x00000786 0x0000079e 0x000007b6 + 0x000007cd 0x000007e5 0x000007fd 0x00000816 0x0000082e 0x00000847 0x0000085f 0x00000878 + 0x00000891 0x000008ab 0x000008c4 0x000008de 0x000008f7 0x00000911 0x0000092b 0x00000945 + 0x00000960 0x0000097a 0x00000995 0x000009af 0x000009ca 0x000009e6 0x00000a01 0x00000a1c + 0x00000a38 0x00000a54 0x00000a6f 0x00000a8c 0x00000aa8 0x00000ac4 0x00000ae1 0x00000afd + 0x00000b1a 0x00000b37 0x00000b54 0x00000b72 0x00000b8f 0x00000bad 0x00000bcb 0x00000be9 + 0x00000c07 0x00000c25 0x00000c44 0x00000c62 0x00000c81 0x00000ca0 0x00000cbf 0x00000cdf + 0x00000cfe 0x00000d1e 0x00000d3e 0x00000d5d 0x00000d7e 0x00000d9e 0x00000dbe 0x00000ddf + 0x00000e00 0x00000e21 0x00000e42 0x00000e63 0x00000e84 0x00000ea6 0x00000ec8 0x00000eea + 0x00000f0c 0x00000f2e 0x00000f50 0x00000f73 0x00000f96 0x00000fb9 0x00000fdc 0x00000fff + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; + cabc-gamma-base = < + /*gamma = 2.2*/ + 0x00010000 0x0000fdd0 0x0000fba8 0x0000f986 0x0000f76a 0x0000f556 0x0000f347 0x0000f140 + 0x0000ef3e 0x0000ed43 0x0000eb4e 0x0000e95e 0x0000e775 0x0000e592 0x0000e3b4 0x0000e1dc + 0x0000e009 0x0000de3c 0x0000dc74 0x0000dab2 0x0000d8f4 0x0000d73c 0x0000d589 0x0000d3db + 0x0000d232 0x0000d08d 0x0000ceee 0x0000cd53 0x0000cbbc 0x0000ca2b 0x0000c89d 0x0000c714 + 0x0000c590 0x0000c410 0x0000c294 0x0000c11c 0x0000bfa8 0x0000be39 0x0000bccd 0x0000bb65 + 0x0000ba01 0x0000b8a1 0x0000b745 0x0000b5ed 0x0000b498 0x0000b347 0x0000b1f9 0x0000b0af + 0x0000af68 0x0000ae25 0x0000ace5 0x0000aba8 0x0000aa6f 0x0000a939 0x0000a806 0x0000a6d7 + 0x0000a5aa 0x0000a480 0x0000a35a 0x0000a236 0x0000a116 0x00009ff8 0x00009edd 0x00009dc5 + 0x00009cb0 0x00009b9e 0x00009a8e 0x00009981 0x00009877 0x0000976f 0x0000966a 0x00009567 + 0x00009467 0x0000936a 0x0000926f 0x00009176 0x00009080 0x00008f8c 0x00008e9a 0x00008dab + 0x00008cbe 0x00008bd3 0x00008aea 0x00008a04 0x00008920 0x0000883e 0x0000875e 0x00008680 + 0x000085a4 0x000084ca 0x000083f3 0x0000831d 0x00008249 0x00008177 0x000080a7 0x00007fd9 + 0x00007f0d 0x00007e42 0x00007d7a 0x00007cb3 0x00007bee 0x00007b2b 0x00007a6a 0x000079aa + 0x000078ec 0x0000782f 0x00007775 0x000076bc 0x00007604 0x0000754f 0x0000749a 0x000073e8 + 0x00007337 0x00007287 0x000071d9 0x0000712c 0x00007081 0x00006fd8 0x00006f30 0x00006e89 + 0x00006de4 0x00006d40 0x00006c9d 0x00006bfc 0x00006b5c 0x00006abe 0x00006a21 0x00006985 + 0x000068ea 0x00006851 0x000067b9 0x00006722 0x0000668d 0x000065f9 0x00006566 0x000064d4 + 0x00006443 0x000063b4 0x00006325 0x00006298 0x0000620c 0x00006181 0x000060f8 0x0000606f + 0x00005fe7 0x00005f61 0x00005edb 0x00005e57 0x00005dd4 0x00005d51 0x00005cd0 0x00005c50 + 0x00005bd1 0x00005b52 0x00005ad5 0x00005a59 0x000059de 0x00005963 0x000058ea 0x00005871 + 0x000057fa 0x00005783 0x0000570d 0x00005699 0x00005625 0x000055b2 0x0000553f 0x000054ce + 0x0000545d 0x000053ee 0x0000537f 0x00005311 0x000052a4 0x00005238 0x000051cc 0x00005161 + 0x000050f7 0x0000508e 0x00005026 0x00004fbe 0x00004f57 0x00004ef1 0x00004e8c 0x00004e27 + 0x00004dc3 0x00004d60 0x00004cfe 0x00004c9c 0x00004c3b 0x00004bdb 0x00004b7b 0x00004b1c + 0x00004abe 0x00004a60 0x00004a03 0x000049a7 0x0000494b 0x000048f0 0x00004896 0x0000483c + 0x000047e3 0x0000478a 0x00004733 0x000046db 0x00004685 0x0000462f 0x000045d9 0x00004584 + 0x00004530 0x000044dc 0x00004489 0x00004437 0x000043e5 0x00004393 0x00004342 0x000042f2 + 0x000042a2 0x00004253 0x00004204 0x000041b6 0x00004169 0x0000411b 0x000040cf 0x00004083 + 0x00004037 0x00003fec 0x00003fa1 0x00003f57 0x00003f0e 0x00003ec5 0x00003e7c 0x00003e34 + 0x00003dec 0x00003da5 0x00003d5e 0x00003d18 0x00003cd2 0x00003c8c 0x00003c48 0x00003c03 + 0x00003bbf 0x00003b7b 0x00003b38 0x00003af5 0x00003ab3 0x00003a71 0x00003a30 0x000039ef + 0x000039ae 0x0000396e 0x0000392e 0x000038ee 0x000038af 0x00003871 0x00003832 0x000037f5>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-LP097Qx1.dtsi b/include/dt-bindings/display/screen-timing/lcd-LP097Qx1.dtsi new file mode 100644 index 000000000000..9a11edbdd84e --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-LP097Qx1.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RockChip. DisplayPort screen LP097QX1 + * + */ + + +disp_timings: display-timings { + native-mode = <&timing0>; + timing0: timing0 { + screen-type = <SCREEN_EDP>; + out-face = <OUT_P666>; + clock-frequency = <205000000>; + hactive = <2048>; + vactive = <1536>; + hback-porch = <5>; + hfront-porch = <150>; + vback-porch = <9>; + vfront-porch = <3>; + hsync-len = <5>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-LP097Qx2.dtsi b/include/dt-bindings/display/screen-timing/lcd-LP097Qx2.dtsi new file mode 100644 index 000000000000..64f99e8f308f --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-LP097Qx2.dtsi @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * include/dt-bindings/display/screen-timing/lcd-LP097QX2.dtsi + * author: xbl@rock-chips.com + * create date: 2016-05-16 + * screen type: edp + * lcd model: lp097qx2 + * resolution: 1536 * 2048 + */ + +disp_timings: display-timings { + native-mode = <&timing0>; + timing0: timing0 { + screen-type = <SCREEN_EDP>; + out-face = <OUT_P888>; + clock-frequency = <200000000>; + hactive = <1536>; + vactive = <2048>; + hback-porch = <52>; + hfront-porch = <16>; + vback-porch = <3>; + vfront-porch = <7>; + hsync-len = <15>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + cabc-lut = < + /*gamma = 2.2*/ + 0x00000383 0x00000392 0x000003a2 0x000003b2 0x000003c2 0x000003d2 0x000003e2 0x000003f3 + 0x00000403 0x00000414 0x00000425 0x00000436 0x00000447 0x00000458 0x0000046a 0x0000047b + 0x0000048d 0x0000049f 0x000004b1 0x000004c3 0x000004d5 0x000004e8 0x000004fa 0x0000050d + 0x00000520 0x00000533 0x00000546 0x0000055a 0x0000056d 0x00000581 0x00000595 0x000005a9 + 0x000005bd 0x000005d1 0x000005e5 0x000005fa 0x0000060f 0x00000624 0x00000639 0x0000064e + 0x00000663 0x00000679 0x0000068e 0x000006a4 0x000006ba 0x000006d0 0x000006e6 0x000006fd + 0x00000713 0x0000072a 0x00000741 0x00000758 0x0000076f 0x00000786 0x0000079e 0x000007b6 + 0x000007cd 0x000007e5 0x000007fd 0x00000816 0x0000082e 0x00000847 0x0000085f 0x00000878 + 0x00000891 0x000008ab 0x000008c4 0x000008de 0x000008f7 0x00000911 0x0000092b 0x00000945 + 0x00000960 0x0000097a 0x00000995 0x000009af 0x000009ca 0x000009e6 0x00000a01 0x00000a1c + 0x00000a38 0x00000a54 0x00000a6f 0x00000a8c 0x00000aa8 0x00000ac4 0x00000ae1 0x00000afd + 0x00000b1a 0x00000b37 0x00000b54 0x00000b72 0x00000b8f 0x00000bad 0x00000bcb 0x00000be9 + 0x00000c07 0x00000c25 0x00000c44 0x00000c62 0x00000c81 0x00000ca0 0x00000cbf 0x00000cdf + 0x00000cfe 0x00000d1e 0x00000d3e 0x00000d5d 0x00000d7e 0x00000d9e 0x00000dbe 0x00000ddf + 0x00000e00 0x00000e21 0x00000e42 0x00000e63 0x00000e84 0x00000ea6 0x00000ec8 0x00000eea + 0x00000f0c 0x00000f2e 0x00000f50 0x00000f73 0x00000f96 0x00000fb9 0x00000fdc 0x00000fff + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-b080xan03.0-mipi.dtsi b/include/dt-bindings/display/screen-timing/lcd-b080xan03.0-mipi.dtsi new file mode 100644 index 000000000000..2d3010ae3c89 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-b080xan03.0-mipi.dtsi @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2014 ROCKCHIP, Inc. + * Licensed under GPLv2 or later. + * arch/arm/boot/dts/lcd-b080xan03.0-mipi.dtsi + * author: chenyf@rock-chips.com + * create date: 2014-09-11 + * lcd model: b080xan03.0 + * resolution: 768 X 1024 + * mipi channel: single + */ + +/* about mipi */ +disp_mipi_init: mipi_dsi_init{ + compatible = "rockchip,mipi_dsi_init"; + rockchip,screen_init = <0>; + rockchip,dsi_lane = <4>; + rockchip,dsi_hs_clk = <528>; + rockchip,mipi_dsi_num = <1>; +}; +disp_mipi_power_ctr: mipi_power_ctr { + compatible = "rockchip,mipi_power_ctr"; + mipi_lcd_rst:mipi_lcd_rst{ + compatible = "rockchip,lcd_rst"; + rockchip,gpios = <&gpio2 GPIO_C2 GPIO_ACTIVE_HIGH>; + rockchip,delay = <20>; + }; + /* mipi_lcd_en:mipi_lcd_en { + compatible = "rockchip,lcd_en"; + rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>; + rockchip,delay = <100>; + };*/ +}; +disp_mipi_init_cmds: screen-on-cmds { + compatible = "rockchip,screen-on-cmds"; + /*rockchip,cmd_debug = <1>; + rockchip,on-cmds1 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <HSDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0xb0 0x02>; + rockchip,cmd_delay = <0>; + }; + */ +}; + + +disp_timings: display-timings { + native-mode = <&timing0>; + compatible = "rockchip,display-timings"; + timing0: timing0 { + screen-type = <SCREEN_MIPI>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_P666>; + clock-frequency = <67000000>; + hactive = <768>; + vactive = <1024>; + hback-porch = <56>; + hfront-porch = <60>; + vback-porch = <30>; + vfront-porch = <36>; + hsync-len = <64>; + vsync-len = <14>; + + /* + hactive = <1024>; + vactive = <768>; + hback-porch = <56>; + hfront-porch = <60>; + vback-porch = <30>; + vfront-porch = <36>; + hsync-len = <64>; + vsync-len = <14>; + */ + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-b101ew05.dtsi b/include/dt-bindings/display/screen-timing/lcd-b101ew05.dtsi new file mode 100644 index 000000000000..ff15d837e166 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-b101ew05.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RockChip. LCD_B101ew05 + * + */ + + +disp_timings: display-timings { + native-mode = <&timing0>; + timing0: timing0 { + screen-type = <SCREEN_LVDS>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_D888_P666>; + color-mode = <COLOR_RGB>; + clock-frequency = <71000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <100>; + hfront-porch = <18>; + vback-porch = <8>; + vfront-porch = <6>; + hsync-len = <10>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + cabc-lut = < + /*gamma = 2.0*/ + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000002 + 0x00000002 0x00000002 0x00000002 0x00000002 0x00000003 0x00000003 0x00000003 0x00000003 + 0x00000004 0x00000004 0x00000004 0x00000004 0x00000005 0x00000005 0x00000005 0x00000005 + 0x00000006 0x00000006 0x00000006 0x00000007 0x00000007 0x00000007 0x00000008 0x00000008 + 0x00000009 0x00000009 0x00000009 0x0000000a 0x0000000a 0x0000000b 0x0000000b 0x0000000b + 0x0000000c 0x0000000c 0x0000000d 0x0000000d 0x0000000e 0x0000000e 0x0000000f 0x0000000f + 0x00000010 0x00000010 0x00000011 0x00000011 0x00000012 0x00000012 0x00000013 0x00000013 + 0x00000014 0x00000014 0x00000015 0x00000016 0x00000016 0x00000017 0x00000017 0x00000018 + 0x00000019 0x00000019 0x0000001a 0x0000001b 0x0000001b 0x0000001c 0x0000001d 0x0000001d + 0x0000001e 0x0000001f 0x0000001f 0x00000020 0x00000021 0x00000021 0x00000022 0x00000023 + 0x00000024 0x00000024 0x00000025 0x00000026 0x00000027 0x00000028 0x00000028 0x00000029 + 0x0000002a 0x0000002b 0x0000002c 0x0000002c 0x0000002d 0x0000002e 0x0000002f 0x00000030 + 0x00000031 0x00000032 0x00000032 0x00000033 0x00000034 0x00000035 0x00000036 0x00000037 + 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d 0x0000003e 0x0000003f + 0x00000040 0x00000041 0x00000042 0x00000043 0x00000044 0x00000045 0x00000046 0x00000047 + 0x00000048 0x00000049 0x0000004a 0x0000004b 0x0000004c 0x0000004d 0x0000004f 0x00000050 + 0x00000051 0x00000052 0x00000053 0x00000054 0x00000055 0x00000057 0x00000058 0x00000059 + 0x0000005a 0x0000005b 0x0000005d 0x0000005e 0x0000005f 0x00000060 0x00000061 0x00000063 + 0x00000064 0x00000065 0x00000066 0x00000068 0x00000069 0x0000006a 0x0000006c 0x0000006d + 0x0000006e 0x00000070 0x00000071 0x00000072 0x00000074 0x00000075 0x00000076 0x00000078 + 0x00000079 0x0000007a 0x0000007c 0x0000007d 0x0000007f 0x00000080 0x00000081 0x00000083 + 0x00000084 0x00000086 0x00000087 0x00000089 0x0000008a 0x0000008c 0x0000008d 0x0000008f + 0x00000090 0x00000092 0x00000093 0x00000095 0x00000096 0x00000098 0x00000099 0x0000009b + 0x0000009c 0x0000009e 0x000000a0 0x000000a1 0x000000a3 0x000000a4 0x000000a6 0x000000a8 + 0x000000a9 0x000000ab 0x000000ac 0x000000ae 0x000000b0 0x000000b1 0x000000b3 0x000000b5 + 0x000000b6 0x000000b8 0x000000ba 0x000000bc 0x000000bd 0x000000bf 0x000000c1 0x000000c3 + 0x000000c4 0x000000c6 0x000000c8 0x000000ca 0x000000cb 0x000000cd 0x000000cf 0x000000d1 + 0x000000d3 0x000000d4 0x000000d6 0x000000d8 0x000000da 0x000000dc 0x000000de 0x000000e0 + 0x000000e1 0x000000e3 0x000000e5 0x000000e7 0x000000e9 0x000000eb 0x000000ed 0x000000ef + 0x000000f1 0x000000f3 0x000000f5 0x000000f7 0x000000f9 0x000000fb 0x000000fd 0x000000ff>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-box.dtsi b/include/dt-bindings/display/screen-timing/lcd-box.dtsi new file mode 100644 index 000000000000..25368db39d29 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-box.dtsi @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RockChip. LCD_BOX + * + */ + + disp_power_ctr: power_ctr { + /* rockchip,debug = <0>; + lcd_en:lcd_en { + rockchip,power_type = <GPIO>; + gpios = <&gpio0 GPIO_B0 GPIO_ACTIVE_HIGH>; + rockchip,delay = <10>; + }; + + bl_en:bl_en { + rockchip,power_type = <GPIO>; + gpios = <&gpio0 GPIO_A2 GPIO_ACTIVE_HIGH>; + rockchip,delay = <10>; + }; + + bl_ctr:bl_ctr { + rockchip,power_type = <GPIO>; + gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>; + rockchip,delay = <10>; + }; + + lcd_rst:lcd_rst { + rockchip,power_type = <REGULATOR>; + rockchip,delay = <5>; + };*/ + +}; + +disp_timings: display-timings { + native-mode = <&timing0>; + timing0: timing0 { + screen-type = <SCREEN_RGB>; + out-face = <OUT_P888>; + color-mode = <COLOR_YCBCR>; + clock-frequency = <74250000>; + hactive = <1280>; + vactive = <720>; + hback-porch = <220>; + hfront-porch = <110>; + vback-porch = <20>; + vfront-porch = <5>; + hsync-len = <40>; + vsync-len = <5>; + hsync-active = <1>; + vsync-active = <1>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; + timing1: timing1 { + screen-type = <SCREEN_RGB>; + out-face = <OUT_P888>; + color-mode = <COLOR_YCBCR>; + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <148>; + hfront-porch = <88>; + vback-porch = <36>; + vfront-porch = <4>; + hsync-len = <44>; + vsync-len = <5>; + hsync-active = <1>; + vsync-active = <1>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; + timing2: timing2 { + screen-type = <SCREEN_RGB>; + out-face = <OUT_P888>; + color-mode = <COLOR_YCBCR>; + clock-frequency = <297000000>; + hactive = <3840>; + vactive = <2160>; + hback-porch = <296>; + hfront-porch = <176>; + vback-porch = <72>; + vfront-porch = <8>; + hsync-len = <88>; + vsync-len = <10>; + hsync-active = <1>; + vsync-active = <1>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-fpga-800x480-rgb.dtsi b/include/dt-bindings/display/screen-timing/lcd-fpga-800x480-rgb.dtsi new file mode 100644 index 000000000000..798262d3654f --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-fpga-800x480-rgb.dtsi @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +disp_timings: display-timings { + native-mode = <&timing0>; + timing0: timing0 { + screen-type = <SCREEN_RGB>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_D888_P666>; + color-mode = <COLOR_RGB>; + clock-frequency = <71000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <206>; + hfront-porch = <1>; + vback-porch = <25>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + cabc-lut = < + /*gamma = 2.0*/ + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000002 + 0x00000002 0x00000002 0x00000002 0x00000002 0x00000003 0x00000003 0x00000003 0x00000003 + 0x00000004 0x00000004 0x00000004 0x00000004 0x00000005 0x00000005 0x00000005 0x00000005 + 0x00000006 0x00000006 0x00000006 0x00000007 0x00000007 0x00000007 0x00000008 0x00000008 + 0x00000009 0x00000009 0x00000009 0x0000000a 0x0000000a 0x0000000b 0x0000000b 0x0000000b + 0x0000000c 0x0000000c 0x0000000d 0x0000000d 0x0000000e 0x0000000e 0x0000000f 0x0000000f + 0x00000010 0x00000010 0x00000011 0x00000011 0x00000012 0x00000012 0x00000013 0x00000013 + 0x00000014 0x00000014 0x00000015 0x00000016 0x00000016 0x00000017 0x00000017 0x00000018 + 0x00000019 0x00000019 0x0000001a 0x0000001b 0x0000001b 0x0000001c 0x0000001d 0x0000001d + 0x0000001e 0x0000001f 0x0000001f 0x00000020 0x00000021 0x00000021 0x00000022 0x00000023 + 0x00000024 0x00000024 0x00000025 0x00000026 0x00000027 0x00000028 0x00000028 0x00000029 + 0x0000002a 0x0000002b 0x0000002c 0x0000002c 0x0000002d 0x0000002e 0x0000002f 0x00000030 + 0x00000031 0x00000032 0x00000032 0x00000033 0x00000034 0x00000035 0x00000036 0x00000037 + 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d 0x0000003e 0x0000003f + 0x00000040 0x00000041 0x00000042 0x00000043 0x00000044 0x00000045 0x00000046 0x00000047 + 0x00000048 0x00000049 0x0000004a 0x0000004b 0x0000004c 0x0000004d 0x0000004f 0x00000050 + 0x00000051 0x00000052 0x00000053 0x00000054 0x00000055 0x00000057 0x00000058 0x00000059 + 0x0000005a 0x0000005b 0x0000005d 0x0000005e 0x0000005f 0x00000060 0x00000061 0x00000063 + 0x00000064 0x00000065 0x00000066 0x00000068 0x00000069 0x0000006a 0x0000006c 0x0000006d + 0x0000006e 0x00000070 0x00000071 0x00000072 0x00000074 0x00000075 0x00000076 0x00000078 + 0x00000079 0x0000007a 0x0000007c 0x0000007d 0x0000007f 0x00000080 0x00000081 0x00000083 + 0x00000084 0x00000086 0x00000087 0x00000089 0x0000008a 0x0000008c 0x0000008d 0x0000008f + 0x00000090 0x00000092 0x00000093 0x00000095 0x00000096 0x00000098 0x00000099 0x0000009b + 0x0000009c 0x0000009e 0x000000a0 0x000000a1 0x000000a3 0x000000a4 0x000000a6 0x000000a8 + 0x000000a9 0x000000ab 0x000000ac 0x000000ae 0x000000b0 0x000000b1 0x000000b3 0x000000b5 + 0x000000b6 0x000000b8 0x000000ba 0x000000bc 0x000000bd 0x000000bf 0x000000c1 0x000000c3 + 0x000000c4 0x000000c6 0x000000c8 0x000000ca 0x000000cb 0x000000cd 0x000000cf 0x000000d1 + 0x000000d3 0x000000d4 0x000000d6 0x000000d8 0x000000da 0x000000dc 0x000000de 0x000000e0 + 0x000000e1 0x000000e3 0x000000e5 0x000000e7 0x000000e9 0x000000eb 0x000000ed 0x000000ef + 0x000000f1 0x000000f3 0x000000f5 0x000000f7 0x000000f9 0x000000fb 0x000000fd 0x000000ff>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-h381dln01-1080x1200-double.dtsi b/include/dt-bindings/display/screen-timing/lcd-h381dln01-1080x1200-double.dtsi new file mode 100644 index 000000000000..6fe841cdf720 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-h381dln01-1080x1200-double.dtsi @@ -0,0 +1,317 @@ +/* + * + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * author: xubilv <xbl@rock-chips.com> + * create date: 2016-08-11 + * resolution: 1080 X 1200 + * mipi channel: double + */ + +/* about mipi */ +disp_mipi_init: mipi_dsi_init { + compatible = "rockchip,mipi_dsi_init"; + rockchip,screen_init = <1>; + rockchip,dsi_lane = <4>; + rockchip,dsi_hs_clk = <970>; + rockchip,mipi_dsi_num = <2>; +}; + +disp_mipi_power_ctr: mipi_power_ctr { + compatible = "rockchip,mipi_power_ctr"; + + /*mipi_lcd_rst:mipi_lcd_rst { + compatible = "rockchip,lcd_rst"; + rockchip,gpios = <&gpio7 GPIO_A1 GPIO_ACTIVE_LOW>; + rockchip,delay = <0>; + }; + + mipi_lcd_avdd:mipi_lcd_avdd { + compatible = "rockchip,lcd_avdd"; + rockchip,gpios = <&gpio7 GPIO_A2 GPIO_ACTIVE_HIGH>; + rockchip,delay = <0>; + }; + + mipi_lcd_ovdd:mipi_lcd_ovdd { + compatible = "rockchip,lcd_ovdd"; + rockchip,gpios = <&gpio7 GPIO_A3 GPIO_ACTIVE_HIGH>; + rockchip,delay = <0>; + }; + + mipi_lcd_ovss:mipi_lcd_ovss { + compatible = "rockchip,lcd_ovss"; + rockchip,gpios = <&gpio7 GPIO_B0 GPIO_ACTIVE_HIGH>; + rockchip,delay = <0>; + }; + mipi_lcd_rst:mipi_lcd_rst{ + compatible = "rockchip,lcd_rst"; + rockchip,gpios = <&gpio7 GPIO_A1 GPIO_ACTIVE_LOW>; + rockchip,delay = <100>; + }; + mipi_lcd_en:mipi_lcd_en { + compatible = "rockchip,lcd_en"; + rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>; + rockchip,delay = <100>; + };*/ +}; + +disp_mipi_init_cmds: screen-on-cmds { + compatible = "rockchip,screen-on-cmds"; + rockchip,cmd_debug = <0>; + rockchip,on-cmds1 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xFE 0x07>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds2 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x00 0xEC>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds3 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x0B 0xEC>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds4 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x16 0xEC>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds5 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x21 0xEC>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds6 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x2D 0xEC>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds7 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xA9 0xBA>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds8 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xAB 0x06>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds9 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xBB 0x84>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds10 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xBC 0x1C>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds11 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xFE 0x08>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds12 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x07 0x1A>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds13 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xFE 0x0A>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds14 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x2A 0x1B>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds15 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xFE 0x0D>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds16 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x02 0x65>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds17 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x4D 0x41>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds18 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x4B 0x0F>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds19 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x53 0xFE>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds20 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xFE 0x00>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds21 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xC2 0x03>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds22 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x51 0xFF>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds23 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x05 0x11>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds24 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x05 0x29>; + rockchip,cmd_delay = <10>; + }; +}; + +disp_timings: display-timings { + native-mode = <&timing0>; + compatible = "rockchip,display-timings"; + timing0: timing0 { + screen-type = <SCREEN_DUAL_MIPI>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_P888>; + clock-frequency = <231795000>; /* 185436000 60fps, 231795000 75fps, 278154000 90fps */ + hactive = <2160>; //1080 + vactive = <1200>; + hback-porch = <180>; + hfront-porch = <200>; + vback-porch = <3>; + vfront-porch = <6>; + hsync-len = <10>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + screen-width = <130>; + screen-hight = <72>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-h381dln01-1080x1200.dtsi b/include/dt-bindings/display/screen-timing/lcd-h381dln01-1080x1200.dtsi new file mode 100644 index 000000000000..994809469890 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-h381dln01-1080x1200.dtsi @@ -0,0 +1,314 @@ +/* + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * author: xubilv <xbl@rock-chips.com> + * create date: 2016-08-11 + * resolution: 1080 X 1200 + * mipi channel: single + */ + +disp_mipi_init: mipi_dsi_init { + compatible = "rockchip,mipi_dsi_init"; + rockchip,screen_init = <1>; + rockchip,dsi_lane = <4>; + rockchip,dsi_hs_clk = <970>; + rockchip,mipi_dsi_num = <1>; +}; + +disp_mipi_power_ctr: mipi_power_ctr { + compatible = "rockchip,mipi_power_ctr"; + + /*mipi_lcd_rst:mipi_lcd_rst { + compatible = "rockchip,lcd_rst"; + rockchip,gpios = <&gpio7 GPIO_A1 GPIO_ACTIVE_LOW>; + rockchip,delay = <0>; + }; + + mipi_lcd_avdd:mipi_lcd_avdd { + compatible = "rockchip,lcd_avdd"; + rockchip,gpios = <&gpio7 GPIO_A2 GPIO_ACTIVE_HIGH>; + rockchip,delay = <0>; + }; + + mipi_lcd_ovdd:mipi_lcd_ovdd { + compatible = "rockchip,lcd_ovdd"; + rockchip,gpios = <&gpio7 GPIO_A3 GPIO_ACTIVE_HIGH>; + rockchip,delay = <0>; + }; + + mipi_lcd_ovss:mipi_lcd_ovss { + compatible = "rockchip,lcd_ovss"; + rockchip,gpios = <&gpio7 GPIO_B0 GPIO_ACTIVE_HIGH>; + rockchip,delay = <0>; + }; + + mipi_lcd_rst:mipi_lcd_rst { + compatible = "rockchip,lcd_rst"; + rockchip,gpios = <&gpio7 GPIO_A1 GPIO_ACTIVE_LOW>; + rockchip,delay = <100>; + }; + + mipi_lcd_en:mipi_lcd_en { + compatible = "rockchip,lcd_en"; + rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>; + rockchip,delay = <100>; + };*/ +}; + +disp_mipi_init_cmds: screen-on-cmds { + compatible = "rockchip,screen-on-cmds"; + rockchip,cmd_debug = <0>; + rockchip,on-cmds1 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0xFE 0x07>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds2 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x00 0xEC>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds3 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x0B 0xEC>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds4 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x16 0xEC>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds5 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x21 0xEC>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds6 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x2D 0xEC>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds7 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0xA9 0xBA>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds8 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0xAB 0x06>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds9 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0xBB 0x84>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds10 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0xBC 0x1C>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds11 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0xFE 0x08>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds12 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x07 0x1A>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds13 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0xFE 0x0A>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds14 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x2A 0x1B>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds15 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0xFE 0x0D>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds16 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x02 0x65>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds17 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x4D 0x41>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds18 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x4B 0x0F>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds19 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x53 0xFE>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds20 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0xFE 0x00>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds21 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0xC2 0x03>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds22 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x51 0xFF>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds23 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x05 0x11>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds24 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x05 0x29>; + rockchip,cmd_delay = <10>; + }; +}; + +disp_timings: display-timings { + native-mode = <&timing0>; + compatible = "rockchip,display-timings"; + timing0: timing0 { + screen-type = <SCREEN_MIPI>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_P888>; + clock-frequency = <139000000>;//139 + hactive = <1080>; + vactive = <1200>; + hback-porch = <90>; + hfront-porch = <100>; + vback-porch = <3>; + vfront-porch = <6>; + hsync-len = <5>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-h546dlb01-mipi.dtsi b/include/dt-bindings/display/screen-timing/lcd-h546dlb01-mipi.dtsi new file mode 100644 index 000000000000..19d427c71e5f --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-h546dlb01-mipi.dtsi @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * include/dt-bindings/display/screen-timing/lcd-h546dlb01-mipi.dtsi + * author: bivvy.bi@rock-chips.com + * create date: 2016-09-02 + * lcd Model: AUO h546dlb01 + * resolution: 1080 X 1920 + * mipi channel: single + */ + +disp_mipi_init: mipi_dsi_init { + compatible = "rockchip,mipi_dsi_init"; + rockchip,screen_init = <1>; + rockchip,dsi_lane = <4>; + rockchip,dsi_hs_clk = <1050>; + rockchip,mipi_dsi_num = <1>; +}; + +disp_mipi_power_ctr: mipi_power_ctr { + compatible = "rockchip,mipi_power_ctr"; +}; + +disp_mipi_init_cmds: screen-on-cmds { + compatible = "rockchip,screen-on-cmds"; + rockchip,cmd_debug = <1>; + + rockchip,on-cmds1 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x23 0xFE 0x08>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds2 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x23 0x03 0x40>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds3 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x23 0x07 0x1a>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds4 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x23 0xfe 0x0d>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds5 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x23 0x53 0xfe>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds6 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x23 0xfe 0x00>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds7 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x23 0x51 0xff>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds8 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x23 0xc2 0x03>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds9 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x05 dcs_exit_sleep_mode>; + rockchip,cmd_delay = <120>; + }; + + rockchip,on-cmds10 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x05 dcs_set_display_on>; + rockchip,cmd_delay = <0>; + }; +}; + +disp_timings: display-timings { + native-mode = <&timing0>; + compatible = "rockchip,display-timings"; + + timing0: timing0 { + screen-type = <SCREEN_MIPI>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_P888>; + clock-frequency = <153000000>; + hactive = <1080>; + vactive = <1920>; + hback-porch = <24>; + hfront-porch = <8>; + vback-porch = <7>; + vfront-porch = <12>; + hsync-len = <5>; + vsync-len = <5>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + screen-width = <68>; + screen-hight = <120>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-ld089wu1-mipi.dtsi b/include/dt-bindings/display/screen-timing/lcd-ld089wu1-mipi.dtsi new file mode 100644 index 000000000000..a20e51a37d69 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-ld089wu1-mipi.dtsi @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2014 ROCKCHIP, Inc. + * arch/arm/boot/dts/lcd-lq070m1sx01-mipi.dtsi + * author: libing@rock-chips.com + * create date: 2014-04-15 + * lcd model: ld089wu1 + * resolution: 1920 X 1200 + * mipi channel: single + */ + +/* about mipi */ +disp_mipi_init: mipi_dsi_init{ + compatible = "rockchip,mipi_dsi_init"; + rockchip,screen_init = <0>; + rockchip,dsi_lane = <4>; + rockchip,dsi_hs_clk = <1000>; + rockchip,mipi_dsi_num = <1>; +}; +disp_mipi_power_ctr: mipi_power_ctr { + compatible = "rockchip,mipi_power_ctr"; + /*mipi_lcd_rst:mipi_lcd_rst{ + compatible = "rockchip,lcd_rst"; + rockchip,gpios = <&gpio2 GPIO_B7 GPIO_ACTIVE_LOW>; + rockchip,delay = <100>; + }; + mipi_lcd_en:mipi_lcd_en { + compatible = "rockchip,lcd_en"; + rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>; + rockchip,delay = <100>; + };*/ +}; +disp_mipi_init_cmds: screen-on-cmds { + compatible = "rockchip,screen-on-cmds"; + /*rockchip,cmd_debug = <1>; + rockchip,on-cmds1 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <HSDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0xb0 0x02>; + rockchip,cmd_delay = <0>; + }; + */ +}; + + +disp_timings: display-timings { + native-mode = <&timing0>; + compatible = "rockchip,display-timings"; + timing0: timing0 { + screen-type = <SCREEN_MIPI>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_P888>; + clock-frequency = <145000000>; + hactive = <1920>; + vactive = <1200>; + hback-porch = <16>; + hfront-porch = <24>; + vback-porch = <10>; + vfront-porch = <16>; + hsync-len = <10>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + cabc-lut = < + /*gamma = 2.2*/ + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000001 + 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 + 0x00000001 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 + 0x00000003 0x00000003 0x00000003 0x00000003 0x00000003 0x00000004 0x00000004 0x00000004 + 0x00000004 0x00000005 0x00000005 0x00000005 0x00000005 0x00000006 0x00000006 0x00000006 + 0x00000006 0x00000007 0x00000007 0x00000007 0x00000008 0x00000008 0x00000008 0x00000009 + 0x00000009 0x00000009 0x0000000a 0x0000000a 0x0000000b 0x0000000b 0x0000000b 0x0000000c + 0x0000000c 0x0000000d 0x0000000d 0x0000000d 0x0000000e 0x0000000e 0x0000000f 0x0000000f + 0x00000010 0x00000010 0x00000011 0x00000011 0x00000012 0x00000012 0x00000013 0x00000013 + 0x00000014 0x00000014 0x00000015 0x00000016 0x00000016 0x00000017 0x00000017 0x00000018 + 0x00000019 0x00000019 0x0000001a 0x0000001a 0x0000001b 0x0000001c 0x0000001c 0x0000001d + 0x0000001e 0x0000001e 0x0000001f 0x00000020 0x00000021 0x00000021 0x00000022 0x00000023 + 0x00000023 0x00000024 0x00000025 0x00000026 0x00000027 0x00000027 0x00000028 0x00000029 + 0x0000002a 0x0000002b 0x0000002b 0x0000002c 0x0000002d 0x0000002e 0x0000002f 0x00000030 + 0x00000031 0x00000031 0x00000032 0x00000033 0x00000034 0x00000035 0x00000036 0x00000037 + 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d 0x0000003e 0x0000003f + 0x00000040 0x00000041 0x00000042 0x00000043 0x00000044 0x00000045 0x00000046 0x00000047 + 0x00000049 0x0000004a 0x0000004b 0x0000004c 0x0000004d 0x0000004e 0x0000004f 0x00000051 + 0x00000052 0x00000053 0x00000054 0x00000055 0x00000057 0x00000058 0x00000059 0x0000005a + 0x0000005b 0x0000005d 0x0000005e 0x0000005f 0x00000061 0x00000062 0x00000063 0x00000064 + 0x00000066 0x00000067 0x00000069 0x0000006a 0x0000006b 0x0000006d 0x0000006e 0x0000006f + 0x00000071 0x00000072 0x00000074 0x00000075 0x00000077 0x00000078 0x00000079 0x0000007b + 0x0000007c 0x0000007e 0x0000007f 0x00000081 0x00000082 0x00000084 0x00000085 0x00000087 + 0x00000089 0x0000008a 0x0000008c 0x0000008d 0x0000008f 0x00000091 0x00000092 0x00000094 + 0x00000095 0x00000097 0x00000099 0x0000009a 0x0000009c 0x0000009e 0x0000009f 0x000000a1 + 0x000000a3 0x000000a5 0x000000a6 0x000000a8 0x000000aa 0x000000ac 0x000000ad 0x000000af + 0x000000b1 0x000000b3 0x000000b5 0x000000b6 0x000000b8 0x000000ba 0x000000bc 0x000000be + 0x000000c0 0x000000c2 0x000000c4 0x000000c5 0x000000c7 0x000000c9 0x000000cb 0x000000cd + 0x000000cf 0x000000d1 0x000000d3 0x000000d5 0x000000d7 0x000000d9 0x000000db 0x000000dd + 0x000000df 0x000000e1 0x000000e3 0x000000e5 0x000000e7 0x000000ea 0x000000ec 0x000000ee + 0x000000f0 0x000000f2 0x000000f4 0x000000f6 0x000000f8 0x000000fb 0x000000fd 0x000000ff>; + cabc-gamma-base = < + /*gamma = 2.2*/ + 0x00010000 0x0000fdd0 0x0000fba8 0x0000f986 0x0000f76a 0x0000f556 0x0000f347 0x0000f140 + 0x0000ef3e 0x0000ed43 0x0000eb4e 0x0000e95e 0x0000e775 0x0000e592 0x0000e3b4 0x0000e1dc + 0x0000e009 0x0000de3c 0x0000dc74 0x0000dab2 0x0000d8f4 0x0000d73c 0x0000d589 0x0000d3db + 0x0000d232 0x0000d08d 0x0000ceee 0x0000cd53 0x0000cbbc 0x0000ca2b 0x0000c89d 0x0000c714 + 0x0000c590 0x0000c410 0x0000c294 0x0000c11c 0x0000bfa8 0x0000be39 0x0000bccd 0x0000bb65 + 0x0000ba01 0x0000b8a1 0x0000b745 0x0000b5ed 0x0000b498 0x0000b347 0x0000b1f9 0x0000b0af + 0x0000af68 0x0000ae25 0x0000ace5 0x0000aba8 0x0000aa6f 0x0000a939 0x0000a806 0x0000a6d7 + 0x0000a5aa 0x0000a480 0x0000a35a 0x0000a236 0x0000a116 0x00009ff8 0x00009edd 0x00009dc5 + 0x00009cb0 0x00009b9e 0x00009a8e 0x00009981 0x00009877 0x0000976f 0x0000966a 0x00009567 + 0x00009467 0x0000936a 0x0000926f 0x00009176 0x00009080 0x00008f8c 0x00008e9a 0x00008dab + 0x00008cbe 0x00008bd3 0x00008aea 0x00008a04 0x00008920 0x0000883e 0x0000875e 0x00008680 + 0x000085a4 0x000084ca 0x000083f3 0x0000831d 0x00008249 0x00008177 0x000080a7 0x00007fd9 + 0x00007f0d 0x00007e42 0x00007d7a 0x00007cb3 0x00007bee 0x00007b2b 0x00007a6a 0x000079aa + 0x000078ec 0x0000782f 0x00007775 0x000076bc 0x00007604 0x0000754f 0x0000749a 0x000073e8 + 0x00007337 0x00007287 0x000071d9 0x0000712c 0x00007081 0x00006fd8 0x00006f30 0x00006e89 + 0x00006de4 0x00006d40 0x00006c9d 0x00006bfc 0x00006b5c 0x00006abe 0x00006a21 0x00006985 + 0x000068ea 0x00006851 0x000067b9 0x00006722 0x0000668d 0x000065f9 0x00006566 0x000064d4 + 0x00006443 0x000063b4 0x00006325 0x00006298 0x0000620c 0x00006181 0x000060f8 0x0000606f + 0x00005fe7 0x00005f61 0x00005edb 0x00005e57 0x00005dd4 0x00005d51 0x00005cd0 0x00005c50 + 0x00005bd1 0x00005b52 0x00005ad5 0x00005a59 0x000059de 0x00005963 0x000058ea 0x00005871 + 0x000057fa 0x00005783 0x0000570d 0x00005699 0x00005625 0x000055b2 0x0000553f 0x000054ce + 0x0000545d 0x000053ee 0x0000537f 0x00005311 0x000052a4 0x00005238 0x000051cc 0x00005161 + 0x000050f7 0x0000508e 0x00005026 0x00004fbe 0x00004f57 0x00004ef1 0x00004e8c 0x00004e27 + 0x00004dc3 0x00004d60 0x00004cfe 0x00004c9c 0x00004c3b 0x00004bdb 0x00004b7b 0x00004b1c + 0x00004abe 0x00004a60 0x00004a03 0x000049a7 0x0000494b 0x000048f0 0x00004896 0x0000483c + 0x000047e3 0x0000478a 0x00004733 0x000046db 0x00004685 0x0000462f 0x000045d9 0x00004584 + 0x00004530 0x000044dc 0x00004489 0x00004437 0x000043e5 0x00004393 0x00004342 0x000042f2 + 0x000042a2 0x00004253 0x00004204 0x000041b6 0x00004169 0x0000411b 0x000040cf 0x00004083 + 0x00004037 0x00003fec 0x00003fa1 0x00003f57 0x00003f0e 0x00003ec5 0x00003e7c 0x00003e34 + 0x00003dec 0x00003da5 0x00003d5e 0x00003d18 0x00003cd2 0x00003c8c 0x00003c48 0x00003c03 + 0x00003bbf 0x00003b7b 0x00003b38 0x00003af5 0x00003ab3 0x00003a71 0x00003a30 0x000039ef + 0x000039ae 0x0000396e 0x0000392e 0x000038ee 0x000038af 0x00003871 0x00003832 0x000037f5>; + }; + }; diff --git a/include/dt-bindings/display/screen-timing/lcd-lq070m1sx01-mipi.dtsi b/include/dt-bindings/display/screen-timing/lcd-lq070m1sx01-mipi.dtsi new file mode 100644 index 000000000000..5f83e3b0d407 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-lq070m1sx01-mipi.dtsi @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2014 ROCKCHIP, Inc. + * arch/arm/boot/dts/lcd-lq070m1sx01-mipi.dtsi + * author: libing@rock-chips.com + * create date: 2014-04-15 + * lcd model: lq070m1sx01 + * resolution: 1920 X 1200 + * mipi channel: dual + */ + +/* about mipi */ +disp_mipi_init: mipi_dsi_init{ + compatible = "rockchip,mipi_dsi_init"; + rockchip,screen_init = <1>; + rockchip,dsi_lane = <2>; + rockchip,dsi_hs_clk = <1000>; + rockchip,mipi_dsi_num = <2>; +}; +disp_mipi_power_ctr: mipi_power_ctr { + compatible = "rockchip,mipi_power_ctr"; + mipi_lcd_rst:mipi_lcd_rst{ + compatible = "rockchip,lcd_rst"; + rockchip,gpios = <&gpio2 GPIO_B7 GPIO_ACTIVE_HIGH>; + rockchip,delay = <10>; + }; + mipi_lcd_en:mipi_lcd_en { + compatible = "rockchip,lcd_en"; + rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>; + rockchip,delay = <10>; + }; +}; +disp_mipi_init_cmds: screen-on-cmds { + rockchip,cmd_debug = <0>; + compatible = "rockchip,screen-on-cmds"; + rockchip,on-cmds1 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xb0 0x02>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds2 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xb1 0x21>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds3 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xb0 0x06>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds4 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xb1 0x21>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds5 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xb4 0x15>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds6 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xb9 0x40>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds7 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xb0 0x00>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds8 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x05 dcs_set_display_on>; + rockchip,cmd_delay = <10>; + }; + rockchip,on-cmds9 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,data_type = <DATA_TYPE_DCS>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x05 dcs_exit_sleep_mode>; + rockchip,cmd_delay = <10>; + }; +}; + +disp_timings: display-timings { + native-mode = <&timing0>; + compatible = "rockchip,display-timings"; + timing0: timing0 { + screen-type = <SCREEN_DUAL_MIPI>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_P888>; + clock-frequency = <150000000>; + hactive = <1200>; + vactive = <1920>; + hsync-len = <8>; + hback-porch = <32>; + hfront-porch = <156>; + + vsync-len = <2>; + vback-porch = <6>; + vfront-porch = <12>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-ls055r1sx04-mipi.dtsi b/include/dt-bindings/display/screen-timing/lcd-ls055r1sx04-mipi.dtsi new file mode 100644 index 000000000000..7e93e7e1c300 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-ls055r1sx04-mipi.dtsi @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * include/dt-bindings/display/screen-timing/lcd-ls055r1sx04-mipi.dtsi + * author: xbl@rock-chips.com + * create date: 2016-05-16 + * lcd model: sharp ls055r1sx04 + * resolution: 1440 * 2560 + * mipi channel: double + */ + +/* about mipi */ +disp_mipi_init: mipi_dsi_init{ + compatible = "rockchip,mipi_dsi_init"; + rockchip,screen_init = <1>; + rockchip,dsi_lane = <4>; + rockchip,dsi_hs_clk = <850>; + rockchip,mipi_dsi_num = <2>; +}; + +disp_mipi_power_ctr: mipi_power_ctr { + compatible = "rockchip,mipi_power_ctr"; + /* mipi_lcd_rst:mipi_lcd_rst{ + compatible = "rockchip,lcd_rst"; + rockchip,gpios = <&gpio2 GPIO_B7 GPIO_ACTIVE_LOW>; + rockchip,delay = <100>; + }; + mipi_lcd_en:mipi_lcd_en { + compatible = "rockchip,lcd_en"; + rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>; + rockchip,delay = <100>; + }; + */ +}; + +disp_mipi_init_cmds: screen-on-cmds { + compatible = "rockchip,screen-on-cmds"; + rockchip,cmd_debug = <1>; + rockchip,on-cmds1 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xb0 0x00>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds2 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xd6 0x01>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds3 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xb3 0x18>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds4 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x39 0x51 0xff>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds5 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x39 0x53 0x0c>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds6 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x39 0x35 0x00>; + rockchip,cmd_delay = <0>; + }; +/* + rockchip,on-cmds7 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xb0 0x03>; + rockchip,cmd_delay = <0>; + }; +*/ + rockchip,on-cmds7 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x05 dcs_set_display_on>; + rockchip,cmd_delay = <10>; + }; + rockchip,on-cmds8 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x05 dcs_exit_sleep_mode>; + rockchip,cmd_delay = <10>; + }; +}; + +disp_timings: display-timings { + native-mode = <&timing0>; + compatible = "rockchip,display-timings"; + timing0: timing0 { + screen-type = <SCREEN_DUAL_MIPI>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_P888>; + clock-frequency = <245000000>; + hactive = <1440>; + vactive = <2560>; + hback-porch = <40>; + hfront-porch = <100>; + vback-porch = <3>; + vfront-porch = <4>; + hsync-len = <6>; + vsync-len = <1>; + screen-width = <68>; + screen-hight = <120>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-mipi-RK055AUWI5003-1440X2560.dtsi b/include/dt-bindings/display/screen-timing/lcd-mipi-RK055AUWI5003-1440X2560.dtsi new file mode 100644 index 000000000000..5d021df56366 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-mipi-RK055AUWI5003-1440X2560.dtsi @@ -0,0 +1,288 @@ +/* + * + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * author: lyx@rock-chips.com + * create date: 2016-04-05 + * resolution: 1440 X 2560 + * mipi channel: single + */ + +/* about mipi */ +disp_mipi_init: mipi_dsi_init{ + compatible = "rockchip,mipi_dsi_init"; + rockchip,screen_init = <1>; + rockchip,dsi_lane = <4>; + rockchip,dsi_hs_clk = <1000>; + rockchip,mipi_dsi_num = <2>; +}; + +disp_mipi_power_ctr: mipi_power_ctr { + compatible = "rockchip,mipi_power_ctr"; + /* + mipi_lcd_rst:mipi_lcd_rst { + compatible = "rockchip,lcd_rst"; + rockchip,gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; + rockchip,delay = <100>; + }; + + mipi_lcd_en:mipi_lcd_en { + compatible = "rockchip,lcd_en"; + rockchip,gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + rockchip,delay = <20>; + }; + */ +}; + +disp_mipi_init_cmds: screen-on-cmds { + rockchip,cmd_debug = <0>; + compatible = "rockchip,screen-on-cmds"; + rockchip,on-cmds1 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x23 0xb0 0x00>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds2 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x23 0xd6 0x01>; + rockchip,cmd_delay = <120>; + }; + + rockchip,on-cmds3 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xb3 0x18 0x00 0x00>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds4 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x23 0xb4 0x00>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds5 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xb6 0x3a 0xd3>; + rockchip,cmd_delay = <20>; + }; + + rockchip,on-cmds6 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x23 0xbe 0x04>; + rockchip,cmd_delay = <120>; + }; + + rockchip,on-cmds7 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xc3 0x00 0x00 0x00>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds8 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x23 0xc5 0x00>; + rockchip,cmd_delay = <20>; + }; + + rockchip,on-cmds9 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xc0 0x00 0x00 0x00 0x00>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds10 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xc1 0x00 0x61 0x00 0x30 0x29 0x10 0x19 0x63 0x61 0xb4 0xe6 0xdc 0x7b 0xef 0x39 0xd7 0xda 0x08 0x8c 0xb1 0x08 0x54 0x82 0x00 0x00 0x00 0x00 0x00 0x02 0x63 0x27 0x03 0x00 0xff 0x11>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds11 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xc2 0x08 0x0a 0x00 0x04 0x04 0xf0 0x00 0x04>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds12 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xc4 0x70 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x05 0x01>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds13 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xc6 0x5a 0x00 0x2d 0x03 0x01 0x02 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x06 0x15 0x08 0x5a>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds14 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xcb 0xff 0xff 0xff 0xff 0x00 0x00 0x00 0x00 0x54 0xe0 0x07 0x2a 0xe0 0x00 0x00>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds15 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x23 0xcc 0x32>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds16 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xd7 0x82 0xff 0x21 0x8e 0x8c 0xf1 0x87 0x3f 0x7e 0x10 0x00 0x00 0x8f>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds17 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xd9 0x00 0x00>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds18 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xd0 0x11 0x17 0x14 0xfd>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds19 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xd2 0xcd 0x2b 0x2b 0x33 0x12 0x33 0x33 0x33 0x77 0x77 0x33 0x33 0x33 0x00 0x00 0x00>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds20 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xd5 0x06 0x00 0x00 0x01 0x40 0x01 0x40>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds21 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xc7 0x00 0x10 0x17 0x21 0x2f 0x3d 0x48 0x58 0x3c 0x44 0x50 0x5d 0x66 0x6c 0x75 0x00 0x10 0x17 0x21 0x2f 0x3d 0x48 0x58 0x3c 0x44 0x50 0x5d 0x66 0x6c 0x75>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds22 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x05 0x29>; + rockchip,cmd_delay = <120>; + }; + + rockchip,on-cmds23 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x05 0x11>; + rockchip,cmd_delay = <100>; + }; +}; + +disp_timings: display-timings { + native-mode = <&timing0>; + compatible = "rockchip,display-timings"; + timing0: timing0 { + screen-type = <SCREEN_DUAL_MIPI>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_P888>; + clock-frequency = <245000000>; + hactive = <1440>; + vactive = <2560>; + hback-porch = <16>; + hfront-porch = <50>; + vback-porch = <20>; + vfront-porch = <20>; + hsync-len = <20>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + screen-width = <68>; + screen-hight = <120>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-rk3128-86v-LVDS1024x600.dtsi b/include/dt-bindings/display/screen-timing/lcd-rk3128-86v-LVDS1024x600.dtsi new file mode 100644 index 000000000000..c4cbc6d9c058 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-rk3128-86v-LVDS1024x600.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RockChip. LCD_LVDS1024x600 FOR rk3128-86V + * + */ + + +disp_timings: display-timings { + native-mode = <&timing0>; + timing0: timing0 { + screen-type = <SCREEN_LVDS>; + lvds-format = <LVDS_8BIT_1>; + out-face = <OUT_P888>; + /* Min Typ Max Unit + * Clock Frequency fclk 44.9 51.2 63 MHz + */ + clock-frequency = <60000000>; + hactive = <1024>; /* Horizontal display area thd 1024 DCLK */ + vactive = <600>; /* Vertical display area tvd 600 H */ + hback-porch = <90>; /* HS Width +Back Porch 160 160 160 DCLK (Thw+ thbp)*/ + hfront-porch = <160>; /* HS front porch thfp 16 160 216 DCLK */ + vback-porch = <13>; /* VS front porch tvfp 1 12 127 H */ + vfront-porch = <12>; /* VS Width+Back Porch 23 23 23 H (Tvw+ tvbp) */ + hsync-len = <70>; /* HS Pulse Width thw 1 - 140 DCLK */ + vsync-len = <10>; /* VS Pulse Width tvw 1 - 20 H */ + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-td043mgeal.dtsi b/include/dt-bindings/display/screen-timing/lcd-td043mgeal.dtsi new file mode 100644 index 000000000000..32583775b084 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-td043mgeal.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RockChip. LCD_TD043MGEA1 FOR FPGA + * + */ + + +disp_timings: display-timings { + native-mode = <&timing0>; + timing0: timing0 { + screen-type = <SCREEN_RGB>; + out-face = <OUT_P888>; + clock-frequency = <27000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <206>; + hfront-porch = <40>; + vback-porch = <25>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-tv080wum-mipi.dtsi b/include/dt-bindings/display/screen-timing/lcd-tv080wum-mipi.dtsi new file mode 100644 index 000000000000..2bf4ef99b506 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-tv080wum-mipi.dtsi @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2014 ROCKCHIP, Inc. + * arch/arm/boot/dts/lcd-lq070m1sx01-mipi.dtsi + * author: libing@rock-chips.com + * create date: 2014-04-15 + * lcd model: ld089wu1 + * resolution: 1920 X 1200 + * mipi channel: single + */ + +/* about mipi */ +disp_mipi_init: mipi_dsi_init{ + compatible = "rockchip,mipi_dsi_init"; + rockchip,screen_init = <0>; + rockchip,dsi_lane = <4>; + rockchip,dsi_hs_clk = <1000>; + rockchip,mipi_dsi_num = <1>; +}; +disp_mipi_power_ctr: mipi_power_ctr { + compatible = "rockchip,mipi_power_ctr"; + /*mipi_lcd_rst:mipi_lcd_rst{ + compatible = "rockchip,lcd_rst"; + rockchip,gpios = <&gpio2 GPIO_B7 GPIO_ACTIVE_LOW>; + rockchip,delay = <100>; + }; + mipi_lcd_en:mipi_lcd_en { + compatible = "rockchip,lcd_en"; + rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>; + rockchip,delay = <100>; + };*/ +}; +disp_mipi_init_cmds: screen-on-cmds { + compatible = "rockchip,screen-on-cmds"; + /*rockchip,cmd_debug = <1>; + rockchip,on-cmds1 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <HSDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0xb0 0x02>; + rockchip,cmd_delay = <0>; + }; + */ +}; + + +disp_timings: display-timings { + native-mode = <&timing0>; + compatible = "rockchip,display-timings"; + timing0: timing0 { + screen-type = <SCREEN_MIPI>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_P888>; + clock-frequency = <150000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <80>; + hfront-porch = <81>; + vback-porch = <21>; + vfront-porch = <21>; + hsync-len = <10>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + cabc-lut = < + /*gamma = 2.2*/ + 0x00000383 0x00000392 0x000003a2 0x000003b2 0x000003c2 0x000003d2 0x000003e2 0x000003f3 + 0x00000403 0x00000414 0x00000425 0x00000436 0x00000447 0x00000458 0x0000046a 0x0000047b + 0x0000048d 0x0000049f 0x000004b1 0x000004c3 0x000004d5 0x000004e8 0x000004fa 0x0000050d + 0x00000520 0x00000533 0x00000546 0x0000055a 0x0000056d 0x00000581 0x00000595 0x000005a9 + 0x000005bd 0x000005d1 0x000005e5 0x000005fa 0x0000060f 0x00000624 0x00000639 0x0000064e + 0x00000663 0x00000679 0x0000068e 0x000006a4 0x000006ba 0x000006d0 0x000006e6 0x000006fd + 0x00000713 0x0000072a 0x00000741 0x00000758 0x0000076f 0x00000786 0x0000079e 0x000007b6 + 0x000007cd 0x000007e5 0x000007fd 0x00000816 0x0000082e 0x00000847 0x0000085f 0x00000878 + 0x00000891 0x000008ab 0x000008c4 0x000008de 0x000008f7 0x00000911 0x0000092b 0x00000945 + 0x00000960 0x0000097a 0x00000995 0x000009af 0x000009ca 0x000009e6 0x00000a01 0x00000a1c + 0x00000a38 0x00000a54 0x00000a6f 0x00000a8c 0x00000aa8 0x00000ac4 0x00000ae1 0x00000afd + 0x00000b1a 0x00000b37 0x00000b54 0x00000b72 0x00000b8f 0x00000bad 0x00000bcb 0x00000be9 + 0x00000c07 0x00000c25 0x00000c44 0x00000c62 0x00000c81 0x00000ca0 0x00000cbf 0x00000cdf + 0x00000cfe 0x00000d1e 0x00000d3e 0x00000d5d 0x00000d7e 0x00000d9e 0x00000dbe 0x00000ddf + 0x00000e00 0x00000e21 0x00000e42 0x00000e63 0x00000e84 0x00000ea6 0x00000ec8 0x00000eea + 0x00000f0c 0x00000f2e 0x00000f50 0x00000f73 0x00000f96 0x00000fb9 0x00000fdc 0x00000fff + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; + cabc-gamma-base = < + /*gamma = 2.2*/ + 0x00010000 0x0000fdd0 0x0000fba8 0x0000f986 0x0000f76a 0x0000f556 0x0000f347 0x0000f140 + 0x0000ef3e 0x0000ed43 0x0000eb4e 0x0000e95e 0x0000e775 0x0000e592 0x0000e3b4 0x0000e1dc + 0x0000e009 0x0000de3c 0x0000dc74 0x0000dab2 0x0000d8f4 0x0000d73c 0x0000d589 0x0000d3db + 0x0000d232 0x0000d08d 0x0000ceee 0x0000cd53 0x0000cbbc 0x0000ca2b 0x0000c89d 0x0000c714 + 0x0000c590 0x0000c410 0x0000c294 0x0000c11c 0x0000bfa8 0x0000be39 0x0000bccd 0x0000bb65 + 0x0000ba01 0x0000b8a1 0x0000b745 0x0000b5ed 0x0000b498 0x0000b347 0x0000b1f9 0x0000b0af + 0x0000af68 0x0000ae25 0x0000ace5 0x0000aba8 0x0000aa6f 0x0000a939 0x0000a806 0x0000a6d7 + 0x0000a5aa 0x0000a480 0x0000a35a 0x0000a236 0x0000a116 0x00009ff8 0x00009edd 0x00009dc5 + 0x00009cb0 0x00009b9e 0x00009a8e 0x00009981 0x00009877 0x0000976f 0x0000966a 0x00009567 + 0x00009467 0x0000936a 0x0000926f 0x00009176 0x00009080 0x00008f8c 0x00008e9a 0x00008dab + 0x00008cbe 0x00008bd3 0x00008aea 0x00008a04 0x00008920 0x0000883e 0x0000875e 0x00008680 + 0x000085a4 0x000084ca 0x000083f3 0x0000831d 0x00008249 0x00008177 0x000080a7 0x00007fd9 + 0x00007f0d 0x00007e42 0x00007d7a 0x00007cb3 0x00007bee 0x00007b2b 0x00007a6a 0x000079aa + 0x000078ec 0x0000782f 0x00007775 0x000076bc 0x00007604 0x0000754f 0x0000749a 0x000073e8 + 0x00007337 0x00007287 0x000071d9 0x0000712c 0x00007081 0x00006fd8 0x00006f30 0x00006e89 + 0x00006de4 0x00006d40 0x00006c9d 0x00006bfc 0x00006b5c 0x00006abe 0x00006a21 0x00006985 + 0x000068ea 0x00006851 0x000067b9 0x00006722 0x0000668d 0x000065f9 0x00006566 0x000064d4 + 0x00006443 0x000063b4 0x00006325 0x00006298 0x0000620c 0x00006181 0x000060f8 0x0000606f + 0x00005fe7 0x00005f61 0x00005edb 0x00005e57 0x00005dd4 0x00005d51 0x00005cd0 0x00005c50 + 0x00005bd1 0x00005b52 0x00005ad5 0x00005a59 0x000059de 0x00005963 0x000058ea 0x00005871 + 0x000057fa 0x00005783 0x0000570d 0x00005699 0x00005625 0x000055b2 0x0000553f 0x000054ce + 0x0000545d 0x000053ee 0x0000537f 0x00005311 0x000052a4 0x00005238 0x000051cc 0x00005161 + 0x000050f7 0x0000508e 0x00005026 0x00004fbe 0x00004f57 0x00004ef1 0x00004e8c 0x00004e27 + 0x00004dc3 0x00004d60 0x00004cfe 0x00004c9c 0x00004c3b 0x00004bdb 0x00004b7b 0x00004b1c + 0x00004abe 0x00004a60 0x00004a03 0x000049a7 0x0000494b 0x000048f0 0x00004896 0x0000483c + 0x000047e3 0x0000478a 0x00004733 0x000046db 0x00004685 0x0000462f 0x000045d9 0x00004584 + 0x00004530 0x000044dc 0x00004489 0x00004437 0x000043e5 0x00004393 0x00004342 0x000042f2 + 0x000042a2 0x00004253 0x00004204 0x000041b6 0x00004169 0x0000411b 0x000040cf 0x00004083 + 0x00004037 0x00003fec 0x00003fa1 0x00003f57 0x00003f0e 0x00003ec5 0x00003e7c 0x00003e34 + 0x00003dec 0x00003da5 0x00003d5e 0x00003d18 0x00003cd2 0x00003c8c 0x00003c48 0x00003c03 + 0x00003bbf 0x00003b7b 0x00003b38 0x00003af5 0x00003ab3 0x00003a71 0x00003a30 0x000039ef + 0x000039ae 0x0000396e 0x0000392e 0x000038ee 0x000038af 0x00003871 0x00003832 0x000037f5>; + }; + }; diff --git a/include/dt-bindings/display/screen-timing/lcd-tv080wum-nl0-mipi.dtsi b/include/dt-bindings/display/screen-timing/lcd-tv080wum-nl0-mipi.dtsi new file mode 100644 index 000000000000..b408d6555de8 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-tv080wum-nl0-mipi.dtsi @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * include/dt-bindings/display/screen-timing/lcd-tv080wum-nl0-mipi.dtsi + * author: hjc@rock-chips.com + * create date: 2016-03-28 + * lcd model: tv080wum-n10 + * resolution: 1200 * 1920 + * mipi channel: single + */ + +/* about mipi */ +disp_mipi_init: mipi_dsi_init{ + compatible = "rockchip,mipi_dsi_init"; + rockchip,screen_init = <0>; + rockchip,dsi_lane = <4>; + rockchip,dsi_hs_clk = <1200>; + rockchip,mipi_dsi_num = <1>; +}; + +disp_mipi_power_ctr: mipi_power_ctr { + compatible = "rockchip,mipi_power_ctr"; + /* mipi_lcd_rst:mipi_lcd_rst{ + compatible = "rockchip,lcd_rst"; + rockchip,gpios = <&gpio2 GPIO_B7 GPIO_ACTIVE_LOW>; + rockchip,delay = <100>; + }; + mipi_lcd_en:mipi_lcd_en { + compatible = "rockchip,lcd_en"; + rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>; + rockchip,delay = <100>; + }; + */ +}; + +disp_mipi_init_cmds: screen-on-cmds { + compatible = "rockchip,screen-on-cmds"; + /* rockchip,cmd_debug = <1>; + rockchip,on-cmds1 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <HSDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0xb0 0x02>; + rockchip,cmd_delay = <0>; + }; + */ +}; + +disp_timings: display-timings { + native-mode = <&timing0>; + compatible = "rockchip,display-timings"; + timing0: timing0 { + screen-type = <SCREEN_MIPI>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_P888>; + clock-frequency = <160000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <21>; + hfront-porch = <120>; + vback-porch = <18>; + vfront-porch = <21>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + cabc-lut = < + /*gamma = 2.2*/ + 0x00000383 0x00000392 0x000003a2 0x000003b2 0x000003c2 0x000003d2 0x000003e2 0x000003f3 + 0x00000403 0x00000414 0x00000425 0x00000436 0x00000447 0x00000458 0x0000046a 0x0000047b + 0x0000048d 0x0000049f 0x000004b1 0x000004c3 0x000004d5 0x000004e8 0x000004fa 0x0000050d + 0x00000520 0x00000533 0x00000546 0x0000055a 0x0000056d 0x00000581 0x00000595 0x000005a9 + 0x000005bd 0x000005d1 0x000005e5 0x000005fa 0x0000060f 0x00000624 0x00000639 0x0000064e + 0x00000663 0x00000679 0x0000068e 0x000006a4 0x000006ba 0x000006d0 0x000006e6 0x000006fd + 0x00000713 0x0000072a 0x00000741 0x00000758 0x0000076f 0x00000786 0x0000079e 0x000007b6 + 0x000007cd 0x000007e5 0x000007fd 0x00000816 0x0000082e 0x00000847 0x0000085f 0x00000878 + 0x00000891 0x000008ab 0x000008c4 0x000008de 0x000008f7 0x00000911 0x0000092b 0x00000945 + 0x00000960 0x0000097a 0x00000995 0x000009af 0x000009ca 0x000009e6 0x00000a01 0x00000a1c + 0x00000a38 0x00000a54 0x00000a6f 0x00000a8c 0x00000aa8 0x00000ac4 0x00000ae1 0x00000afd + 0x00000b1a 0x00000b37 0x00000b54 0x00000b72 0x00000b8f 0x00000bad 0x00000bcb 0x00000be9 + 0x00000c07 0x00000c25 0x00000c44 0x00000c62 0x00000c81 0x00000ca0 0x00000cbf 0x00000cdf + 0x00000cfe 0x00000d1e 0x00000d3e 0x00000d5d 0x00000d7e 0x00000d9e 0x00000dbe 0x00000ddf + 0x00000e00 0x00000e21 0x00000e42 0x00000e63 0x00000e84 0x00000ea6 0x00000ec8 0x00000eea + 0x00000f0c 0x00000f2e 0x00000f50 0x00000f73 0x00000f96 0x00000fb9 0x00000fdc 0x00000fff + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; + cabc-gamma-base = < + /*gamma = 2.2*/ + 0x00010000 0x0000fdd0 0x0000fba8 0x0000f986 0x0000f76a 0x0000f556 0x0000f347 0x0000f140 + 0x0000ef3e 0x0000ed43 0x0000eb4e 0x0000e95e 0x0000e775 0x0000e592 0x0000e3b4 0x0000e1dc + 0x0000e009 0x0000de3c 0x0000dc74 0x0000dab2 0x0000d8f4 0x0000d73c 0x0000d589 0x0000d3db + 0x0000d232 0x0000d08d 0x0000ceee 0x0000cd53 0x0000cbbc 0x0000ca2b 0x0000c89d 0x0000c714 + 0x0000c590 0x0000c410 0x0000c294 0x0000c11c 0x0000bfa8 0x0000be39 0x0000bccd 0x0000bb65 + 0x0000ba01 0x0000b8a1 0x0000b745 0x0000b5ed 0x0000b498 0x0000b347 0x0000b1f9 0x0000b0af + 0x0000af68 0x0000ae25 0x0000ace5 0x0000aba8 0x0000aa6f 0x0000a939 0x0000a806 0x0000a6d7 + 0x0000a5aa 0x0000a480 0x0000a35a 0x0000a236 0x0000a116 0x00009ff8 0x00009edd 0x00009dc5 + 0x00009cb0 0x00009b9e 0x00009a8e 0x00009981 0x00009877 0x0000976f 0x0000966a 0x00009567 + 0x00009467 0x0000936a 0x0000926f 0x00009176 0x00009080 0x00008f8c 0x00008e9a 0x00008dab + 0x00008cbe 0x00008bd3 0x00008aea 0x00008a04 0x00008920 0x0000883e 0x0000875e 0x00008680 + 0x000085a4 0x000084ca 0x000083f3 0x0000831d 0x00008249 0x00008177 0x000080a7 0x00007fd9 + 0x00007f0d 0x00007e42 0x00007d7a 0x00007cb3 0x00007bee 0x00007b2b 0x00007a6a 0x000079aa + 0x000078ec 0x0000782f 0x00007775 0x000076bc 0x00007604 0x0000754f 0x0000749a 0x000073e8 + 0x00007337 0x00007287 0x000071d9 0x0000712c 0x00007081 0x00006fd8 0x00006f30 0x00006e89 + 0x00006de4 0x00006d40 0x00006c9d 0x00006bfc 0x00006b5c 0x00006abe 0x00006a21 0x00006985 + 0x000068ea 0x00006851 0x000067b9 0x00006722 0x0000668d 0x000065f9 0x00006566 0x000064d4 + 0x00006443 0x000063b4 0x00006325 0x00006298 0x0000620c 0x00006181 0x000060f8 0x0000606f + 0x00005fe7 0x00005f61 0x00005edb 0x00005e57 0x00005dd4 0x00005d51 0x00005cd0 0x00005c50 + 0x00005bd1 0x00005b52 0x00005ad5 0x00005a59 0x000059de 0x00005963 0x000058ea 0x00005871 + 0x000057fa 0x00005783 0x0000570d 0x00005699 0x00005625 0x000055b2 0x0000553f 0x000054ce + 0x0000545d 0x000053ee 0x0000537f 0x00005311 0x000052a4 0x00005238 0x000051cc 0x00005161 + 0x000050f7 0x0000508e 0x00005026 0x00004fbe 0x00004f57 0x00004ef1 0x00004e8c 0x00004e27 + 0x00004dc3 0x00004d60 0x00004cfe 0x00004c9c 0x00004c3b 0x00004bdb 0x00004b7b 0x00004b1c + 0x00004abe 0x00004a60 0x00004a03 0x000049a7 0x0000494b 0x000048f0 0x00004896 0x0000483c + 0x000047e3 0x0000478a 0x00004733 0x000046db 0x00004685 0x0000462f 0x000045d9 0x00004584 + 0x00004530 0x000044dc 0x00004489 0x00004437 0x000043e5 0x00004393 0x00004342 0x000042f2 + 0x000042a2 0x00004253 0x00004204 0x000041b6 0x00004169 0x0000411b 0x000040cf 0x00004083 + 0x00004037 0x00003fec 0x00003fa1 0x00003f57 0x00003f0e 0x00003ec5 0x00003e7c 0x00003e34 + 0x00003dec 0x00003da5 0x00003d5e 0x00003d18 0x00003cd2 0x00003c8c 0x00003c48 0x00003c03 + 0x00003bbf 0x00003b7b 0x00003b38 0x00003af5 0x00003ab3 0x00003a71 0x00003a30 0x000039ef + 0x000039ae 0x0000396e 0x0000392e 0x000038ee 0x000038af 0x00003871 0x00003832 0x000037f5>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-vga.dtsi b/include/dt-bindings/display/screen-timing/lcd-vga.dtsi new file mode 100644 index 000000000000..13d214b2e8c8 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-vga.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RockChip. VGA timing + * + */ + +disp_timings: display-timings { + native-mode = <&timing1>; + timing0: timing0 { + screen-type = <SCREEN_RGB>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_D888_P666>; + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <160>; + hfront-porch = <24>; + vback-porch = <29>; + vfront-porch = <3>; + hsync-len = <136>; + vsync-len = <6>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; + + timing1: timing1 { + screen-type = <SCREEN_RGB>; + out-face = <OUT_D888_P666>; + lvds-format = <LVDS_8BIT_2>; + clock-frequency = <88750000>; + hactive = <1440>; + vactive = <900>; + hback-porch = <80>; + hfront-porch = <48>; + vback-porch = <17>; + vfront-porch = <3>; + hsync-len = <32>; + vsync-len = <6>; + hsync-active = <1>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; + + timing2: timing2 { + screen-type = <SCREEN_RGB>; + out-face = <OUT_D888_P666>; + lvds-format = <LVDS_8BIT_2>; + clock-frequency = <106500000>; + hactive = <1440>; + vactive = <900>; + hback-porch = <232>; + hfront-porch = <80>; + vback-porch = <25>; + vfront-porch = <3>; + hsync-len = <152>; + vsync-len = <6>; + hsync-active = <0>; + vsync-active = <1>; + de-active = <0>; + pixelclk-active = <1>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-wqxga-mipi.dtsi b/include/dt-bindings/display/screen-timing/lcd-wqxga-mipi.dtsi new file mode 100644 index 000000000000..e41c7d147747 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-wqxga-mipi.dtsi @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2014 ROCKCHIP, Inc. + * arch/arm/boot/dts/lcd-lq070m1sx01-mipi.dtsi + * author: libing@rock-chips.com + * create date: 2014-04-15 + * lcd model: wqxga + * resolution: 2560 X 1600 + * mipi channel: dual + */ + +/* about mipi */ +disp_mipi_init: mipi_dsi_init{ + compatible = "rockchip,mipi_dsi_init"; + rockchip,screen_init = <1>; + rockchip,dsi_lane = <4>; + rockchip,dsi_hs_clk = <940>; + rockchip,mipi_dsi_num = <2>; +}; +disp_mipi_power_ctr: mipi_power_ctr { + compatible = "rockchip,mipi_power_ctr"; + mipi_lcd_rst:mipi_lcd_rst{ + compatible = "rockchip,lcd_rst"; + rockchip,gpios = <&gpio7 GPIO_B2 GPIO_ACTIVE_HIGH>; + rockchip,delay = <10>; + }; + mipi_lcd_en:mipi_lcd_en { + compatible = "rockchip,lcd_en"; + rockchip,gpios = <&gpio6 GPIO_A7 GPIO_ACTIVE_HIGH>; + rockchip,delay = <10>; + }; +}; +disp_mipi_init_cmds: screen-on-cmds { + rockchip,cmd_debug = <0>; + compatible = "rockchip,screen-on-cmds"; + rockchip,on-cmds1 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x05 0x01>; //set soft reset + rockchip,cmd_delay = <10>; + }; + + rockchip,on-cmds2 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x05 0x01>; //set soft reset + rockchip,cmd_delay = <10>; + }; + rockchip,on-cmds3 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x3a 0x77>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds4 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x39 0x2a 0x00 0x00 0x04 0xff>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds5 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x39 0x2b 0x00 0x00 0x06 0x3f>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds6 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x35 0x00>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds7 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x39 0x44 0x00 0x00>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds8 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x51 0xff>; //0xff + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds9 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x53 0x04>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds10 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x51 0xff>; //0xff + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds11 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x53 0x04>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds12 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x55 0x00>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds13 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x05 dcs_exit_sleep_mode>; + rockchip,cmd_delay = <120>; + }; + + rockchip,on-cmds14 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x23 0xb0 0x00>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds15 { //video + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xb3 0x1c>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds16 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xce 0x7d 0x40 0x48 0x56 0x67 0x78 0x88 0x98 0xa7 0xb5 0xc3 0xd1 0xde 0xe9 0xf2 0xfa 0xff 0x04 0x00>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds17 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x23 0xb0 0x03>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds18 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x39 0x2c >; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds19 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x05 dcs_set_display_on>; + rockchip,cmd_delay = <10>; + }; + +}; + +disp_timings: display-timings { + native-mode = <&timing0>; + compatible = "rockchip,display-timings"; + timing0: timing0 { + screen-type = <SCREEN_DUAL_MIPI>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_P888>; + clock-frequency = <265000000>; + hactive = <2560>; + vactive = <1600>; + + hsync-len = <38>;//19 + hback-porch = <40>;//40 + hfront-porch = <108>;//123 + + vsync-len = <4>; + vback-porch = <4>; + vfront-porch = <12>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-y81349.dtsi b/include/dt-bindings/display/screen-timing/lcd-y81349.dtsi new file mode 100644 index 000000000000..f0db3a36b142 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-y81349.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RockChip. LCD_Y81349 FOR 86V + * + */ + + +disp_timings: display-timings { + native-mode = <&timing0>; + timing0: timing0 { + screen-type = <SCREEN_RGB>; + out-face = <OUT_P666>; + clock-frequency = <33000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <10>; + hfront-porch = <210>; + vback-porch = <10>; + vfront-porch = <22>; + hsync-len = <30>; + vsync-len = <13>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; +}; diff --git a/include/dt-bindings/dram/rockchip,rk322x.h b/include/dt-bindings/dram/rockchip,rk322x.h new file mode 100644 index 000000000000..1ab3317d700e --- /dev/null +++ b/include/dt-bindings/dram/rockchip,rk322x.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H +#define _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H + +#define DDR3_DS_34ohm (1 << 1) +#define DDR3_DS_40ohm (0x0) + +#define LP2_DS_34ohm (0x1) +#define LP2_DS_40ohm (0x2) +#define LP2_DS_48ohm (0x3) +#define LP2_DS_60ohm (0x4) +#define LP2_DS_68_6ohm (0x5)/* optional */ +#define LP2_DS_80ohm (0x6) +#define LP2_DS_120ohm (0x7)/* optional */ + +#define LP3_DS_34ohm (0x1) +#define LP3_DS_40ohm (0x2) +#define LP3_DS_48ohm (0x3) +#define LP3_DS_60ohm (0x4) +#define LP3_DS_80ohm (0x6) +#define LP3_DS_34D_40U (0x9) +#define LP3_DS_40D_48U (0xa) +#define LP3_DS_34D_48U (0xb) + +#define DDR3_ODT_DIS (0) +#define DDR3_ODT_40ohm ((1 << 2) | (1 << 6)) +#define DDR3_ODT_60ohm (1 << 2) +#define DDR3_ODT_120ohm (1 << 6) + +#define LP3_ODT_DIS (0) +#define LP3_ODT_60ohm (1) +#define LP3_ODT_120ohm (2) +#define LP3_ODT_240ohm (3) + +#define PHY_DDR3_RON_RTT_DISABLE (0) +#define PHY_DDR3_RON_RTT_451ohm (1) +#define PHY_DDR3_RON_RTT_225ohm (2) +#define PHY_DDR3_RON_RTT_150ohm (3) +#define PHY_DDR3_RON_RTT_112ohm (4) +#define PHY_DDR3_RON_RTT_90ohm (5) +#define PHY_DDR3_RON_RTT_75ohm (6) +#define PHY_DDR3_RON_RTT_64ohm (7) +#define PHY_DDR3_RON_RTT_56ohm (16) +#define PHY_DDR3_RON_RTT_50ohm (17) +#define PHY_DDR3_RON_RTT_45ohm (18) +#define PHY_DDR3_RON_RTT_41ohm (19) +#define PHY_DDR3_RON_RTT_37ohm (20) +#define PHY_DDR3_RON_RTT_34ohm (21) +#define PHY_DDR3_RON_RTT_33ohm (22) +#define PHY_DDR3_RON_RTT_30ohm (23) +#define PHY_DDR3_RON_RTT_28ohm (24) +#define PHY_DDR3_RON_RTT_26ohm (25) +#define PHY_DDR3_RON_RTT_25ohm (26) +#define PHY_DDR3_RON_RTT_23ohm (27) +#define PHY_DDR3_RON_RTT_22ohm (28) +#define PHY_DDR3_RON_RTT_21ohm (29) +#define PHY_DDR3_RON_RTT_20ohm (30) +#define PHY_DDR3_RON_RTT_19ohm (31) + +#define PHY_LP23_RON_RTT_DISABLE (0) +#define PHY_LP23_RON_RTT_480ohm (1) +#define PHY_LP23_RON_RTT_240ohm (2) +#define PHY_LP23_RON_RTT_160ohm (3) +#define PHY_LP23_RON_RTT_120ohm (4) +#define PHY_LP23_RON_RTT_96ohm (5) +#define PHY_LP23_RON_RTT_80ohm (6) +#define PHY_LP23_RON_RTT_68ohm (7) +#define PHY_LP23_RON_RTT_60ohm (16) +#define PHY_LP23_RON_RTT_53ohm (17) +#define PHY_LP23_RON_RTT_48ohm (18) +#define PHY_LP23_RON_RTT_43ohm (19) +#define PHY_LP23_RON_RTT_40ohm (20) +#define PHY_LP23_RON_RTT_37ohm (21) +#define PHY_LP23_RON_RTT_34ohm (22) +#define PHY_LP23_RON_RTT_32ohm (23) +#define PHY_LP23_RON_RTT_30ohm (24) +#define PHY_LP23_RON_RTT_28ohm (25) +#define PHY_LP23_RON_RTT_26ohm (26) +#define PHY_LP23_RON_RTT_25ohm (27) +#define PHY_LP23_RON_RTT_24ohm (28) +#define PHY_LP23_RON_RTT_22ohm (29) +#define PHY_LP23_RON_RTT_21ohm (30) +#define PHY_LP23_RON_RTT_20ohm (31) + +#endif /* _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H */ diff --git a/include/dt-bindings/dram/rockchip,rk3368.h b/include/dt-bindings/dram/rockchip,rk3368.h new file mode 100644 index 000000000000..993f1eed9816 --- /dev/null +++ b/include/dt-bindings/dram/rockchip,rk3368.h @@ -0,0 +1,80 @@ +/* + * + * Copyright (C) 2011-2014 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3368_H +#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3368_H + +#define DDR3_DS_34ohm (1<<1) +#define DDR3_DS_40ohm (0x0) + +#define LP2_DS_34ohm (0x1) +#define LP2_DS_40ohm (0x2) +#define LP2_DS_48ohm (0x3) +#define LP2_DS_60ohm (0x4) +#define LP2_DS_68_6ohm (0x5)/*optional*/ +#define LP2_DS_80ohm (0x6) +#define LP2_DS_120ohm (0x7)/*optional*/ + +#define LP3_DS_34ohm (0x1) +#define LP3_DS_40ohm (0x2) +#define LP3_DS_48ohm (0x3) +#define LP3_DS_60ohm (0x4) +#define LP3_DS_80ohm (0x6) +#define LP3_DS_34D_40U (0x9) +#define LP3_DS_40D_48U (0xa) +#define LP3_DS_34D_48U (0xb) + +#define DDR3_ODT_DIS (0) +#define DDR3_ODT_40ohm ((1<<2)|(1<<6)) +#define DDR3_ODT_60ohm (1<<2) +#define DDR3_ODT_120ohm (1<<6) + +#define LP3_ODT_DIS (0) +#define LP3_ODT_60ohm (1) +#define LP3_ODT_120ohm (2) +#define LP3_ODT_240ohm (3) + +#define PHY_RON_DISABLE (0) +#define PHY_RON_272ohm (1) +#define PHY_RON_135ohm (2) +#define PHY_RON_91ohm (3) +#define PHY_RON_38ohm (7) +#define PHY_RON_68ohm (8) +#define PHY_RON_54ohm (9) +#define PHY_RON_45ohm (10) +#define PHY_RON_39ohm (11) +#define PHY_RON_34ohm (12) +#define PHY_RON_30ohm (13) +#define PHY_RON_27ohm (14) +#define PHY_RON_25ohm (15) + +#define PHY_RTT_DISABLE (0) +#define PHY_RTT_1116ohm (1) +#define PHY_RTT_558ohm (2) +#define PHY_RTT_372ohm (3) +#define PHY_RTT_279ohm (4) +#define PHY_RTT_223ohm (5) +#define PHY_RTT_186ohm (6) +#define PHY_RTT_159ohm (7) +#define PHY_RTT_139ohm (8) +#define PHY_RTT_124ohm (9) +#define PHY_RTT_112ohm (10) +#define PHY_RTT_101ohm (11) +#define PHY_RTT_93ohm (12) +#define PHY_RTT_86ohm (13) +#define PHY_RTT_80ohm (14) +#define PHY_RTT_74ohm (15) + +#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3368_H*/ diff --git a/include/dt-bindings/input/rk-input.h b/include/dt-bindings/input/rk-input.h new file mode 100644 index 000000000000..00b412927890 --- /dev/null +++ b/include/dt-bindings/input/rk-input.h @@ -0,0 +1,814 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Device properties and quirks + */ + +#define INPUT_PROP_POINTER 0x00 /* needs a pointer */ +#define INPUT_PROP_DIRECT 0x01 /* direct input devices */ +#define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */ +#define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */ + +#define INPUT_PROP_MAX 0x1f +#define INPUT_PROP_CNT (INPUT_PROP_MAX + 1) + +/* + * Event types + */ + +#define EV_SYN 0x00 +#define EV_KEY 0x01 +#define EV_REL 0x02 +#define EV_ABS 0x03 +#define EV_MSC 0x04 +#define EV_SW 0x05 +#define EV_LED 0x11 +#define EV_SND 0x12 +#define EV_REP 0x14 +#define EV_FF 0x15 +#define EV_PWR 0x16 +#define EV_FF_STATUS 0x17 +#define EV_MAX 0x1f +#define EV_CNT (EV_MAX+1) + +/* + * Synchronization events. + */ + +#define SYN_REPORT 0 +#define SYN_CONFIG 1 +#define SYN_MT_REPORT 2 +#define SYN_DROPPED 3 + +/* + * Keys and buttons + * + * Most of the keys/buttons are modeled after USB HUT 1.12 + * (see http://www.usb.org/developers/hidpage). + * Abbreviations in the comments: + * AC - Application Control + * AL - Application Launch Button + * SC - System Control + */ + +#define KEY_RESERVED 0 +#define KEY_ESC 1 +#define KEY_1 2 +#define KEY_2 3 +#define KEY_3 4 +#define KEY_4 5 +#define KEY_5 6 +#define KEY_6 7 +#define KEY_7 8 +#define KEY_8 9 +#define KEY_9 10 +#define KEY_0 11 +#define KEY_MINUS 12 +#define KEY_EQUAL 13 +#define KEY_BACKSPACE 14 +#define KEY_TAB 15 +#define KEY_Q 16 +#define KEY_W 17 +#define KEY_E 18 +#define KEY_R 19 +#define KEY_T 20 +#define KEY_Y 21 +#define KEY_U 22 +#define KEY_I 23 +#define KEY_O 24 +#define KEY_P 25 +#define KEY_LEFTBRACE 26 +#define KEY_RIGHTBRACE 27 +#define KEY_ENTER 28 +#define KEY_LEFTCTRL 29 +#define KEY_A 30 +#define KEY_S 31 +#define KEY_D 32 +#define KEY_F 33 +#define KEY_G 34 +#define KEY_H 35 +#define KEY_J 36 +#define KEY_K 37 +#define KEY_L 38 +#define KEY_SEMICOLON 39 +#define KEY_APOSTROPHE 40 +#define KEY_GRAVE 41 +#define KEY_LEFTSHIFT 42 +#define KEY_BACKSLASH 43 +#define KEY_Z 44 +#define KEY_X 45 +#define KEY_C 46 +#define KEY_V 47 +#define KEY_B 48 +#define KEY_N 49 +#define KEY_M 50 +#define KEY_COMMA 51 +#define KEY_DOT 52 +#define KEY_SLASH 53 +#define KEY_RIGHTSHIFT 54 +#define KEY_KPASTERISK 55 +#define KEY_LEFTALT 56 +#define KEY_SPACE 57 +#define KEY_CAPSLOCK 58 +#define KEY_F1 59 +#define KEY_F2 60 +#define KEY_F3 61 +#define KEY_F4 62 +#define KEY_F5 63 +#define KEY_F6 64 +#define KEY_F7 65 +#define KEY_F8 66 +#define KEY_F9 67 +#define KEY_F10 68 +#define KEY_NUMLOCK 69 +#define KEY_SCROLLLOCK 70 +#define KEY_KP7 71 +#define KEY_KP8 72 +#define KEY_KP9 73 +#define KEY_KPMINUS 74 +#define KEY_KP4 75 +#define KEY_KP5 76 +#define KEY_KP6 77 +#define KEY_KPPLUS 78 +#define KEY_KP1 79 +#define KEY_KP2 80 +#define KEY_KP3 81 +#define KEY_KP0 82 +#define KEY_KPDOT 83 + +#define KEY_ZENKAKUHANKAKU 85 +#define KEY_102ND 86 +#define KEY_F11 87 +#define KEY_F12 88 +#define KEY_RO 89 +#define KEY_KATAKANA 90 +#define KEY_HIRAGANA 91 +#define KEY_HENKAN 92 +#define KEY_KATAKANAHIRAGANA 93 +#define KEY_MUHENKAN 94 +#define KEY_KPJPCOMMA 95 +#define KEY_KPENTER 96 +#define KEY_RIGHTCTRL 97 +#define KEY_KPSLASH 98 +#define KEY_SYSRQ 99 +#define KEY_RIGHTALT 100 +#define KEY_LINEFEED 101 +#define KEY_HOME 102 +#define KEY_UP 103 +#define KEY_PAGEUP 104 +#define KEY_LEFT 105 +#define KEY_RIGHT 106 +#define KEY_END 107 +#define KEY_DOWN 108 +#define KEY_PAGEDOWN 109 +#define KEY_INSERT 110 +#define KEY_DELETE 111 +#define KEY_MACRO 112 +#define KEY_MUTE 113 +#define KEY_VOLUMEDOWN 114 +#define KEY_VOLUMEUP 115 +#define KEY_POWER 116 /* SC System Power Down */ +#define KEY_KPEQUAL 117 +#define KEY_KPPLUSMINUS 118 +#define KEY_PAUSE 119 +#define KEY_SCALE 120 /* AL Compiz Scale (Expose) */ + +#define KEY_KPCOMMA 121 +#define KEY_HANGEUL 122 +#define KEY_HANGUEL KEY_HANGEUL +#define KEY_HANJA 123 +#define KEY_YEN 124 +#define KEY_LEFTMETA 125 +#define KEY_RIGHTMETA 126 +#define KEY_COMPOSE 127 + +#define KEY_STOP 128 /* AC Stop */ +#define KEY_AGAIN 129 +#define KEY_PROPS 130 /* AC Properties */ +#define KEY_UNDO 131 /* AC Undo */ +#define KEY_FRONT 132 +#define KEY_COPY 133 /* AC Copy */ +#define KEY_OPEN 134 /* AC Open */ +#define KEY_PASTE 135 /* AC Paste */ +#define KEY_FIND 136 /* AC Search */ +#define KEY_CUT 137 /* AC Cut */ +#define KEY_HELP 138 /* AL Integrated Help Center */ +#define KEY_MENU 139 /* Menu (show menu) */ +#define KEY_CALC 140 /* AL Calculator */ +#define KEY_SETUP 141 +#define KEY_SLEEP 142 /* SC System Sleep */ +#define KEY_WAKEUP 143 /* System Wake Up */ +#define KEY_FILE 144 /* AL Local Machine Browser */ +#define KEY_SENDFILE 145 +#define KEY_DELETEFILE 146 +#define KEY_XFER 147 +#define KEY_PROG1 148 +#define KEY_PROG2 149 +#define KEY_WWW 150 /* AL Internet Browser */ +#define KEY_MSDOS 151 +#define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */ +#define KEY_SCREENLOCK KEY_COFFEE +#define KEY_DIRECTION 153 +#define KEY_CYCLEWINDOWS 154 +#define KEY_MAIL 155 +#define KEY_BOOKMARKS 156 /* AC Bookmarks */ +#define KEY_COMPUTER 157 +#define KEY_BACK 158 /* AC Back */ +#define KEY_FORWARD 159 /* AC Forward */ +#define KEY_CLOSECD 160 +#define KEY_EJECTCD 161 +#define KEY_EJECTCLOSECD 162 +#define KEY_NEXTSONG 163 +#define KEY_PLAYPAUSE 164 +#define KEY_PREVIOUSSONG 165 +#define KEY_STOPCD 166 +#define KEY_RECORD 167 +#define KEY_REWIND 168 +#define KEY_PHONE 169 /* Media Select Telephone */ +#define KEY_ISO 170 +#define KEY_CONFIG 171 /* AL Consumer Control Configuration */ +#define KEY_HOMEPAGE 172 /* AC Home */ +#define KEY_REFRESH 173 /* AC Refresh */ +#define KEY_EXIT 174 /* AC Exit */ +#define KEY_MOVE 175 +#define KEY_EDIT 176 +#define KEY_SCROLLUP 177 +#define KEY_SCROLLDOWN 178 +#define KEY_KPLEFTPAREN 179 +#define KEY_KPRIGHTPAREN 180 +#define KEY_NEW 181 /* AC New */ +#define KEY_REDO 182 /* AC Redo/Repeat */ + +#define KEY_F13 183 +#define KEY_F14 184 +#define KEY_F15 185 +#define KEY_F16 186 +#define KEY_F17 187 +#define KEY_F18 188 +#define KEY_F19 189 +#define KEY_F20 190 +#define KEY_F21 191 +#define KEY_F22 192 +#define KEY_F23 193 +#define KEY_F24 194 + +#define KEY_PLAYCD 200 +#define KEY_PAUSECD 201 +#define KEY_PROG3 202 +#define KEY_PROG4 203 +#define KEY_DASHBOARD 204 /* AL Dashboard */ +#define KEY_SUSPEND 205 +#define KEY_CLOSE 206 /* AC Close */ +#define KEY_PLAY 207 +#define KEY_FASTFORWARD 208 +#define KEY_BASSBOOST 209 +#define KEY_PRINT 210 /* AC Print */ +#define KEY_HP 211 +#define KEY_CAMERA 212 +#define KEY_SOUND 213 +#define KEY_QUESTION 214 +#define KEY_EMAIL 215 +#define KEY_CHAT 216 +#define KEY_SEARCH 217 +#define KEY_CONNECT 218 +#define KEY_FINANCE 219 /* AL Checkbook/Finance */ +#define KEY_SPORT 220 +#define KEY_SHOP 221 +#define KEY_ALTERASE 222 +#define KEY_CANCEL 223 /* AC Cancel */ +#define KEY_BRIGHTNESSDOWN 224 +#define KEY_BRIGHTNESSUP 225 +#define KEY_MEDIA 226 + +#define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video + outputs (Monitor/LCD/TV-out/etc) */ +#define KEY_KBDILLUMTOGGLE 228 +#define KEY_KBDILLUMDOWN 229 +#define KEY_KBDILLUMUP 230 + +#define KEY_SEND 231 /* AC Send */ +#define KEY_REPLY 232 /* AC Reply */ +#define KEY_FORWARDMAIL 233 /* AC Forward Msg */ +#define KEY_SAVE 234 /* AC Save */ +#define KEY_DOCUMENTS 235 + +#define KEY_BATTERY 236 + +#define KEY_BLUETOOTH 237 +#define KEY_WLAN 238 +#define KEY_UWB 239 + +#define KEY_UNKNOWN 240 + +#define KEY_VIDEO_NEXT 241 /* drive next video source */ +#define KEY_VIDEO_PREV 242 /* drive previous video source */ +#define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */ +#define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual + brightness control is off, + rely on ambient */ +#define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO +#define KEY_DISPLAY_OFF 245 /* display device to off state */ + +#define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */ +#define KEY_WIMAX KEY_WWAN +#define KEY_RFKILL 247 /* Key that controls all radios */ + +#define KEY_MICMUTE 248 /* Mute / unmute the microphone */ + +/* Code 255 is reserved for special needs of AT keyboard driver */ + +#define BTN_MISC 0x100 +#define BTN_0 0x100 +#define BTN_1 0x101 +#define BTN_2 0x102 +#define BTN_3 0x103 +#define BTN_4 0x104 +#define BTN_5 0x105 +#define BTN_6 0x106 +#define BTN_7 0x107 +#define BTN_8 0x108 +#define BTN_9 0x109 + +#define BTN_MOUSE 0x110 +#define BTN_LEFT 0x110 +#define BTN_RIGHT 0x111 +#define BTN_MIDDLE 0x112 +#define BTN_SIDE 0x113 +#define BTN_EXTRA 0x114 +#define BTN_FORWARD 0x115 +#define BTN_BACK 0x116 +#define BTN_TASK 0x117 + +#define BTN_JOYSTICK 0x120 +#define BTN_TRIGGER 0x120 +#define BTN_THUMB 0x121 +#define BTN_THUMB2 0x122 +#define BTN_TOP 0x123 +#define BTN_TOP2 0x124 +#define BTN_PINKIE 0x125 +#define BTN_BASE 0x126 +#define BTN_BASE2 0x127 +#define BTN_BASE3 0x128 +#define BTN_BASE4 0x129 +#define BTN_BASE5 0x12a +#define BTN_BASE6 0x12b +#define BTN_DEAD 0x12f + +#define BTN_GAMEPAD 0x130 +#define BTN_SOUTH 0x130 +#define BTN_A BTN_SOUTH +#define BTN_EAST 0x131 +#define BTN_B BTN_EAST +#define BTN_C 0x132 +#define BTN_NORTH 0x133 +#define BTN_X BTN_NORTH +#define BTN_WEST 0x134 +#define BTN_Y BTN_WEST +#define BTN_Z 0x135 +#define BTN_TL 0x136 +#define BTN_TR 0x137 +#define BTN_TL2 0x138 +#define BTN_TR2 0x139 +#define BTN_SELECT 0x13a +#define BTN_START 0x13b +#define BTN_MODE 0x13c +#define BTN_THUMBL 0x13d +#define BTN_THUMBR 0x13e + +#define BTN_DIGI 0x140 +#define BTN_TOOL_PEN 0x140 +#define BTN_TOOL_RUBBER 0x141 +#define BTN_TOOL_BRUSH 0x142 +#define BTN_TOOL_PENCIL 0x143 +#define BTN_TOOL_AIRBRUSH 0x144 +#define BTN_TOOL_FINGER 0x145 +#define BTN_TOOL_MOUSE 0x146 +#define BTN_TOOL_LENS 0x147 +#define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */ +#define BTN_TOUCH 0x14a +#define BTN_STYLUS 0x14b +#define BTN_STYLUS2 0x14c +#define BTN_TOOL_DOUBLETAP 0x14d +#define BTN_TOOL_TRIPLETAP 0x14e +#define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */ + +#define BTN_WHEEL 0x150 +#define BTN_GEAR_DOWN 0x150 +#define BTN_GEAR_UP 0x151 + +#define KEY_OK 0x160 +#define KEY_SELECT 0x161 +#define KEY_GOTO 0x162 +#define KEY_CLEAR 0x163 +#define KEY_POWER2 0x164 +#define KEY_OPTION 0x165 +#define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */ +#define KEY_TIME 0x167 +#define KEY_VENDOR 0x168 +#define KEY_ARCHIVE 0x169 +#define KEY_PROGRAM 0x16a /* Media Select Program Guide */ +#define KEY_CHANNEL 0x16b +#define KEY_FAVORITES 0x16c +#define KEY_EPG 0x16d +#define KEY_PVR 0x16e /* Media Select Home */ +#define KEY_MHP 0x16f +#define KEY_LANGUAGE 0x170 +#define KEY_TITLE 0x171 +#define KEY_SUBTITLE 0x172 +#define KEY_ANGLE 0x173 +#define KEY_ZOOM 0x174 +#define KEY_MODE 0x175 +#define KEY_KEYBOARD 0x176 +#define KEY_SCREEN 0x177 +#define KEY_PC 0x178 /* Media Select Computer */ +#define KEY_TV 0x179 /* Media Select TV */ +#define KEY_TV2 0x17a /* Media Select Cable */ +#define KEY_VCR 0x17b /* Media Select VCR */ +#define KEY_VCR2 0x17c /* VCR Plus */ +#define KEY_SAT 0x17d /* Media Select Satellite */ +#define KEY_SAT2 0x17e +#define KEY_CD 0x17f /* Media Select CD */ +#define KEY_TAPE 0x180 /* Media Select Tape */ +#define KEY_RADIO 0x181 +#define KEY_TUNER 0x182 /* Media Select Tuner */ +#define KEY_PLAYER 0x183 +#define KEY_TEXT 0x184 +#define KEY_DVD 0x185 /* Media Select DVD */ +#define KEY_AUX 0x186 +#define KEY_MP3 0x187 +#define KEY_AUDIO 0x188 /* AL Audio Browser */ +#define KEY_VIDEO 0x189 /* AL Movie Browser */ +#define KEY_DIRECTORY 0x18a +#define KEY_LIST 0x18b +#define KEY_MEMO 0x18c /* Media Select Messages */ +#define KEY_CALENDAR 0x18d +#define KEY_RED 0x18e +#define KEY_GREEN 0x18f +#define KEY_YELLOW 0x190 +#define KEY_BLUE 0x191 +#define KEY_CHANNELUP 0x192 /* Channel Increment */ +#define KEY_CHANNELDOWN 0x193 /* Channel Decrement */ +#define KEY_FIRST 0x194 +#define KEY_LAST 0x195 /* Recall Last */ +#define KEY_AB 0x196 +#define KEY_NEXT 0x197 +#define KEY_RESTART 0x198 +#define KEY_SLOW 0x199 +#define KEY_SHUFFLE 0x19a +#define KEY_BREAK 0x19b +#define KEY_PREVIOUS 0x19c +#define KEY_DIGITS 0x19d +#define KEY_TEEN 0x19e +#define KEY_TWEN 0x19f +#define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */ +#define KEY_GAMES 0x1a1 /* Media Select Games */ +#define KEY_ZOOMIN 0x1a2 /* AC Zoom In */ +#define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */ +#define KEY_ZOOMRESET 0x1a4 /* AC Zoom */ +#define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */ +#define KEY_EDITOR 0x1a6 /* AL Text Editor */ +#define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */ +#define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */ +#define KEY_PRESENTATION 0x1a9 /* AL Presentation App */ +#define KEY_DATABASE 0x1aa /* AL Database App */ +#define KEY_NEWS 0x1ab /* AL Newsreader */ +#define KEY_VOICEMAIL 0x1ac /* AL Voicemail */ +#define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */ +#define KEY_MESSENGER 0x1ae /* AL Instant Messaging */ +#define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */ +#define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE +#define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */ +#define KEY_LOGOFF 0x1b1 /* AL Logoff */ + +#define KEY_DOLLAR 0x1b2 +#define KEY_EURO 0x1b3 + +#define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */ +#define KEY_FRAMEFORWARD 0x1b5 +#define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */ +#define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */ +#define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */ +#define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */ +#define KEY_IMAGES 0x1ba /* AL Image Browser */ + +#define KEY_DEL_EOL 0x1c0 +#define KEY_DEL_EOS 0x1c1 +#define KEY_INS_LINE 0x1c2 +#define KEY_DEL_LINE 0x1c3 + +#define KEY_FN 0x1d0 +#define KEY_FN_ESC 0x1d1 +#define KEY_FN_F1 0x1d2 +#define KEY_FN_F2 0x1d3 +#define KEY_FN_F3 0x1d4 +#define KEY_FN_F4 0x1d5 +#define KEY_FN_F5 0x1d6 +#define KEY_FN_F6 0x1d7 +#define KEY_FN_F7 0x1d8 +#define KEY_FN_F8 0x1d9 +#define KEY_FN_F9 0x1da +#define KEY_FN_F10 0x1db +#define KEY_FN_F11 0x1dc +#define KEY_FN_F12 0x1dd +#define KEY_FN_1 0x1de +#define KEY_FN_2 0x1df +#define KEY_FN_D 0x1e0 +#define KEY_FN_E 0x1e1 +#define KEY_FN_F 0x1e2 +#define KEY_FN_S 0x1e3 +#define KEY_FN_B 0x1e4 + +#define KEY_BRL_DOT1 0x1f1 +#define KEY_BRL_DOT2 0x1f2 +#define KEY_BRL_DOT3 0x1f3 +#define KEY_BRL_DOT4 0x1f4 +#define KEY_BRL_DOT5 0x1f5 +#define KEY_BRL_DOT6 0x1f6 +#define KEY_BRL_DOT7 0x1f7 +#define KEY_BRL_DOT8 0x1f8 +#define KEY_BRL_DOT9 0x1f9 +#define KEY_BRL_DOT10 0x1fa + +#define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */ +#define KEY_NUMERIC_1 0x201 /* and other keypads */ +#define KEY_NUMERIC_2 0x202 +#define KEY_NUMERIC_3 0x203 +#define KEY_NUMERIC_4 0x204 +#define KEY_NUMERIC_5 0x205 +#define KEY_NUMERIC_6 0x206 +#define KEY_NUMERIC_7 0x207 +#define KEY_NUMERIC_8 0x208 +#define KEY_NUMERIC_9 0x209 +#define KEY_NUMERIC_STAR 0x20a +#define KEY_NUMERIC_POUND 0x20b + +#define KEY_CAMERA_FOCUS 0x210 +#define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */ + +#define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */ +#define KEY_TOUCHPAD_ON 0x213 +#define KEY_TOUCHPAD_OFF 0x214 + +#define KEY_CAMERA_ZOOMIN 0x215 +#define KEY_CAMERA_ZOOMOUT 0x216 +#define KEY_CAMERA_UP 0x217 +#define KEY_CAMERA_DOWN 0x218 +#define KEY_CAMERA_LEFT 0x219 +#define KEY_CAMERA_RIGHT 0x21a + +#define KEY_ATTENDANT_ON 0x21b +#define KEY_ATTENDANT_OFF 0x21c +#define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */ +#define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */ + +#define BTN_DPAD_UP 0x220 +#define BTN_DPAD_DOWN 0x221 +#define BTN_DPAD_LEFT 0x222 +#define BTN_DPAD_RIGHT 0x223 + +#define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */ + +#define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */ +#define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */ +#define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */ +#define KEY_CONTROLPANEL 0x243 /* AL Control Panel */ +#define KEY_APPSELECT 0x244 /* AL Select Task/Application */ +#define KEY_SCREENSAVER 0x245 /* AL Screen Saver */ +#define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */ + +#define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */ +#define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */ + +#define BTN_TRIGGER_HAPPY 0x2c0 +#define BTN_TRIGGER_HAPPY1 0x2c0 +#define BTN_TRIGGER_HAPPY2 0x2c1 +#define BTN_TRIGGER_HAPPY3 0x2c2 +#define BTN_TRIGGER_HAPPY4 0x2c3 +#define BTN_TRIGGER_HAPPY5 0x2c4 +#define BTN_TRIGGER_HAPPY6 0x2c5 +#define BTN_TRIGGER_HAPPY7 0x2c6 +#define BTN_TRIGGER_HAPPY8 0x2c7 +#define BTN_TRIGGER_HAPPY9 0x2c8 +#define BTN_TRIGGER_HAPPY10 0x2c9 +#define BTN_TRIGGER_HAPPY11 0x2ca +#define BTN_TRIGGER_HAPPY12 0x2cb +#define BTN_TRIGGER_HAPPY13 0x2cc +#define BTN_TRIGGER_HAPPY14 0x2cd +#define BTN_TRIGGER_HAPPY15 0x2ce +#define BTN_TRIGGER_HAPPY16 0x2cf +#define BTN_TRIGGER_HAPPY17 0x2d0 +#define BTN_TRIGGER_HAPPY18 0x2d1 +#define BTN_TRIGGER_HAPPY19 0x2d2 +#define BTN_TRIGGER_HAPPY20 0x2d3 +#define BTN_TRIGGER_HAPPY21 0x2d4 +#define BTN_TRIGGER_HAPPY22 0x2d5 +#define BTN_TRIGGER_HAPPY23 0x2d6 +#define BTN_TRIGGER_HAPPY24 0x2d7 +#define BTN_TRIGGER_HAPPY25 0x2d8 +#define BTN_TRIGGER_HAPPY26 0x2d9 +#define BTN_TRIGGER_HAPPY27 0x2da +#define BTN_TRIGGER_HAPPY28 0x2db +#define BTN_TRIGGER_HAPPY29 0x2dc +#define BTN_TRIGGER_HAPPY30 0x2dd +#define BTN_TRIGGER_HAPPY31 0x2de +#define BTN_TRIGGER_HAPPY32 0x2df +#define BTN_TRIGGER_HAPPY33 0x2e0 +#define BTN_TRIGGER_HAPPY34 0x2e1 +#define BTN_TRIGGER_HAPPY35 0x2e2 +#define BTN_TRIGGER_HAPPY36 0x2e3 +#define BTN_TRIGGER_HAPPY37 0x2e4 +#define BTN_TRIGGER_HAPPY38 0x2e5 +#define BTN_TRIGGER_HAPPY39 0x2e6 +#define BTN_TRIGGER_HAPPY40 0x2e7 + +/* We avoid low common keys in module aliases so they don't get huge. */ +#define KEY_MIN_INTERESTING KEY_MUTE +#define KEY_MAX 0x2ff +#define KEY_CNT (KEY_MAX+1) + +/* + * Relative axes + */ + +#define REL_X 0x00 +#define REL_Y 0x01 +#define REL_Z 0x02 +#define REL_RX 0x03 +#define REL_RY 0x04 +#define REL_RZ 0x05 +#define REL_HWHEEL 0x06 +#define REL_DIAL 0x07 +#define REL_WHEEL 0x08 +#define REL_MISC 0x09 +#define REL_MAX 0x0f +#define REL_CNT (REL_MAX+1) + +/* + * Absolute axes + */ + +#define ABS_X 0x00 +#define ABS_Y 0x01 +#define ABS_Z 0x02 +#define ABS_RX 0x03 +#define ABS_RY 0x04 +#define ABS_RZ 0x05 +#define ABS_THROTTLE 0x06 +#define ABS_RUDDER 0x07 +#define ABS_WHEEL 0x08 +#define ABS_GAS 0x09 +#define ABS_BRAKE 0x0a +#define ABS_HAT0X 0x10 +#define ABS_HAT0Y 0x11 +#define ABS_HAT1X 0x12 +#define ABS_HAT1Y 0x13 +#define ABS_HAT2X 0x14 +#define ABS_HAT2Y 0x15 +#define ABS_HAT3X 0x16 +#define ABS_HAT3Y 0x17 +#define ABS_PRESSURE 0x18 +#define ABS_DISTANCE 0x19 +#define ABS_TILT_X 0x1a +#define ABS_TILT_Y 0x1b +#define ABS_TOOL_WIDTH 0x1c + +#define ABS_VOLUME 0x20 + +#define ABS_MISC 0x28 + +#define ABS_MT_SLOT 0x2f /* MT slot being modified */ +#define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */ +#define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */ +#define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */ +#define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */ +#define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */ +#define ABS_MT_POSITION_X 0x35 /* Center X touch position */ +#define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */ +#define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */ +#define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */ +#define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */ +#define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */ +#define ABS_MT_DISTANCE 0x3b /* Contact hover distance */ +#define ABS_MT_TOOL_X 0x3c /* Center X tool position */ +#define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */ + + +#define ABS_MAX 0x3f +#define ABS_CNT (ABS_MAX+1) + +/* + * Switch events + */ + +#define SW_LID 0x00 /* set = lid shut */ +#define SW_TABLET_MODE 0x01 /* set = tablet mode */ +#define SW_HEADPHONE_INSERT 0x02 /* set = inserted */ +#define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any" + set = radio enabled */ +#define SW_RADIO SW_RFKILL_ALL /* deprecated */ +#define SW_MICROPHONE_INSERT 0x04 /* set = inserted */ +#define SW_DOCK 0x05 /* set = plugged into dock */ +#define SW_LINEOUT_INSERT 0x06 /* set = inserted */ +#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */ +#define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */ +#define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */ +#define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */ +#define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */ +#define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ +#define SW_LINEIN_INSERT 0x0d /* set = inserted */ +#define SW_MUTE_DEVICE 0x0e /* set = device disabled */ +#define SW_MAX 0x0f +#define SW_CNT (SW_MAX+1) + +/* + * Misc events + */ + +#define MSC_SERIAL 0x00 +#define MSC_PULSELED 0x01 +#define MSC_GESTURE 0x02 +#define MSC_RAW 0x03 +#define MSC_SCAN 0x04 +#define MSC_TIMESTAMP 0x05 +#define MSC_MAX 0x07 +#define MSC_CNT (MSC_MAX+1) + +/* + * LEDs + */ + +#define LED_NUML 0x00 +#define LED_CAPSL 0x01 +#define LED_SCROLLL 0x02 +#define LED_COMPOSE 0x03 +#define LED_KANA 0x04 +#define LED_SLEEP 0x05 +#define LED_SUSPEND 0x06 +#define LED_MUTE 0x07 +#define LED_MISC 0x08 +#define LED_MAIL 0x09 +#define LED_CHARGING 0x0a +#define LED_MAX 0x0f +#define LED_CNT (LED_MAX+1) + +/* + * Autorepeat values + */ + +#define REP_DELAY 0x00 +#define REP_PERIOD 0x01 +#define REP_MAX 0x01 +#define REP_CNT (REP_MAX+1) + +/* + * Sounds + */ + +#define SND_CLICK 0x00 +#define SND_BELL 0x01 +#define SND_TONE 0x02 +#define SND_MAX 0x07 +#define SND_CNT (SND_MAX+1) + +/* + * IDs. + */ + +#define ID_BUS 0 +#define ID_VENDOR 1 +#define ID_PRODUCT 2 +#define ID_VERSION 3 + +#define BUS_PCI 0x01 +#define BUS_ISAPNP 0x02 +#define BUS_USB 0x03 +#define BUS_HIL 0x04 +#define BUS_BLUETOOTH 0x05 +#define BUS_VIRTUAL 0x06 + +#define BUS_ISA 0x10 +#define BUS_I8042 0x11 +#define BUS_XTKBD 0x12 +#define BUS_RS232 0x13 +#define BUS_GAMEPORT 0x14 +#define BUS_PARPORT 0x15 +#define BUS_AMIGA 0x16 +#define BUS_ADB 0x17 +#define BUS_I2C 0x18 +#define BUS_HOST 0x19 +#define BUS_GSC 0x1A +#define BUS_ATARI 0x1B +#define BUS_SPI 0x1C + +/* + * MT_TOOL types + */ +#define MT_TOOL_FINGER 0 +#define MT_TOOL_PEN 1 +#define MT_TOOL_MAX 1 + +/* + * Values describing the status of a force-feedback effect + */ +#define FF_STATUS_STOPPED 0x00 +#define FF_STATUS_PLAYING 0x01 +#define FF_STATUS_MAX 0x01 diff --git a/include/dt-bindings/leds/leds-pca9532.h b/include/dt-bindings/leds/leds-pca9532.h new file mode 100644 index 000000000000..4d917aab7e1e --- /dev/null +++ b/include/dt-bindings/leds/leds-pca9532.h @@ -0,0 +1,18 @@ +/* + * This header provides constants for pca9532 LED bindings. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef _DT_BINDINGS_LEDS_PCA9532_H +#define _DT_BINDINGS_LEDS_PCA9532_H + +#define PCA9532_TYPE_NONE 0 +#define PCA9532_TYPE_LED 1 +#define PCA9532_TYPE_N2100_BEEP 2 +#define PCA9532_TYPE_GPIO 3 +#define PCA9532_LED_TIMER2 4 + +#endif /* _DT_BINDINGS_LEDS_PCA9532_H */ diff --git a/include/dt-bindings/memory/px30-dram.h b/include/dt-bindings/memory/px30-dram.h new file mode 100644 index 000000000000..17d799d802d9 --- /dev/null +++ b/include/dt-bindings/memory/px30-dram.h @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_PX30_H +#define _DT_BINDINGS_DRAM_ROCKCHIP_PX30_H + +#define DDR2_DS_FULL (0) +#define DDR2_DS_REDUCE (1) + +#define DDR2_ODT_DIS (0) +#define DDR2_ODT_50ohm (50) /* optional */ +#define DDR2_ODT_75ohm (75) +#define DDR2_ODT_150ohm (150) + +#define DDR3_DS_34ohm (34) +#define DDR3_DS_40ohm (40) + +#define DDR3_ODT_DIS (0) +#define DDR3_ODT_40ohm (40) +#define DDR3_ODT_60ohm (60) +#define DDR3_ODT_120ohm (120) + +#define LP2_DS_34ohm (34) +#define LP2_DS_40ohm (40) +#define LP2_DS_48ohm (48) +#define LP2_DS_60ohm (60) +#define LP2_DS_68_6ohm (68) /* optional */ +#define LP2_DS_80ohm (80) +#define LP2_DS_120ohm (120) /* optional */ + +#define LP3_DS_34ohm (34) +#define LP3_DS_40ohm (40) +#define LP3_DS_48ohm (48) +#define LP3_DS_60ohm (60) +#define LP3_DS_80ohm (80) +#define LP3_DS_34D_40U (3440) +#define LP3_DS_40D_48U (4048) +#define LP3_DS_34D_48U (3448) + +#define LP3_ODT_DIS (0) +#define LP3_ODT_60ohm (60) +#define LP3_ODT_120ohm (120) +#define LP3_ODT_240ohm (240) + +#define LP4_PDDS_40ohm (40) +#define LP4_PDDS_48ohm (48) +#define LP4_PDDS_60ohm (60) +#define LP4_PDDS_80ohm (80) +#define LP4_PDDS_120ohm (120) +#define LP4_PDDS_240ohm (240) + +#define LP4_DQ_ODT_40ohm (40) +#define LP4_DQ_ODT_48ohm (48) +#define LP4_DQ_ODT_60ohm (60) +#define LP4_DQ_ODT_80ohm (80) +#define LP4_DQ_ODT_120ohm (120) +#define LP4_DQ_ODT_240ohm (240) +#define LP4_DQ_ODT_DIS (0) + +#define LP4_CA_ODT_40ohm (40) +#define LP4_CA_ODT_48ohm (48) +#define LP4_CA_ODT_60ohm (60) +#define LP4_CA_ODT_80ohm (80) +#define LP4_CA_ODT_120ohm (120) +#define LP4_CA_ODT_240ohm (240) +#define LP4_CA_ODT_DIS (0) + +#define DDR4_DS_34ohm (34) +#define DDR4_DS_48ohm (48) +#define DDR4_RTT_NOM_DIS (0) +#define DDR4_RTT_NOM_60ohm (60) +#define DDR4_RTT_NOM_120ohm (120) +#define DDR4_RTT_NOM_40ohm (40) +#define DDR4_RTT_NOM_240ohm (240) +#define DDR4_RTT_NOM_48ohm (48) +#define DDR4_RTT_NOM_80ohm (80) +#define DDR4_RTT_NOM_34ohm (34) + +#define PHY_DDR3_RON_RTT_DISABLE (0) +#define PHY_DDR3_RON_RTT_451ohm (1) +#define PHY_DDR3_RON_RTT_225ohm (2) +#define PHY_DDR3_RON_RTT_150ohm (3) +#define PHY_DDR3_RON_RTT_112ohm (4) +#define PHY_DDR3_RON_RTT_90ohm (5) +#define PHY_DDR3_RON_RTT_75ohm (6) +#define PHY_DDR3_RON_RTT_64ohm (7) +#define PHY_DDR3_RON_RTT_56ohm (16) +#define PHY_DDR3_RON_RTT_50ohm (17) +#define PHY_DDR3_RON_RTT_45ohm (18) +#define PHY_DDR3_RON_RTT_41ohm (19) +#define PHY_DDR3_RON_RTT_37ohm (20) +#define PHY_DDR3_RON_RTT_34ohm (21) +#define PHY_DDR3_RON_RTT_33ohm (22) +#define PHY_DDR3_RON_RTT_30ohm (23) +#define PHY_DDR3_RON_RTT_28ohm (24) +#define PHY_DDR3_RON_RTT_26ohm (25) +#define PHY_DDR3_RON_RTT_25ohm (26) +#define PHY_DDR3_RON_RTT_23ohm (27) +#define PHY_DDR3_RON_RTT_22ohm (28) +#define PHY_DDR3_RON_RTT_21ohm (29) +#define PHY_DDR3_RON_RTT_20ohm (30) +#define PHY_DDR3_RON_RTT_19ohm (31) + +#define PHY_DDR4_LPDDR3_2_RON_RTT_DISABLE (0) +#define PHY_DDR4_LPDDR3_2_RON_RTT_480ohm (1) +#define PHY_DDR4_LPDDR3_2_RON_RTT_240ohm (2) +#define PHY_DDR4_LPDDR3_2_RON_RTT_160ohm (3) +#define PHY_DDR4_LPDDR3_2_RON_RTT_120ohm (4) +#define PHY_DDR4_LPDDR3_2_RON_RTT_96ohm (5) +#define PHY_DDR4_LPDDR3_2_RON_RTT_80ohm (6) +#define PHY_DDR4_LPDDR3_2_RON_RTT_68ohm (7) +#define PHY_DDR4_LPDDR3_2_RON_RTT_60ohm (16) +#define PHY_DDR4_LPDDR3_2_RON_RTT_53ohm (17) +#define PHY_DDR4_LPDDR3_2_RON_RTT_48ohm (18) +#define PHY_DDR4_LPDDR3_2_RON_RTT_43ohm (19) +#define PHY_DDR4_LPDDR3_2_RON_RTT_40ohm (20) +#define PHY_DDR4_LPDDR3_2_RON_RTT_37ohm (21) +#define PHY_DDR4_LPDDR3_2_RON_RTT_34ohm (22) +#define PHY_DDR4_LPDDR3_2_RON_RTT_32ohm (23) +#define PHY_DDR4_LPDDR3_2_RON_RTT_30ohm (24) +#define PHY_DDR4_LPDDR3_2_RON_RTT_28ohm (25) +#define PHY_DDR4_LPDDR3_2_RON_RTT_26ohm (26) +#define PHY_DDR4_LPDDR3_2_RON_RTT_25ohm (27) +#define PHY_DDR4_LPDDR3_2_RON_RTT_24ohm (28) +#define PHY_DDR4_LPDDR3_2_RON_RTT_22ohm (29) +#define PHY_DDR4_LPDDR3_2_RON_RTT_21ohm (30) +#define PHY_DDR4_LPDDR3_2_RON_RTT_20ohm (31) + +#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_PX30_H*/ diff --git a/include/dt-bindings/memory/rk1808-dram.h b/include/dt-bindings/memory/rk1808-dram.h new file mode 100644 index 000000000000..522bd75a4a55 --- /dev/null +++ b/include/dt-bindings/memory/rk1808-dram.h @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK1808_H +#define _DT_BINDINGS_DRAM_ROCKCHIP_RK1808_H + +#define DDR2_DS_FULL (0) +#define DDR2_DS_REDUCE (1) + +#define DDR2_ODT_DIS (0) +#define DDR2_ODT_50ohm (50) /* optional */ +#define DDR2_ODT_75ohm (75) +#define DDR2_ODT_150ohm (150) + +#define DDR3_DS_34ohm (34) +#define DDR3_DS_40ohm (40) + +#define DDR3_ODT_DIS (0) +#define DDR3_ODT_40ohm (40) +#define DDR3_ODT_60ohm (60) +#define DDR3_ODT_120ohm (120) + +#define LP2_DS_34ohm (34) +#define LP2_DS_40ohm (40) +#define LP2_DS_48ohm (48) +#define LP2_DS_60ohm (60) +#define LP2_DS_68_6ohm (68) /* optional */ +#define LP2_DS_80ohm (80) +#define LP2_DS_120ohm (120) /* optional */ + +#define LP3_DS_34ohm (34) +#define LP3_DS_40ohm (40) +#define LP3_DS_48ohm (48) +#define LP3_DS_60ohm (60) +#define LP3_DS_80ohm (80) +#define LP3_DS_34D_40U (3440) +#define LP3_DS_40D_48U (4048) +#define LP3_DS_34D_48U (3448) + +#define LP3_ODT_DIS (0) +#define LP3_ODT_60ohm (60) +#define LP3_ODT_120ohm (120) +#define LP3_ODT_240ohm (240) + +#define LP4_PDDS_40ohm (40) +#define LP4_PDDS_48ohm (48) +#define LP4_PDDS_60ohm (60) +#define LP4_PDDS_80ohm (80) +#define LP4_PDDS_120ohm (120) +#define LP4_PDDS_240ohm (240) + +#define LP4_DQ_ODT_40ohm (40) +#define LP4_DQ_ODT_48ohm (48) +#define LP4_DQ_ODT_60ohm (60) +#define LP4_DQ_ODT_80ohm (80) +#define LP4_DQ_ODT_120ohm (120) +#define LP4_DQ_ODT_240ohm (240) +#define LP4_DQ_ODT_DIS (0) + +#define LP4_CA_ODT_40ohm (40) +#define LP4_CA_ODT_48ohm (48) +#define LP4_CA_ODT_60ohm (60) +#define LP4_CA_ODT_80ohm (80) +#define LP4_CA_ODT_120ohm (120) +#define LP4_CA_ODT_240ohm (240) +#define LP4_CA_ODT_DIS (0) + +#define DDR4_DS_34ohm (34) +#define DDR4_DS_48ohm (48) +#define DDR4_RTT_NOM_DIS (0) +#define DDR4_RTT_NOM_60ohm (60) +#define DDR4_RTT_NOM_120ohm (120) +#define DDR4_RTT_NOM_40ohm (40) +#define DDR4_RTT_NOM_240ohm (240) +#define DDR4_RTT_NOM_48ohm (48) +#define DDR4_RTT_NOM_80ohm (80) +#define DDR4_RTT_NOM_34ohm (34) + +#define PHY_DDR3_RON_DISABLE (0) +#define PHY_DDR3_RON_340ohm (1) +#define PHY_DDR3_RON_170ohm (2) +#define PHY_DDR3_RON_113ohm (3) +#define PHY_DDR3_RON_85ohm (4) +#define PHY_DDR3_RON_68ohm (5) +#define PHY_DDR3_RON_57ohm (6) +#define PHY_DDR3_RON_49ohm (7) +#define PHY_DDR3_RON_43ohm (16) +#define PHY_DDR3_RON_38ohm (17) +#define PHY_DDR3_RON_34ohm (18) +#define PHY_DDR3_RON_31ohm (19) +#define PHY_DDR3_RON_28ohm (20) +#define PHY_DDR3_RON_26ohm (21) +#define PHY_DDR3_RON_24ohm (22) +#define PHY_DDR3_RON_23ohm (23) +#define PHY_DDR3_RON_21ohm (24) +#define PHY_DDR3_RON_20ohm (25) +#define PHY_DDR3_RON_19ohm (26) +#define PHY_DDR3_RON_18ohm (27) +#define PHY_DDR3_RON_17ohm (28) +#define PHY_DDR3_RON_16ohm (29) +#define PHY_DDR3_RON_15ohm (31) + +#define PHY_DDR3_RTT_DISABLE (0) +#define PHY_DDR3_RTT_852ohm (1) +#define PHY_DDR3_RTT_427ohm (2) +#define PHY_DDR3_RTT_284ohm (3) +#define PHY_DDR3_RTT_213ohm (4) +#define PHY_DDR3_RTT_171ohm (5) +#define PHY_DDR3_RTT_142ohm (6) +#define PHY_DDR3_RTT_122ohm (7) +#define PHY_DDR3_RTT_107ohm (16) +#define PHY_DDR3_RTT_95ohm (17) +#define PHY_DDR3_RTT_85ohm (18) +#define PHY_DDR3_RTT_78ohm (19) +#define PHY_DDR3_RTT_71ohm (20) +#define PHY_DDR3_RTT_66ohm (21) +#define PHY_DDR3_RTT_61ohm (22) +#define PHY_DDR3_RTT_57ohm (23) +#define PHY_DDR3_RTT_53ohm (24) +#define PHY_DDR3_RTT_50ohm (25) +#define PHY_DDR3_RTT_47ohm (26) +#define PHY_DDR3_RTT_45ohm (27) +#define PHY_DDR3_RTT_43ohm (28) +#define PHY_DDR3_RTT_41ohm (29) +#define PHY_DDR3_RTT_39ohm (30) +#define PHY_DDR3_RTT_37ohm (31) + +#define PHY_DDR4_LPDDR2_3_RON_DISABLE (0) +#define PHY_DDR4_LPDDR2_3_RON_376ohm (1) +#define PHY_DDR4_LPDDR2_3_RON_188ohm (2) +#define PHY_DDR4_LPDDR2_3_RON_125ohm (3) +#define PHY_DDR4_LPDDR2_3_RON_94ohm (4) +#define PHY_DDR4_LPDDR2_3_RON_75ohm (5) +#define PHY_DDR4_LPDDR2_3_RON_63ohm (6) +#define PHY_DDR4_LPDDR2_3_RON_54ohm (7) +#define PHY_DDR4_LPDDR2_3_RON_47ohm (16) +#define PHY_DDR4_LPDDR2_3_RON_42ohm (17) +#define PHY_DDR4_LPDDR2_3_RON_38ohm (18) +#define PHY_DDR4_LPDDR2_3_RON_34ohm (19) +#define PHY_DDR4_LPDDR2_3_RON_31ohm (20) +#define PHY_DDR4_LPDDR2_3_RON_29ohm (21) +#define PHY_DDR4_LPDDR2_3_RON_27ohm (22) +#define PHY_DDR4_LPDDR2_3_RON_25ohm (23) +#define PHY_DDR4_LPDDR2_3_RON_23ohm (24) +#define PHY_DDR4_LPDDR2_3_RON_22ohm (25) +#define PHY_DDR4_LPDDR2_3_RON_21ohm (26) +#define PHY_DDR4_LPDDR2_3_RON_20ohm (27) +#define PHY_DDR4_LPDDR2_3_RON_19ohm (28) +#define PHY_DDR4_LPDDR2_3_RON_18ohm (29) +#define PHY_DDR4_LPDDR2_3_RON_17ohm (30) +#define PHY_DDR4_LPDDR2_3_RON_16ohm (31) + +#define PHY_DDR4_LPDDR2_3_RTT_DISABLE (0) +#define PHY_DDR4_LPDDR2_3_RTT_915ohm (1) +#define PHY_DDR4_LPDDR2_3_RTT_458ohm (2) +#define PHY_DDR4_LPDDR2_3_RTT_305ohm (3) +#define PHY_DDR4_LPDDR2_3_RTT_229ohm (4) +#define PHY_DDR4_LPDDR2_3_RTT_183ohm (5) +#define PHY_DDR4_LPDDR2_3_RTT_153ohm (6) +#define PHY_DDR4_LPDDR2_3_RTT_131ohm (7) +#define PHY_DDR4_LPDDR2_3_RTT_115ohm (16) +#define PHY_DDR4_LPDDR2_3_RTT_102ohm (17) +#define PHY_DDR4_LPDDR2_3_RTT_92ohm (18) +#define PHY_DDR4_LPDDR2_3_RTT_83ohm (19) +#define PHY_DDR4_LPDDR2_3_RTT_76ohm (20) +#define PHY_DDR4_LPDDR2_3_RTT_70ohm (21) +#define PHY_DDR4_LPDDR2_3_RTT_65ohm (22) +#define PHY_DDR4_LPDDR2_3_RTT_61ohm (23) +#define PHY_DDR4_LPDDR2_3_RTT_57ohm (24) +#define PHY_DDR4_LPDDR2_3_RTT_54ohm (25) +#define PHY_DDR4_LPDDR2_3_RTT_51ohm (26) +#define PHY_DDR4_LPDDR2_3_RTT_48ohm (27) +#define PHY_DDR4_LPDDR2_3_RTT_46ohm (28) +#define PHY_DDR4_LPDDR2_3_RTT_44ohm (29) +#define PHY_DDR4_LPDDR2_3_RTT_42ohm (30) +#define PHY_DDR4_LPDDR2_3_RTT_40ohm (31) + +#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK1808_H*/ diff --git a/include/dt-bindings/memory/rk3128-dram.h b/include/dt-bindings/memory/rk3128-dram.h new file mode 100644 index 000000000000..2598ac98e525 --- /dev/null +++ b/include/dt-bindings/memory/rk3128-dram.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3128_H +#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3128_H + +#define BIT(nr) (1UL << (nr)) + +#define DDR3_DS_34ohm BIT(1) +#define DDR3_DS_40ohm (0x0) + +#define LP2_DS_34ohm (0x1) +#define LP2_DS_40ohm (0x2) +#define LP2_DS_48ohm (0x3) +#define LP2_DS_60ohm (0x4) +#define LP2_DS_68_6ohm (0x5) /* optional */ +#define LP2_DS_80ohm (0x6) +#define LP2_DS_120ohm (0x7) /* optional */ + +#define DDR3_ODT_DIS (0) +#define DDR3_ODT_40ohm (BIT(2) | BIT(6)) +#define DDR3_ODT_60ohm BIT(2) +#define DDR3_ODT_120ohm BIT(6) + +#define PHY_RON_DISABLE (0) +#define PHY_RON_309ohm (1) +#define PHY_RON_155ohm (2) +#define PHY_RON_103ohm (3) +#define PHY_RON_77ohm (4) +#define PHY_RON_63ohm (5) +#define PHY_RON_52ohm (6) +#define PHY_RON_45ohm (7) +#define PHY_RON_62ohm (9) +#define PHY_RON_44ohm (11) +#define PHY_RON_39ohm (12) +#define PHY_RON_34ohm (13) +#define PHY_RON_31ohm (14) +#define PHY_RON_28ohm (15) + +#define PHY_RTT_DISABLE (0) +#define PHY_RTT_816ohm (1) +#define PHY_RTT_431ohm (2) +#define PHY_RTT_287ohm (3) +#define PHY_RTT_216ohm (4) +#define PHY_RTT_172ohm (5) +#define PHY_RTT_145ohm (6) +#define PHY_RTT_124ohm (7) +#define PHY_RTT_215ohm (8) +#define PHY_RTT_144ohm (10) +#define PHY_RTT_123ohm (11) +#define PHY_RTT_108ohm (12) +#define PHY_RTT_96ohm (13) +#define PHY_RTT_86ohm (14) +#define PHY_RTT_78ohm (15) + +#endif /* _DT_BINDINGS_DRAM_ROCKCHIP_RK3128_H */ diff --git a/include/dt-bindings/memory/rk3288-dram.h b/include/dt-bindings/memory/rk3288-dram.h new file mode 100644 index 000000000000..1c531dca755c --- /dev/null +++ b/include/dt-bindings/memory/rk3288-dram.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3288_H +#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3288_H + +#define DDR3_DS_34ohm (34) +#define DDR3_DS_40ohm (40) + +#define DDR3_ODT_DIS (0) +#define DDR3_ODT_40ohm (40) +#define DDR3_ODT_60ohm (60) +#define DDR3_ODT_120ohm (120) + +#define LP2_DS_34ohm (34) +#define LP2_DS_40ohm (40) +#define LP2_DS_48ohm (48) +#define LP2_DS_60ohm (60) +#define LP2_DS_68_6ohm (68) /* optional */ +#define LP2_DS_80ohm (80) +#define LP2_DS_120ohm (120) /* optional */ + +#define LP3_DS_34ohm (34) +#define LP3_DS_40ohm (40) +#define LP3_DS_48ohm (48) +#define LP3_DS_60ohm (60) +#define LP3_DS_80ohm (80) +#define LP3_DS_34D_40U (3440) +#define LP3_DS_40D_48U (4048) +#define LP3_DS_34D_48U (3448) + +#define LP3_ODT_DIS (0) +#define LP3_ODT_60ohm (60) +#define LP3_ODT_120ohm (120) +#define LP3_ODT_240ohm (240) + +/* PHY DRV ODT strength*/ +#define PHY_DDR3_RON_114ohm (7) +#define PHY_DDR3_RON_95ohm (4) +#define PHY_DDR3_RON_81ohm (5) +#define PHY_DDR3_RON_71ohm (0xc) +#define PHY_DDR3_RON_63ohm (0xd) +#define PHY_DDR3_RON_57ohm (0xe) +#define PHY_DDR3_RON_52ohm (0xf) +#define PHY_DDR3_RON_47ohm (0xa) +#define PHY_DDR3_RON_44ohm (0xb) +#define PHY_DDR3_RON_41ohm (0x8) +#define PHY_DDR3_RON_38ohm (0x9) +#define PHY_DDR3_RON_34ohm (0x19) +#define PHY_DDR3_RON_30ohm (0x1b) +#define PHY_DDR3_RON_26ohm (0x1c) +#define PHY_DDR3_RON_23ohm (0x15) +#define PHY_DDR3_RON_20ohm (0x12) +#define PHY_DDR3_RON_18ohm (0x11) + +#define PHY_DDR3_RTT_368ohm (0x1) +#define PHY_DDR3_RTT_155ohm (0x2) +#define PHY_DDR3_RTT_113ohm (0x3) +#define PHY_DDR3_RTT_80ohm (0x6) +#define PHY_DDR3_RTT_64ohm (0x7) +#define PHY_DDR3_RTT_54ohm (0x4) +#define PHY_DDR3_RTT_40ohm (0xc) +#define PHY_DDR3_RTT_30ohm (0xf) + +#define PHY_LP23_RON_110ohm (4) +#define PHY_LP23_RON_83ohm (0xc) +#define PHY_LP23_RON_73ohm (0xd) +#define PHY_LP23_RON_66ohm (0xe) +#define PHY_LP23_RON_60ohm (0xf) +#define PHY_LP23_RON_55ohm (0xa) +#define PHY_LP23_RON_51ohm (0xb) +#define PHY_LP23_RON_44ohm (0x9) +#define PHY_LP23_RON_39ohm (0x19) +#define PHY_LP23_RON_35ohm (0x1b) +#define PHY_LP23_RON_30ohm (0x1c) +#define PHY_LP23_RON_26ohm (0x16) +#define PHY_LP23_RON_22ohm (0x10) + +#define PHY_LP23_RTT_368ohm (0x1) +#define PHY_LP23_RTT_155ohm (0x2) +#define PHY_LP23_RTT_113ohm (0x3) +#define PHY_LP23_RTT_80ohm (0x6) +#define PHY_LP23_RTT_64ohm (0x7) +#define PHY_LP23_RTT_54ohm (0x4) +#define PHY_LP23_RTT_40ohm (0xc) +#define PHY_LP23_RTT_30ohm (0xf) + +#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3288_H*/ diff --git a/include/dt-bindings/memory/rk3328-dram.h b/include/dt-bindings/memory/rk3328-dram.h new file mode 100644 index 000000000000..171f41c256d3 --- /dev/null +++ b/include/dt-bindings/memory/rk3328-dram.h @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H +#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H + +#define DDR3_DS_34ohm (34) +#define DDR3_DS_40ohm (40) + +#define DDR3_ODT_DIS (0) +#define DDR3_ODT_40ohm (40) +#define DDR3_ODT_60ohm (60) +#define DDR3_ODT_120ohm (120) + +#define LP2_DS_34ohm (34) +#define LP2_DS_40ohm (40) +#define LP2_DS_48ohm (48) +#define LP2_DS_60ohm (60) +#define LP2_DS_68_6ohm (68) /* optional */ +#define LP2_DS_80ohm (80) +#define LP2_DS_120ohm (120) /* optional */ + +#define LP3_DS_34ohm (34) +#define LP3_DS_40ohm (40) +#define LP3_DS_48ohm (48) +#define LP3_DS_60ohm (60) +#define LP3_DS_80ohm (80) +#define LP3_DS_34D_40U (3440) +#define LP3_DS_40D_48U (4048) +#define LP3_DS_34D_48U (3448) + +#define LP3_ODT_DIS (0) +#define LP3_ODT_60ohm (60) +#define LP3_ODT_120ohm (120) +#define LP3_ODT_240ohm (240) + +#define LP4_PDDS_40ohm (40) +#define LP4_PDDS_48ohm (48) +#define LP4_PDDS_60ohm (60) +#define LP4_PDDS_80ohm (80) +#define LP4_PDDS_120ohm (120) +#define LP4_PDDS_240ohm (240) + +#define LP4_DQ_ODT_40ohm (40) +#define LP4_DQ_ODT_48ohm (48) +#define LP4_DQ_ODT_60ohm (60) +#define LP4_DQ_ODT_80ohm (80) +#define LP4_DQ_ODT_120ohm (120) +#define LP4_DQ_ODT_240ohm (240) +#define LP4_DQ_ODT_DIS (0) + +#define LP4_CA_ODT_40ohm (40) +#define LP4_CA_ODT_48ohm (48) +#define LP4_CA_ODT_60ohm (60) +#define LP4_CA_ODT_80ohm (80) +#define LP4_CA_ODT_120ohm (120) +#define LP4_CA_ODT_240ohm (240) +#define LP4_CA_ODT_DIS (0) + +#define DDR4_DS_34ohm (34) +#define DDR4_DS_48ohm (48) +#define DDR4_RTT_NOM_DIS (0) +#define DDR4_RTT_NOM_60ohm (60) +#define DDR4_RTT_NOM_120ohm (120) +#define DDR4_RTT_NOM_40ohm (40) +#define DDR4_RTT_NOM_240ohm (240) +#define DDR4_RTT_NOM_48ohm (48) +#define DDR4_RTT_NOM_80ohm (80) +#define DDR4_RTT_NOM_34ohm (34) + +#define PHY_DDR3_RON_RTT_DISABLE (0) +#define PHY_DDR3_RON_RTT_451ohm (1) +#define PHY_DDR3_RON_RTT_225ohm (2) +#define PHY_DDR3_RON_RTT_150ohm (3) +#define PHY_DDR3_RON_RTT_112ohm (4) +#define PHY_DDR3_RON_RTT_90ohm (5) +#define PHY_DDR3_RON_RTT_75ohm (6) +#define PHY_DDR3_RON_RTT_64ohm (7) +#define PHY_DDR3_RON_RTT_56ohm (16) +#define PHY_DDR3_RON_RTT_50ohm (17) +#define PHY_DDR3_RON_RTT_45ohm (18) +#define PHY_DDR3_RON_RTT_41ohm (19) +#define PHY_DDR3_RON_RTT_37ohm (20) +#define PHY_DDR3_RON_RTT_34ohm (21) +#define PHY_DDR3_RON_RTT_33ohm (22) +#define PHY_DDR3_RON_RTT_30ohm (23) +#define PHY_DDR3_RON_RTT_28ohm (24) +#define PHY_DDR3_RON_RTT_26ohm (25) +#define PHY_DDR3_RON_RTT_25ohm (26) +#define PHY_DDR3_RON_RTT_23ohm (27) +#define PHY_DDR3_RON_RTT_22ohm (28) +#define PHY_DDR3_RON_RTT_21ohm (29) +#define PHY_DDR3_RON_RTT_20ohm (30) +#define PHY_DDR3_RON_RTT_19ohm (31) + +#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0) +#define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1) +#define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2) +#define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3) +#define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4) +#define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5) +#define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6) +#define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7) +#define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16) +#define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17) +#define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18) +#define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19) +#define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20) +#define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21) +#define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22) +#define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23) +#define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24) +#define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25) +#define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26) +#define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27) +#define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28) +#define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29) +#define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30) +#define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31) + +#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H*/ diff --git a/include/dt-bindings/memory/rk3368-dram.h b/include/dt-bindings/memory/rk3368-dram.h new file mode 100644 index 000000000000..400f7b52a59f --- /dev/null +++ b/include/dt-bindings/memory/rk3368-dram.h @@ -0,0 +1,106 @@ +/* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3368_H +#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3368_H + +#define DDR3_DS_34ohm (0x2) +#define DDR3_DS_40ohm (0x0) + +#define LP2_DS_34ohm (0x1) +#define LP2_DS_40ohm (0x2) +#define LP2_DS_48ohm (0x3) +#define LP2_DS_60ohm (0x4) +#define LP2_DS_68_6ohm (0x5)/* optional */ +#define LP2_DS_80ohm (0x6) +#define LP2_DS_120ohm (0x7)/* optional */ + +#define LP3_DS_34ohm (0x1) +#define LP3_DS_40ohm (0x2) +#define LP3_DS_48ohm (0x3) +#define LP3_DS_60ohm (0x4) +#define LP3_DS_80ohm (0x6) +#define LP3_DS_34D_40U (0x9) +#define LP3_DS_40D_48U (0xa) +#define LP3_DS_34D_48U (0xb) + +#define DDR3_ODT_DIS (0) +#define DDR3_ODT_40ohm (0x44) +#define DDR3_ODT_60ohm (0x4) +#define DDR3_ODT_120ohm (0x40) + +#define LP3_ODT_DIS (0) +#define LP3_ODT_60ohm (1) +#define LP3_ODT_120ohm (2) +#define LP3_ODT_240ohm (3) + +#define PHY_RON_DISABLE (0) +#define PHY_RON_272ohm (1) +#define PHY_RON_135ohm (2) +#define PHY_RON_91ohm (3) +#define PHY_RON_38ohm (7) +#define PHY_RON_68ohm (8) +#define PHY_RON_54ohm (9) +#define PHY_RON_45ohm (10) +#define PHY_RON_39ohm (11) +#define PHY_RON_34ohm (12) +#define PHY_RON_30ohm (13) +#define PHY_RON_27ohm (14) +#define PHY_RON_25ohm (15) + +#define PHY_RTT_DISABLE (0) +#define PHY_RTT_1116ohm (1) +#define PHY_RTT_558ohm (2) +#define PHY_RTT_372ohm (3) +#define PHY_RTT_279ohm (4) +#define PHY_RTT_223ohm (5) +#define PHY_RTT_186ohm (6) +#define PHY_RTT_159ohm (7) +#define PHY_RTT_139ohm (8) +#define PHY_RTT_124ohm (9) +#define PHY_RTT_112ohm (10) +#define PHY_RTT_101ohm (11) +#define PHY_RTT_93ohm (12) +#define PHY_RTT_86ohm (13) +#define PHY_RTT_80ohm (14) +#define PHY_RTT_74ohm (15) + +#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3368_H*/ diff --git a/include/dt-bindings/memory/rk3399-dram.h b/include/dt-bindings/memory/rk3399-dram.h new file mode 100644 index 000000000000..44abb0aafb05 --- /dev/null +++ b/include/dt-bindings/memory/rk3399-dram.h @@ -0,0 +1,107 @@ +/* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3399_H +#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3399_H + +#define DDR3_DS_34ohm (34) +#define DDR3_DS_40ohm (40) + +#define DDR3_ODT_DIS (0) +#define DDR3_ODT_40ohm (40) +#define DDR3_ODT_60ohm (60) +#define DDR3_ODT_120ohm (120) + +#define LP2_DS_34ohm (34) +#define LP2_DS_40ohm (40) +#define LP2_DS_48ohm (48) +#define LP2_DS_60ohm (60) +#define LP2_DS_68_6ohm (68) /* optional */ +#define LP2_DS_80ohm (80) +#define LP2_DS_120ohm (120) /* optional */ + +#define LP3_DS_34ohm (34) +#define LP3_DS_40ohm (40) +#define LP3_DS_48ohm (48) +#define LP3_DS_60ohm (60) +#define LP3_DS_80ohm (80) +#define LP3_DS_34D_40U (3440) +#define LP3_DS_40D_48U (4048) +#define LP3_DS_34D_48U (3448) + +#define LP3_ODT_DIS (0) +#define LP3_ODT_60ohm (60) +#define LP3_ODT_120ohm (120) +#define LP3_ODT_240ohm (240) + +#define LP4_PDDS_40ohm (40) +#define LP4_PDDS_48ohm (48) +#define LP4_PDDS_60ohm (60) +#define LP4_PDDS_80ohm (80) +#define LP4_PDDS_120ohm (120) +#define LP4_PDDS_240ohm (240) + +#define LP4_DQ_ODT_40ohm (40) +#define LP4_DQ_ODT_48ohm (48) +#define LP4_DQ_ODT_60ohm (60) +#define LP4_DQ_ODT_80ohm (80) +#define LP4_DQ_ODT_120ohm (120) +#define LP4_DQ_ODT_240ohm (240) +#define LP4_DQ_ODT_DIS (0) + +#define LP4_CA_ODT_40ohm (40) +#define LP4_CA_ODT_48ohm (48) +#define LP4_CA_ODT_60ohm (60) +#define LP4_CA_ODT_80ohm (80) +#define LP4_CA_ODT_120ohm (120) +#define LP4_CA_ODT_240ohm (240) +#define LP4_CA_ODT_DIS (0) + +#define PHY_DRV_ODT_Hi_Z (0) +#define PHY_DRV_ODT_240 (240) +#define PHY_DRV_ODT_120 (120) +#define PHY_DRV_ODT_80 (80) +#define PHY_DRV_ODT_60 (60) +#define PHY_DRV_ODT_48 (48) +#define PHY_DRV_ODT_40 (40) +#define PHY_DRV_ODT_34_3 (34) + +#endif /* _DT_BINDINGS_DRAM_ROCKCHIP_RK3399_H */ diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h index 172744a72eb7..7b1656427cbe 100644 --- a/include/dt-bindings/net/ti-dp83867.h +++ b/include/dt-bindings/net/ti-dp83867.h @@ -42,4 +42,18 @@ #define DP83867_RGMIIDCTL_3_75_NS 0xe #define DP83867_RGMIIDCTL_4_00_NS 0xf +/* IO_MUX_CFG - Clock output selection */ +#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 +#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 +#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 +#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 +#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 +#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 +#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 +#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 +#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 +#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 +#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA +#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB +#define DP83867_CLK_O_SEL_REF_CLK 0xC #endif diff --git a/include/dt-bindings/pinctrl/rockchip-rk3036.h b/include/dt-bindings/pinctrl/rockchip-rk3036.h new file mode 100644 index 000000000000..553c33579065 --- /dev/null +++ b/include/dt-bindings/pinctrl/rockchip-rk3036.h @@ -0,0 +1,267 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_RK3036_H__ +#define __DT_BINDINGS_ROCKCHIP_PINCTRL_RK3036_H__ + + /* GPIO0_A */ + #define GPIO0_A0 0x0a00 + #define I2C0_SCL 0x0a01 + #define PWM1 0x0a02 + + #define GPIO0_A1 0x0a10 + #define I2C0_SDA 0x0a11 + #define PWM2 0x0a12 + + #define GPIO0_A2 0x0a20 + #define I2C1_SCL 0x0a21 + + #define GPIO0_A3 0x0a30 + #define I2C1_SDA 0x0a31 + + + /* GPIO0_B */ + #define GPIO0_B0 0x0b00 + #define MMC1_CMD 0x0b01 + #define I2S1_SDO 0x0b02 + + #define GPIO0_B1 0x0b10 + #define MMC1_CLKOUT 0x0b11 + #define I2S1_MCLK 0x0b12 + + #define GPIO0_B3 0x0b30 + #define MMC1_D0 0x0b31 + #define I2S1_LRCKRX 0x0b32 + + #define GPIO0_B4 0x0b40 + #define MMC1_D1 0x0b41 + #define I2S1_LRCKTX 0x0b42 + + #define GPIO0_B5 0x0b50 + #define MMC1_D2 0x0b51 + #define I2S1_SDI 0x0b52 + + #define GPIO0_B6 0x0b60 + #define MMC1_D3 0x0b61 + #define I2S1_SCLK 0x0b62 + + + /* GPIO0_C */ + #define GPIO0_C0 0x0c00 + #define UART0_SOUT 0x0c01 + + #define GPIO0_C1 0x0c10 + #define UART0_SIN 0x0c11 + + #define GPIO0_C2 0x0c20 + #define UART0_RTSN 0x0c21 + + #define GPIO0_C3 0x0c30 + #define UART0_CTSN 0x0c31 + + #define GPIO0_C4 0x0c40 + #define DRIVE_VBUS 0x0c41 + + + /* GPIO0_D */ + #define GPIO0_D2 0x0d20 + #define PWM0 0x0d21 + + #define GPIO0_D3 0x0d30 + #define PWM3(IR) 0x0d31 + + #define GPIO0_D4 0x0d40 + #define SPDIF_TX 0x0d41 + + + /* GPIO1_A */ + #define GPIO1_A0 0x1a00 + #define I2S0_MCLK 0x1a01 + + #define GPIO1_A1 0x1a10 + #define I2S0_SCLK 0x1a11 + + #define GPIO1_A2 0x1a20 + #define I2S0_LRCKRX 0x1a21 + #define PWM1_0 0x1a22 + + #define GPIO1_A3 0x1a30 + #define I2S0_LRCKTX 0x1a31 + + #define GPIO1_A4 0x1a40 + #define I2S0_SDO 0x1a41 + + #define GPIO1_A5 0x1a50 + #define I2S0_SDI 0x1a51 + + + /* GPIO1_B */ + #define GPIO1_B0 0x1b00 + #define HDMI_CEC 0x1b01 + + #define GPIO1_B1 0x1b10 + #define HDMI_SDA 0x1b11 + + #define GPIO1_B2 0x1b20 + #define HDMI_SCL 0x1b21 + + #define GPIO1_B3 0x1b30 + #define HDMI_HPD 0x1b31 + + #define GPIO1_B7 0x1b70 + #define MMC0_CMD 0x1b71 + + + /* GPIO1_C */ + #define GPIO1_C0 0x1c00 + #define MMC0_CLKOUT 0x1c01 + + #define GPIO1_C1 0x1c10 + #define MMC0_DETN 0x1c11 + + #define GPIO1_C2 0x1c20 + #define MMC0_D0 0x1c21 + #define UART2_SIN 0x1c22 + + #define GPIO1_C3 0x1c30 + #define MMC0_D1 0x1c31 + #define UART2_SOUT 0x1c32 + + #define GPIO1_C4 0x1c40 + #define MMC0_D2 0x1c41 + #define JTAG_TCK 0x1c42 + + #define GPIO1_C5 0x1c50 + #define MMC0_D3 0x1c51 + #define JTAG_TMS 0x1c52 + + + /* GPIO1_D */ + #define GPIO1_D0 0x1d00 + #define NAND_D0 0x1d01 + #define EMMC_D0 0x1d02 + #define SFC_SIO0 0x1d03 + + #define GPIO1_D1 0x1d10 + #define NAND_D1 0x1d11 + #define EMMC_D1 0x1d12 + #define SFC_SIO1 0x1d13 + + #define GPIO1_D2 0x1d20 + #define NAND_D2 0x1d21 + #define EMMC_D2 0x1d22 + #define SFC_SIO2 0x1d23 + + #define GPIO1_D3 0x1d30 + #define NAND_D3 0x1d31 + #define EMMC_D3 0x1d32 + #define SFC_SIO3 0x1d33 + + #define GPIO1_D4 0x1d40 + #define NAND_D4 0x1d41 + #define EMMC_D4 0x1d42 + #define SPI0_RXD 0x1d43 + + #define GPIO1_D5 0x1d50 + #define NAND_D5 0x1d51 + #define EMMC_D5 0x1d52 + #define SPI0_TXD 0x1d53 + + #define GPIO1_D6 0x1d60 + #define NAND_D6 0x1d61 + #define EMMC_D6 0x1d62 + #define SPI0_CS0 0x1d63 + + #define GPIO1_D7 0x1d70 + #define NAND_D7 0x1d71 + #define EMMC_D7 0x1d72 + #define SPI0_CS1 0x1d73 + + + /* GPIO2_A */ + #define GPIO2_A0 0x2a00 + #define NAND_ALE 0x2a01 + #define SPI0_CLK 0x2a02 + + #define GPIO2_A1 0x2a10 + #define NAND_CLE 0x2a11 + #define EMMC_CLKOUT 0x2a12 + + #define GPIO2_A2 0x2a20 + #define NAND_WRN 0x2a21 + #define SFC_CSN0 0x2a22 + + #define GPIO2_A3 0x2a30 + #define NAND_RDN 0x2a31 + #define SFC_CSN1 0x2a32 + + #define GPIO2_A4 0x2a40 + #define NAND_RDY 0x2a41 + #define EMMC_CMD 0x2a42 + #define SFC_CLK 0x2a43 + + #define GPIO2_A6 0x2a60 + #define NAND_CS0 0x2a61 + + #define GPIO2_A7 0x2a70 + #define TESTCLK_OUT 0x2a71 + + + /* GPIO2_B */ + #define GPIO2_B2 0x2b20 + #define MAC_CRS 0x2b21 + + #define GPIO2_B4 0x2b40 + #define MAC_MDIO 0x2b41 + + #define GPIO2_B5 0x2b50 + #define MAC_TXEN 0x2b51 + + #define GPIO2_B6 0x2b60 + #define MAC_CLKOUT 0x2b61 + #define MAC_CLKIN 0x2b62 + + #define GPIO2_B7 0x2b70 + #define MAC_RXER 0x2b71 + + + /* GPIO2_C */ + #define GPIO2_C0 0x2c00 + #define MAC_RXD1 0x2c01 + + #define GPIO2_C1 0x2c10 + #define MAC_RXD0 0x2c11 + + #define GPIO2_C2 0x2c20 + #define MAC_TXD1 0x2c21 + + #define GPIO2_C3 0x2c30 + #define MAC_TXD0 0x2c31 + + #define GPIO2_C4 0x2c40 + #define I2C2_SDA 0x2c41 + + #define GPIO2_C5 0x2c50 + #define I2C2_SCL 0x2c51 + + #define GPIO2_C6 0x2c60 + #define UART1_SIN 0x2c61 + + #define GPIO2_C7 0x2c70 + #define UART1_SOUT 0x2c71 + #define TESTCLK_OUT1 0x2c72 + + + /* GPIO2_D */ + #define GPIO2_D1 0x2d10 + #define MAC_MDC 0x2d11 + + #define GPIO2_D4 0x2d40 + #define I2S0_SDO3 0x2d41 + + #define GPIO2_D5 0x2d50 + #define I2S0_SDO2 0x2d51 + + #define GPIO2_D6 0x2d60 + #define I2S0_SDO1 0x2d61 + + +#endif diff --git a/include/dt-bindings/pinctrl/rockchip-rk312x.h b/include/dt-bindings/pinctrl/rockchip-rk312x.h new file mode 100644 index 000000000000..e0fa5976c18f --- /dev/null +++ b/include/dt-bindings/pinctrl/rockchip-rk312x.h @@ -0,0 +1,384 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_RK312X_H__ +#define __DT_BINDINGS_ROCKCHIP_PINCTRL_RK312X_H__ + +/* GPIO0_A */ +#define GPIO0_A0 0x0a00 +#define I2C0_SCL 0x0a01 + +#define GPIO0_A1 0x0a10 +#define I2C0_SDA 0x0a11 + +#define GPIO0_A2 0x0a20 +#define I2C1_SCL 0x0a21 + +#define GPIO0_A3 0x0a30 +#define I2C1_SDA 0x0a31 +#define MMC1_CMD 0x0a32 + +#define GPIO0_A6 0x0a60 +#define I2C3_SCL 0x0a61 +#define HDMI_DSCL 0x0a62 + +#define GPIO0_A7 0x0a70 +#define I2C3_SDA 0x0a71 +#define HDMI_DSDA 0x0a72 + + +/* GPIO0_B */ +#define GPIO0_B0 0x0b00 +#define I2S0_MCLK_MUX0 0x0b01 + +#define GPIO0_B1 0x0b10 +#define I2S0_SCLK_MUX0 0x0b11 +#define SPI0_CLK_MUX2 0x0b12 + +#define GPIO0_B3 0x0b30 +#define I2S0_LRCKRX_MUX0 0x0b31 +#define SPI0_TXD_MUX2 0x0b32 + +#define GPIO0_B4 0x0b40 +#define I2S0_LRCKTX_MUX0 0x0b41 + +#define GPIO0_B5 0x0b50 +#define I2S0_SDO_MUX0 0x0b51 +#define SPI0_RXD_MUX2 0x0b52 + +#define GPIO0_B6 0x0b60 +#define I2S0_SDI_MUX0 0x0b61 +#define SPI0_CS0_MUX2 0x0b62 + +#define GPIO0_B7 0x0b70 +#define HDMI_HPD 0x0b71 + + +/* GPIO0_C */ +#define GPIO0_C1 0x0c10 +#define SC_IO 0x0c11 +#define UART0_RTSN 0x0c12 + +#define GPIO0_C4 0x0c40 +#define HDMI_CEC 0x0c41 + +#define GPIO0_C7 0x0c70 +#define NAND_CS1 0x0c71 + + +/* GPIO0_D */ +#define GPIO0_D0 0x0d00 +#define UART2_RTSN 0x0d01 +#define PMIC_SLEEP_MUX0 0x0d02 + +#define GPIO0_D1 0x0d10 +#define UART2_CTSN 0x0d11 + +#define GPIO0_D2 0x0d20 +#define PWM0 0x0d21 + +#define GPIO0_D3 0x0d30 +#define PWM1 0x0d31 + +#define GPIO0_D4 0x0d40 +#define PWM2 0x0d41 + +#define GPIO0_D6 0x0d60 +#define MMC1_PWREN 0x0d61 + + +/* GPIO1_A */ +#define GPIO1_A0 0x1a00 +#define I2S0_MCLK_MUX1 0x1a01 +#define SDMMC_CLKOUT 0x1a02 +#define XIN32K 0x1a03 + +#define GPIO1_A1 0x1a10 +#define I2S0_SCLK_MUX1 0x1a11 +#define SDMMC_DATA0 0x1a12 +#define PMIC_SLEEP_MUX1 0x1a13 + +#define GPIO1_A2 0x1a20 +#define I2S0_LRCKRX_MUX1 0x1a21 +#define SDMMC_DATA1 0x1a22 + +#define GPIO1_A3 0x1a30 +#define I2S0_LRCKTX_MUX1 0x1a31 + +#define GPIO1_A4 0x1a40 +#define I2S0_SDO_MUX1 0x1a41 +#define SDMMC_DATA2 0x1a42 + +#define GPIO1_A5 0x1a50 +#define I2S0_SDI_MUX1 0x1a51 +#define SDMMC_DATA3 0x1a52 + +#define GPIO1_A7 0x1a70 +#define MMC0_WRPRT 0x1a71 + + +/* GPIO1_B */ +#define GPIO1_B0 0x1b00 +#define SPI0_CLK_MUX0 0x1b01 +#define UART1_CTSN 0x1b02 + +#define GPIO1_B1 0x1b10 +#define SPI0_TXD_MUX0 0x1b11 +#define UART1_SOUT 0x1b12 + +#define GPIO1_B2 0x1b20 +#define SPI0_RXD_MUX0 0x1b21 +#define UART1_SIN 0x1b22 + +#define GPIO1_B3 0x1b30 +#define SPI0_CS0_MUX0 0x1b31 +#define UART1_RTSN 0x1b32 + +#define GPIO1_B4 0x1b40 +#define SPI0_CS1_MUX0 0x1b41 + +#define GPIO1_B6 0x1b60 +#define MMC0_PWREN 0x1b61 + +#define GPIO1_B7 0x1b70 +#define MMC0_CMD 0x1b71 + + +/* GPIO1_C */ +#define GPIO1_C0 0x1c00 +#define MMC0_CLKOUT 0x1c01 + +#define GPIO1_C1 0x1c10 +#define MMC0_DETN 0x1c11 + +#define GPIO1_C2 0x1c20 +#define MMC0_D0 0x1c21 +#define UART2_SOUT 0x1c22 + +#define GPIO1_C3 0x1c30 +#define MMC0_D1 0x1c31 +#define UART2_SIN 0x1c32 + +#define GPIO1_C4 0x1c40 +#define MMC0_D2 0x1c41 +#define JTAG_TCK 0x1c42 + +#define GPIO1_C5 0x1c50 +#define MMC0_D3 0x1c51 +#define JTAG_TMS 0x1c52 + +#define GPIO1_C6 0x1c60 +#define NAND_CS2 0x1c61 +#define EMMC_CMD_MUX0 0x1c62 + +#define GPIO1_C7 0x1c70 +#define NAND_CS3 0x1c71 +#define EMMC_RSTNOUT 0x1c72 + + +/* GPIO1_D */ +#define GPIO1_D0 0x1d00 +#define NAND_D0 0x1d01 +#define EMMC_D0 0x1d02 +#define SFC_D0 0x1d03 + +#define GPIO1_D1 0x1d10 +#define NAND_D1 0x1d11 +#define EMMC_D1 0x1d12 +#define SFC_D1 0x1d13 + +#define GPIO1_D2 0x1d20 +#define NAND_D2 0x1d21 +#define EMMC_D2 0x1d22 +#define SFC_D2 0x1d23 + +#define GPIO1_D3 0x1d30 +#define NAND_D3 0x1d31 +#define EMMC_D3 0x1d32 +#define SFC_D3 0x1d33 + +#define GPIO1_D4 0x1d40 +#define NAND_D4 0x1d41 +#define EMMC_D4 0x1d42 +#define SPI0_RXD_MUX1 0x1d43 + +#define GPIO1_D5 0x1d50 +#define NAND_D5 0x1d51 +#define EMMC_D5 0x1d52 +#define SPI0_TXD_MUX1 0x1d53 + +#define GPIO1_D6 0x1d60 +#define NAND_D6 0x1d61 +#define EMMC_D6 0x1d62 +#define SPI0_CS0_MUX1 0x1d63 + +#define GPIO1_D7 0x1d70 +#define NAND_D7 0x1d71 +#define EMMC_D7 0x1d72 +#define SPI0_CS1_MUX1 0x1d73 + + +/* GPIO2_A */ +#define GPIO2_A0 0x2a00 +#define NAND_ALE 0x2a01 +#define SPI0_CLK_MUX1 0x2a02 + +#define GPIO2_A1 0x2a10 +#define NAND_CLE 0x2a11 + +#define GPIO2_A2 0x2a20 +#define NAND_WRN 0x2a21 +#define SFC_CSN0 0x2a22 + +#define GPIO2_A3 0x2a30 +#define NAND_RDN 0x2a31 +#define SFC_CSN1 0x2a32 + +#define GPIO2_A4 0x2a40 +#define NAND_RDY 0x2a41 +#define EMMC_CMD_MUX1 0x2a42 +#define SFC_CLK 0x2a43 + +#define GPIO2_A5 0x2a50 +#define NAND_WP 0x2a51 +#define EMMC_PWREN 0x2a52 + +#define GPIO2_A6 0x2a60 +#define NAND_CS0 0x2a61 + +#define GPIO2_A7 0x2a70 +#define NAND_DQS 0x2a71 +#define EMMC_CLKOUT 0x2a72 + + +/* GPIO2_B */ +#define GPIO2_B0 0x2b00 +#define LCDC0_DCLK 0x2b01 +#define EBC_SDCLK 0x2b02 +#define GMAC_RXDV 0x2b03 + +#define GPIO2_B1 0x2b10 +#define LCDC0_HSYNC 0x2b11 +#define EBC_SDLE 0x2b12 +#define GMAC_TXCLK 0x2b13 + +#define GPIO2_B2 0x2b20 +#define LCDC0_VSYNC 0x2b21 +#define EBC_SDOE 0x2b22 +#define GMAC_CRS 0x2b23 + +#define GPIO2_B3 0x2b30 +#define LCDC0_DEN 0x2b31 +#define EBC_GDCLK 0x2b32 +#define GMAC_RXCLK 0x2b33 + +#define GPIO2_B4 0x2b40 +#define LCDC0_D10 0x2b41 +#define EBC_SDCE2 0x2b42 +#define GMAC_MDIO 0x2b43 + +#define GPIO2_B5 0x2b50 +#define LCDC0_D11 0x2b51 +#define EBC_SDCE3 0x2b52 +#define GMAC_TXEN 0x2b53 + +#define GPIO2_B6 0x2b60 +#define LCDC0_D12 0x2b61 +#define EBC_SDCE4 0x2b62 +#define GMAC_CLK 0x2b63 + +#define GPIO2_B7 0x2b70 +#define LCDC0_D13 0x2b71 +#define EBC_SDCE5 0x2b72 +#define GMAC_RXER 0x2b73 + + +/* GPIO2_C */ +#define GPIO2_C0 0x2c00 +#define LCDC0_D14 0x2c01 +#define EBC_VCOM 0x2c02 +#define GMAC_RXD1 0x2c03 + +#define GPIO2_C1 0x2c10 +#define LCDC0_D15 0x2c11 +#define EBC_GDOE 0x2c12 +#define GMAC_RXD0 0x2c13 + +#define GPIO2_C2 0x2c20 +#define LCDC0_D16 0x2c21 +#define EBC_GDSP 0x2c22 +#define GMAC_TXD1 0x2c23 + +#define GPIO2_C3 0x2c30 +#define LCDC0_D17 0x2c31 +#define EBC_GDPWR0 0x2c32 +#define GMAC_TXD0 0x2c33 + +#define GPIO2_C4 0x2c40 +#define LCDC0_D18 0x2c41 +#define EBC_GDRL 0x2c42 +#define I2C2_SDA 0x2c43 +#define GMAC_RXD3 0x2c44 + +#define GPIO2_C5 0x2c50 +#define LCDC0_D19 0x2c51 +#define EBC_SDSHR 0x2c52 +#define I2C2_SCL 0x2c53 +#define GMAC_RXD2 0x2c54 + +#define GPIO2_C6 0x2c60 +#define LCDC0_D20 0x2c61 +#define EBC_BORDER0 0x2c62 +#define GPS_SIGN 0x2c63 +#define GMAC_TXD2 0x2c64 + +#define GPIO2_C7 0x2c70 +#define LCDC0_D21 0x2c71 +#define EBC_BORDER1 0x2c72 +#define GPS_MAG 0x2c73 +#define GMAC_TXD3 0x2c74 + + +/* GPIO2_D */ +#define GPIO2_D0 0x2d00 +#define LCDC0_D22 0x2d01 +#define EBC_GDPWR1 0x2d02 +#define GPS_CLK 0x2d03 +#define GMAC_COL 0x2d04 + +#define GPIO2_D1 0x2d10 +#define LCDC0_D23 0x2d11 +#define EBC_GDPWR2 0x2d12 +#define GMAC_MDC 0x2d13 + +#define GPIO2_D2 0x2d20 +#define SC_RST 0x2d21 +#define UART0_SOUT 0x2d22 + +#define GPIO2_D3 0x2d30 +#define SC_CLK 0x2d31 +#define UART0_SIN 0x2d32 + +#define GPIO2_D5 0x2d50 +#define SC_DET 0x2d51 +#define UART0_CTSN 0x2d52 + + +/* GPIO3_A */ +/* GPIO3_B */ +#define GPIO3_B3 0x3b30 +#define TESTCLK_OUT 0x3b31 + + +/* GPIO3_C */ +#define GPIO3_C1 0x3c10 +#define OTG_DRVVBUS 0x3c11 + + +/* GPIO3_D */ +#define GPIO3_D2 0x3d20 +#define PWM_IRIN 0x3d21 + +#define GPIO3_D3 0x3d30 +#define SPDIF_TX 0x3d31 + + +#endif diff --git a/include/dt-bindings/pinctrl/rockchip-rk3188.h b/include/dt-bindings/pinctrl/rockchip-rk3188.h new file mode 100755 index 000000000000..58bba225d1de --- /dev/null +++ b/include/dt-bindings/pinctrl/rockchip-rk3188.h @@ -0,0 +1,457 @@ +/* + * Header providing constants for Rockchip pinctrl bindings. + * + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_RK3188_H__ +#define __DT_BINDINGS_ROCKCHIP_PINCTRL_RK3188_H__ + + +/* GPIO0_A */ +#define GPIO0_A0 0x0A00 +#define GPIO0_A1 0x0A10 + +/* GPIO0_B */ +/* GPIO0_C */ +#define GPIO0_C0 0x0c00 +#define NAND_D8 0x0c01 + +#define GPIO0_C1 0x0c10 +#define NAND_D9 0x0c11 + +#define GPIO0_C2 0x0c20 +#define NAND_D10 0x0c21 + +#define GPIO0_C3 0x0c30 +#define NAND_D11 0x0c31 + +#define GPIO0_C4 0x0c40 +#define NAND_D12 0x0c41 + +#define GPIO0_C5 0x0c50 +#define NAND_D13 0x0c51 + +#define GPIO0_C6 0x0c60 +#define NAND_D14 0x0c61 + +#define GPIO0_C7 0x0c70 +#define NAND_D15 0x0c71 + + +/* GPIO0_D */ +#define GPIO0_D0 0x0d00 +#define NAND_DQS 0x0d01 +#define EMMC_CLKOUT 0x0d02 + +#define GPIO0_D1 0x0d10 +#define NAND_CS1 0x0d11 + +#define GPIO0_D2 0x0d20 +#define NAND_CS2 0x0d21 +#define EMMC_CMD 0x0d22 + +#define GPIO0_D3 0x0d30 +#define NAND_CS3 0x0d31 +#define EMMC_RSTNOUT 0x0d32 + +#define GPIO0_D4 0x0d40 +#define SPI1_RXD 0x0d41 + +#define GPIO0_D5 0x0d50 +#define SPI1_TXD 0x0d51 + +#define GPIO0_D6 0x0d60 +#define SPI1_CLK 0x0d61 + +#define GPIO0_D7 0x0d70 +#define SPI1_CS0 0x0d71 + + +/* GPIO1_A */ +#define GPIO1_A0 0x1a00 +#define UART0_SIN 0x1a01 + +#define GPIO1_A1 0x1a10 +#define UART0_SOUT 0x1a11 + +#define GPIO1_A2 0x1a20 +#define UART0_CTSN 0x1a21 + +#define GPIO1_A3 0x1a30 +#define UART0_RTSN 0x1a31 + +#define GPIO1_A4 0x1a40 +#define UART1_SIN 0x1a41 +#define SPI0_RXD 0x1a42 + +#define GPIO1_A5 0x1a50 +#define UART1_SOUT 0x1a51 +#define SPI0_TXD 0x1a52 + +#define GPIO1_A6 0x1a60 +#define UART1_CTSN 0x1a61 +#define SPI0_CLK 0x1a62 + +#define GPIO1_A7 0x1a70 +#define UART1_RTSN 0x1a71 +#define SPI0_CS0 0x1a72 + +/* GPIO1_B */ +#define GPIO1_B0 0x1b00 +#define UART2_SIN 0x1b01 +#define JTAG_TDI 0x1b02 + +#define GPIO1_B1 0x1b10 +#define UART2_SOUT 0x1b11 +#define JTAG_TDO 0x1b12 + +#define GPIO1_B2 0x1b20 +#define UART3_SIN 0x1b21 +#define GPS_MAG 0x1b22 + +#define GPIO1_B3 0x1b30 +#define UART3_SOUT 0x1b31 +#define GPS_SIG 0x1b32 + +#define GPIO1_B4 0x1b40 +#define UART3_CTSN 0x1b41 +#define GPS_RFCLK 0x1b42 + +#define GPIO1_B5 0x1b50 +#define UART3_RTSN 0x1b51 + +#define GPIO1_B6 0x1b60 +#define SPDIF_TX 0x1b61 +#define SPI1_CS1 0x1b62 + +#define GPIO1_B7 0x1b70 +#define SPI0_CS1 0x1b71 + + +/* GPIO1_C */ +#define GPIO1_C0 0x1c00 +#define I2S0_MCLK 0x1c01 + +#define GPIO1_C1 0x1c10 +#define I2S0_SCLK 0x1c11 + +#define GPIO1_C2 0x1c20 +#define I2S0_LRCKRX 0x1c21 + +#define GPIO1_C3 0x1c30 +#define I2S0_LRCKTX 0x1c31 + +#define GPIO1_C4 0x1c40 +#define I2S0_SDI 0x1c41 + +#define GPIO1_C5 0x1c50 +#define I2S0_SDO 0x1c51 + + +/* GPIO1_D */ +#define GPIO1_D0 0x1d00 +#define I2C0_SDA 0x1d01 + +#define GPIO1_D1 0x1d10 +#define I2C0_SCL 0x1d11 + +#define GPIO1_D2 0x1d20 +#define I2C1_SDA 0x1d21 + +#define GPIO1_D3 0x1d30 +#define I2C1_SCL 0x1d31 + +#define GPIO1_D4 0x1d40 +#define I2C2_SDA 0x1d41 + +#define GPIO1_D5 0x1d50 +#define I2C2_SCL 0x1d51 + +#define GPIO1_D6 0x1d60 +#define I2C4_SDA 0x1d61 + +#define GPIO1_D7 0x1d70 +#define I2C4_SCL 0x1d71 + + +/* GPIO2_A */ +#define GPIO2_A0 0x2a00 +#define LCDC1_D0 0x2a01 +#define SMC_D0 0x2a02 +#define TRACE_D0 0x2a03 + +#define GPIO2_A1 0x2a10 +#define LCDC1_D1 0x2a11 +#define SMC_D1 0x2a12 +#define TRACE_D1 0x2a13 + +#define GPIO2_A2 0x2a20 +#define LCDC1_D2 0x2a21 +#define SMC_D2 0x2a22 +#define TRACE_D2 0x2a23 + +#define GPIO2_A3 0x2a30 +#define LCDC1_D3 0x2a31 +#define SMC_D3 0x2a32 +#define TRACE_D3 0x2a33 + +#define GPIO2_A4 0x2a40 +#define LCDC1_D4 0x2a41 +#define SMC_D4 0x2a42 +#define TRACE_D4 0x2a43 + +#define GPIO2_A5 0x2a50 +#define LCDC1_D5 0x2a51 +#define SMC_D5 0x2a52 +#define TRACE_D5 0x2a53 + +#define GPIO2_A6 0x2a60 +#define LCDC1_D6 0x2a61 +#define SMC_D6 0x2a62 +#define TRACE_D6 0x2a63 + +#define GPIO2_A7 0x2a70 +#define LCDC1_D7 0x2a71 +#define SMC_D7 0x2a72 +#define TRACE_D7 0x2a73 + + +/* GPIO2_B */ +#define GPIO2_B0 0x2b00 +#define LCDC1_D8 0x2b01 +#define SMC_D8 0x2b02 +#define TRACE_D8 0x2b03 + +#define GPIO2_B1 0x2b10 +#define LCDC1_D9 0x2b11 +#define SMC_D9 0x2b11 +#define TRACE_D9 0x2b12 + +#define GPIO2_B2 0x2b20 +#define LCDC1_D10 0x2b21 +#define SMC_D10 0x2b22 +#define TRACE_D10 0x2b23 + +#define GPIO2_B3 0x2b30 +#define LCDC1_D11 0x2b31 +#define SMC_D11 0x2b32 +#define TRACE_D11 0x2b33 + +#define GPIO2_B4 0x2b40 +#define LCDC1_D12 0x2b41 +#define SMC_D12 0x2b42 +#define TRACE_D12 0x2b43 + +#define GPIO2_B5 0x2b50 +#define LCDC1_D13 0x2b51 +#define SMC_D13 0x2b52 +#define TRACE_D13 0x2b53 + +#define GPIO2_B6 0x2b60 +#define LCDC1_D14 0x2b61 +#define SMC_D14 0x2b62 +#define TRACE_D14 0x2b63 + + +#define GPIO2_B7 0x2b70 +#define LCDC1_D15 0x2b71 +#define SMC_D15 0x2b72 +#define TRACE_D15 0x2b73 + + +/* GPIO2_C */ +#define GPIO2_C0 0x2c00 +#define LCDC1_D16 0x2c01 +#define SMC_R0 0x2c02 +#define TRACE_CLK 0x2c03 + +#define GPIO2_C1 0x2c10 +#define LCDC1_D17 0x2c11 +#define SMC_R1 0x2c12 +#define TRACE_CTL 0x2c13 + +#define GPIO2_C2 0x2c20 +#define LCDC1_D18 0x2c21 +#define SMC_R2 0x2c22 + +#define GPIO2_C3 0x2c30 +#define LCDC1_D19 0x2c31 +#define SMC_R3 0x2c32 + +#define GPIO2_C4 0x2c40 +#define LCDC1_D20 0x2c41 +#define SMC_R4 0x2c42 + +#define GPIO2_C5 0x2c50 +#define LCDC1_D21 0x2c51 +#define SMC_R5 0x2c52 + +#define GPIO2_C6 0x2c60 +#define LCDC1_D22 0x2c61 +#define SMC_R6 0x2c62 + +#define GPIO2_C7 0x2c70 +#define LCDC1_D23 0x2c71 +#define SMC_R7 0x2c72 + + +/* GPIO2_D */ +#define GPIO2_D0 0x2d00 +#define LCDC1_DCLK 0x2d01 +#define SMC_CS0 0x2d02 + +#define GPIO2_D1 0x2d10 +#define LCDC1_DEN 0x2d11 +#define SMC_WEN 0x2d12 + +#define GPIO2_D2 0x2d20 +#define LCDC1_HSYNC 0x2d21 +#define SMC_OEN 0x2d22 + +#define GPIO2_D3 0x2d30 +#define LCDC1_VSYNC 0x2d31 +#define SMC_ADVN 0x2d32 + +#define GPIO2_D4 0x2d40 +#define SMC_BLSN0 0x2d41 + +#define GPIO2_D5 0x2d50 +#define SMC_BLSN1 0x2d51 + +#define GPIO2_D6 0x2d60 +#define SMC_CS1 0x2d61 + +#define GPIO2_D7 0x2d70 +#define TEST_CLK_OUT 0x2d71 + + +/* GPIO3_A */ +#define GPIO3_A0 0x3a00 +#define MMC0_RSTNOUT 0x3a01 + +#define GPIO3_A1 0x3a10 +#define MMC0_PWREN 0x3a11 + +#define GPIO3_A2 0x3a20 +#define MMC0_CLKOUT 0x3a21 + +#define GPIO3_A3 0x3a30 +#define MMC0_CMD 0x3a31 + +#define GPIO3_A4 0x3a40 +#define MMC0_D0 0x3a41 + +#define GPIO3_A5 0x3a50 +#define MMC0_D1 0x3a51 + +#define GPIO3_A6 0x3a60 +#define MMC0_D2 0x3a61 + +#define GPIO3_A7 0x3a70 +#define MMC0_D3 0x3a71 + + +/* GPIO3_B */ +#define GPIO3_B0 0x3b00 +#define MMC0_DETN 0x3b01 + +#define GPIO3_B1 0x3b10 +#define MMC0_WRPRT 0x3b11 + +#define GPIO3_B3 0x3b30 +#define CIF0_CLKOUT 0x3b31 + +#define GPIO3_B4 0x3b40 +#define CIF0_D0 0x3b41 +#define HSADC_D8 0x3b42 + +#define GPIO3_B5 0x3b50 +#define CIF0_D1 0x3b51 +#define HSADC_D9 0x3b52 + +#define GPIO3_B6 0x3b60 +#define CIF0_D10 0x3b61 +#define I2C3_SDA 0x3b62 + +#define GPIO3_B7 0x3b70 +#define CIF0_D11 0x3b71 +#define I2C3_SCL 0x3b72 + + +/* GPIO3_C */ +#define GPIO3_C0 0x3c00 +#define MMC1_CMD 0x3c01 +#define RMII_TXEN 0x3c02 + +#define GPIO3_C1 0x3c10 +#define MMC1_D0 0x3c11 +#define RMII_TXD1 0x3c12 + +#define GPIO3_C2 0x3c20 +#define MMC1_D1 0x3c21 +#define RMII_TXD0 0x3c22 + +#define GPIO3_C3 0x3c30 +#define MMC1_D2 0x3c31 +#define RMII_RXD0 0x3c32 + +#define GPIO3_C4 0x3c40 +#define MMC1_D3 0x3c41 +#define RMII_RXD1 0x3c42 + +#define GPIO3_C5 0x3c50 +#define MMC1_CLKOUT 0x3c51 +#define RMII_CLKOUT 0x3c52 +#define RMII_CLKIN 0x3c52 + +#define GPIO3_C6 0x3c60 +#define MMC1_DETN 0x3c61 +#define RMII_RXERR 0x3c62 + +#define GPIO3_C7 0x3c70 +#define MMC1_WRPRT 0x3c71 +#define RMII_CRS 0x3c72 + + +/* GPIO3_D */ +#define GPIO3_D0 0x3d00 +#define MMC1_PWREN 0x3d01 +#define RMII_MD 0x3d02 + +#define GPIO3_D1 0x3d10 +#define MMC1_BKEPWR 0x3d11 +#define RMII_MDCLK 0x3d12 + +#define GPIO3_D2 0x3d20 +#define MMC1_INTN 0x3d21 + +#define GPIO3_D3 0x3d30 +#define PWM0 0x3d31 + +#define GPIO3_D4 0x3d40 +#define PWM1 0x3d41 +#define JTAG_TRSTN 0x3d42 + +#define GPIO3_D5 0x3d50 +#define PWM2 0x3d51 +#define JTAG_TCK 0x3d52 +#define OTG_DRV_VBUS 0x3d53 + +#define GPIO3_D6 0x3d60 +#define PWM3 0x3d61 +#define JTAG_TMS 0x3d62 +#define HOST_DRV_VBUS 0x3d63 + +#endif diff --git a/include/dt-bindings/pinctrl/rockchip-rk3288.h b/include/dt-bindings/pinctrl/rockchip-rk3288.h new file mode 100755 index 000000000000..97aa66e2b329 --- /dev/null +++ b/include/dt-bindings/pinctrl/rockchip-rk3288.h @@ -0,0 +1,666 @@ +/* + * Header providing constants for Rockchip pinctrl bindings. + * + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_RK3288_H__ +#define __DT_BINDINGS_ROCKCHIP_PINCTRL_RK3288_H__ + +/* GPIO0_A */ +#define GPIO0_A0 0x0a00 +#define GLOBAL_PWROFF 0x0a01 + +#define GPIO0_A1 0x0a10 +#define DDRIO_PWROFF 0x0a11 + +#define GPIO0_A2 0x0a20 +#define DDR0_RETENTION 0x0a21 + +#define GPIO0_A3 0x0a30 +#define DDR1_RETENTION 0x0a31 + +#define GPIO0_A4 0x0a40 + +#define GPIO0_A5 0x0a50 + +#define GPIO0_A6 0x0a60 + +#define GPIO0_A7 0x0a70 + +/* GPIO0_B */ +#define GPIO0_B0 0x0b00 + +#define GPIO0_B1 0x0b10 + +#define GPIO0_B2 0x0b20 +#define TSADC_INT 0x0b21 + +#define GPIO0_B3 0x0b30 + +#define GPIO0_B4 0x0b40 + +#define GPIO0_B5 0x0b50 +#define CLK_27M 0x0b51 + +#define GPIO0_B6 0x0b60 + +#define GPIO0_B7 0x0b70 +#define I2C0PMU_SDA 0x0b71 + + +/* GPIO0_C */ +#define GPIO0_C0 0x0c00 +#define I2C0PMU_SCL 0x0c01 + +#define GPIO0_C1 0x0c10 +#define TEST_CLKOUT 0x0c11 +#define CLKT1_27M 0x0c12 + +#define GPIO0_C2 0x0c20 + + +/* GPIO1_A */ +/* GPIO1_B */ +/* GPIO1_C */ +/* GPIO1_D */ +#define GPIO1_D0 0x1d00 +#define LCDC0_HSYNC_GPIO1D 0x1d01 + +#define GPIO1_D1 0x1d10 +#define LCDC0_VSYNC_GPIO1D 0x1d11 + +#define GPIO1_D2 0x1d20 +#define LCDC0_DEN_GPIO1D 0x1d21 + +#define GPIO1_D3 0x1d30 +#define LCDC0_DCLK_GPIO1D 0x1d31 + + +/* GPIO2_A */ +#define GPIO2_A0 0x2a00 +#define CIF_DATA2 0x2a01 +#define HOST_DIN0 0x2a02 +#define HSADC_DATA0 0x2a03 + +#define GPIO2_A1 0x2a10 +#define CIF_DATA3 0x2a11 +#define HOST_DIN1 0x2a12 +#define HSADC_DATA1 0x2a13 + +#define GPIO2_A2 0x2a20 +#define CIF_DATA4 0x2a21 +#define HOST_DIN2 0x2a22 +#define HSADC_DATA2 0x2a23 + +#define GPIO2_A3 0x2a30 +#define CIF_DATA5 0x2a31 +#define HOST_DIN3 0x2a32 +#define HSADC_DATA3 0x2a33 + +#define GPIO2_A4 0x2a40 +#define CIF_DATA6 0x2a41 +#define HOST_CKINP 0x2a42 +#define HSADC_DATA4 0x2a43 + +#define GPIO2_A5 0x2a50 +#define CIF_DATA7 0x2a51 +#define HOST_CKINN 0x2a52 +#define HSADC_DATA5 0x2a53 + +#define GPIO2_A6 0x2a60 +#define CIF_DATA8 0x2a61 +#define HOST_DIN4 0x2a62 +#define HSADC_DATA6 0x2a63 + +#define GPIO2_A7 0x2a70 +#define CIF_DATA9 0x2a71 +#define HOST_DIN5 0x2a72 +#define HSADC_DATA7 0x2a73 + + +/* GPIO2_B */ +#define GPIO2_B0 0x2b00 +#define CIF_VSYNC 0x2b01 +#define HOST_DIN6 0x2b02 +#define HSADCTS_SYNC 0x2b03 + +#define GPIO2_B1 0x2b10 +#define CIF_HREF 0x2b11 +#define HOST_DIN7 0x2b12 +#define HSADCTS_VALID 0x2b13 + +#define GPIO2_B2 0x2b20 +#define CIF_CLKIN 0x2b21 +#define HOST_WKACK 0x2b22 +#define GPS_CLK 0x2b23 + +#define GPIO2_B3 0x2b30 +#define CIF_CLKOUT 0x2b31 +#define HOST_WKREQ 0x2b32 +#define HSADCTS_FAIL 0x2b33 + +#define GPIO2_B4 0x2b40 +#define CIF_DATA0 0x2b41 + +#define GPIO2_B5 0x2b50 +#define CIF_DATA1 0x2b51 + +#define GPIO2_B6 0x2b60 +#define CIF_DATA10 0x2b61 + +#define GPIO2_B7 0x2b70 +#define CIF_DATA11 0x2b71 + + +/* GPIO2_C */ +#define GPIO2_C0 0x2c00 +#define I2C3CAM_SCL 0x2c01 + +#define GPIO2_C1 0x2c10 +#define I2C3CAM_SDA 0x2c11 + + +/* GPIO2_D */ +/* GPIO3_A */ +#define GPIO3_A0 0x3a00 +#define FLASH0_DATA0 0x3a01 +#define EMMC_DATA0 0x3a02 + +#define GPIO3_A1 0x3a10 +#define FLASH0_DATA1 0x3a11 +#define EMMC_DATA1 0x3a12 + +#define GPIO3_A2 0x3a20 +#define FLASH0_DATA2 0x3a21 +#define EMMC_DATA2 0x3a22 + +#define GPIO3_A3 0x3a30 +#define FLASH0_DATA3 0x3a31 +#define EMMC_DATA3 0x3a32 + +#define GPIO3_A4 0x3a40 +#define FLASH0_DATA4 0x3a41 +#define EMMC_DATA4 0x3a42 + +#define GPIO3_A5 0x3a50 +#define FLASH0_DATA5 0x3a51 +#define EMMC_DATA5 0x3a52 + +#define GPIO3_A6 0x3a60 +#define FLASH0_DATA6 0x3a61 +#define EMMC_DATA6 0x3a62 + +#define GPIO3_A7 0x3a70 +#define FLASH0_DATA7 0x3a71 +#define EMMC_DATA7 0x3a72 + + +/* GPIO3_B */ +#define GPIO3_B0 0x3b00 +#define FLASH0_RDY 0x3b01 + +#define GPIO3_B1 0x3b10 +#define FLASH0_WP 0x3b11 +#define EMMC_PWREN 0x3b12 + +#define GPIO3_B2 0x3b20 +#define FLASH0_RDN 0x3b21 + +#define GPIO3_B3 0x3b30 +#define FLASH0_ALE 0x3b31 + +#define GPIO3_B4 0x3b40 +#define FLASH0_CLE 0x3b41 + +#define GPIO3_B5 0x3b50 +#define FLASH0_WRN 0x3b51 + +#define GPIO3_B6 0x3b60 +#define FLASH0_CSN0 0x3b61 + +#define GPIO3_B7 0x3b70 +#define FLASH0_CSN1 0x3b71 + + +/* GPIO3_C */ +#define GPIO3_C0 0x3c00 +#define FLASH0_CSN2 0x3c01 +#define EMMC_CMD 0x3c02 + +#define GPIO3_C1 0x3c10 +#define FLASH0_CSN3 0x3c11 +#define EMMC_RSTNOUT 0x3c12 + +#define GPIO3_C2 0x3c20 +#define FLASH0_DQS 0x3c21 +#define EMMC_CLKOUT 0x3c22 + + +/* GPIO3_D */ +#define GPIO3_D0 0x3d00 +#define FLASH1_DATA0 0x3d01 +#define HOST_DOUT0 0x3d02 +#define MAC_TXD2 0x3d03 +#define SDIO1_DATA0 0x3d04 + +#define GPIO3_D1 0x3d10 +#define FLASH1_DATA1 0x3d11 +#define HOST_DOUT1 0x3d12 +#define MAC_TXD3 0x3d13 +#define SDIO1_DATA1 0x3d14 + +#define GPIO3_D2 0x3d20 +#define FLASH1_DATA2 0x3d21 +#define HOST_DOUT2 0x3d22 +#define MAC_RXD2 0x3d23 +#define SDIO1_DATA2 0x3d24 + +#define GPIO3_D3 0x3d30 +#define FLASH1_DATA3 0x3d31 +#define HOST_DOUT3 0x3d32 +#define MAC_RXD3 0x3d33 +#define SDIO1_DATA3 0x3d34 + +#define GPIO3_D4 0x3d40 +#define FLASH1_DATA4 0x3d41 +#define HOST_DOUT4 0x3d42 +#define MAC_TXD0 0x3d43 +#define SDIO1_DETECTN 0x3d44 + +#define GPIO3_D5 0x3d50 +#define FLASH1_DATA5 0x3d51 +#define HOST_DOUT5 0x3d52 +#define MAC_TXD1 0x3d53 +#define SDIO1_WRPRT 0x3d54 + +#define GPIO3_D6 0x3d60 +#define FLASH1_DATA6 0x3d61 +#define HOST_DOUT6 0x3d62 +#define MAC_RXD0 0x3d63 +#define SDIO1_BKPWR 0x3d64 + +#define GPIO3_D7 0x3d70 +#define FLASH1_DATA7 0x3d71 +#define HOST_DOUT7 0x3d72 +#define MAC_RXD1 0x3d73 +#define SDIO1_INTN 0x3d74 + + +/* GPIO4_A */ +#define GPIO4_A0 0x4a00 +#define FLASH1_RDY 0x4a01 +#define HOST_CKOUTP 0x4a02 +#define MAC_MDC 0x4a03 + +#define GPIO4_A1 0x4a10 +#define FLASH1_WP 0x4a11 +#define HOST_CKOUTN 0x4a12 +#define MAC_RXDV 0x4a13 +#define FLASH0_CSN4 0x4a14 + +#define GPIO4_A2 0x4a20 +#define FLASH1_RDN 0x4a21 +#define HOST_DOUT8 0x4a22 +#define MAC_RXER 0x4a23 +#define FLASH0_CSN5 0x4a24 + +#define GPIO4_A3 0x4a30 +#define FLASH1_ALE 0x4a31 +#define HOST_DOUT9 0x4a32 +#define MAC_CLK 0x4a33 +#define FLASH0_CSN6 0x4a34 + +#define GPIO4_A4 0x4a40 +#define FLASH1_CLE 0x4a41 +#define HOST_DOUT10 0x4a42 +#define MAC_TXEN 0x4a43 +#define FLASH0_CSN7 0x4a44 + +#define GPIO4_A5 0x4a50 +#define FLASH1_WRN 0x4a51 +#define HOST_DOUT11 0x4a52 +#define MAC_MDIO 0x4a53 + +#define GPIO4_A6 0x4a60 +#define FLASH1_CSN0 0x4a61 +#define HOST_DOUT12 0x4a62 +#define MAC_RXCLK 0x4a63 +#define SDIO1_CMD 0x4a64 + +#define GPIO4_A7 0x4a70 +#define FLASH1_CSN1 0x4a71 +#define HOST_DOUT13 0x4a72 +#define MAC_CRS 0x4a73 +#define SDIO1_CLKOUT 0x4a74 + + +/* GPIO4_B */ +#define GPIO4_B0 0x4b00 +#define FLASH1_DQS 0x4b01 +#define HOST_DOUT14 0x4b02 +#define MAC_COL 0x4b03 +#define FLASH1_CSN3 0x4b04 + +#define GPIO4_B1 0x4b10 +#define FLASH1_CSN2 0x4b11 +#define HOST_DOUT15 0x4b12 +#define MAC_TXCLK 0x4b13 +#define SDIO1_PWREN 0x4b14 + + +/* GPIO4_C */ +#define GPIO4_C0 0x4c00 +#define UART0BT_SIN 0x4c01 + +#define GPIO4_C1 0x4c10 +#define UART0BT_SOUT 0x4c11 + +#define GPIO4_C2 0x4c20 +#define UART0BT_CTSN 0x4c21 + +#define GPIO4_C3 0x4c30 +#define UART0BT_RTSN 0x4c31 + +#define GPIO4_C4 0x4c40 +#define SDIO0_DATA0 0x4c41 + +#define GPIO4_C5 0x4c50 +#define SDIO0_DATA1 0x4c51 + +#define GPIO4_C6 0x4c60 +#define SDIO0_DATA2 0x4c61 + +#define GPIO4_C7 0x4c70 +#define SDIO0_DATA3 0x4c71 + + +/* GPIO4_D */ +#define GPIO4_D0 0x4d00 +#define SDIO0_CMD 0x4d01 + +#define GPIO4_D1 0x4d10 +#define SDIO0_CLKOUT 0x4d11 + +#define GPIO4_D2 0x4d20 +#define SDIO0_DETECTN 0x4d21 + +#define GPIO4_D3 0x4d30 +#define SDIO0_WRPRT 0x4d31 + +#define GPIO4_D4 0x4d40 +#define SDIO0_PWREN 0x4d41 + +#define GPIO4_D5 0x4d50 +#define SDIO0_BKPWR 0x4d51 + +#define GPIO4_D6 0x4d60 +#define SDIO0_INTN 0x4d61 + + +/* GPIO5_A */ +/* GPIO5_B */ +#define GPIO5_B0 0x5b00 +#define UART1BB_SIN 0x5b01 +#define TS0_DATA0 0x5b02 + +#define GPIO5_B1 0x5b10 +#define UART1BB_SOUT 0x5b11 +#define TS0_DATA1 0x5b12 + +#define GPIO5_B2 0x5b20 +#define UART1BB_CTSN 0x5b21 +#define TS0_DATA2 0x5b22 + +#define GPIO5_B3 0x5b30 +#define UART1BB_RTSN 0x5b31 +#define TS0_DATA3 0x5b32 + +#define GPIO5_B4 0x5b40 +#define SPI0_CLK 0x5b41 +#define TS0_DATA4 0x5b42 +#define UART4EXP_CTSN 0x5b43 + +#define GPIO5_B5 0x5b50 +#define SPI0_CS0 0x5b51 +#define TS0_DATA5 0x5b52 +#define UART4EXP_RTSN 0x5b53 + +#define GPIO5_B6 0x5b60 +#define SPI0_TXD 0x5b61 +#define TS0_DATA6 0x5b62 +#define UART4EXP_SOUT 0x5b63 + +#define GPIO5_B7 0x5b70 +#define SPI0_RXD 0x5b71 +#define TS0_DATA7 0x5b72 +#define UART4EXP_SIN 0x5b73 + + +/* GPIO5_C */ +#define GPIO5_C0 0x5c00 +#define SPI0_CS1 0x5c01 +#define TS0_SYNC 0x5c02 + +#define GPIO5_C1 0x5c10 +#define TS0_VALID 0x5c11 + +#define GPIO5_C2 0x5c20 +#define TS0_CLK 0x5c21 + +#define GPIO5_C3 0x5c30 +#define TS0_ERR 0x5c31 + + +/* GPIO5_D */ +/* GPIO6_A */ +#define GPIO6_A0 0x6a00 +#define I2S_SCLK 0x6a01 + +#define GPIO6_A1 0x6a10 +#define I2S_LRCKRX 0x6a11 + +#define GPIO6_A2 0x6a20 +#define I2S_LRCKTX 0x6a21 + +#define GPIO6_A3 0x6a30 +#define I2S_SDI 0x6a31 + +#define GPIO6_A4 0x6a40 +#define I2S_SDO0 0x6a41 + +#define GPIO6_A5 0x6a50 +#define I2S_SDO1 0x6a51 + +#define GPIO6_A6 0x6a60 +#define I2S_SDO2 0x6a61 + +#define GPIO6_A7 0x6a70 +#define I2S_SDO3 0x6a71 + + +/* GPIO6_B */ +#define GPIO6_B0 0x6b00 +#define I2S_CLK 0x6b01 + +#define GPIO6_B1 0x6b10 +#define I2C2AUDIO_SDA 0x6b11 + +#define GPIO6_B2 0x6b20 +#define I2C2AUDIO_SCL 0x6b21 + +#define GPIO6_B3 0x6b30 +#define SPDIF_TX 0x6b31 + + +/* GPIO6_C */ +#define GPIO6_C0 0x6c00 +#define SDMMC0_DATA0 0x6c01 +#define JTAG_TMS 0x6c02 + +#define GPIO6_C1 0x6c10 +#define SDMMC0_DATA1 0x6c11 +#define JTAG_TRSTN 0x6c12 + +#define GPIO6_C2 0x6c20 +#define SDMMC0_DATA2 0x6c21 +#define JTAG_TDI 0x6c22 + +#define GPIO6_C3 0x6c30 +#define SDMMC0_DATA3 0x6c31 +#define JTAG_TCK 0x6c32 + +#define GPIO6_C4 0x6c40 +#define SDMMC0_CLKOUT 0x6c41 +#define JTAG_TDO 0x6c42 + +#define GPIO6_C5 0x6c50 +#define SDMMC0_CMD 0x6c51 + +#define GPIO6_C6 0x6c60 +#define SDMMC0_DECTN 0x6c61 + + +/* GPIO6_D */ +/* GPIO7_A */ +#define GPIO7_A0 0x7a00 +#define PWM0 0x7a01 +#define VOP0_PWM 0x7a02 +#define VOP1_PWM 0x7a03 + +#define GPIO7_A1 0x7a10 +#define PWM1 0x7a11 + +#define GPIO7_A7 0x7a70 +#define UART3GPS_SIN 0x7a71 +#define GPS_MAG 0x7a72 +#define HSADCT1_DATA0 0x7a73 + + +/* GPIO7_B */ +#define GPIO7_B0 0x7b00 +#define UART3GPS_SOUT 0x7b01 +#define GPS_SIG 0x7b02 +#define HSADCT1_DATA1 0x7b03 + +#define GPIO7_B1 0x7b10 +#define UART3GPS_CTSN 0x7b11 +#define GPS_RFCLK 0x7b12 +#define GPST1_CLK 0x7b13 + +#define GPIO7_B2 0x7b20 +#define UART3GPS_RTSN 0x7b21 +#define USB_DRVVBUS0 0x7b22 + +#define GPIO7_B3 0x7b30 +#define USB_DRVVBUS1 0x7b31 +#define EDP_HOTPLUG 0x7b32 + +#define GPIO7_B4 0x7b40 +#define ISP_SHUTTEREN 0x7b41 +#define SPI1_CLK 0x7b42 + +#define GPIO7_B5 0x7b50 +#define ISP_FLASHTRIGOUTSPI1_CS0 0x7b51 +#define SPI1_CS0 0x7b52 + +#define GPIO7_B6 0x7b60 +#define ISP_PRELIGHTTRIGSPI1_RXD 0x7b61 +#define SPI1_RXD 0x7b62 + +#define GPIO7_B7 0x7b70 +#define ISP_SHUTTERTRIG 0x7b71 +#define SPI1_TXD 0x7b72 + + +/* GPIO7_C */ +#define GPIO7_C0 0x7c00 +#define ISP_FLASHTRIGIN 0x7c01 +#define EDPHDMI_CECINOUTRESERVED 0x7c02 + +#define GPIO7_C1 0x7c10 +#define I2C4TP_SDA 0x7c11 + +#define GPIO7_C2 0x7c20 +#define I2C4TP_SCL 0x7c21 + +#define GPIO7_C3 0x7c30 +#define I2C5HDMI_SDA 0x7c31 +#define EDPHDMII2C_SDA 0x7c32 + +#define GPIO7_C4 0x7c40 +#define I2C5HDMI_SCL 0x7c41 +#define EDPHDMII2C_SCL 0x7c42 + +#define GPIO7_C6 0x7c60 +#define UART2DBG_SIN 0x7c61 +#define UART2DBG_SIRIN 0x7c62 +#define PWM2 0x7c63 + +#define GPIO7_C7 0x7c70 +#define UART2DBG_SOUT 0x7c71 +#define UART2DBG_SIROUT 0x7c72 +#define PWM3 0x7c73 +#define EDPHDMI_CECINOUT 0x7c74 + + +/* GPIO7_D */ +/* GPIO8_A */ +#define GPIO8_A0 0x8a00 +#define PS2_CLK 0x8a01 +#define SC_VCC18V 0x8a02 + +#define GPIO8_A1 0x8a10 +#define PS2_DATA 0x8a11 +#define SC_VCC33V 0x8a12 + +#define GPIO8_A2 0x8a20 +#define SC_DETECTT1 0x8a21 + +#define GPIO8_A3 0x8a30 +#define SPI2_CS1 0x8a31 +#define SC_IOT1 0x8a32 + +#define GPIO8_A4 0x8a40 +#define I2C1SENSOR_SDA 0x8a41 +#define SC_RST_GPIO8A 0x8a42 + +#define GPIO8_A5 0x8a50 +#define I2C1SENSOR_SCL 0x8a51 +#define SC_CLK_GPIO8A 0x8a52 + +#define GPIO8_A6 0x8a60 +#define SPI2_CLK 0x8a61 +#define SC_IO 0x8a62 + +#define GPIO8_A7 0x8a70 +#define SPI2_CS0 0x8a71 +#define SC_DETECT 0x8a72 + + +/* GPIO8_B */ +#define GPIO8_B0 0x8b00 +#define SPI2_RXD 0x8b01 +#define SC_RST_GPIO8B 0x8b02 + +#define GPIO8_B1 0x8b10 +#define SPI2_TXD 0x8b11 +#define SC_CLK_GPIO8B 0x8b12 + + +/* GPIO8_C */ +/* GPIO8_D */ + + +#endif diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h index 743e66a95e13..bc2b6af99444 100644 --- a/include/dt-bindings/pinctrl/rockchip.h +++ b/include/dt-bindings/pinctrl/rockchip.h @@ -25,10 +25,46 @@ #define RK_GPIO4 4 #define RK_GPIO6 6 +#define RK_PA0 0 +#define RK_PA1 1 +#define RK_PA2 2 +#define RK_PA3 3 +#define RK_PA4 4 +#define RK_PA5 5 +#define RK_PA6 6 +#define RK_PA7 7 +#define RK_PB0 8 +#define RK_PB1 9 +#define RK_PB2 10 +#define RK_PB3 11 +#define RK_PB4 12 +#define RK_PB5 13 +#define RK_PB6 14 +#define RK_PB7 15 +#define RK_PC0 16 +#define RK_PC1 17 +#define RK_PC2 18 +#define RK_PC3 19 +#define RK_PC4 20 +#define RK_PC5 21 +#define RK_PC6 22 +#define RK_PC7 23 +#define RK_PD0 24 +#define RK_PD1 25 +#define RK_PD2 26 +#define RK_PD3 27 +#define RK_PD4 28 +#define RK_PD5 29 +#define RK_PD6 30 +#define RK_PD7 31 + #define RK_FUNC_GPIO 0 #define RK_FUNC_1 1 #define RK_FUNC_2 2 #define RK_FUNC_3 3 #define RK_FUNC_4 4 +#define RK_FUNC_5 5 +#define RK_FUNC_6 6 +#define RK_FUNC_7 7 #endif diff --git a/include/dt-bindings/power/px30-power.h b/include/dt-bindings/power/px30-power.h new file mode 100644 index 000000000000..4ed482e80950 --- /dev/null +++ b/include/dt-bindings/power/px30-power.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +#ifndef __DT_BINDINGS_POWER_PX30_POWER_H__ +#define __DT_BINDINGS_POWER_PX30_POWER_H__ + +/* VD_CORE */ +#define PX30_PD_A35_0 0 +#define PX30_PD_A35_1 1 +#define PX30_PD_A35_2 2 +#define PX30_PD_A35_3 3 +#define PX30_PD_SCU 4 + +/* VD_LOGIC */ +#define PX30_PD_USB 5 +#define PX30_PD_DDR 6 +#define PX30_PD_SDCARD 7 +#define PX30_PD_CRYPTO 8 +#define PX30_PD_GMAC 9 +#define PX30_PD_MMC_NAND 10 +#define PX30_PD_VPU 11 +#define PX30_PD_VO 12 +#define PX30_PD_VI 13 +#define PX30_PD_GPU 14 + +/* VD_PMU */ +#define PX30_PD_PMU 15 + +#endif diff --git a/include/dt-bindings/power/rk1808-power.h b/include/dt-bindings/power/rk1808-power.h new file mode 100644 index 000000000000..32342c1e7ded --- /dev/null +++ b/include/dt-bindings/power/rk1808-power.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK1808_POWER_H__ +#define __DT_BINDINGS_POWER_RK1808_POWER_H__ + +/* VD_CORE */ +#define RK1808_PD_A35_0 0 +#define RK1808_PD_A35_1 1 +#define RK1808_PD_SCU 2 +#define RK1808_VD_CORE 3 + +/* VD_NPU */ +#define RK1808_VD_NPU 4 + +/* VD_LOGIC */ +#define RK1808_PD_DDR 5 +#define RK1808_PD_PCIE 6 +#define RK1808_PD_VPU 7 +#define RK1808_PD_VIO 8 + +#endif diff --git a/include/dt-bindings/power/rk3036-power.h b/include/dt-bindings/power/rk3036-power.h new file mode 100644 index 000000000000..59e09f1c5af7 --- /dev/null +++ b/include/dt-bindings/power/rk3036-power.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Author: Caesar Wang <wxt@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_POWER_RK3036_POWER_H__ +#define __DT_BINDINGS_POWER_RK3036_POWER_H__ + +#define RK3036_PD_MSCH 0 +#define RK3036_PD_CORE 1 +#define RK3036_PD_PERI 2 +#define RK3036_PD_VIO 3 +#define RK3036_PD_VPU 4 +#define RK3036_PD_GPU 5 +#define RK3036_PD_SYS 6 + +#endif diff --git a/include/dt-bindings/power/rk3128-power.h b/include/dt-bindings/power/rk3128-power.h new file mode 100644 index 000000000000..26aef519cd94 --- /dev/null +++ b/include/dt-bindings/power/rk3128-power.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang <zhangqing@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_POWER_RK3128_POWER_H__ +#define __DT_BINDINGS_POWER_RK3128_POWER_H__ + +/* VD_CORE */ +#define RK3128_PD_CORE 0 + +/* VD_LOGIC */ +#define RK3128_PD_VIO 1 +#define RK3128_PD_VIDEO 2 +#define RK3128_PD_GPU 3 +#define RK3128_PD_MSCH 4 + +#endif diff --git a/include/dt-bindings/power/rk3228-power.h b/include/dt-bindings/power/rk3228-power.h new file mode 100644 index 000000000000..fa1264d5a995 --- /dev/null +++ b/include/dt-bindings/power/rk3228-power.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +#ifndef __DT_BINDINGS_POWER_RK3228_POWER_H__ +#define __DT_BINDINGS_POWER_RK3228_POWER_H__ + +/** + * RK3228 idle id Summary. + */ + +#define RK3228_PD_CORE 0 +#define RK3228_PD_MSCH 1 +#define RK3228_PD_BUS 2 +#define RK3228_PD_SYS 3 +#define RK3228_PD_VIO 4 +#define RK3228_PD_VOP 5 +#define RK3228_PD_VPU 6 +#define RK3228_PD_RKVDEC 7 +#define RK3228_PD_GPU 8 +#define RK3228_PD_PERI 9 +#define RK3228_PD_GMAC 10 + +#endif diff --git a/include/dt-bindings/power/rk3328-power.h b/include/dt-bindings/power/rk3328-power.h new file mode 100644 index 000000000000..02e3d7fc1cce --- /dev/null +++ b/include/dt-bindings/power/rk3328-power.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3328_POWER_H__ +#define __DT_BINDINGS_POWER_RK3328_POWER_H__ + +/** + * RK3328 idle id Summary. + */ +#define RK3328_PD_CORE 0 +#define RK3328_PD_GPU 1 +#define RK3328_PD_BUS 2 +#define RK3328_PD_MSCH 3 +#define RK3328_PD_PERI 4 +#define RK3328_PD_VIDEO 5 +#define RK3328_PD_HEVC 6 +#define RK3328_PD_SYS 7 +#define RK3328_PD_VPU 8 +#define RK3328_PD_VIO 9 + +#endif diff --git a/include/dt-bindings/power/rk3366-power.h b/include/dt-bindings/power/rk3366-power.h new file mode 100644 index 000000000000..af912a40b410 --- /dev/null +++ b/include/dt-bindings/power/rk3366-power.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3366_POWER_H__ +#define __DT_BINDINGS_POWER_RK3366_POWER_H__ + +/* VD_CORE */ +#define RK3366_PD_A53_0 0 +#define RK3366_PD_A53_1 1 +#define RK3366_PD_A53_2 2 +#define RK3366_PD_A53_3 3 + +/* VD_LOGIC */ +#define RK3366_PD_BUS 4 +#define RK3366_PD_PERI 5 +#define RK3366_PD_VIO 6 +#define RK3366_PD_VIDEO 7 +#define RK3366_PD_RKVDEC 8 +#define RK3366_PD_WIFIBT 9 +#define RK3366_PD_VPU 10 +#define RK3366_PD_GPU 11 +#define RK3366_PD_ALIVE 12 + +/* VD_PMU */ +#define RK3366_PD_PMU 13 + +#endif diff --git a/include/dt-bindings/power/rk3368-power.h b/include/dt-bindings/power/rk3368-power.h new file mode 100644 index 000000000000..5e602dbd64ec --- /dev/null +++ b/include/dt-bindings/power/rk3368-power.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3368_POWER_H__ +#define __DT_BINDINGS_POWER_RK3368_POWER_H__ + +/* VD_CORE */ +#define RK3368_PD_A53_L0 0 +#define RK3368_PD_A53_L1 1 +#define RK3368_PD_A53_L2 2 +#define RK3368_PD_A53_L3 3 +#define RK3368_PD_SCU_L 4 +#define RK3368_PD_A53_B0 5 +#define RK3368_PD_A53_B1 6 +#define RK3368_PD_A53_B2 7 +#define RK3368_PD_A53_B3 8 +#define RK3368_PD_SCU_B 9 + +/* VD_LOGIC */ +#define RK3368_PD_BUS 10 +#define RK3368_PD_PERI 11 +#define RK3368_PD_VIO 12 +#define RK3368_PD_ALIVE 13 +#define RK3368_PD_VIDEO 14 +#define RK3368_PD_GPU_0 15 +#define RK3368_PD_GPU_1 16 + +/* VD_PMU */ +#define RK3368_PD_PMU 17 + +#endif diff --git a/include/dt-bindings/power/rk3399-power.h b/include/dt-bindings/power/rk3399-power.h new file mode 100644 index 000000000000..aedd8b180fe4 --- /dev/null +++ b/include/dt-bindings/power/rk3399-power.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3399_POWER_H__ +#define __DT_BINDINGS_POWER_RK3399_POWER_H__ + +/* VD_CORE_L */ +#define RK3399_PD_A53_L0 0 +#define RK3399_PD_A53_L1 1 +#define RK3399_PD_A53_L2 2 +#define RK3399_PD_A53_L3 3 +#define RK3399_PD_SCU_L 4 + +/* VD_CORE_B */ +#define RK3399_PD_A72_B0 5 +#define RK3399_PD_A72_B1 6 +#define RK3399_PD_SCU_B 7 + +/* VD_LOGIC */ +#define RK3399_PD_TCPD0 8 +#define RK3399_PD_TCPD1 9 +#define RK3399_PD_CCI 10 +#define RK3399_PD_CCI0 11 +#define RK3399_PD_CCI1 12 +#define RK3399_PD_PERILP 13 +#define RK3399_PD_PERIHP 14 +#define RK3399_PD_VIO 15 +#define RK3399_PD_VO 16 +#define RK3399_PD_VOPB 17 +#define RK3399_PD_VOPL 18 +#define RK3399_PD_ISP0 19 +#define RK3399_PD_ISP1 20 +#define RK3399_PD_HDCP 21 +#define RK3399_PD_GMAC 22 +#define RK3399_PD_EMMC 23 +#define RK3399_PD_USB3 24 +#define RK3399_PD_EDP 25 +#define RK3399_PD_GIC 26 +#define RK3399_PD_SD 27 +#define RK3399_PD_SDIOAUDIO 28 +#define RK3399_PD_ALIVE 29 + +/* VD_CENTER */ +#define RK3399_PD_CENTER 30 +#define RK3399_PD_VCODEC 31 +#define RK3399_PD_VDU 32 +#define RK3399_PD_RGA 33 +#define RK3399_PD_IEP 34 + +/* VD_GPU */ +#define RK3399_PD_GPU 35 + +/* VD_PMU */ +#define RK3399_PD_PMU 36 + +#endif diff --git a/include/dt-bindings/sensor-dev.h b/include/dt-bindings/sensor-dev.h new file mode 100644 index 000000000000..e03f0027d325 --- /dev/null +++ b/include/dt-bindings/sensor-dev.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __DT_BINDINGS_ROCKCHIP_SENSORDEV_H__ +#define __DT_BINDINGS_ROCKCHIP_SENSORDEV_H__ + +#define SENSOR_TYPE_NULL 0 +#define SENSOR_TYPE_ANGLE 1 +#define SENSOR_TYPE_ACCEL 2 +#define SENSOR_TYPE_COMPASS 3 +#define SENSOR_TYPE_GYROSCOPE 4 +#define SENSOR_TYPE_LIGHT 5 +#define SENSOR_TYPE_PROXIMITY 6 +#define SENSOR_TYPE_TEMPERATURE 7 +#define SENSOR_TYPE_PRESSURE 8 +#define SENSOR_TYPE_HALL 9 +#define SENSOR_NUM_TYPES 10 + +#endif diff --git a/include/dt-bindings/soc/rockchip,boot-mode.h b/include/dt-bindings/soc/rockchip,boot-mode.h new file mode 100644 index 000000000000..01e934fbec40 --- /dev/null +++ b/include/dt-bindings/soc/rockchip,boot-mode.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ROCKCHIP_BOOT_MODE_H +#define __ROCKCHIP_BOOT_MODE_H + +/* high 24 bits is tag, low 8 bits is type */ +#define REBOOT_FLAG 0x5242C300 +/* normal boot */ +#define BOOT_NORMAL (REBOOT_FLAG + 0) +/* enter bootloader rockusb mode */ +#define BOOT_BL_DOWNLOAD (REBOOT_FLAG + 1) +/* enter recovery */ +#define BOOT_RECOVERY (REBOOT_FLAG + 3) +/* enter fastboot mode */ +#define BOOT_FASTBOOT (REBOOT_FLAG + 9) +/* enter charging mode */ +#define BOOT_CHARGING (REBOOT_FLAG + 11) +/* enter usb mass storage mode */ +#define BOOT_UMS (REBOOT_FLAG + 12) + +#endif diff --git a/include/dt-bindings/soc/rockchip-system-status.h b/include/dt-bindings/soc/rockchip-system-status.h new file mode 100644 index 000000000000..fe103a55f222 --- /dev/null +++ b/include/dt-bindings/soc/rockchip-system-status.h @@ -0,0 +1,43 @@ +/* + * + * Copyright (C) 2017 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _DT_BINDINGS_SOC_ROCKCHIP_SYSTEM_STATUS_H +#define _DT_BINDINGS_SOC_ROCKCHIP_SYSTEM_STATUS_H + +#define SYS_STATUS_NORMAL (1 << 0) +#define SYS_STATUS_SUSPEND (1 << 1) +#define SYS_STATUS_IDLE (1 << 2) +#define SYS_STATUS_REBOOT (1 << 3) +#define SYS_STATUS_VIDEO_4K (1 << 4) +#define SYS_STATUS_VIDEO_1080P (1 << 5) +#define SYS_STATUS_GPU (1 << 6) +#define SYS_STATUS_RGA (1 << 7) +#define SYS_STATUS_CIF0 (1 << 8) +#define SYS_STATUS_CIF1 (1 << 9) +#define SYS_STATUS_LCDC0 (1 << 10) +#define SYS_STATUS_LCDC1 (1 << 11) +#define SYS_STATUS_BOOST (1 << 12) +#define SYS_STATUS_PERFORMANCE (1 << 13) +#define SYS_STATUS_ISP (1 << 14) +#define SYS_STATUS_HDMI (1 << 15) +#define SYS_STATUS_VIDEO_4K_10B (1 << 16) +#define SYS_STATUS_LOW_POWER (1 << 17) + +#define SYS_STATUS_VIDEO (SYS_STATUS_VIDEO_4K | \ + SYS_STATUS_VIDEO_1080P | \ + SYS_STATUS_VIDEO_4K_10B) +#define SYS_STATUS_DUALVIEW (SYS_STATUS_LCDC0 | SYS_STATUS_LCDC1) + +#endif diff --git a/include/dt-bindings/suspend/rockchip-px30.h b/include/dt-bindings/suspend/rockchip-px30.h new file mode 100644 index 000000000000..4362028f677c --- /dev/null +++ b/include/dt-bindings/suspend/rockchip-px30.h @@ -0,0 +1,53 @@ +/* + * Header providing constants for Rockchip suspend bindings. + * + * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd + * Author: XiaoDong.Huang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __DT_BINDINGS_ROCKCHIP_PM_H__ +#define __DT_BINDINGS_ROCKCHIP_PM_H__ +/******************************bits ops************************************/ + +#ifndef BIT +#define BIT(nr) (1 << (nr)) +#endif + +#define RKPM_SLP_ARMPD BIT(0) +#define RKPM_SLP_ARMOFF BIT(1) +#define RKPM_SLP_ARMOFF_DDRPD BIT(2) +#define RKPM_SLP_ARMOFF_LOGOFF BIT(3) + +/* all plls except ddr's pll*/ +#define RKPM_SLP_PMU_HW_PLLS_PD BIT(8) +#define RKPM_SLP_PMU_PMUALIVE_32K BIT(9) +#define RKPM_SLP_PMU_DIS_OSC BIT(10) + +#define RKPM_SLP_CLK_GT BIT(16) +#define RKPM_SLP_PMIC_LP BIT(17) + +#define RKPM_SLP_32K_EXT BIT(24) +#define RKPM_SLP_TIME_OUT_WKUP BIT(25) +#define RKPM_SLP_PMU_DBG BIT(26) + +/* the wake up source */ +#define RKPM_CLUSTER_WKUP_EN BIT(0) +#define RKPM_GPIO_WKUP_EN BIT(2) +#define RKPM_SDIO_WKUP_EN BIT(3) +#define RKPM_SDMMC_WKUP_EN BIT(4) +#define RKPM_UART0_WKUP_EN BIT(5) +#define RKPM_TIMER_WKUP_EN BIT(6) +#define RKPM_USB_WKUP_EN BIT(7) +#define RKPM_SFT_WKUP_EN BIT(8) +#define RKPM_TIME_OUT_WKUP_EN BIT(10) + +#endif diff --git a/include/dt-bindings/suspend/rockchip-rk1808.h b/include/dt-bindings/suspend/rockchip-rk1808.h new file mode 100644 index 000000000000..3d565faabf4d --- /dev/null +++ b/include/dt-bindings/suspend/rockchip-rk1808.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Header providing constants for Rockchip suspend bindings. + * + * Copyright (C) 2018, Fuzhou Rockchip Electronics Co., Ltd + * Author: XiaoDong.Huang + */ + +#ifndef __DT_BINDINGS_RK1808_PM_H__ +#define __DT_BINDINGS_RK1808_PM_H__ +/******************************bits ops************************************/ + +#ifndef BIT +#define BIT(nr) (1 << (nr)) +#endif + +#define RKPM_SLP_ARMPD BIT(0) +#define RKPM_SLP_ARMOFF BIT(1) +#define RKPM_SLP_ARMOFF_DDRPD BIT(2) +#define RKPM_SLP_ARMOFF_LOGOFF BIT(3) + +/* all plls except ddr's pll*/ +#define RKPM_SLP_PMU_HW_PLLS_PD BIT(8) +#define RKPM_SLP_PMU_PMUALIVE_32K BIT(9) +#define RKPM_SLP_PMU_DIS_OSC BIT(10) + +#define RKPM_SLP_CLK_GT BIT(16) +#define RKPM_SLP_PMIC_LP BIT(17) + +#define RKPM_SLP_32K_EXT BIT(24) +#define RKPM_SLP_TIME_OUT_WKUP BIT(25) +#define RKPM_SLP_PMU_DBG BIT(26) + +/* the wake up source */ +#define RKPM_CLUSTER_WKUP_EN BIT(0) +#define RKPM_GPIO_WKUP_EN BIT(2) +#define RKPM_SDIO_WKUP_EN BIT(3) +#define RKPM_SDMMC_WKUP_EN BIT(4) +#define RKPM_UART0_WKUP_EN BIT(5) +#define RKPM_TIMER_WKUP_EN BIT(6) +#define RKPM_USB_WKUP_EN BIT(7) +#define RKPM_SFT_WKUP_EN BIT(8) +#define RKPM_VAD_WKUP_EN BIT(9) +#define RKPM_TIME_OUT_WKUP_EN BIT(10) + +#endif diff --git a/include/dt-bindings/suspend/rockchip-rk322x.h b/include/dt-bindings/suspend/rockchip-rk322x.h new file mode 100644 index 000000000000..882ae053fa22 --- /dev/null +++ b/include/dt-bindings/suspend/rockchip-rk322x.h @@ -0,0 +1,57 @@ +/* + * Header providing constants for Rockchip suspend bindings. + * + * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd + * Author: XiaoDong.Huang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_SUSPEND_ROCKCHIP_RK322X_H__ +#define __DT_BINDINGS_SUSPEND_ROCKCHIP_RK322X_H__ + +#ifndef BIT +#define BIT(nr) (1 << (nr)) +#endif + +/* the suspend mode */ +#define RKPM_CTR_PWR_DMNS BIT(0) +#define RKPM_CTR_GTCLKS BIT(1) +#define RKPM_CTR_PLLS BIT(2) +#define RKPM_CTR_VOLTS BIT(3) +#define RKPM_CTR_GPIOS BIT(4) +#define RKPM_CTR_DDR BIT(5) +#define RKPM_CTR_PMIC BIT(6) + +/* system clk is 24M,and div to min */ +#define RKPM_CTR_SYSCLK_DIV BIT(7) +/* switch sysclk to 32k, need hardwart support, and div to min */ +#define RKPM_CTR_SYSCLK_32K BIT(8) +/* switch sysclk to 32k,disable 24M OSC, + * need hardwart susport. and div to min + */ +#define RKPM_CTR_SYSCLK_OSC_DIS BIT(9) +#define RKPM_CTR_VOL_PWM0 BIT(10) +#define RKPM_CTR_VOL_PWM1 BIT(11) +#define RKPM_CTR_VOL_PWM2 BIT(12) +#define RKPM_CTR_VOL_PWM3 BIT(13) +#define RKPM_CTR_BUS_IDLE BIT(14) +#define RKPM_CTR_SRAM BIT(15) +/*Low Power Function Selection*/ +#define RKPM_CTR_IDLESRAM_MD BIT(16) +#define RKPM_CTR_IDLEAUTO_MD BIT(17) +#define RKPM_CTR_ARMDP_LPMD BIT(18) +#define RKPM_CTR_ARMOFF_LPMD BIT(19) +#define RKPM_CTR_ARMLOGDP_LPMD BIT(20) +#define RKPM_CTR_ARMOFF_LOGDP_LPMD BIT(21) +#define RKPM_CTR_ARMLOGOFF_DLPMD BIT(22) + +#endif diff --git a/include/dt-bindings/suspend/rockchip-rk3288.h b/include/dt-bindings/suspend/rockchip-rk3288.h new file mode 100644 index 000000000000..d07cced43877 --- /dev/null +++ b/include/dt-bindings/suspend/rockchip-rk3288.h @@ -0,0 +1,59 @@ +/* + * Header providing constants for Rockchip suspend bindings. + * + * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd + * Author: Power.xu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3288_H__ +#define __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3288_H__ + +/* the suspend mode */ +#define RKPM_CTR_PWR_DMNS (1 << 0) +#define RKPM_CTR_GTCLKS (1 << 1) +#define RKPM_CTR_PLLS (1 << 2) +#define RKPM_CTR_VOLTS (1 << 3) +#define RKPM_CTR_GPIOS (1 << 4) +#define RKPM_CTR_DDR (1 << 5) +#define RKPM_CTR_PMIC (1 << 6) +/* system clk is 24M,and div to min */ +#define RKPM_CTR_SYSCLK_DIV (1 << 7) +/* switch sysclk to 32k, need hardwart support, and div to min */ +#define RKPM_CTR_SYSCLK_32K (1 << 8) +/* switch sysclk to 32k,disable 24M OSC, + * need hardwart susport. and div to min + */ +#define RKPM_CTR_SYSCLK_OSC_DIS (1 << 9) +#define RKPM_CTR_BUS_IDLE (1 << 14) +#define RKPM_CTR_SRAM (1 << 15) +/*Low Power Function Selection*/ +#define RKPM_CTR_IDLESRAM_MD (1 << 16) +#define RKPM_CTR_IDLEAUTO_MD (1 << 17) +#define RKPM_CTR_ARMDP_LPMD (1 << 18) +#define RKPM_CTR_ARMOFF_LPMD (1 << 19) +#define RKPM_CTR_ARMLOGDP_LPMD (1 << 20) +#define RKPM_CTR_ARMOFF_LOGDP_LPMD (1 << 21) +#define RKPM_CTR_ARMLOGOFF_DLPMD (1 << 22) + +/* the wake up source */ +#define RKPM_ARMINT_WKUP_EN (1 << 0) +#define RKPM_SDMMC_WKUP_EN (1 << 2) +#define RKPM_GPIO_WKUP_EN (1 << 3) + +/* the pwm regulator */ +#define PWM0_REGULATOR_EN (1 << 0) +#define PWM1_REGULATOR_EN (1 << 1) +#define PWM2_REGULATOR_EN (1 << 2) +#define PWM3_REGULATOR_EN (1 << 3) + +#endif diff --git a/include/dt-bindings/suspend/rockchip-rk3308.h b/include/dt-bindings/suspend/rockchip-rk3308.h new file mode 100644 index 000000000000..86ac23b83b48 --- /dev/null +++ b/include/dt-bindings/suspend/rockchip-rk3308.h @@ -0,0 +1,103 @@ +/* + * Header providing constants for Rockchip suspend bindings. + * + * Copyright (C) 2018, Fuzhou Rockchip Electronics Co., Ltd + * Author: Joseph Chen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __DT_BINDINGS_RK3308_PM_H__ +#define __DT_BINDINGS_RK3308_PM_H__ +/******************************bits ops************************************/ + +#ifndef BIT +#define BIT(nr) (1 << (nr)) +#endif + +/* + * RK3308 system suspend mode configure definitions. + * + * Driver: + * These configures are pass to ATF by SMC in: + * drivers/soc/rockchip/rockchip_pm_config.c + * + * DTS: + * rockchip_suspend: rockchip-suspend { + * rockchip,sleep-mode-config = <...>; + * rockchip,wakeup-config = <...>; + * rockchip,apios-suspend = <...>; + * rockchip,pwm-regulator-config = <...>; + * }; + */ + +/* + * Suspend mode: + * rockchip,sleep-mode-config = <...>; + */ +#define RKPM_ARMOFF BIT(0) /* vdd_arm off */ +#define RKPM_VADOFF BIT(1) /* assume vad off, enter lowest system suspend */ +#define RKPM_PMU_HW_PLLS_PD BIT(3) /* disable PLLs by PMU hardware, recommend */ +#define RKPM_PMU_DIS_OSC BIT(4) /* disable 24M osc */ +#define RKPM_PMU_PMUALIVE_32K BIT(5) /* pvtm 32khz */ +#define RKPM_PMU_EXT_32K BIT(6) /* ext 32khz osc */ +#define RKPM_DDR_SREF_HARDWARE BIT(7) /* ddr enter self-refresh by PMU hardware, not recommend */ +#define RKPM_DDR_EXIT_SRPD_IDLE BIT(8) /* ddr exit sr/pd idle by ddr controller, not recommend */ +#define RKPM_PDM_CLK_OFF BIT(9) /* armoff with pdm clk off, not recommend */ + +/* + * Regulator mode: + * rockchip,pwm-regulator-config = <...>; + */ +#define RKPM_PWM_REGULATOR BIT(2) /* support pwm regulator */ + +/* + * Wakeup source: + * rockchip,wakeup-config = <...>; + */ +#define RKPM_ARM_PRE_WAKEUP_EN BIT(11) /* all interrupts can wakeup(gic doesn't filter these) */ +#define RKPM_ARM_GIC_WAKEUP_EN BIT(12) /* all interrupts can wakeup(gic filter these) */ +#define RKPM_SDMMC_WAKEUP_EN BIT(13) /* sdmmc can wakeup */ +#define RKPM_SDMMC_GRF_IRQ_WAKEUP_EN BIT(14) /* sdmmc grf irq can wakeup */ +#define RKPM_TIMER_WAKEUP_EN BIT(15) /* rk timers can wakeup */ +#define RKPM_USBDEV_WAKEUP_EN BIT(16) /* usbdev can wakeup */ +#define RKPM_TIMEOUT_WAKEUP_EN BIT(17) /* PMU timeout can wakeup, for self test */ +#define RKPM_GPIO0_WAKEUP_EN BIT(18) /* gpio0(only) can wakeup */ +#define RKPM_VAD_WAKEUP_EN BIT(19) /* vad can wakeup */ + +/* + * Debug control in system suspend: + * rockchip,sleep-mode-config = <...>; + */ +#define RKPM_DBG_INT_TIMER_TEST BIT(22) /* enable RKPM_TIMEOUT_WAKEUP_EN */ +#define RKPM_DBG_WOARKAROUND BIT(23) /* ignore, useless */ +#define RKPM_DBG_VAD_INT_OFF BIT(24) /* enable RKPM_VADOFF */ +#define RKPM_DBG_CLK_UNGATE BIT(25) /* enable all clks */ +#define RKPM_DBG_CLKOUT BIT(26) /* enable test_out clk output */ +#define RKPM_DBG_FSM_SOUT BIT(27) /* FSM state one pin out */ +#define RKPM_DBG_FSM_STATE BIT(28) /* FSM state multi pins out */ +#define RKPM_DBG_REG BIT(29) /* verbose regs */ +#define RKPM_DBG_VERBOSE BIT(30) /* verbose more message */ +#define RKPM_CONFIG_WAKEUP_END BIT(31) /* ignore, it's a placeholder */ + +/* + * GPIOn/PWMn ignore global 1st reset, usually used for pwr_hold pin: + * rockchip,apios-suspend = <...>; + */ +#define GLB1RST_IGNORE_PWM0 BIT(23) /* pwm0 ignore global 1st reset */ +#define GLB1RST_IGNORE_PWM1 BIT(24) /* pwm1 ignore global 1st reset */ +#define GLB1RST_IGNORE_PWM2 BIT(25) /* pwm2 ignore global 1st reset */ +#define GLB1RST_IGNORE_GPIO0 BIT(26) /* gpio0 ignore global 1st reset */ +#define GLB1RST_IGNORE_GPIO1 BIT(27) /* gpio1 ignore global 1st reset */ +#define GLB1RST_IGNORE_GPIO2 BIT(28) /* gpio2 ignore global 1st reset */ +#define GLB1RST_IGNORE_GPIO3 BIT(29) /* gpio3 ignore global 1st reset */ +#define GLB1RST_IGNORE_GPIO4 BIT(30) /* gpio4 ignore global 1st reset */ + +#endif diff --git a/include/dt-bindings/suspend/rockchip-rk3328.h b/include/dt-bindings/suspend/rockchip-rk3328.h new file mode 100644 index 000000000000..972f8bb5e281 --- /dev/null +++ b/include/dt-bindings/suspend/rockchip-rk3328.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Header providing constants for Rockchip suspend bindings. + * + * Copyright (C) 2018, Fuzhou Rockchip Electronics Co., Ltd + * Author: XiaoDong.Huang + */ +#ifndef __DT_BINDINGS_ROCKCHIP_PM_H__ +#define __DT_BINDINGS_ROCKCHIP_PM_H__ +/******************************bits ops************************************/ + +#ifndef BIT +#define BIT(nr) (1 << (nr)) +#endif + +#define RKPM_SLP_CTR_VOL_PWM0 BIT(10) +#define RKPM_SLP_CTR_VOL_PWM1 BIT(11) + +#endif diff --git a/include/dt-bindings/suspend/rockchip-rk3368.h b/include/dt-bindings/suspend/rockchip-rk3368.h new file mode 100644 index 000000000000..9873f8236a8b --- /dev/null +++ b/include/dt-bindings/suspend/rockchip-rk3368.h @@ -0,0 +1,56 @@ +/* + * Header providing constants for Rockchip suspend bindings. + * + * Copyright (C) 2015, Fuzhou Rockchip Electronics Co., Ltd + * Author: Tony.Xie + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __DT_BINDINGS_ROCKCHIP_PM_H__ +#define __DT_BINDINGS_ROCKCHIP_PM_H__ +/******************************bits ops************************************/ + +#ifndef BIT +#define BIT(nr) (1 << (nr)) +#endif + +#define RKPM_SLP_WFI BIT(0) +#define RKPM_SLP_ARMPD BIT(1) +#define RKPM_SLP_ARMOFF BIT(2) +#define RKPM_SLP_ARMOFF_LOGPD BIT(3) +#define RKPM_SLP_ARMOFF_LOGOFF BIT(4) +#define RKPM_RUNNING_ARMMODE BIT(5) + +/* func ctrl by pmu auto ctr */ +#define RKPM_SLP_PMU_PLLS_PWRDN BIT(8) /* all plls except ddr's pll*/ +#define RKPM_SLP_PMU_PMUALIVE_32K BIT(9) +#define RKPM_SLP_PMU_DIS_OSC BIT(10) + +/* func ctrl by software set */ +#define RKPM_SLP_SFT_PLLS_DEEP BIT(16) /* all plls except ddr's pll*/ +#define RKPM_SLP_SFT_32K_EXT BIT(17) +#define RKPM_SLP_SFT_PD_PERI BIT(18) +#define RKPM_SLP_SFT_PD_NBSCUS BIT(19) /* noboot scus in muti-cluster */ + +/* the wake up source */ +#define RKPM_CLUSTER_L_WKUP_EN BIT(0) +#define RKPM_CLUSTER_B_WKUPB_EN BIT(1) +#define RKPM_GPIO_WKUP_EN BIT(2) +#define RKPM_SDIO_WKUP_EN BIT(3) +#define RKPM_SDMMC_WKUP_EN BIT(4) +#define RKPM_SIM_WKUP_EN BIT(5) +#define RKPM_TIMER_WKUP_EN BIT(6) +#define RKPM_USB_WKUP_EN BIT(7) +#define RKPM_SFT_WKUP_EN BIT(8) +#define RKPM_WDT_M0_WKUP_EN BIT(9) +#define RKPM_TIME_OUT_WKUP_EN BIT(10) + +#endif diff --git a/include/dt-bindings/suspend/rockchip-rk3399.h b/include/dt-bindings/suspend/rockchip-rk3399.h new file mode 100644 index 000000000000..176c7cfcd989 --- /dev/null +++ b/include/dt-bindings/suspend/rockchip-rk3399.h @@ -0,0 +1,61 @@ +/* + * Header providing constants for Rockchip suspend bindings. + * + * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd + * Author: Tony.Xie + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3399_H__ +#define __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3399_H__ + +/* the suspend mode */ +#define RKPM_SLP_WFI (1 << 0) +#define RKPM_SLP_ARMPD (1 << 1) +#define RKPM_SLP_PERILPPD (1 << 2) +#define RKPM_SLP_DDR_RET (1 << 3) +#define RKPM_SLP_PLLPD (1 << 4) +#define RKPM_SLP_OSC_DIS (1 << 5) +#define RKPM_SLP_CENTER_PD (1 << 6) +#define RKPM_SLP_AP_PWROFF (1 << 7) + +/* the wake up source */ +#define RKPM_CLUSTER_L_WKUP_EN (1 << 0) +#define RKPM_CLUSTER_B_WKUPB_EN (1 << 1) +#define RKPM_GPIO_WKUP_EN (1 << 2) +#define RKPM_SDIO_WKUP_EN (1 << 3) +#define RKPM_SDMMC_WKUP_EN (1 << 4) +#define RKPM_TIMER_WKUP_EN (1 << 6) +#define RKPM_USB_WKUP_EN (1 << 7) +#define RKPM_SFT_WKUP_EN (1 << 8) +#define RKPM_WDT_M0_WKUP_EN (1 << 9) +#define RKPM_TIME_OUT_WKUP_EN (1 << 10) +#define RKPM_PWM_WKUP_EN (1 << 11) +#define RKPM_PCIE_WKUP_EN (1 << 13) +#define RKPM_USB_LINESTATE_WKUP_EN (1 << 14) + +/* the pwm regulator */ +#define PWM0_REGULATOR_EN (1 << 0) +#define PWM1_REGULATOR_EN (1 << 1) +#define PWM2_REGULATOR_EN (1 << 2) +#define PWM3A_REGULATOR_EN (1 << 3) +#define PWM3B_REGULATOR_EN (1 << 4) + +/* the APIO voltage domain */ +#define RKPM_APIO0_SUSPEND (1 << 0) +#define RKPM_APIO1_SUSPEND (1 << 1) +#define RKPM_APIO2_SUSPEND (1 << 2) +#define RKPM_APIO3_SUSPEND (1 << 3) +#define RKPM_APIO4_SUSPEND (1 << 4) +#define RKPM_APIO5_SUSPEND (1 << 5) + +#endif diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 3672893b275e..a3e0856c9600 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -54,6 +54,9 @@ static inline acpi_handle acpi_device_handle(struct acpi_device *adev) acpi_fwnode_handle(adev) : NULL) #define ACPI_HANDLE(dev) acpi_device_handle(ACPI_COMPANION(dev)) + +extern const struct fwnode_operations acpi_fwnode_ops; + /** * ACPI_DEVICE_CLASS - macro used to describe an ACPI device with * the PCI-defined class-code information @@ -504,6 +507,12 @@ static inline struct acpi_data_node *to_acpi_data_node(struct fwnode_handle *fwn return NULL; } +static inline bool acpi_data_node_match(struct fwnode_handle *fwnode, + const char *name) +{ + return false; +} + static inline struct fwnode_handle *acpi_fwnode_handle(struct acpi_device *adev) { return NULL; @@ -804,8 +813,16 @@ int acpi_node_prop_read(struct fwnode_handle *fwnode, const char *propname, int acpi_dev_prop_read(struct acpi_device *adev, const char *propname, enum dev_prop_type proptype, void *val, size_t nval); -struct fwnode_handle *acpi_get_next_subnode(struct device *dev, - struct fwnode_handle *subnode); +struct fwnode_handle *acpi_get_next_subnode(struct fwnode_handle *fwnode, + struct fwnode_handle *child); +struct fwnode_handle *acpi_node_get_parent(struct fwnode_handle *fwnode); + +struct fwnode_handle *acpi_graph_get_next_endpoint(struct fwnode_handle *fwnode, + struct fwnode_handle *prev); +int acpi_graph_get_remote_endpoint(struct fwnode_handle *fwnode, + struct fwnode_handle **remote, + struct fwnode_handle **port, + struct fwnode_handle **endpoint); struct acpi_probe_entry; typedef bool (*acpi_probe_entry_validate_subtbl)(struct acpi_subtable_header *, @@ -914,12 +931,34 @@ static inline int acpi_dev_prop_read(struct acpi_device *adev, return -ENXIO; } -static inline struct fwnode_handle *acpi_get_next_subnode(struct device *dev, - struct fwnode_handle *subnode) +static inline struct fwnode_handle * +acpi_get_next_subnode(struct fwnode_handle *fwnode, struct fwnode_handle *child) +{ + return NULL; +} + +static inline struct fwnode_handle * +acpi_node_get_parent(struct fwnode_handle *fwnode) { return NULL; } +static inline struct fwnode_handle * +acpi_graph_get_next_endpoint(struct fwnode_handle *fwnode, + struct fwnode_handle *prev) +{ + return ERR_PTR(-ENXIO); +} + +static inline int +acpi_graph_get_remote_endpoint(struct fwnode_handle *fwnode, + struct fwnode_handle **remote, + struct fwnode_handle **port, + struct fwnode_handle **endpoint) +{ + return -ENXIO; +} + #define ACPI_DECLARE_PROBE_ENTRY(table, name, table_id, subtable, valid, data, fn) \ static const void * __acpi_table_##name[] \ __attribute__((unused)) \ diff --git a/include/linux/backlight.h b/include/linux/backlight.h index 1e7a69adbe6f..ef008bfe22b0 100644 --- a/include/linux/backlight.h +++ b/include/linux/backlight.h @@ -129,6 +129,38 @@ static inline int backlight_update_status(struct backlight_device *bd) return ret; } +/** + * backlight_enable - Enable backlight + * @bd: the backlight device to enable + */ +static inline int backlight_enable(struct backlight_device *bd) +{ + if (!bd) + return 0; + + bd->props.power = FB_BLANK_UNBLANK; + bd->props.fb_blank = FB_BLANK_UNBLANK; + bd->props.state &= ~BL_CORE_FBBLANK; + + return backlight_update_status(bd); +} + +/** + * backlight_disable - Disable backlight + * @bd: the backlight device to disable + */ +static inline int backlight_disable(struct backlight_device *bd) +{ + if (!bd) + return 0; + + bd->props.power = FB_BLANK_POWERDOWN; + bd->props.fb_blank = FB_BLANK_POWERDOWN; + bd->props.state |= BL_CORE_FBBLANK; + + return backlight_update_status(bd); +} + extern struct backlight_device *backlight_device_register(const char *name, struct device *dev, void *devdata, const struct backlight_ops *ops, const struct backlight_properties *props); @@ -141,9 +173,10 @@ extern void devm_backlight_device_unregister(struct device *dev, struct backlight_device *bd); extern void backlight_force_update(struct backlight_device *bd, enum backlight_update_reason reason); -extern bool backlight_device_registered(enum backlight_type type); extern int backlight_register_notifier(struct notifier_block *nb); extern int backlight_unregister_notifier(struct notifier_block *nb); +extern struct backlight_device *backlight_device_get_by_type(enum backlight_type type); +extern int backlight_device_set_brightness(struct backlight_device *bd, unsigned long brightness); #define to_backlight_device(obj) container_of(obj, struct backlight_device, dev) diff --git a/include/linux/bcm2079x.h b/include/linux/bcm2079x.h new file mode 100644 index 000000000000..359a00839325 --- /dev/null +++ b/include/linux/bcm2079x.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2012 Broadcom Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _BCM2079X_H +#define _BCM2079X_H + +#define BCMNFC_MAGIC 0xFA + +/* + * BCMNFC power control via ioctl + * BCMNFC_POWER_CTL(0): power off + * BCMNFC_POWER_CTL(1): power on + * BCMNFC_WAKE_CTL(0): wake off + * BCMNFC_WAKE_CTL(1): wake on + */ +#define BCMNFC_POWER_CTL _IO(BCMNFC_MAGIC, 0x01) +#define BCMNFC_CHANGE_ADDR _IO(BCMNFC_MAGIC, 0x02) +#define BCMNFC_READ_FULL_PACKET _IO(BCMNFC_MAGIC, 0x03) +#define BCMNFC_SET_WAKE_ACTIVE_STATE _IO(BCMNFC_MAGIC, 0x04) +#define BCMNFC_WAKE_CTL _IO(BCMNFC_MAGIC, 0x05) +#define BCMNFC_READ_MULTI_PACKETS _IO(BCMNFC_MAGIC, 0x06) + +struct bcm2079x_platform_data { + unsigned int irq_gpio; + unsigned int en_gpio; + int wake_gpio; +}; + +#endif diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h index c30dbb2b5615..490d06de44b5 100644 --- a/include/linux/blkdev.h +++ b/include/linux/blkdev.h @@ -1057,6 +1057,7 @@ struct blk_plug { struct list_head cb_list; /* md requires an unplug callback */ }; #define BLK_MAX_REQUEST_COUNT 16 +#define BLK_PLUG_FLUSH_SIZE (128 * 1024) struct blk_plug_cb; typedef void (*blk_plug_cb_fn)(struct blk_plug_cb *, bool); diff --git a/include/linux/cdev.h b/include/linux/cdev.h index f8763615a5f2..408bc09ce497 100644 --- a/include/linux/cdev.h +++ b/include/linux/cdev.h @@ -4,6 +4,7 @@ #include <linux/kobject.h> #include <linux/kdev_t.h> #include <linux/list.h> +#include <linux/device.h> struct file_operations; struct inode; @@ -26,6 +27,10 @@ void cdev_put(struct cdev *p); int cdev_add(struct cdev *, dev_t, unsigned); +void cdev_set_parent(struct cdev *p, struct kobject *kobj); +int cdev_device_add(struct cdev *cdev, struct device *dev); +void cdev_device_del(struct cdev *cdev, struct device *dev); + void cdev_del(struct cdev *); void cd_forget(struct inode *); diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 7cd0171963ae..0c67f04dfb13 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -31,6 +31,8 @@ #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ +#define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ +#define CLK_KEEP_REQ_RATE BIT(12) /* keep reqrate on parent rate change */ struct clk; struct clk_hw; @@ -275,6 +277,8 @@ struct clk_fixed_rate { u8 flags; }; +#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw) + extern const struct clk_ops clk_fixed_rate_ops; struct clk *clk_register_fixed_rate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, @@ -313,6 +317,8 @@ struct clk_gate { spinlock_t *lock; }; +#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) + #define CLK_GATE_SET_TO_DISABLE BIT(0) #define CLK_GATE_HIWORD_MASK BIT(1) @@ -375,6 +381,8 @@ struct clk_divider { spinlock_t *lock; }; +#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) + #define CLK_DIVIDER_ONE_BASED BIT(0) #define CLK_DIVIDER_POWER_OF_TWO BIT(1) #define CLK_DIVIDER_ALLOW_ZERO BIT(2) @@ -440,6 +448,8 @@ struct clk_mux { spinlock_t *lock; }; +#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) + #define CLK_MUX_INDEX_ONE BIT(0) #define CLK_MUX_INDEX_BIT BIT(1) #define CLK_MUX_HIWORD_MASK BIT(2) @@ -483,6 +493,8 @@ struct clk_fixed_factor { unsigned int div; }; +#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) + extern const struct clk_ops clk_fixed_factor_ops; struct clk *clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, @@ -497,6 +509,7 @@ struct clk *clk_register_fixed_factor(struct device *dev, const char *name, * @mwidth: width of the numerator bit field * @nshift: shift to the denominator bit field * @nwidth: width of the denominator bit field + * @max_parent: the maximum frequency of fractional divider parent clock * @lock: register lock * * Clock with adjustable fractional divider affecting its output frequency. @@ -511,9 +524,17 @@ struct clk_fractional_divider { u8 nwidth; u32 nmask; u8 flags; + unsigned long max_prate; + void (*approximation)(struct clk_hw *hw, + unsigned long rate, + unsigned long *parent_rate, + unsigned long *m, + unsigned long *n); spinlock_t *lock; }; +#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) + extern const struct clk_ops clk_fractional_divider_ops; struct clk *clk_register_fractional_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, @@ -550,6 +571,8 @@ struct clk_multiplier { spinlock_t *lock; }; +#define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw) + #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0) #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1) @@ -579,6 +602,8 @@ struct clk_composite { const struct clk_ops *gate_ops; }; +#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) + struct clk *clk_register_composite(struct device *dev, const char *name, const char * const *parent_names, int num_parents, struct clk_hw *mux_hw, const struct clk_ops *mux_ops, @@ -601,6 +626,8 @@ struct clk_gpio { struct gpio_desc *gpiod; }; +#define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw) + extern const struct clk_ops clk_gpio_gate_ops; struct clk *clk_register_gpio_gate(struct device *dev, const char *name, const char *parent_name, unsigned gpio, bool active_low, diff --git a/include/linux/clk.h b/include/linux/clk.h index 0df4a51e1a78..d185d86b75ce 100644 --- a/include/linux/clk.h +++ b/include/linux/clk.h @@ -17,10 +17,9 @@ #include <linux/notifier.h> struct device; - struct clk; - -#ifdef CONFIG_COMMON_CLK +struct device_node; +struct of_phandle_args; /** * DOC: clk notifier callback types @@ -79,6 +78,23 @@ struct clk_notifier_data { }; /** + * struct clk_bulk_data - Data used for bulk clk operations. + * + * @id: clock consumer ID + * @clk: struct clk * to store the associated clock + * + * The CLK APIs provide a series of clk_bulk_() API calls as + * a convenience to consumers which require multiple clks. This + * structure is used to manage data for these calls. + */ +struct clk_bulk_data { + const char *id; + struct clk *clk; +}; + +#ifdef CONFIG_COMMON_CLK + +/** * clk_notifier_register: register a clock rate-change notifier callback * @clk: clock whose rate we are interested in * @nb: notifier block with callback function pointer @@ -140,6 +156,18 @@ bool clk_is_match(const struct clk *p, const struct clk *q); #else +static inline int clk_notifier_register(struct clk *clk, + struct notifier_block *nb) +{ + return -ENOTSUPP; +} + +static inline int clk_notifier_unregister(struct clk *clk, + struct notifier_block *nb) +{ + return -ENOTSUPP; +} + static inline long clk_get_accuracy(struct clk *clk) { return -ENOTSUPP; @@ -172,12 +200,20 @@ static inline bool clk_is_match(const struct clk *p, const struct clk *q) */ #ifdef CONFIG_HAVE_CLK_PREPARE int clk_prepare(struct clk *clk); +int __must_check clk_bulk_prepare(int num_clks, + const struct clk_bulk_data *clks); #else static inline int clk_prepare(struct clk *clk) { might_sleep(); return 0; } + +static inline int __must_check clk_bulk_prepare(int num_clks, struct clk_bulk_data *clks) +{ + might_sleep(); + return 0; +} #endif /** @@ -191,11 +227,16 @@ static inline int clk_prepare(struct clk *clk) */ #ifdef CONFIG_HAVE_CLK_PREPARE void clk_unprepare(struct clk *clk); +void clk_bulk_unprepare(int num_clks, const struct clk_bulk_data *clks); #else static inline void clk_unprepare(struct clk *clk) { might_sleep(); } +static inline void clk_bulk_unprepare(int num_clks, struct clk_bulk_data *clks) +{ + might_sleep(); +} #endif #ifdef CONFIG_HAVE_CLK @@ -217,6 +258,44 @@ static inline void clk_unprepare(struct clk *clk) struct clk *clk_get(struct device *dev, const char *id); /** + * clk_bulk_get - lookup and obtain a number of references to clock producer. + * @dev: device for clock "consumer" + * @num_clks: the number of clk_bulk_data + * @clks: the clk_bulk_data table of consumer + * + * This helper function allows drivers to get several clk consumers in one + * operation. If any of the clk cannot be acquired then any clks + * that were obtained will be freed before returning to the caller. + * + * Returns 0 if all clocks specified in clk_bulk_data table are obtained + * successfully, or valid IS_ERR() condition containing errno. + * The implementation uses @dev and @clk_bulk_data.id to determine the + * clock consumer, and thereby the clock producer. + * The clock returned is stored in each @clk_bulk_data.clk field. + * + * Drivers must assume that the clock source is not enabled. + * + * clk_bulk_get should not be called from within interrupt context. + */ +int __must_check clk_bulk_get(struct device *dev, int num_clks, + struct clk_bulk_data *clks); + +/** + * devm_clk_bulk_get - managed get multiple clk consumers + * @dev: device for clock "consumer" + * @num_clks: the number of clk_bulk_data + * @clks: the clk_bulk_data table of consumer + * + * Return 0 on success, an errno on failure. + * + * This helper function allows drivers to get several clk + * consumers in one operation with management, the clks will + * automatically be freed when the device is unbound. + */ +int __must_check devm_clk_bulk_get(struct device *dev, int num_clks, + struct clk_bulk_data *clks); + +/** * devm_clk_get - lookup and obtain a managed reference to a clock producer. * @dev: device for clock "consumer" * @id: clock consumer ID @@ -237,6 +316,23 @@ struct clk *clk_get(struct device *dev, const char *id); struct clk *devm_clk_get(struct device *dev, const char *id); /** + * devm_get_clk_from_child - lookup and obtain a managed reference to a + * clock producer from child node. + * @dev: device for clock "consumer" + * @np: pointer to clock consumer node + * @con_id: clock consumer ID + * + * This function parses the clocks, and uses them to look up the + * struct clk from the registered list of clock providers by using + * @np and @con_id + * + * The clock will automatically be freed when the device is unbound + * from the bus. + */ +struct clk *devm_get_clk_from_child(struct device *dev, + struct device_node *np, const char *con_id); + +/** * clk_enable - inform the system when the clock source should be running. * @clk: clock source * @@ -249,6 +345,18 @@ struct clk *devm_clk_get(struct device *dev, const char *id); int clk_enable(struct clk *clk); /** + * clk_bulk_enable - inform the system when the set of clks should be running. + * @num_clks: the number of clk_bulk_data + * @clks: the clk_bulk_data table of consumer + * + * May be called from atomic contexts. + * + * Returns success (0) or negative errno. + */ +int __must_check clk_bulk_enable(int num_clks, + const struct clk_bulk_data *clks); + +/** * clk_disable - inform the system when the clock source is no longer required. * @clk: clock source * @@ -265,6 +373,24 @@ int clk_enable(struct clk *clk); void clk_disable(struct clk *clk); /** + * clk_bulk_disable - inform the system when the set of clks is no + * longer required. + * @num_clks: the number of clk_bulk_data + * @clks: the clk_bulk_data table of consumer + * + * Inform the system that a set of clks is no longer required by + * a driver and may be shut down. + * + * May be called from atomic contexts. + * + * Implementation detail: if the set of clks is shared between + * multiple drivers, clk_bulk_enable() calls must be balanced by the + * same number of clk_bulk_disable() calls for the clock source to be + * disabled. + */ +void clk_bulk_disable(int num_clks, const struct clk_bulk_data *clks); + +/** * clk_get_rate - obtain the current clock rate (in Hz) for a clock source. * This is only valid once the clock source has been enabled. * @clk: clock source @@ -284,6 +410,19 @@ unsigned long clk_get_rate(struct clk *clk); void clk_put(struct clk *clk); /** + * clk_bulk_put - "free" the clock source + * @num_clks: the number of clk_bulk_data + * @clks: the clk_bulk_data table of consumer + * + * Note: drivers must ensure that all clk_bulk_enable calls made on this + * clock source are balanced by clk_bulk_disable calls prior to calling + * this function. + * + * clk_bulk_put should not be called from within interrupt context. + */ +void clk_bulk_put(int num_clks, struct clk_bulk_data *clks); + +/** * devm_clk_put - "free" a managed clock source * @dev: device used to acquire the clock * @clk: clock source acquired with devm_clk_get() @@ -415,13 +554,33 @@ static inline struct clk *clk_get(struct device *dev, const char *id) return NULL; } +static inline int __must_check clk_bulk_get(struct device *dev, int num_clks, + struct clk_bulk_data *clks) +{ + return 0; +} + static inline struct clk *devm_clk_get(struct device *dev, const char *id) { return NULL; } +static inline int __must_check devm_clk_bulk_get(struct device *dev, int num_clks, + struct clk_bulk_data *clks) +{ + return 0; +} + +static inline struct clk *devm_get_clk_from_child(struct device *dev, + struct device_node *np, const char *con_id) +{ + return NULL; +} + static inline void clk_put(struct clk *clk) {} +static inline void clk_bulk_put(int num_clks, struct clk_bulk_data *clks) {} + static inline void devm_clk_put(struct device *dev, struct clk *clk) {} static inline int clk_enable(struct clk *clk) @@ -429,8 +588,17 @@ static inline int clk_enable(struct clk *clk) return 0; } +static inline int __must_check clk_bulk_enable(int num_clks, struct clk_bulk_data *clks) +{ + return 0; +} + static inline void clk_disable(struct clk *clk) {} + +static inline void clk_bulk_disable(int num_clks, + struct clk_bulk_data *clks) {} + static inline unsigned long clk_get_rate(struct clk *clk) { return 0; @@ -461,6 +629,10 @@ static inline struct clk *clk_get_parent(struct clk *clk) return NULL; } +static inline struct clk *clk_get_sys(const char *dev_id, const char *con_id) +{ + return NULL; +} #endif /* clk_prepare_enable helps cases using clk_enable in non-atomic context. */ @@ -485,8 +657,27 @@ static inline void clk_disable_unprepare(struct clk *clk) clk_unprepare(clk); } -struct device_node; -struct of_phandle_args; +static inline int __must_check clk_bulk_prepare_enable(int num_clks, + struct clk_bulk_data *clks) +{ + int ret; + + ret = clk_bulk_prepare(num_clks, clks); + if (ret) + return ret; + ret = clk_bulk_enable(num_clks, clks); + if (ret) + clk_bulk_unprepare(num_clks, clks); + + return ret; +} + +static inline void clk_bulk_disable_unprepare(int num_clks, + struct clk_bulk_data *clks) +{ + clk_bulk_disable(num_clks, clks); + clk_bulk_unprepare(num_clks, clks); +} #if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK) struct clk *of_clk_get(struct device_node *np, int index); diff --git a/include/linux/console.h b/include/linux/console.h index ea731af2451e..67cc09b887de 100644 --- a/include/linux/console.h +++ b/include/linux/console.h @@ -116,6 +116,9 @@ static inline int con_debug_leave(void) #define CON_ANYTIME (16) /* Safe to call when cpu is offline */ #define CON_BRL (32) /* Used for a braille device */ #define CON_EXTENDED (64) /* Use the extended output format a la /dev/kmsg */ +#if defined(CONFIG_ARCH_ROCKCHIP) && defined(CONFIG_PSTORE_CONSOLE) +#define CON_PSTORE (128) /* Print to pstore console anyway */ +#endif struct console { char name[16]; diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index 490d577aa144..91f97be1ede7 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -695,4 +695,53 @@ int cpufreq_generic_init(struct cpufreq_policy *policy, struct sched_domain; unsigned long cpufreq_scale_freq_capacity(struct sched_domain *sd, int cpu); unsigned long cpufreq_scale_max_freq_capacity(int cpu); +#ifdef CONFIG_ARM_ROCKCHIP_CPUFREQ +unsigned int rockchip_cpufreq_adjust_target(int cpu, unsigned int freq); +int rockchip_cpufreq_get_scale(int cpu); +int rockchip_cpufreq_set_scale_rate(struct device *dev, unsigned long rate); +int rockchip_cpufreq_set_temp_limit_rate(struct device *dev, + unsigned long rate); +int rockchip_cpufreq_check_rate_volt(struct device *dev); +int rockchip_cpufreq_update_policy(struct device *dev); +int rockchip_cpufreq_update_cur_volt(struct device *dev); +#else +static inline unsigned int rockchip_cpufreq_adjust_target(int cpu, + unsigned int freq) +{ + return freq; +} + +static inline int rockchip_cpufreq_get_scale(int cpu) +{ + return -EINVAL; +} + +static inline int rockchip_cpufreq_set_scale_rate(struct device *dev, + unsigned long rate) +{ + return -EINVAL; +} + +static inline int rockchip_cpufreq_check_rate_volt(struct device *dev) +{ + return -EINVAL; +} + +static inline int rockchip_cpufreq_set_temp_limit_rate(struct device *dev, + unsigned long rate) +{ + return -EINVAL; +} + +static inline int rockchip_cpufreq_update_policy(struct device *dev) +{ + return -EINVAL; +} + +static inline int rockchip_cpufreq_update_cur_volt(struct device *dev) +{ + return -EINVAL; +} + +#endif #endif /* _LINUX_CPUFREQ_H */ diff --git a/include/linux/debugfs.h b/include/linux/debugfs.h index 19c066dce1da..33d708d91a5c 100644 --- a/include/linux/debugfs.h +++ b/include/linux/debugfs.h @@ -46,6 +46,8 @@ extern struct dentry *arch_debugfs_dir; /* declared over in file.c */ extern const struct file_operations debugfs_file_operations; +struct dentry *debugfs_lookup(const char *name, struct dentry *parent); + struct dentry *debugfs_create_file(const char *name, umode_t mode, struct dentry *parent, void *data, const struct file_operations *fops); @@ -134,6 +136,12 @@ ssize_t debugfs_write_file_bool(struct file *file, const char __user *user_buf, * want to duplicate the design decision mistakes of procfs and devfs again. */ +static inline struct dentry *debugfs_lookup(const char *name, + struct dentry *parent) +{ + return ERR_PTR(-ENODEV); +} + static inline struct dentry *debugfs_create_file(const char *name, umode_t mode, struct dentry *parent, void *data, const struct file_operations *fops) diff --git a/include/linux/devfreq.h b/include/linux/devfreq.h index 68030e22af35..073cec2659f2 100644 --- a/include/linux/devfreq.h +++ b/include/linux/devfreq.h @@ -19,6 +19,13 @@ #define DEVFREQ_NAME_LEN 16 +/* DEVFREQ notifier interface */ +#define DEVFREQ_TRANSITION_NOTIFIER (0) + +/* Transition notifiers of DEVFREQ_TRANSITION_NOTIFIER */ +#define DEVFREQ_PRECHANGE (0) +#define DEVFREQ_POSTCHANGE (1) + struct devfreq; /** @@ -143,6 +150,7 @@ struct devfreq_governor { * @trans_table: Statistics of devfreq transitions * @time_in_state: Statistics of devfreq states * @last_stat_updated: The last time stat updated + * @transition_notifier_list: list head of DEVFREQ_TRANSITION_NOTIFIER notifier * * This structure stores the devfreq information for a give device. * @@ -177,6 +185,13 @@ struct devfreq { unsigned int *trans_table; unsigned long *time_in_state; unsigned long last_stat_updated; + + struct srcu_notifier_head transition_notifier_list; +}; + +struct devfreq_freqs { + unsigned long old; + unsigned long new; }; #if defined(CONFIG_PM_DEVFREQ) @@ -207,6 +222,22 @@ extern int devm_devfreq_register_opp_notifier(struct device *dev, struct devfreq *devfreq); extern void devm_devfreq_unregister_opp_notifier(struct device *dev, struct devfreq *devfreq); +extern int devfreq_register_notifier(struct devfreq *devfreq, + struct notifier_block *nb, + unsigned int list); +extern int devfreq_unregister_notifier(struct devfreq *devfreq, + struct notifier_block *nb, + unsigned int list); +extern int devm_devfreq_register_notifier(struct device *dev, + struct devfreq *devfreq, + struct notifier_block *nb, + unsigned int list); +extern void devm_devfreq_unregister_notifier(struct device *dev, + struct devfreq *devfreq, + struct notifier_block *nb, + unsigned int list); +extern struct devfreq *devfreq_get_devfreq_by_phandle(struct device *dev, + int index); /** * devfreq_update_stats() - update the last_status pointer in struct devfreq @@ -307,6 +338,41 @@ static inline void devm_devfreq_unregister_opp_notifier(struct device *dev, { } +static inline int devfreq_register_notifier(struct devfreq *devfreq, + struct notifier_block *nb, + unsigned int list) +{ + return 0; +} + +static inline int devfreq_unregister_notifier(struct devfreq *devfreq, + struct notifier_block *nb, + unsigned int list) +{ + return 0; +} + +static inline int devm_devfreq_register_notifier(struct device *dev, + struct devfreq *devfreq, + struct notifier_block *nb, + unsigned int list) +{ + return 0; +} + +static inline void devm_devfreq_unregister_notifier(struct device *dev, + struct devfreq *devfreq, + struct notifier_block *nb, + unsigned int list) +{ +} + +static inline struct devfreq *devfreq_get_devfreq_by_phandle(struct device *dev, + int index) +{ + return ERR_PTR(-ENODEV); +} + static inline int devfreq_update_stats(struct devfreq *df) { return -EINVAL; diff --git a/include/linux/devfreq_cooling.h b/include/linux/devfreq_cooling.h index 7adf6cc4b305..b84123b62d83 100644 --- a/include/linux/devfreq_cooling.h +++ b/include/linux/devfreq_cooling.h @@ -20,7 +20,6 @@ #include <linux/devfreq.h> #include <linux/thermal.h> -#ifdef CONFIG_DEVFREQ_THERMAL /** * struct devfreq_cooling_power - Devfreq cooling power ops @@ -37,12 +36,16 @@ * @dyn_power_coeff * frequency * voltage^2 */ struct devfreq_cooling_power { - unsigned long (*get_static_power)(unsigned long voltage); - unsigned long (*get_dynamic_power)(unsigned long freq, + unsigned long (*get_static_power)(struct devfreq *devfreq, + unsigned long voltage); + unsigned long (*get_dynamic_power)(struct devfreq *devfreq, + unsigned long freq, unsigned long voltage); unsigned long dyn_power_coeff; }; +#ifdef CONFIG_DEVFREQ_THERMAL + struct thermal_cooling_device * of_devfreq_cooling_register_power(struct device_node *np, struct devfreq *df, struct devfreq_cooling_power *dfc_power); @@ -53,7 +56,7 @@ void devfreq_cooling_unregister(struct thermal_cooling_device *dfc); #else /* !CONFIG_DEVFREQ_THERMAL */ -struct thermal_cooling_device * +static inline struct thermal_cooling_device * of_devfreq_cooling_register_power(struct device_node *np, struct devfreq *df, struct devfreq_cooling_power *dfc_power) { diff --git a/include/linux/device.h b/include/linux/device.h index 834000903525..5f9fa7fb2088 100644 --- a/include/linux/device.h +++ b/include/linux/device.h @@ -679,10 +679,26 @@ extern void devm_free_pages(struct device *dev, unsigned long addr); void __iomem *devm_ioremap_resource(struct device *dev, struct resource *res); +void __iomem *devm_of_iomap(struct device *dev, + struct device_node *node, int index, + resource_size_t *size); + /* allows to add/remove a custom action to devres stack */ int devm_add_action(struct device *dev, void (*action)(void *), void *data); void devm_remove_action(struct device *dev, void (*action)(void *), void *data); +static inline int devm_add_action_or_reset(struct device *dev, + void (*action)(void *), void *data) +{ + int ret; + + ret = devm_add_action(dev, action, data); + if (ret) + action(data); + + return ret; +} + struct device_dma_parameters { /* * a low level driver may set these to teach IOMMU code about diff --git a/include/linux/display-sys.h b/include/linux/display-sys.h new file mode 100644 index 000000000000..328e26aebeec --- /dev/null +++ b/include/linux/display-sys.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _LINUX_DISPLAY_RK_H +#define _LINUX_DISPLAY_RK_H + +#include <linux/device.h> +#include <linux/fb.h> +#include <linux/list.h> +#include <dt-bindings/display/rk_fb.h> + +struct rk_display_device; + +enum rk_display_priority { + DISPLAY_PRIORITY_TV = 0, + DISPLAY_PRIORITY_YPBPR, + DISPLAY_PRIORITY_VGA, + DISPLAY_PRIORITY_HDMI, + DISPLAY_PRIORITY_LCD, +}; + +enum { + DISPLAY_SCALE_X = 0, + DISPLAY_SCALE_Y +}; + +enum rk_display_property { + DISPLAY_MAIN = 0, + DISPLAY_AUX +}; + + +/* HDMI mode list*/ +struct display_modelist { + struct list_head list; + struct fb_videomode mode; + unsigned int vic; + unsigned int format_3d; + unsigned int detail_3d; +}; + +/* This structure defines all the properties of a Display. */ +struct rk_display_driver { + void (*suspend)(struct rk_display_device *, pm_message_t state); + void (*resume)(struct rk_display_device *); + int (*probe)(struct rk_display_device *, void *); + int (*remove)(struct rk_display_device *); +}; + +struct rk_display_ops { + int (*setenable)(struct rk_display_device *, int enable); + int (*getenable)(struct rk_display_device *); + int (*getstatus)(struct rk_display_device *); + int (*getmodelist)(struct rk_display_device *, + struct list_head **modelist); + int (*setmode)(struct rk_display_device *, + struct fb_videomode *mode); + int (*getmode)(struct rk_display_device *, + struct fb_videomode *mode); + int (*setscale)(struct rk_display_device *, int, int); + int (*getscale)(struct rk_display_device *, int); + int (*get3dmode)(struct rk_display_device *); + int (*set3dmode)(struct rk_display_device *, int); + int (*getcolor)(struct rk_display_device *, char *); + int (*setcolor)(struct rk_display_device *, const char *, int); + int (*setdebug)(struct rk_display_device *, int); + int (*getdebug)(struct rk_display_device *, char *); + int (*getedidaudioinfo)(struct rk_display_device *, + char *audioinfo, int len); + int (*getmonspecs)(struct rk_display_device *, + struct fb_monspecs *monspecs); + int (*getvrinfo)(struct rk_display_device *, char *); +}; + +struct rk_display_device { + struct module *owner; /* Owner module */ + struct rk_display_driver *driver; + struct device *parent; /* This is the parent */ + struct device *dev; /* This is this display device */ + struct mutex lock; + void *priv_data; + char type[16]; + char *name; + int idx; + struct rk_display_ops *ops; + int priority; + int property; + struct list_head list; +}; + +struct rk_display_devicelist { + struct list_head list; + struct rk_display_device *dev; +}; + +struct rk_display_device + *rk_display_device_register(struct rk_display_driver *driver, + struct device *parent, void *devdata); +void rk_display_device_unregister(struct rk_display_device *dev); +void rk_display_device_enable(struct rk_display_device *ddev); +void rk_display_device_enable_other(struct rk_display_device *ddev); +void rk_display_device_disable_other(struct rk_display_device *ddev); +void rk_display_device_select(int property, int priority); + +int display_add_videomode(const struct fb_videomode *mode, + struct list_head *head); +#endif diff --git a/include/linux/dma-attrs.h b/include/linux/dma-attrs.h index c8e1831d7572..78e2d5ab9d4d 100644 --- a/include/linux/dma-attrs.h +++ b/include/linux/dma-attrs.h @@ -18,6 +18,7 @@ enum dma_attr { DMA_ATTR_NO_KERNEL_MAPPING, DMA_ATTR_SKIP_CPU_SYNC, DMA_ATTR_FORCE_CONTIGUOUS, + DMA_ATTR_ALLOC_SINGLE_PAGES, DMA_ATTR_MAX, }; diff --git a/include/linux/dma-buf.h b/include/linux/dma-buf.h index f98bd7068d55..d58bd33d6435 100644 --- a/include/linux/dma-buf.h +++ b/include/linux/dma-buf.h @@ -90,6 +90,9 @@ struct dma_buf_ops { * if the call would block. */ + int (*set_release_callback)(void (*release_callback)(void *data), + void *data); + void *(*get_release_callback_data)(void *callback); /* after final dma_buf_put() */ void (*release)(struct dma_buf *); @@ -125,6 +128,7 @@ struct dma_buf { size_t size; struct file *file; struct list_head attachments; + struct list_head release_callbacks; const struct dma_buf_ops *ops; /* mutex to serialize list manipulation, attach/detach and vmap/unmap */ struct mutex lock; @@ -209,6 +213,12 @@ static inline void get_dma_buf(struct dma_buf *dmabuf) get_file(dmabuf->file); } +int dma_buf_set_release_callback(struct dma_buf *dmabuf, + void (*callback)(void *), void *data); + +void *dma_buf_get_release_callback_data(struct dma_buf *dmabuf, + void (*callback)(void *)); + struct dma_buf_attachment *dma_buf_attach(struct dma_buf *dmabuf, struct device *dev); void dma_buf_detach(struct dma_buf *dmabuf, diff --git a/include/linux/dma-iommu.h b/include/linux/dma-iommu.h index 19baa7f4f403..67503d43e49f 100644 --- a/include/linux/dma-iommu.h +++ b/include/linux/dma-iommu.h @@ -63,6 +63,10 @@ void iommu_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, int iommu_dma_supported(struct device *dev, u64 mask); int iommu_dma_mapping_error(struct device *dev, dma_addr_t dma_addr); +bool common_iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, + const struct iommu_ops *ops); +void common_iommu_teardown_dma_ops(struct device *dev); + #else struct iommu_domain; @@ -81,6 +85,16 @@ static inline void iommu_put_dma_cookie(struct iommu_domain *domain) { } +static inline bool common_iommu_setup_dma_ops(struct device *dev, u64 dma_base, + u64 size, const struct iommu_ops *ops) +{ + return false; +} + +static inline void common_iommu_teardown_dma_ops(struct device *dev) +{ +} + #endif /* CONFIG_IOMMU_DMA */ #endif /* __KERNEL__ */ #endif /* __DMA_IOMMU_H */ diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index a16d1851cfb1..3050f88daf9e 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -365,6 +365,8 @@ struct dma_slave_config { u32 dst_maxburst; bool device_fc; unsigned int slave_id; + unsigned int src_interlace_size; + unsigned int dst_interlace_size; }; /** @@ -401,6 +403,7 @@ enum dma_residue_granularity { * since the enum dma_transfer_direction is not defined as bits for each * type of direction, the dma controller should fill (1 << <TYPE>) and same * should be checked by controller as well + * @max_burst: max burst capability per-transfer * @cmd_pause: true, if pause and thereby resume is supported * @cmd_terminate: true, if terminate cmd is supported * @residue_granularity: granularity of the reported transfer residue @@ -411,6 +414,7 @@ struct dma_slave_caps { u32 src_addr_widths; u32 dst_addr_widths; u32 directions; + u32 max_burst; bool cmd_pause; bool cmd_terminate; enum dma_residue_granularity residue_granularity; @@ -627,6 +631,7 @@ enum dmaengine_alignment { * the enum dma_transfer_direction is not defined as bits for * each type of direction, the dma controller should fill (1 << * <TYPE>) and same should be checked by controller as well + * @max_burst: max burst capability per-transfer * @residue_granularity: granularity of the transfer residue reported * by tx_status * @device_alloc_chan_resources: allocate resources and return the @@ -654,6 +659,8 @@ enum dmaengine_alignment { * paused. Returns 0 or an error code * @device_terminate_all: Aborts all transfers on a channel. Returns 0 * or an error code + * @device_synchronize: Synchronizes the termination of a transfers to the + * current context. * @device_tx_status: poll for transaction completion, the optional * txstate parameter can be supplied with a pointer to get a * struct with auxiliary transfer status information, otherwise the call @@ -681,6 +688,7 @@ struct dma_device { u32 src_addr_widths; u32 dst_addr_widths; u32 directions; + u32 max_burst; enum dma_residue_granularity residue_granularity; int (*device_alloc_chan_resources)(struct dma_chan *chan); @@ -737,6 +745,7 @@ struct dma_device { int (*device_pause)(struct dma_chan *chan); int (*device_resume)(struct dma_chan *chan); int (*device_terminate_all)(struct dma_chan *chan); + void (*device_synchronize)(struct dma_chan *chan); enum dma_status (*device_tx_status)(struct dma_chan *chan, dma_cookie_t cookie, @@ -846,6 +855,13 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_sg( src_sg, src_nents, flags); } +/** + * dmaengine_terminate_all() - Terminate all active DMA transfers + * @chan: The channel for which to terminate the transfers + * + * This function is DEPRECATED use either dmaengine_terminate_sync() or + * dmaengine_terminate_async() instead. + */ static inline int dmaengine_terminate_all(struct dma_chan *chan) { if (chan->device->device_terminate_all) @@ -854,6 +870,86 @@ static inline int dmaengine_terminate_all(struct dma_chan *chan) return -ENOSYS; } +/** + * dmaengine_terminate_async() - Terminate all active DMA transfers + * @chan: The channel for which to terminate the transfers + * + * Calling this function will terminate all active and pending descriptors + * that have previously been submitted to the channel. It is not guaranteed + * though that the transfer for the active descriptor has stopped when the + * function returns. Furthermore it is possible the complete callback of a + * submitted transfer is still running when this function returns. + * + * dmaengine_synchronize() needs to be called before it is safe to free + * any memory that is accessed by previously submitted descriptors or before + * freeing any resources accessed from within the completion callback of any + * perviously submitted descriptors. + * + * This function can be called from atomic context as well as from within a + * complete callback of a descriptor submitted on the same channel. + * + * If none of the two conditions above apply consider using + * dmaengine_terminate_sync() instead. + */ +static inline int dmaengine_terminate_async(struct dma_chan *chan) +{ + if (chan->device->device_terminate_all) + return chan->device->device_terminate_all(chan); + + return -EINVAL; +} + +/** + * dmaengine_synchronize() - Synchronize DMA channel termination + * @chan: The channel to synchronize + * + * Synchronizes to the DMA channel termination to the current context. When this + * function returns it is guaranteed that all transfers for previously issued + * descriptors have stopped and and it is safe to free the memory assoicated + * with them. Furthermore it is guaranteed that all complete callback functions + * for a previously submitted descriptor have finished running and it is safe to + * free resources accessed from within the complete callbacks. + * + * The behavior of this function is undefined if dma_async_issue_pending() has + * been called between dmaengine_terminate_async() and this function. + * + * This function must only be called from non-atomic context and must not be + * called from within a complete callback of a descriptor submitted on the same + * channel. + */ +static inline void dmaengine_synchronize(struct dma_chan *chan) +{ + if (chan->device->device_synchronize) + chan->device->device_synchronize(chan); +} + +/** + * dmaengine_terminate_sync() - Terminate all active DMA transfers + * @chan: The channel for which to terminate the transfers + * + * Calling this function will terminate all active and pending transfers + * that have previously been submitted to the channel. It is similar to + * dmaengine_terminate_async() but guarantees that the DMA transfer has actually + * stopped and that all complete callbacks have finished running when the + * function returns. + * + * This function must only be called from non-atomic context and must not be + * called from within a complete callback of a descriptor submitted on the same + * channel. + */ +static inline int dmaengine_terminate_sync(struct dma_chan *chan) +{ + int ret; + + ret = dmaengine_terminate_async(chan); + if (ret) + return ret; + + dmaengine_synchronize(chan); + + return 0; +} + static inline int dmaengine_pause(struct dma_chan *chan) { if (chan->device->device_pause) diff --git a/include/linux/dp501.h b/include/linux/dp501.h new file mode 100644 index 000000000000..82cac02b82cd --- /dev/null +++ b/include/linux/dp501.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DP501_H_ +#define __DP501_H_ + +#include <linux/i2c.h> +#include<linux/earlysuspend.h> + + +#define DP501_P0_ADDR (0x30) +#define DP501_P1_ADDR (0x32) +#define DP501_P2_ADDR (0x34) +#define DP501_P3_ADDR (0x36) + +#define DP501_SCL_RATE (100*1000) +#define MAX_REG (0xff) + + + +#define CHIP_ID_L (0x80) +#define CHIP_ID_H (0x81) + +struct dp501_platform_data { + unsigned int dvdd33_en_pin; + int dvdd33_en_val; + unsigned int dvdd18_en_pin; + int dvdd18_en_val; + unsigned int edp_rst_pin; + int (*power_ctl)(void); +}; + +struct dp501 { + struct i2c_client *client; + struct dp501_platform_data *pdata; + int (*edp_init)(struct i2c_client *client); +#ifdef CONFIG_HAS_EARLYSUSPEND + struct early_suspend early_suspend; +#endif +}; + +#endif diff --git a/include/linux/extcon.h b/include/linux/extcon.h index 7abf674c388c..dd1f925d0e01 100644 --- a/include/linux/extcon.h +++ b/include/linux/extcon.h @@ -29,6 +29,15 @@ #include <linux/device.h> /* + * Define the type of supported external connectors + */ +#define EXTCON_TYPE_USB BIT(0) /* USB connector */ +#define EXTCON_TYPE_CHG BIT(1) /* Charger connector */ +#define EXTCON_TYPE_JACK BIT(2) /* Jack connector */ +#define EXTCON_TYPE_DISP BIT(3) /* Display connector */ +#define EXTCON_TYPE_MISC BIT(4) /* Miscellaneous connector */ + +/* * Define the unique id of supported external connectors */ #define EXTCON_NONE 0 @@ -36,6 +45,7 @@ /* USB external connector */ #define EXTCON_USB 1 #define EXTCON_USB_HOST 2 +#define EXTCON_USB_VBUS_EN 3 /* Charging external connector */ #define EXTCON_CHG_USB_SDP 5 /* Standard Downstream Port */ @@ -60,6 +70,7 @@ #define EXTCON_DISP_MHL 41 /* Mobile High-Definition Link */ #define EXTCON_DISP_DVI 42 /* Digital Visual Interface */ #define EXTCON_DISP_VGA 43 /* Video Graphics Array */ +#define EXTCON_DISP_DP 44 /* Display Port */ /* Miscellaneous external connector */ #define EXTCON_DOCK 60 @@ -68,6 +79,74 @@ #define EXTCON_NUM 63 +/* + * Define the property of supported external connectors. + * + * When adding the new extcon property, they *must* have + * the type/value/default information. Also, you *have to* + * modify the EXTCON_PROP_[type]_START/END definitions + * which mean the range of the supported properties + * for each extcon type. + * + * The naming style of property + * : EXTCON_PROP_[type]_[property name] + * + * EXTCON_PROP_USB_[property name] : USB property + * EXTCON_PROP_CHG_[property name] : Charger property + * EXTCON_PROP_JACK_[property name] : Jack property + * EXTCON_PROP_DISP_[property name] : Display property + */ + +/* + * Properties of EXTCON_TYPE_USB. + * + * - EXTCON_PROP_USB_VBUS + * @type: integer (intval) + * @value: 0 (low) or 1 (high) + * @default: 0 (low) + * - EXTCON_PROP_USB_TYPEC_POLARITY + * @type: integer (intval) + * @value: 0 (normal) or 1 (flip) + * @default: 0 (normal) + * - EXTCON_PROP_USB_SS (SuperSpeed) + * @type: integer (intval) + * @value: 0 (USB/USB2) or 1 (USB3) + * @default: 0 (USB/USB2) + * + */ +#define EXTCON_PROP_USB_VBUS 0 +#define EXTCON_PROP_USB_TYPEC_POLARITY 1 +#define EXTCON_PROP_USB_SS 2 + +#define EXTCON_PROP_USB_MIN 0 +#define EXTCON_PROP_USB_MAX 2 +#define EXTCON_PROP_USB_CNT (EXTCON_PROP_USB_MAX - EXTCON_PROP_USB_MIN + 1) + +/* Properties of EXTCON_TYPE_CHG. */ +#define EXTCON_PROP_CHG_MIN 50 +#define EXTCON_PROP_CHG_MAX 50 +#define EXTCON_PROP_CHG_CNT (EXTCON_PROP_CHG_MAX - EXTCON_PROP_CHG_MIN + 1) + +/* Properties of EXTCON_TYPE_JACK. */ +#define EXTCON_PROP_JACK_MIN 100 +#define EXTCON_PROP_JACK_MAX 100 +#define EXTCON_PROP_JACK_CNT (EXTCON_PROP_JACK_MAX - EXTCON_PROP_JACK_MIN + 1) + +/* Properties of EXTCON_TYPE_DISP. */ +#define EXTCON_PROP_DISP_MIN 150 +#define EXTCON_PROP_DISP_MAX 150 +#define EXTCON_PROP_DISP_CNT (EXTCON_PROP_DISP_MAX - EXTCON_PROP_DISP_MIN + 1) + +/* + * Define the type of property's value. + * + * Define the property's value as union type. Because each property + * would need the different data type to store it. + */ +union extcon_property_value { + int intval; /* type : integer (intval) */ +}; + struct extcon_cable; /** @@ -126,42 +205,6 @@ struct extcon_dev { struct device_attribute *d_attrs_muex; }; -/** - * struct extcon_cable - An internal data for each cable of extcon device. - * @edev: The extcon device - * @cable_index: Index of this cable in the edev - * @attr_g: Attribute group for the cable - * @attr_name: "name" sysfs entry - * @attr_state: "state" sysfs entry - * @attrs: Array pointing to attr_name and attr_state for attr_g - */ -struct extcon_cable { - struct extcon_dev *edev; - int cable_index; - - struct attribute_group attr_g; - struct device_attribute attr_name; - struct device_attribute attr_state; - - struct attribute *attrs[3]; /* to be fed to attr_g.attrs */ -}; - -/** - * struct extcon_specific_cable_nb - An internal data for - * extcon_register_interest(). - * @user_nb: user provided notifier block for events from - * a specific cable. - * @cable_index: the target cable. - * @edev: the target extcon device. - * @previous_value: the saved previous event value. - */ -struct extcon_specific_cable_nb { - struct notifier_block *user_nb; - int cable_index; - struct extcon_dev *edev; - unsigned long previous_value; -}; - #if IS_ENABLED(CONFIG_EXTCON) /* @@ -186,43 +229,43 @@ extern struct extcon_dev *devm_extcon_dev_allocate(struct device *dev, extern void devm_extcon_dev_free(struct device *dev, struct extcon_dev *edev); /* - * get/set/update_state access the 32b encoded state value, which represents - * states of all possible cables of the multistate port. For example, if one - * calls extcon_set_state(edev, 0x7), it may mean that all the three cables - * are attached to the port. + * get/set_state access each bit of the 32b encoded state value. + * They are used to access the status of each cable based on the cable id. */ -static inline u32 extcon_get_state(struct extcon_dev *edev) -{ - return edev->state; -} - -extern int extcon_set_state(struct extcon_dev *edev, u32 state); -extern int extcon_update_state(struct extcon_dev *edev, u32 mask, u32 state); +extern int extcon_get_state(struct extcon_dev *edev, unsigned int id); +extern int extcon_set_state(struct extcon_dev *edev, unsigned int id, + bool cable_state); +extern int extcon_set_state_sync(struct extcon_dev *edev, unsigned int id, + bool cable_state); /* - * get/set_cable_state access each bit of the 32b encoded state value. - * They are used to access the status of each cable based on the cable_name. + * Synchronize the state and property data for a specific external connector. */ -extern int extcon_get_cable_state_(struct extcon_dev *edev, unsigned int id); -extern int extcon_set_cable_state_(struct extcon_dev *edev, unsigned int id, - bool cable_state); +extern int extcon_sync(struct extcon_dev *edev, unsigned int id); -extern int extcon_get_cable_state(struct extcon_dev *edev, - const char *cable_name); -extern int extcon_set_cable_state(struct extcon_dev *edev, - const char *cable_name, bool cable_state); +/* + * get/set_property access the property value of each external connector. + * They are used to access the property of each cable based on the property id. + */ +extern int extcon_get_property(struct extcon_dev *edev, unsigned int id, + unsigned int prop, + union extcon_property_value *prop_val); +extern int extcon_set_property(struct extcon_dev *edev, unsigned int id, + unsigned int prop, + union extcon_property_value prop_val); +extern int extcon_set_property_sync(struct extcon_dev *edev, unsigned int id, + unsigned int prop, + union extcon_property_value prop_val); /* - * Following APIs are for notifiees (those who want to be notified) - * to register a callback for events from a specific cable of the extcon. - * Notifiees are the connected device drivers wanting to get notified by - * a specific external port of a connection device. + * get/set_property_capability set the capability of the property for each + * external connector. They are used to set the capability of the property + * of each external connector based on the id and property. */ -extern int extcon_register_interest(struct extcon_specific_cable_nb *obj, - const char *extcon_name, - const char *cable_name, - struct notifier_block *nb); -extern int extcon_unregister_interest(struct extcon_specific_cable_nb *nb); +extern int extcon_get_property_capability(struct extcon_dev *edev, + unsigned int id, unsigned int prop); +extern int extcon_set_property_capability(struct extcon_dev *edev, + unsigned int id, unsigned int prop); /* * Following APIs are to monitor every action of a notifier. @@ -235,6 +278,12 @@ extern int extcon_register_notifier(struct extcon_dev *edev, unsigned int id, struct notifier_block *nb); extern int extcon_unregister_notifier(struct extcon_dev *edev, unsigned int id, struct notifier_block *nb); +extern int devm_extcon_register_notifier(struct device *dev, + struct extcon_dev *edev, unsigned int id, + struct notifier_block *nb); +extern void devm_extcon_unregister_notifier(struct device *dev, + struct extcon_dev *edev, unsigned int id, + struct notifier_block *nb); /* * Following API get the extcon device from devicetree. @@ -246,6 +295,7 @@ extern struct extcon_dev *extcon_get_edev_by_phandle(struct device *dev, /* Following API to get information of extcon device */ extern const char *extcon_get_edev_name(struct extcon_dev *edev); + #else /* CONFIG_EXTCON */ static inline int extcon_dev_register(struct extcon_dev *edev) { @@ -278,42 +328,57 @@ static inline struct extcon_dev *devm_extcon_dev_allocate(struct device *dev, static inline void devm_extcon_dev_free(struct extcon_dev *edev) { } -static inline u32 extcon_get_state(struct extcon_dev *edev) + +static inline int extcon_get_state(struct extcon_dev *edev, unsigned int id) { return 0; } -static inline int extcon_set_state(struct extcon_dev *edev, u32 state) +static inline int extcon_set_state(struct extcon_dev *edev, unsigned int id, + bool cable_state) { return 0; } -static inline int extcon_update_state(struct extcon_dev *edev, u32 mask, - u32 state) +static inline int extcon_set_state_sync(struct extcon_dev *edev, unsigned int id, + bool cable_state) { return 0; } -static inline int extcon_get_cable_state_(struct extcon_dev *edev, - unsigned int id) +static inline int extcon_sync(struct extcon_dev *edev, unsigned int id) +{ + return 0; +} + +static inline int extcon_get_property(struct extcon_dev *edev, unsigned int id, + unsigned int prop, + union extcon_property_value *prop_val) +{ + return 0; +} +static inline int extcon_set_property(struct extcon_dev *edev, unsigned int id, + unsigned int prop, + union extcon_property_value prop_val) { return 0; } -static inline int extcon_set_cable_state_(struct extcon_dev *edev, - unsigned int id, bool cable_state) +static inline int extcon_set_property_sync(struct extcon_dev *edev, + unsigned int id, unsigned int prop, + union extcon_property_value prop_val) { return 0; } -static inline int extcon_get_cable_state(struct extcon_dev *edev, - const char *cable_name) +static inline int extcon_get_property_capability(struct extcon_dev *edev, + unsigned int id, unsigned int prop) { return 0; } -static inline int extcon_set_cable_state(struct extcon_dev *edev, - const char *cable_name, int state) +static inline int extcon_set_property_capability(struct extcon_dev *edev, + unsigned int id, unsigned int prop) { return 0; } @@ -337,24 +402,56 @@ static inline int extcon_unregister_notifier(struct extcon_dev *edev, return 0; } +static inline int devm_extcon_register_notifier(struct device *dev, + struct extcon_dev *edev, unsigned int id, + struct notifier_block *nb) +{ + return -ENOSYS; +} + +static inline void devm_extcon_unregister_notifier(struct device *dev, + struct extcon_dev *edev, unsigned int id, + struct notifier_block *nb) { } + +static inline struct extcon_dev *extcon_get_edev_by_phandle(struct device *dev, + int index) +{ + return ERR_PTR(-ENODEV); +} +#endif /* CONFIG_EXTCON */ + +/* + * Following structure and API are deprecated. EXTCON remains the function + * definition to prevent the build break. + */ +struct extcon_specific_cable_nb { + struct notifier_block *user_nb; + int cable_index; + struct extcon_dev *edev; + unsigned long previous_value; +}; + static inline int extcon_register_interest(struct extcon_specific_cable_nb *obj, - const char *extcon_name, - const char *cable_name, - struct notifier_block *nb) + const char *extcon_name, const char *cable_name, + struct notifier_block *nb) { - return 0; + return -EINVAL; } static inline int extcon_unregister_interest(struct extcon_specific_cable_nb *obj) { - return 0; + return -EINVAL; } -static inline struct extcon_dev *extcon_get_edev_by_phandle(struct device *dev, - int index) +static inline int extcon_get_cable_state_(struct extcon_dev *edev, unsigned int id) { - return ERR_PTR(-ENODEV); + return extcon_get_state(edev, id); +} + +static inline int extcon_set_cable_state_(struct extcon_dev *edev, unsigned int id, + bool cable_state) +{ + return extcon_set_state_sync(edev, id, cable_state); } -#endif /* CONFIG_EXTCON */ #endif /* __LINUX_EXTCON_H__ */ diff --git a/include/linux/extcon/extcon-adc-jack.h b/include/linux/extcon/extcon-adc-jack.h index 53c60806bcfb..9666a8830758 100644 --- a/include/linux/extcon/extcon-adc-jack.h +++ b/include/linux/extcon/extcon-adc-jack.h @@ -20,8 +20,8 @@ /** * struct adc_jack_cond - condition to use an extcon state - * @state: the corresponding extcon state (if 0, this struct * denotes the last adc_jack_cond element among the array) + * @id: the unique id of each external connector * @min_adc: min adc value for this condition * @max_adc: max adc value for this condition * @@ -33,7 +33,7 @@ * because when no adc_jack_cond is met, state = 0 is automatically chosen. */ struct adc_jack_cond { - u32 state; /* extcon state value. 0 if invalid */ + unsigned int id; u32 min_adc; u32 max_adc; }; diff --git a/include/linux/fb.h b/include/linux/fb.h index 3d003805aac3..33564b062803 100644 --- a/include/linux/fb.h +++ b/include/linux/fb.h @@ -305,6 +305,9 @@ struct fb_ops { /* called at KDB enter and leave time to prepare the console */ int (*fb_debug_enter)(struct fb_info *info); int (*fb_debug_leave)(struct fb_info *info); + + /* Export the frame buffer as a dmabuf object */ + struct dma_buf *(*fb_dmabuf_export)(struct fb_info *info); }; #ifdef CONFIG_FB_TILEBLITTING diff --git a/include/linux/fwnode.h b/include/linux/fwnode.h index 851671742790..c3ea0a27d17c 100644 --- a/include/linux/fwnode.h +++ b/include/linux/fwnode.h @@ -12,6 +12,8 @@ #ifndef _LINUX_FWNODE_H_ #define _LINUX_FWNODE_H_ +#include <linux/types.h> + enum fwnode_type { FWNODE_INVALID = 0, FWNODE_OF, @@ -21,9 +23,111 @@ enum fwnode_type { FWNODE_IRQCHIP, }; +struct fwnode_operations; + struct fwnode_handle { enum fwnode_type type; struct fwnode_handle *secondary; + const struct fwnode_operations *ops; }; +/** + * struct fwnode_endpoint - Fwnode graph endpoint + * @port: Port number + * @id: Endpoint id + * @local_fwnode: reference to the related fwnode + */ +struct fwnode_endpoint { + unsigned int port; + unsigned int id; + const struct fwnode_handle *local_fwnode; +}; + +#define NR_OF_FWNODE_REFERENCE_ARGS 8 + +/** + * struct fwnode_reference_args - Fwnode reference with additional arguments + * @fwnode:- A reference to the base fwnode + * @nargs: Number of elements in @args array + * @args: Integer arguments on the fwnode + */ +struct fwnode_reference_args { + struct fwnode_handle *fwnode; + unsigned int nargs; + unsigned int args[NR_OF_FWNODE_REFERENCE_ARGS]; +}; + +/** + * struct fwnode_operations - Operations for fwnode interface + * @get: Get a reference to an fwnode. + * @put: Put a reference to an fwnode. + * @property_present: Return true if a property is present. + * @property_read_integer_array: Read an array of integer properties. Return + * zero on success, a negative error code + * otherwise. + * @property_read_string_array: Read an array of string properties. Return zero + * on success, a negative error code otherwise. + * @get_parent: Return the parent of an fwnode. + * @get_next_child_node: Return the next child node in an iteration. + * @get_named_child_node: Return a child node with a given name. + * @get_reference_args: Return a reference pointed to by a property, with args + * @graph_get_next_endpoint: Return an endpoint node in an iteration. + * @graph_get_remote_endpoint: Return the remote endpoint node of a local + * endpoint node. + * @graph_get_port_parent: Return the parent node of a port node. + * @graph_parse_endpoint: Parse endpoint for port and endpoint id. + */ +struct fwnode_operations { + void (*get)(struct fwnode_handle *fwnode); + void (*put)(struct fwnode_handle *fwnode); + bool (*device_is_available)(struct fwnode_handle *fwnode); + bool (*property_present)(struct fwnode_handle *fwnode, + const char *propname); + int (*property_read_int_array)(struct fwnode_handle *fwnode, + const char *propname, + unsigned int elem_size, void *val, + size_t nval); + int (*property_read_string_array)(struct fwnode_handle *fwnode_handle, + const char *propname, + const char **val, size_t nval); + struct fwnode_handle *(*get_parent)(struct fwnode_handle *fwnode); + struct fwnode_handle * + (*get_next_child_node)(struct fwnode_handle *fwnode, + struct fwnode_handle *child); + struct fwnode_handle * + (*get_named_child_node)(struct fwnode_handle *fwnode, const char *name); + int (*get_reference_args)(struct fwnode_handle *fwnode, + const char *prop, const char *nargs_prop, + unsigned int nargs, unsigned int index, + struct fwnode_reference_args *args); + struct fwnode_handle * + (*graph_get_next_endpoint)(struct fwnode_handle *fwnode, + struct fwnode_handle *prev); + struct fwnode_handle * + (*graph_get_remote_endpoint)(struct fwnode_handle *fwnode); + struct fwnode_handle * + (*graph_get_port_parent)(struct fwnode_handle *fwnode); + int (*graph_parse_endpoint)(struct fwnode_handle *fwnode, + struct fwnode_endpoint *endpoint); +}; + +#define fwnode_has_op(fwnode, op) \ + ((fwnode) && (fwnode)->ops && (fwnode)->ops->op) +#define fwnode_call_int_op(fwnode, op, ...) \ + (fwnode ? (fwnode_has_op(fwnode, op) ? \ + (fwnode)->ops->op(fwnode, ## __VA_ARGS__) : -ENXIO) : \ + -EINVAL) +#define fwnode_call_bool_op(fwnode, op, ...) \ + (fwnode ? (fwnode_has_op(fwnode, op) ? \ + (fwnode)->ops->op(fwnode, ## __VA_ARGS__) : false) : \ + false) +#define fwnode_call_ptr_op(fwnode, op, ...) \ + (fwnode_has_op(fwnode, op) ? \ + (fwnode)->ops->op(fwnode, ## __VA_ARGS__) : NULL) +#define fwnode_call_void_op(fwnode, op, ...) \ + do { \ + if (fwnode_has_op(fwnode, op)) \ + (fwnode)->ops->op(fwnode, ## __VA_ARGS__); \ + } while (false) + #endif diff --git a/include/linux/genhd.h b/include/linux/genhd.h index 5012fcdb4c9e..f69821f597a0 100644 --- a/include/linux/genhd.h +++ b/include/linux/genhd.h @@ -202,6 +202,8 @@ struct gendisk { struct request_queue *queue; void *private_data; + /* Flag of rockchip specific disk: eMMC/eSD, NVMe, etc. */ + bool is_rk_disk; int flags; struct device *driverfs_dev; // FIXME: remove struct kobject *slave_dir; diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h index d1baebf350d8..c4c33b3fffcd 100644 --- a/include/linux/gpio/driver.h +++ b/include/linux/gpio/driver.h @@ -20,9 +20,10 @@ struct seq_file; /** * struct gpio_chip - abstract a GPIO controller * @label: for diagnostics - * @dev: optional device providing the GPIOs + * @parent: optional parent device providing the GPIOs * @cdev: class device used by sysfs interface (may be NULL) * @owner: helps prevent removal of modules exporting active GPIOs + * @data: per-instance data assigned by the driver * @list: links gpio_chips together for traversal * @request: optional hook for chip-specific activation, such as * enabling module power and clock; may sleep @@ -89,9 +90,10 @@ struct seq_file; */ struct gpio_chip { const char *label; - struct device *dev; + struct device *parent; struct device *cdev; struct module *owner; + void *data; struct list_head list; int (*request)(struct gpio_chip *chip, @@ -166,8 +168,16 @@ extern const char *gpiochip_is_requested(struct gpio_chip *chip, unsigned offset); /* add/remove chips */ -extern int gpiochip_add(struct gpio_chip *chip); +extern int gpiochip_add_data(struct gpio_chip *chip, void *data); +static inline int gpiochip_add(struct gpio_chip *chip) +{ + return gpiochip_add_data(chip, NULL); +} extern void gpiochip_remove(struct gpio_chip *chip); +extern int devm_gpiochip_add_data(struct device *dev, struct gpio_chip *chip, + void *data); +extern void devm_gpiochip_remove(struct device *dev, struct gpio_chip *chip); + extern struct gpio_chip *gpiochip_find(void *data, int (*match)(struct gpio_chip *chip, void *data)); @@ -175,6 +185,12 @@ extern struct gpio_chip *gpiochip_find(void *data, int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset); void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset); +/* get driver data */ +static inline void *gpiochip_get_data(struct gpio_chip *chip) +{ + return chip->data; +} + struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc); #ifdef CONFIG_GPIOLIB_IRQCHIP diff --git a/include/linux/gpio_detection.h b/include/linux/gpio_detection.h new file mode 100644 index 000000000000..57b2ff92bc50 --- /dev/null +++ b/include/linux/gpio_detection.h @@ -0,0 +1,51 @@ +/* + * include/linux/gpio_detection.h + * + * Platform data structure for GPIO detection driver + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#ifndef __GPIO_DETECTION_H +#define __GPIO_DETECTION_H + +#define GPIO_EVENT 1 + +/* + * gpio event + * @val: 0 event active, 1 event over + * @name: event name + */ + +struct gpio_event { + int val; + const char *name; +}; + +#if IS_ENABLED(CONFIG_GPIO_DET) + +int gpio_det_register_notifier(struct notifier_block *nb); +int gpio_det_unregister_notifier(struct notifier_block *nb); +int gpio_det_notifier_call_chain(unsigned long val, void *v); + +#else + +static inline int gpio_det_register_notifier(struct notifier_block *nb) +{ + return -EINVAL; +}; + +static inline int gpio_det_unregister_notifier(struct notifier_block *nb) +{ + return -EINVAL; +}; + +static inline int gpio_det_notifier_call_chain(unsigned long val, void *v) +{ + return -EINVAL; +}; + +#endif + +#endif diff --git a/include/linux/hdmi-notifier.h b/include/linux/hdmi-notifier.h new file mode 100644 index 000000000000..b75b0da280c9 --- /dev/null +++ b/include/linux/hdmi-notifier.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef LINUX_HDMI_NOTIFIER_H +#define LINUX_HDMI_NOTIFIER_H + +#include <linux/types.h> + +enum { + HDMI_CONNECTED, + HDMI_DISCONNECTED, + HDMI_NEW_EDID, + HDMI_NEW_ELD, +}; + +struct hdmi_event_base { + struct device *source; +}; + +struct hdmi_event_new_edid { + struct hdmi_event_base base; + const void *edid; + size_t size; +}; + +struct hdmi_event_new_eld { + struct hdmi_event_base base; + unsigned char eld[128]; +}; + +union hdmi_event { + struct hdmi_event_base base; + struct hdmi_event_new_edid edid; + struct hdmi_event_new_eld eld; +}; + +struct notifier_block; + +int hdmi_register_notifier(struct notifier_block *nb); +int hdmi_unregister_notifier(struct notifier_block *nb); + +void hdmi_event_connect(struct device *dev); +void hdmi_event_disconnect(struct device *dev); +void hdmi_event_new_edid(struct device *dev, const void *edid, size_t size); +void hdmi_event_new_eld(struct device *dev, const void *eld); + +#endif diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h index e9744202fa29..a8095e1d62b5 100644 --- a/include/linux/hdmi.h +++ b/include/linux/hdmi.h @@ -32,9 +32,11 @@ enum hdmi_infoframe_type { HDMI_INFOFRAME_TYPE_AVI = 0x82, HDMI_INFOFRAME_TYPE_SPD = 0x83, HDMI_INFOFRAME_TYPE_AUDIO = 0x84, + HDMI_INFOFRAME_TYPE_DRM = 0x87, }; #define HDMI_IEEE_OUI 0x000c03 +#define HDMI_FORUM_IEEE_OUI 0xc45dd8 #define HDMI_INFOFRAME_HEADER_SIZE 4 #define HDMI_AVI_INFOFRAME_SIZE 13 #define HDMI_SPD_INFOFRAME_SIZE 25 @@ -78,6 +80,8 @@ enum hdmi_picture_aspect { HDMI_PICTURE_ASPECT_NONE, HDMI_PICTURE_ASPECT_4_3, HDMI_PICTURE_ASPECT_16_9, + HDMI_PICTURE_ASPECT_64_27, + HDMI_PICTURE_ASPECT_256_135, HDMI_PICTURE_ASPECT_RESERVED, }; @@ -157,10 +161,29 @@ struct hdmi_avi_infoframe { unsigned short right_bar; }; +struct hdmi_drm_infoframe { + enum hdmi_infoframe_type type; + unsigned char version; + unsigned char length; + uint16_t eotf; + uint16_t metadata_type; + uint16_t display_primaries_x[3]; + uint16_t display_primaries_y[3]; + uint16_t white_point_x; + uint16_t white_point_y; + uint16_t max_mastering_display_luminance; + uint16_t min_mastering_display_luminance; + uint16_t max_fall; + uint16_t max_cll; + uint16_t min_cll; +}; + int hdmi_avi_infoframe_init(struct hdmi_avi_infoframe *frame); ssize_t hdmi_avi_infoframe_pack(struct hdmi_avi_infoframe *frame, void *buffer, size_t size); +int hdmi_drm_infoframe_init(struct hdmi_drm_infoframe *frame); + enum hdmi_spd_sdi { HDMI_SPD_SDI_UNKNOWN, HDMI_SPD_SDI_DSTB, @@ -325,6 +348,7 @@ union hdmi_infoframe { struct hdmi_spd_infoframe spd; union hdmi_vendor_any_infoframe vendor; struct hdmi_audio_infoframe audio; + struct hdmi_drm_infoframe drm; }; ssize_t diff --git a/include/linux/i2c.h b/include/linux/i2c.h index 768063baafbf..7c45181f41ab 100644 --- a/include/linux/i2c.h +++ b/include/linux/i2c.h @@ -414,6 +414,22 @@ struct i2c_algorithm { }; /** + * struct i2c_timings - I2C timing information + * @bus_freq_hz: the bus frequency in Hz + * @scl_rise_ns: time SCL signal takes to rise in ns; t(r) in the I2C specification + * @scl_fall_ns: time SCL signal takes to fall in ns; t(f) in the I2C specification + * @scl_int_delay_ns: time IP core additionally needs to setup SCL in ns + * @sda_fall_ns: time SDA signal takes to fall in ns; t(f) in the I2C specification + */ +struct i2c_timings { + u32 bus_freq_hz; + u32 scl_rise_ns; + u32 scl_fall_ns; + u32 scl_int_delay_ns; + u32 sda_fall_ns; +}; + +/** * struct i2c_bus_recovery_info - I2C bus recovery information * @recover_bus: Recover routine. Either pass driver's recover_bus() routine, or * i2c_generic_scl_recovery() or i2c_generic_gpio_recovery(). @@ -602,6 +618,7 @@ extern void i2c_clients_command(struct i2c_adapter *adap, extern struct i2c_adapter *i2c_get_adapter(int nr); extern void i2c_put_adapter(struct i2c_adapter *adap); +void i2c_parse_fw_timings(struct device *dev, struct i2c_timings *t, bool use_defaults); /* Return the functionality mask */ static inline u32 i2c_get_functionality(struct i2c_adapter *adap) @@ -644,6 +661,7 @@ extern struct i2c_adapter *of_find_i2c_adapter_by_node(struct device_node *node) /* must call i2c_put_adapter() when done with returned i2c_adapter device */ struct i2c_adapter *of_get_i2c_adapter_by_node(struct device_node *node); + #else static inline struct i2c_client *of_find_i2c_device_by_node(struct device_node *node) diff --git a/include/linux/iio/consumer.h b/include/linux/iio/consumer.h index fad58671c49e..e1e033d6a81f 100644 --- a/include/linux/iio/consumer.h +++ b/include/linux/iio/consumer.h @@ -49,6 +49,33 @@ struct iio_channel *iio_channel_get(struct device *dev, void iio_channel_release(struct iio_channel *chan); /** + * devm_iio_channel_get() - Resource managed version of iio_channel_get(). + * @dev: Pointer to consumer device. Device name must match + * the name of the device as provided in the iio_map + * with which the desired provider to consumer mapping + * was registered. + * @consumer_channel: Unique name to identify the channel on the consumer + * side. This typically describes the channels use within + * the consumer. E.g. 'battery_voltage' + * + * Returns a pointer to negative errno if it is not able to get the iio channel + * otherwise returns valid pointer for iio channel. + * + * The allocated iio channel is automatically released when the device is + * unbound. + */ +struct iio_channel *devm_iio_channel_get(struct device *dev, + const char *consumer_channel); +/** + * devm_iio_channel_release() - Resource managed version of + * iio_channel_release(). + * @dev: Pointer to consumer device for which resource + * is allocared. + * @chan: The channel to be released. + */ +void devm_iio_channel_release(struct device *dev, struct iio_channel *chan); + +/** * iio_channel_get_all() - get all channels associated with a client * @dev: Pointer to consumer device. * diff --git a/include/linux/irq.h b/include/linux/irq.h index f7cade00c525..589d7dc65b9c 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -206,6 +206,7 @@ enum { IRQD_IRQ_INPROGRESS = (1 << 18), IRQD_WAKEUP_ARMED = (1 << 19), IRQD_FORWARDED_TO_VCPU = (1 << 20), + IRQD_IRQ_STARTED = (1 << 22), }; #define __irqd_to_state(d) ((d)->common->state_use_accessors) @@ -299,6 +300,11 @@ static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d) __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU; } +static inline bool irqd_is_started(struct irq_data *d) +{ + return __irqd_to_state(d) & IRQD_IRQ_STARTED; +} + static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) { return d->hwirq; @@ -517,6 +523,10 @@ static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *c } extern int irq_set_percpu_devid(unsigned int irq); +extern int irq_set_percpu_devid_partition(unsigned int irq, + const struct cpumask *affinity); +extern int irq_get_percpu_devid_partition(unsigned int irq, + struct cpumask *affinity); extern void __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, diff --git a/include/linux/irqchip/irq-partition-percpu.h b/include/linux/irqchip/irq-partition-percpu.h new file mode 100644 index 000000000000..87433a5d1285 --- /dev/null +++ b/include/linux/irqchip/irq-partition-percpu.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2016 ARM Limited, All Rights Reserved. + * Author: Marc Zyngier <marc.zyngier@arm.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/fwnode.h> +#include <linux/cpumask.h> +#include <linux/irqdomain.h> + +struct partition_affinity { + cpumask_t mask; + void *partition_id; +}; + +struct partition_desc; + +#ifdef CONFIG_PARTITION_PERCPU +int partition_translate_id(struct partition_desc *desc, void *partition_id); +struct partition_desc *partition_create_desc(struct fwnode_handle *fwnode, + struct partition_affinity *parts, + int nr_parts, + int chained_irq, + const struct irq_domain_ops *ops); +struct irq_domain *partition_get_domain(struct partition_desc *dsc); +#else +static inline int partition_translate_id(struct partition_desc *desc, + void *partition_id) +{ + return -EINVAL; +} + +static inline +struct partition_desc *partition_create_desc(struct fwnode_handle *fwnode, + struct partition_affinity *parts, + int nr_parts, + int chained_irq, + const struct irq_domain_ops *ops) +{ + return NULL; +} + +static inline +struct irq_domain *partition_get_domain(struct partition_desc *dsc) +{ + return NULL; +} +#endif diff --git a/include/linux/irqdesc.h b/include/linux/irqdesc.h index a587a33363c7..914cf10e0c40 100644 --- a/include/linux/irqdesc.h +++ b/include/linux/irqdesc.h @@ -63,6 +63,7 @@ struct irq_desc { int threads_handled_last; raw_spinlock_t lock; struct cpumask *percpu_enabled; + const struct cpumask *percpu_affinity; #ifdef CONFIG_SMP const struct cpumask *affinity_hint; struct irq_affinity_notify *affinity_notify; diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h index d5e5c5bef28c..8f031ce06a76 100644 --- a/include/linux/irqdomain.h +++ b/include/linux/irqdomain.h @@ -70,6 +70,7 @@ struct irq_fwspec { */ enum irq_domain_bus_token { DOMAIN_BUS_ANY = 0, + DOMAIN_BUS_WIRED, DOMAIN_BUS_PCI_MSI, DOMAIN_BUS_PLATFORM_MSI, DOMAIN_BUS_NEXUS, @@ -93,6 +94,8 @@ enum irq_domain_bus_token { struct irq_domain_ops { int (*match)(struct irq_domain *d, struct device_node *node, enum irq_domain_bus_token bus_token); + int (*select)(struct irq_domain *d, struct irq_fwspec *fwspec, + enum irq_domain_bus_token bus_token); int (*map)(struct irq_domain *d, unsigned int virq, irq_hw_number_t hw); void (*unmap)(struct irq_domain *d, unsigned int virq); int (*xlate)(struct irq_domain *d, struct device_node *node, @@ -202,7 +205,7 @@ struct irq_domain *irq_domain_add_legacy(struct device_node *of_node, irq_hw_number_t first_hwirq, const struct irq_domain_ops *ops, void *host_data); -extern struct irq_domain *irq_find_matching_fwnode(struct fwnode_handle *fwnode, +extern struct irq_domain *irq_find_matching_fwspec(struct irq_fwspec *fwspec, enum irq_domain_bus_token bus_token); extern void irq_set_default_host(struct irq_domain *host); @@ -211,6 +214,22 @@ static inline struct fwnode_handle *of_node_to_fwnode(struct device_node *node) return node ? &node->fwnode : NULL; } +static inline bool is_fwnode_irqchip(struct fwnode_handle *fwnode) +{ + return fwnode && fwnode->type == FWNODE_IRQCHIP; +} + +static inline +struct irq_domain *irq_find_matching_fwnode(struct fwnode_handle *fwnode, + enum irq_domain_bus_token bus_token) +{ + struct irq_fwspec fwspec = { + .fwnode = fwnode, + }; + + return irq_find_matching_fwspec(&fwspec, bus_token); +} + static inline struct irq_domain *irq_find_matching_host(struct device_node *node, enum irq_domain_bus_token bus_token) { diff --git a/include/linux/l3g4200d.h b/include/linux/l3g4200d.h new file mode 100644 index 000000000000..fa82a58f44c6 --- /dev/null +++ b/include/linux/l3g4200d.h @@ -0,0 +1,145 @@ +/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +* +* File Name : l3g4200d.c +* Authors : MH - C&I BU - Application Team +* : Carmine Iascone (carmine.iascone@st.com) +* : Matteo Dameno (matteo.dameno@st.com) +* Version : V 0.2 +* Date : 09/04/2010 +* Description : L3G4200D digital output gyroscope sensor API +* +******************************************************************************** +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* THE PRESENT SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES +* OR CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED, FOR THE SOLE +* PURPOSE TO SUPPORT YOUR APPLICATION DEVELOPMENT. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +* THIS SOFTWARE IS SPECIFICALLY DESIGNED FOR EXCLUSIVE USE WITH ST PARTS. +* +******************************************************************************** +* REVISON HISTORY +* +* VERSION | DATE | AUTHORS | DESCRIPTION +* +* 0.1 | 29/01/2010 | Carmine Iascone | First Release +* +* 0.2 | 09/04/2010 | Carmine Iascone | Updated the struct l3g4200d_t +* +*******************************************************************************/ + +#ifndef __L3G4200D_H__ +#define __L3G4200D_H__ + +#include <linux/ioctl.h> /* For IOCTL macros */ + +/** This define controls compilation of the master device interface */ +/*#define L3G4200D_MASTER_DEVICE*/ + +#define L3G4200D_IOCTL_BASE 77 + +#define L3G4200D_IOCTL_SET_DELAY _IOW(L3G4200D_IOCTL_BASE, 0, int) +#define L3G4200D_IOCTL_GET_DELAY _IOR(L3G4200D_IOCTL_BASE, 1, int) +#define L3G4200D_IOCTL_SET_ENABLE _IOW(L3G4200D_IOCTL_BASE, 2, int) +#define L3G4200D_IOCTL_GET_ENABLE _IOR(L3G4200D_IOCTL_BASE, 3, int) +#define L3G4200D_IOCTL_GET_CALIBRATION _IOR(L3G4200D_IOCTL_BASE, 4, int[3]) + +#define L3G4200D_FS_250DPS 0x00 +#define L3G4200D_FS_500DPS 0x10 +#define L3G4200D_FS_2000DPS 0x30 + +#define PM_OFF 0x00 +#define PM_NORMAL 0x08 +#define ENABLE_ALL_AXES 0x07 + +/* l3g4200d gyroscope registers */ +#define GYRO_WHO_AM_I 0x0F +#define GYRO_CTRL_REG1 0x20 /* power control reg */ +#define GYRO_CTRL_REG2 0x21 /* power control reg */ +#define GYRO_CTRL_REG3 0x22 /* power control reg */ +#define GYRO_CTRL_REG4 0x23 /* interrupt control reg */ +#define GYRO_CTRL_REG5 0x24 /* interrupt control reg */ +#define GYRO_DATA_REG 0x28 +#define GYRO_INT_SRC 0x31 + + + + +/*status*/ +#define L3G4200D_SUSPEND 2 +#define L3G4200D_OPEN 1 +#define L3G4200D_CLOSE 0 + +#define ODR100_BW12_5 0x00 /* ODR = 100Hz; BW = 12.5Hz */ +#define ODR100_BW25 0x10 /* ODR = 100Hz; BW = 25Hz */ +#define ODR200_BW12_5 0x40 /* ODR = 200Hz; BW = 12.5Hz */ +#define ODR200_BW25 0x50 /* ODR = 200Hz; BW = 25Hz */ +#define ODR200_BW50 0x60 /* ODR = 200Hz; BW = 50Hz */ +#define ODR400_BW25 0x90 /* ODR = 400Hz; BW = 25Hz */ +#define ODR400_BW50 0xA0 /* ODR = 400Hz; BW = 50Hz */ +#define ODR400_BW110 0xB0 /* ODR = 400Hz; BW = 110Hz */ +#define ODR800_BW50 0xE0 /* ODR = 800Hz; BW = 50Hz */ +#define ODR800_BW100 0xF0 /* ODR = 800Hz; BW = 100Hz */ + +#define L3G4200D_REG_WHO_AM_I 0x0f +#define L3G4200D_REG_CTRL_REG1 0x20 +#define ACTIVE_MASK 0x08 + +#define GYRO_DEVID_L3G4200D 0xD3 +#define GYRO_DEVID_L3G20D 0xD4 + + +#ifdef __KERNEL__ +struct l3g4200d_platform_data { + u8 fs_range; + + u8 axis_map_x; + u8 axis_map_y; + u8 axis_map_z; + + u8 negate_x; + u8 negate_y; + u8 negate_z; + signed char orientation[9]; + int x_min; + int y_min; + int z_min; + int (*init)(void); + void (*exit)(void); + int (*power_on)(void); + int (*power_off)(void); + +}; + +#endif /* __KERNEL__ */ + +struct l3g4200d_axis { + int x; + int y; + int z; +}; + + +struct l3g4200d_data { + char status; + char curr_tate; + unsigned int devid; + struct input_dev *input_dev; + struct i2c_client *client; + struct work_struct work; + struct delayed_work delaywork; /*report second event*/ + struct l3g4200d_platform_data *pdata; + struct l3g4200d_axis axis; +}; + +#define GSENSOR_DEV_PATH "/dev/gyrosensors" + + +#endif /* __L3G4200D_H__ */ diff --git a/include/linux/leds-pca9532.h b/include/linux/leds-pca9532.h index b8d6fffed4d8..d215b4561180 100644 --- a/include/linux/leds-pca9532.h +++ b/include/linux/leds-pca9532.h @@ -16,6 +16,7 @@ #include <linux/leds.h> #include <linux/workqueue.h> +#include <dt-bindings/leds/leds-pca9532.h> enum pca9532_state { PCA9532_OFF = 0x0, @@ -24,16 +25,14 @@ enum pca9532_state { PCA9532_PWM1 = 0x3 }; -enum pca9532_type { PCA9532_TYPE_NONE, PCA9532_TYPE_LED, - PCA9532_TYPE_N2100_BEEP, PCA9532_TYPE_GPIO }; - struct pca9532_led { u8 id; struct i2c_client *client; - char *name; + const char *name; + const char *default_trigger; struct led_classdev ldev; struct work_struct work; - enum pca9532_type type; + u32 type; enum pca9532_state state; }; diff --git a/include/linux/mc3230.h b/include/linux/mc3230.h new file mode 100755 index 000000000000..7d71f6665bba --- /dev/null +++ b/include/linux/mc3230.h @@ -0,0 +1,226 @@ +/* + * MCube mc3230 acceleration sensor driver + * + * Copyright (C) 2011 MCube Inc., + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * *****************************************************************************/ + +#ifndef MC3230_H +#define MC3230_H + +#include <linux/ioctl.h> + +#define MC3230_REG_CHIP_ID 0x18 +#define MC3230_REG_X_OUT 0x0 //RO +#define MC3230_REG_Y_OUT 0x1 //RO +#define MC3230_REG_Z_OUT 0x2 //RO +#define MC3230_REG_STAT 0x04 +#define MC3230_REG_SLEEP_COUNTER 0x05 +#define MC3230_REG_INTMOD 0x06 +#define MC3230_REG_SYSMOD 0x07 +#define MC3230_REG_RATE_SAMP 0x08 + +#define MC32X0_XOUT_EX_L_REG 0x0d + +#define MC3230_REG_RBM_DATA 0x0D +#define MC3230_REG_PRODUCT_CODE 0x3b + + + + + +#define MCIO 0xA1 + +#define RBUFF_SIZE 12 /* Rx buffer size */ +/* IOCTLs for MC3230 library */ +#define MC_IOCTL_INIT _IO(MCIO, 0x01) +#define MC_IOCTL_RESET _IO(MCIO, 0x04) +#define MC_IOCTL_CLOSE _IO(MCIO, 0x02) +#define MC_IOCTL_START _IO(MCIO, 0x03) +#define MC_IOCTL_GETDATA _IOR(MCIO, 0x08, char[RBUFF_SIZE+1]) + +/* IOCTLs for APPs */ +#define MC_IOCTL_APP_SET_RATE _IOW(MCIO, 0x10, char) + +#if 0 +/*wake mode rate Samples/Second (0~2)*/ +#define MC3230_RATE_128 0 +#define MC3230_RATE_64 1 +#define MC3230_RATE_32 2 +#define MC3230_RATE_16 3 +#define MC3230_RATE_8 4 +#define MC3230_RATE_4 5 +#define MC3230_RATE_2 6 +#define MC3230_RATE_1 7 +#endif + +/*sniffr mode rate Samples/Second (3~4)*/ +#define MC3230_SNIFFR_RATE_32 0 +#define MC3230_SNIFFR_RATE_16 1 +#define MC3230_SNIFFR_RATE_8 2 +#define MC3230_SNIFFR_RATE_1 3 +#define MC3230_SNIFFR_RATE_SHIFT 3 + +//#define ACTIVE_MASK 1 +//#define FREAD_MASK 2 + + +/*status*/ +#define MC3230_OPEN 1 +#define MC3230_CLOSE 0 + +#define MC3230_RANGE 1500000 +#define MC3230_IIC_ADDR 0x4c +#define MC3230_PRECISION 8 //8bit data +#define MC3230_BOUNDARY (0x1 << (MC3230_PRECISION - 1)) +#define MC3230_GRAVITY_STEP MC3230_RANGE/MC3230_BOUNDARY //110 //2g full scale range + + +struct mc3230_axis { + int x; + int y; + int z; +}; + +//#define GSENSOR_DEV_PATH "/dev/mma8452_daemon" + + + +//add accel calibrate IO +typedef struct { + unsigned short x; /**< X axis */ + unsigned short y; /**< Y axis */ + unsigned short z; /**< Z axis */ +} GSENSOR_VECTOR3D; + +typedef struct{ + int x; + int y; + int z; +}SENSOR_DATA; +//=========================================add by guanj============================ +struct mc3230_platform_data { + u16 model; + u16 swap_xy; + u16 swap_xyz; + signed char orientation[9]; + int (*get_pendown_state)(void); + int (*init_platform_hw)(void); + int (*mc3230_platform_sleep)(void); + int (*mc3230_platform_wakeup)(void); + void (*exit_platform_hw)(void); +}; + +#define GSENSOR 0x85 +//#define GSENSOR_IOCTL_INIT _IO(GSENSOR, 0x01) +#define GSENSOR_IOCTL_READ_CHIPINFO _IOR(GSENSOR, 0x02, int) +#define GSENSOR_IOCTL_READ_SENSORDATA _IOR(GSENSOR, 0x03, int) +#define GSENSOR_IOCTL_READ_OFFSET _IOR(GSENSOR, 0x04, GSENSOR_VECTOR3D) +#define GSENSOR_IOCTL_READ_GAIN _IOR(GSENSOR, 0x05, GSENSOR_VECTOR3D) +#define GSENSOR_IOCTL_READ_RAW_DATA _IOR(GSENSOR, 0x06, int) +#define GSENSOR_IOCTL_SET_CALI _IOW(GSENSOR, 0x06, SENSOR_DATA) +#define GSENSOR_IOCTL_GET_CALI _IOW(GSENSOR, 0x07, SENSOR_DATA) +#define GSENSOR_IOCTL_CLR_CALI _IO(GSENSOR, 0x08) +#define GSENSOR_MCUBE_IOCTL_READ_RBM_DATA _IOR(GSENSOR, 0x09, SENSOR_DATA) +#define GSENSOR_MCUBE_IOCTL_SET_RBM_MODE _IO(GSENSOR, 0x0a) +#define GSENSOR_MCUBE_IOCTL_CLEAR_RBM_MODE _IO(GSENSOR, 0x0b) +#define GSENSOR_MCUBE_IOCTL_SET_CALI _IOW(GSENSOR, 0x0c, SENSOR_DATA) +#define GSENSOR_MCUBE_IOCTL_REGISTER_MAP _IO(GSENSOR, 0x0d) +#define GSENSOR_IOCTL_SET_CALI_MODE _IOW(GSENSOR, 0x0e,int) + + + + +/* IOCTLs for Msensor misc. device library */ +#define MSENSOR 0x83 +#define MSENSOR_IOCTL_INIT _IO(MSENSOR, 0x01) +#define MSENSOR_IOCTL_READ_CHIPINFO _IOR(MSENSOR, 0x02, int) +#define MSENSOR_IOCTL_READ_SENSORDATA _IOR(MSENSOR, 0x03, int) +#define MSENSOR_IOCTL_READ_POSTUREDATA _IOR(MSENSOR, 0x04, int) +#define MSENSOR_IOCTL_READ_CALIDATA _IOR(MSENSOR, 0x05, int) +#define MSENSOR_IOCTL_READ_CONTROL _IOR(MSENSOR, 0x06, int) +#define MSENSOR_IOCTL_SET_CONTROL _IOW(MSENSOR, 0x07, int) +#define MSENSOR_IOCTL_SET_MODE _IOW(MSENSOR, 0x08, int) +#define MSENSOR_IOCTL_SET_POSTURE _IOW(MSENSOR, 0x09, int) +#define MSENSOR_IOCTL_SET_CALIDATA _IOW(MSENSOR, 0x0a, int) +#define MSENSOR_IOCTL_SENSOR_ENABLE _IOW(MSENSOR, 0x51, int) +#define MSENSOR_IOCTL_READ_FACTORY_SENSORDATA _IOW(MSENSOR, 0x52, int) + + +#if 0 +/* IOCTLs for AKM library */ +#define ECS_IOCTL_WRITE _IOW(MSENSOR, 0x0b, char*) +#define ECS_IOCTL_READ _IOWR(MSENSOR, 0x0c, char*) +#define ECS_IOCTL_RESET _IO(MSENSOR, 0x0d) /* NOT used in AK8975 */ +#define ECS_IOCTL_SET_MODE _IOW(MSENSOR, 0x0e, short) +#define ECS_IOCTL_GETDATA _IOR(MSENSOR, 0x0f, char[SENSOR_DATA_SIZE]) +#define ECS_IOCTL_SET_YPR _IOW(MSENSOR, 0x10, short[12]) +#define ECS_IOCTL_GET_OPEN_STATUS _IOR(MSENSOR, 0x11, int) +#define ECS_IOCTL_GET_CLOSE_STATUS _IOR(MSENSOR, 0x12, int) +#define ECS_IOCTL_GET_OSENSOR_STATUS _IOR(MSENSOR, 0x13, int) +#define ECS_IOCTL_GET_DELAY _IOR(MSENSOR, 0x14, short) +#define ECS_IOCTL_GET_PROJECT_NAME _IOR(MSENSOR, 0x15, char[64]) +#define ECS_IOCTL_GET_MATRIX _IOR(MSENSOR, 0x16, short [4][3][3]) +#define ECS_IOCTL_GET_LAYOUT _IOR(MSENSOR, 0x17, int[3]) +#endif +#define ECS_IOCTL_GET_OUTBIT _IOR(MSENSOR, 0x23, char) +#define ECS_IOCTL_GET_ACCEL _IOR(MSENSOR, 0x24, short[3]) +#define MMC31XX_IOC_RM _IO(MSENSOR, 0x25) +#define MMC31XX_IOC_RRM _IO(MSENSOR, 0x26) + + + +/* IOCTLs for MMC31XX device */ +#define MMC31XX_IOC_TM _IO(MSENSOR, 0x18) +#define MMC31XX_IOC_SET _IO(MSENSOR, 0x19) +#define MMC31XX_IOC_RESET _IO(MSENSOR, 0x1a) +#define MMC31XX_IOC_READ _IOR(MSENSOR, 0x1b, int[3]) +#define MMC31XX_IOC_READXYZ _IOR(MSENSOR, 0x1c, int[3]) + +#define ECOMPASS_IOC_GET_DELAY _IOR(MSENSOR, 0x1d, int) +#define ECOMPASS_IOC_GET_MFLAG _IOR(MSENSOR, 0x1e, short) +#define ECOMPASS_IOC_GET_OFLAG _IOR(MSENSOR, 0x1f, short) +#define ECOMPASS_IOC_GET_OPEN_STATUS _IOR(MSENSOR, 0x20, int) +#define ECOMPASS_IOC_SET_YPR _IOW(MSENSOR, 0x21, int[12]) +#define ECOMPASS_IOC_GET_LAYOUT _IOR(MSENSOR, 0X22, int) + + + + +#define ALSPS 0X84 +#define ALSPS_SET_PS_MODE _IOW(ALSPS, 0x01, int) +#define ALSPS_GET_PS_MODE _IOR(ALSPS, 0x02, int) +#define ALSPS_GET_PS_DATA _IOR(ALSPS, 0x03, int) +#define ALSPS_GET_PS_RAW_DATA _IOR(ALSPS, 0x04, int) +#define ALSPS_SET_ALS_MODE _IOW(ALSPS, 0x05, int) +#define ALSPS_GET_ALS_MODE _IOR(ALSPS, 0x06, int) +#define ALSPS_GET_ALS_DATA _IOR(ALSPS, 0x07, int) +#define ALSPS_GET_ALS_RAW_DATA _IOR(ALSPS, 0x08, int) + +#define GYROSCOPE 0X86 +#define GYROSCOPE_IOCTL_INIT _IO(GYROSCOPE, 0x01) +#define GYROSCOPE_IOCTL_SMT_DATA _IOR(GYROSCOPE, 0x02, int) +#define GYROSCOPE_IOCTL_READ_SENSORDATA _IOR(GYROSCOPE, 0x03, int) +#define GYROSCOPE_IOCTL_SET_CALI _IOW(GYROSCOPE, 0x04, SENSOR_DATA) +#define GYROSCOPE_IOCTL_GET_CALI _IOW(GYROSCOPE, 0x05, SENSOR_DATA) +#define GYROSCOPE_IOCTL_CLR_CALI _IO(GYROSCOPE, 0x06) + +#define BROMETER 0X87 +#define BAROMETER_IOCTL_INIT _IO(BROMETER, 0x01) +#define BAROMETER_GET_PRESS_DATA _IOR(BROMETER, 0x02, int) +#define BAROMETER_GET_TEMP_DATA _IOR(BROMETER, 0x03, int) +#define BAROMETER_IOCTL_READ_CHIPINFO _IOR(BROMETER, 0x04, int) + +extern long mc3230_ioctl( struct file *file, unsigned int cmd,unsigned long arg,struct i2c_client *client); +#endif + diff --git a/include/linux/mfd/rk610_core.h b/include/linux/mfd/rk610_core.h new file mode 100644 index 000000000000..19f341107db7 --- /dev/null +++ b/include/linux/mfd/rk610_core.h @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __RK610_CONTROL_H_ +#define __RK610_CONTROL_H_ + +#define INVALID_GPIO -1 +//#define RK610_DEBUG + +#ifdef RK610_DEBUG +#define RK610_DBG(dev, format, arg...) \ +do{\ + dev_printk(KERN_INFO , dev , format , ## arg);\ +}while(0) +#else +#define RK610_DBG(dev, format, arg...) +#endif +#define RK610_ERR(dev, format, arg...) \ +do{\ + dev_printk(KERN_ERR , dev , format , ## arg);\ +}while(0) + +#define RK610_CONTROL_REG_C_PLL_CON0 0x00 +#define RK610_CONTROL_REG_C_PLL_CON1 0x01 +#define RK610_CONTROL_REG_C_PLL_CON2 0x02 +#define RK610_CONTROL_REG_C_PLL_CON3 0x03 +#define RK610_CONTROL_REG_C_PLL_CON4 0x04 +#define RK610_CONTROL_REG_C_PLL_CON5 0x05 + #define C_PLL_DISABLE_FRAC 1 << 0 + #define C_PLL_BYPSS_ENABLE 1 << 1 + #define C_PLL_POWER_ON 1 << 2 + #define C_PLL_LOCLED 1 << 7 + +#define RK610_CONTROL_REG_TVE_CON 0x29 + #define TVE_CONTROL_VDAC_R_BYPASS_ENABLE 1 << 7 + #define TVE_CONTROL_VDAC_R_BYPASS_DISABLE 0 << 7 + #define TVE_CONTROL_CVBS_3_CHANNEL_ENALBE 1 << 6 + #define TVE_CONTROL_CVBS_3_CHANNEL_DISALBE 0 << 5 +enum { + INPUT_DATA_FORMAT_RGB888 = 0, + INPUT_DATA_FORMAT_RGB666, + INPUT_DATA_FORMAT_RGB565, + INPUT_DATA_FORMAT_YUV +}; + #define RGB2CCIR_INPUT_DATA_FORMAT(n) n << 4 + + #define RGB2CCIR_RGB_SWAP_ENABLE 1 << 3 + #define RGB2CCIR_RGB_SWAP_DISABLE 0 << 3 + + #define RGB2CCIR_INPUT_INTERLACE 1 << 2 + #define RGB2CCIR_INPUT_PROGRESSIVE 0 << 2 + + #define RGB2CCIR_CVBS_PAL 0 << 1 + #define RGB2CCIR_CVBS_NTSC 1 << 1 + + #define RGB2CCIR_DISABLE 0 + #define RGB2CCIR_ENABLE 1 + +#define RK610_CONTROL_REG_CCIR_RESET 0x2a + +#define RK610_CONTROL_REG_CLOCK_CON0 0x2b +#define RK610_CONTROL_REG_CLOCK_CON1 0x2c + #define CLOCK_CON1_I2S_CLK_CODEC_PLL 1 << 5 + #define CLOCK_CON1_I2S_DVIDER_MASK 0x1F +#define RK610_CONTROL_REG_CODEC_CON 0x2d + #define CODEC_CON_BIT_HDMI_BLCK_INTERANL 1<<4 + #define CODEC_CON_BIT_DAC_LRCL_OUTPUT_DISABLE 1<<3 + #define CODEC_CON_BIT_ADC_LRCK_OUTPUT_DISABLE 1<<2 + #define CODEC_CON_BIT_INTERAL_CODEC_DISABLE 1<<0 + +#define RK610_CONTROL_REG_I2C_CON 0x2e + +/******************************************************************** +** ½á¹¹¶¨Òå * +********************************************************************/ +/* RK610µÄ¼Ä´æÆ÷½á¹¹ */ +/* CODEC PLL REG */ +#define C_PLL_CON0 0x00 +#define C_PLL_CON1 0x01 +#define C_PLL_CON2 0x02 +#define C_PLL_CON3 0x03 +#define C_PLL_CON4 0x04 +#define C_PLL_CON5 0x05 + +/* SCALER PLL REG */ +#define S_PLL_CON0 0x06 +#define S_PLL_CON1 0x07 +#define S_PLL_CON2 0x08 + +/* LVDS REG */ +#define LVDS_CON0 0x09 +#define LVDS_CON1 0x0a + +/* LCD1 REG */ +#define LCD1_CON 0x0b + +/* SCALER REG */ +#define SCL_CON0 0x0c +#define SCL_CON1 0x0d +#define SCL_CON2 0x0e +#define SCL_CON3 0x0f +#define SCL_CON4 0x10 +#define SCL_CON5 0x11 +#define SCL_CON6 0x12 +#define SCL_CON7 0x13 +#define SCL_CON8 0x14 +#define SCL_CON9 0x15 +#define SCL_CON10 0x16 +#define SCL_CON11 0x17 +#define SCL_CON12 0x18 +#define SCL_CON13 0x19 +#define SCL_CON14 0x1a +#define SCL_CON15 0x1b +#define SCL_CON16 0x1c +#define SCL_CON17 0x1d +#define SCL_CON18 0x1e +#define SCL_CON19 0x1f +#define SCL_CON20 0x20 +#define SCL_CON21 0x21 +#define SCL_CON22 0x22 +#define SCL_CON23 0x23 +#define SCL_CON24 0x24 +#define SCL_CON25 0x25 +#define SCL_CON26 0x26 +#define SCL_CON27 0x27 +#define SCL_CON28 0x28 + +/* TVE REG */ +#define TVE_CON 0x29 + +/* CCIR REG */ +#define CCIR_RESET 0X2a + +/* CLOCK REG */ +#define CLOCK_CON0 0X2b +#define CLOCK_CON1 0X2c + +/* CODEC REG */ +#define CODEC_CON 0x2e +#define I2C_CON 0x2f + + +struct rk610_core_info{ + struct i2c_client *client; + struct device *dev; + + struct dentry *debugfs_dir; + void *lcd_pdata; + struct clk *i2s_clk; + int reset_gpio; +}; + +extern int rk610_control_send_byte(const char reg, const char data); + +#endif /*end of __RK610_CONTROL_H_*/ diff --git a/include/linux/mfd/rk616.h b/include/linux/mfd/rk616.h new file mode 100644 index 000000000000..93125b75bf7b --- /dev/null +++ b/include/linux/mfd/rk616.h @@ -0,0 +1,297 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _RK616_H_ +#define _RK616_H_ + +#include <linux/types.h> +#include <linux/i2c.h> +#include <linux/rk_fb.h> +#include <linux/clk.h> +#include <linux/delay.h> + +#if defined(CONFIG_RK616_DEBUG) +#define rk616_dbg(dev, format, arg...) \ + dev_info(dev , format , ## arg) +#else +#define rk616_dbg(dev, format, arg...) do{}while(0) +#endif + +#define VIF0_REG0 0x0000 +#define VIF0_DDR_CLK_EN (1<<3) +#define VIF0_DDR_PHASEN_EN (1<<2) //negative edge first en +#define VIF0_DDR_MODE_EN (1<<1) +#define VIF0_EN (1<<0) + +#define VIF0_REG1 0x0004 +#define VIF0_REG2 0x0008 +#define VIF0_REG3 0x000C +#define VIF0_REG4 0x0010 +#define VIF0_REG5 0x0014 +#define VIF1_REG0 0x0018 +#define VIF1_REG1 0x001C +#define VIF1_REG2 0x0020 +#define VIF1_REG3 0x0024 +#define VIF1_REG4 0x0028 +#define VIF1_REG5 0x002C +#define SCL_REG0 0x0030 +#define SCL_EN (1<<0) + +#define SCL_REG1 0x0034 +#define SCL_REG2 0x0038 +#define SCL_REG3 0x003C +#define SCL_REG4 0x0040 +#define SCL_REG5 0x0044 +#define SCL_REG6 0x0048 +#define SCL_REG7 0x004C +#define SCL_REG8 0x0050 +#define FRC_REG 0x0054 +#define FRC_DEN_INV (1<<6) +#define FRC_SYNC_INV (1<<5) +#define FRC_DCLK_INV (1<<4) +#define FRC_OUT_ZERO (1<<3) +#define FRC_RGB18_MODE (1<<2) +#define FRC_HIFRC_MODE (1<<1) +#define FRC_DITHER_EN (1<<0) + +#define CRU_CLKSEL0_CON 0x0058 +#define PLL1_CLK_SEL_MASK (0x3<<24) +#define PLL0_CLK_SEL_MASK (0x3<<22) +#define LCD1_CLK_DIV_MASK (0x7<<19) +#define LCD0_CLK_DIV_MASK (0x7<<16) +#define PLL1_CLK_SEL(x) (((x)&3)<<8) +#define PLL0_CLK_SEL(x) (((x)&3)<<6) +#define LCD0_DCLK 0 +#define LCD1_DCLK 1 +#define MCLK_12M 2 +#define LCD1_CLK_DIV(x) (((x)&7)<<3) +#define LCD0_CLK_DIV(x) (((x)&7)<<0) + +#define CRU_CLKSEL1_CON 0x005C +#define SCLK_SEL_MASK (1<<19) +#define CODEC_MCLK_SEL_MASK (3<<16) +#define LCDC_CLK_GATE (1<<12) +#define LCDC1_CLK_GATE (1<<11) +#define MIPI_CLK_GATE (1<<10) +#define LVDS_CLK_GATE (1<<9) +#define HDMI_CLK_GATE (1<<8) +#define SCL_CLK_DIV(x) (((x)&7)<<5) +#define SCL_CLK_GATE (1<<4) +#define SCLK_SEL(x) (((x)&1)<<3) +#define SCLK_SEL_PLL0 0 +#define SCLK_SEL_PLL1 1 +#define CODEC_CLK_GATE (1<<2) +#define CODEC_MCLK_SEL(x) (((x)&3)<<0) +#define CODEC_MCLK_SEL_PLL0 0 +#define CODEC_MCLK_SEL_PLL1 1 +#define CODEC_MCLK_SEL_12M 2 + +#define CRU_CODEC_DIV 0x0060 + +#define CRU_CLKSEL2_CON 0x0064 +#define SCL_IN_SEL_MASK (1<<31) +#define DITHER_IN_SEL_MASK (1<<30) +#define HDMI_IN_SEL_MASK (3<<28) +#define VIF1_CLK_DIV_MASK (7<<25) +#define VIF0_CLK_DIV_MASK (7<<19) +#define VIF1_CLKIN_SEL_MASK (1<<22) +#define VIF0_CLKIN_SEL_MASK (1<<16) +#define SCL_IN_SEL(x) (((x)&1)<<15) +#define SCL_SEL_VIF0 0 +#define SCL_SEL_VIF1 1 +#define DITHER_IN_SEL(x) (((x)&1)<<14) +#define DITHER_SEL_VIF0 0 +#define DITHER_SEL_SCL 1 + +#define HDMI_IN_SEL(x) (((x)&3)<<12) //hdmi data in select +#define HDMI_IN_SEL_VIF1 0 +#define HDMI_IN_SEL_SCL 1 +#define HDMI_IN_SEL_VIF0 2 +#define VIF1_CLK_DIV(x) (((x)&7)<<9) +#define VIF1_CLK_GATE (1<<8) +#define VIF1_CLK_BYPASS (1<<7) +#define VIF1_CLKIN_SEL(x) (((x)&1)<<6) +#define VIF_CLKIN_SEL_PLL0 0 +#define VIF_CLKIN_SEL_PLL1 1 +#define VIF0_CLK_DIV(x) (((x)&7)<<3) +#define VIF0_CLK_GATE (1<<2) +#define VIF0_CLK_BYPASS (1<<1) +#define VIF0_CLKIN_SEL(x) (((x)&1)<<0) + + +#define CRU_PLL0_CON0 0x0068 +#define PLL0_POSTDIV1_MASK (7<<28) +#define PLL0_FBDIV_MASK (0xfff << 16) +#define PLL0_BYPASS (1<<15) +#define PLL0_POSTDIV1(x) (((x)&7)<<12) +#define PLL0_FBDIV(x) (((x)&0xfff)<<0) + +#define CRU_PLL0_CON1 0x006C +#define PLL0_DIV_MODE_MASK (1<<25) +#define PLL0_POSTDIV2_MASK (7<<22) +#define PLL0_REFDIV_MASK (0x3f<<16) +#define PLL0_LOCK (1<<15) +#define PLL0_PWR_DN (1<<10) +#define PLL0_DIV_MODE(x) (((x)&1)<<9) +#define PLL0_POSTDIV2(x) (((x)&7)<<6) +#define PLL0_REFDIV(x) (((x)&0x3f)<<0) + +#define CRU_PLL0_CON2 0x0070 +#define PLL0_FOUT4_PWR_DN (1<<27) +#define PLL0_FOUTVCO_PWR_DN (1<<26) +#define PLL0_POSTDIV_PWR_DN (1<<25) +#define PLL0_DAC_PWR_DN (1<<24) +#define PLL0_FRAC(x) (((x)&0xffffff)<<0) + +#define CRU_PLL1_CON0 0x0074 +#define PLL1_POSTDIV1_MASK (7<<28) +#define PLL1_FBDIV_MASK (0xfff << 16) +#define PLL1_BYPASS (1<<15) +#define PLL1_POSTDIV1(x) (((x)&7)<<12) +#define PLL1_FBDIV(x) (((x)&0xfff)<<0) + +#define CRU_PLL1_CON1 0x0078 +#define PLL1_POSTDIV2_MASK (7<<22) +#define PLL1_REFDIV_MASK (0x3f<<16) +#define PLL1_LOCK (1<<15) +#define PLL1_PWR_DN (1<<10) +#define PLL1_DIV_MODE (1<<9) +#define PLL1_POSTDIV2(x) (((x)&7)<<6) +#define PLL1_REFDIV(x) (((x)&0x3f)<<0) + +#define CRU_PLL1_CON2 0x007C +#define PLL1_FOUT4_PWR_DN (1<<27) +#define PLL1_FOUTVCO_PWR_DN (1<<26) +#define PLL1_POSTDIV_PWR_DN (1<<25) +#define PLL1_DAC_PWR_DN (1<<24) +#define PLL1_FRAC(x) (((x)&0xffffff)<<0) + +#define CRU_I2C_CON0 0x0080 + +#define CRU_LVDS_CON0 0x0084 +#define LVDS_HBP_ODD_MASK (0x1<<30) +#define LVDS_OUT_FORMAT_MASK (3<<16) +#define LVDS_HBP_ODD(x) (((x)&1)<<14) +#define LVDS_DCLK_INV (1<<13) +#define LVDS_CH1_LOAD (1<<12) +#define LVDS_CH0_LOAD (1<<11) +#define LVDS_CH1TTL_EN (1<<10) +#define LVDS_CH0TTL_EN (1<<9) +#define LVDS_CH1_PWR_EN (1<<8) +#define LVDS_CH0_PWR_EN (1<<7) +#define LVDS_CBG_PWR_EN (1<<6) +#define LVDS_PLL_PWR_DN (1<<5) +#define LVDS_START_CH_SEL (1<<4) +#define LVDS_CH_SEL (1<<3) +#define LVDS_MSB_SEL (1<<2) +#define LVDS_OUT_FORMAT(x) (((x)&3)<<0) + + +#define CRU_IO_CON0 0x0088 +#define VIF1_SYNC_EN (1<<15) +#define VIF0_SYNC_EN (1<<14) +#define I2S1_OUT_DISABLE (1<<13) +#define I2S0_OUT_DISABLE (1<<12) +#define LVDS_OUT_EN (1<<11) +#define LCD1_INPUT_EN (1<<10) +#define LVDS_RGBIO_PD_DISABLE (1<<9) +#define LCD1_IO_PD_DISABLE (1<<8) +#define LCD0_IO_PD_DISABLE (1<<7) +#define HDMI_IO_PU_DISABLE (1<<6) +#define SPDIF_IO_PD_DISABLE (1<<5) +#define I2S1_PD_DISABLE (1<<4) +#define I2S0_PD_DISABLE (1<<3) +#define I2C_PU_DISABLE (1<<2) +#define INT_IO_PU (1<<1) +#define CLKIN_PU (1<<0) + + +#define CRU_IO_CON1 0x008C +#define LVDS_RGBIO_SI_EN (1<<9) //shmitt input enable +#define LCD1_SI_EN (1<<8) +#define LCD0_SI_EN (1<<7) +#define HDMI_SI_EN (1<<6) +#define SPDIF_SI_EN (1<<5) +#define I2S1_SI_EN (1<<4) +#define I2S0_SI_EN (1<<3) +#define I2C_SI_EN (1<<2) +#define INT_SI_EN (1<<1) +#define CLKIN_SI_EN (1<<0) +#define CRU_PCM2IS2_CON0 0x0090 +#define CRU_PCM2IS2_CON1 0x0094 +#define CRU_PCM2IS2_CON2 0x0098 +#define CRU_CFGMISC_CON 0x009C +#define HDMI_CLK_SEL_MASK (3<<12) +#define HDMI_CLK_SEL(x) (((x)&3)<<12) //hdmi data in select +#define HDMI_CLK_SEL_VIF1 0 +#define HDMI_CLK_SEL_SCL 1 +#define HDMI_CLK_SEL_VIF0 2 + + +enum lcd_port_func{ // the function of lcd ports(lcd0,lcd1),the lcd0 only can be used as input or unused + UNUSED, // the lcd1 can be used as input,output or unused + INPUT, + OUTPUT, +}; + +enum lvds_mode { + RGB, + LVDS, +}; +struct rk616_platform_data { + int (*power_init)(void); + int (*power_deinit)(void); + int scl_rate; + enum lcd_port_func lcd0_func; + enum lcd_port_func lcd1_func; + int lvds_ch_nr; //the number of used lvds channel + int hdmi_irq; +}; + +struct rk616_route { + u16 vif0_bypass; + u8 vif0_en; + u16 vif0_clk_sel; + u16 vif1_bypass; + u8 vif1_en; + u16 vif1_clk_sel; + u16 sclin_sel; + u8 scl_en; + u8 scl_bypass; + u16 dither_sel; + u16 hdmi_sel; + u16 hdmi_clk_sel; + u16 pll0_clk_sel; + u16 pll1_clk_sel; + u16 sclk_sel; + u8 lcd1_input; + u8 lvds_en; + enum lvds_mode lvds_mode; //RGB or LVDS + int lvds_ch_nr; //the number of used lvds channel +}; + +struct mfd_rk616 { + struct mutex reg_lock; + + struct device *dev; + unsigned int irq_base; + struct rk616_platform_data *pdata; + struct rk616_route route; //display path router + struct i2c_client *client; + struct clk *mclk; + u64 pll0_rate; + u64 pll1_rate; + unsigned int resume; + struct dentry *debugfs_dir; + int (*read_dev)(struct mfd_rk616 *rk616,u16 reg,u32 *pval); + int (*write_dev)(struct mfd_rk616 *rk616,u16 reg,u32 *pval); + int (*write_dev_bits)(struct mfd_rk616 *rk616,u16 reg,u32 mask,u32 *pval); + int (*write_bulk)(struct mfd_rk616 *rk616,u16 reg,int count,u32 *pval); +}; + +extern int rk616_set_vif(struct mfd_rk616 * rk616,struct rk_screen * screen,bool connect); +extern int rk616_display_router_cfg(struct mfd_rk616 *rk616,struct rk_screen *screen,bool enable); +extern void rk616_mclk_set_rate(struct clk *mclk,unsigned long rate); + + + +#endif + diff --git a/include/linux/mfd/rk618.h b/include/linux/mfd/rk618.h new file mode 100644 index 000000000000..94525e1cb137 --- /dev/null +++ b/include/linux/mfd/rk618.h @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __RK618_H__ +#define __RK618_H__ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/regmap.h> + +#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) +#define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16)) + +#define RK618_LVDS_CON 0x0084 +#define LVDS_CON_START_PHASE(x) HIWORD_UPDATE(x, 14, 14) +#define LVDS_DCLK_INV HIWORD_UPDATE(1, 13, 13) +#define LVDS_CON_CHADS_10PF HIWORD_UPDATE(3, 12, 11) +#define LVDS_CON_CHADS_5PF HIWORD_UPDATE(2, 12, 11) +#define LVDS_CON_CHADS_7PF HIWORD_UPDATE(1, 12, 11) +#define LVDS_CON_CHADS_3PF HIWORD_UPDATE(0, 12, 11) +#define LVDS_CON_CHA1TTL_ENABLE HIWORD_UPDATE(1, 10, 10) +#define LVDS_CON_CHA1TTL_DISABLE HIWORD_UPDATE(0, 10, 10) +#define LVDS_CON_CHA0TTL_ENABLE HIWORD_UPDATE(1, 9, 9) +#define LVDS_CON_CHA0TTL_DISABLE HIWORD_UPDATE(0, 9, 9) +#define LVDS_CON_CHA1_POWER_UP HIWORD_UPDATE(1, 8, 8) +#define LVDS_CON_CHA1_POWER_DOWN HIWORD_UPDATE(0, 8, 8) +#define LVDS_CON_CHA0_POWER_UP HIWORD_UPDATE(1, 7, 7) +#define LVDS_CON_CHA0_POWER_DOWN HIWORD_UPDATE(0, 7, 7) +#define LVDS_CON_CBG_POWER_UP HIWORD_UPDATE(1, 6, 6) +#define LVDS_CON_CBG_POWER_DOWN HIWORD_UPDATE(0, 6, 6) +#define LVDS_CON_PLL_POWER_DOWN HIWORD_UPDATE(1, 5, 5) +#define LVDS_CON_PLL_POWER_UP HIWORD_UPDATE(0, 5, 5) +#define LVDS_CON_START_SEL_EVEN_PIXEL HIWORD_UPDATE(1, 4, 4) +#define LVDS_CON_START_SEL_ODD_PIXEL HIWORD_UPDATE(0, 4, 4) +#define LVDS_CON_CHASEL_DOUBLE_CHANNEL HIWORD_UPDATE(1, 3, 3) +#define LVDS_CON_CHASEL_SINGLE_CHANNEL HIWORD_UPDATE(0, 3, 3) +#define LVDS_CON_MSBSEL_D7 HIWORD_UPDATE(1, 2, 2) +#define LVDS_CON_MSBSEL_D0 HIWORD_UPDATE(0, 2, 2) +#define LVDS_CON_SELECT(x) HIWORD_UPDATE(x, 1, 0) +#define LVDS_CON_SELECT_6BIT_MODE HIWORD_UPDATE(3, 1, 0) +#define LVDS_CON_SELECT_8BIT_MODE_3 HIWORD_UPDATE(2, 1, 0) +#define LVDS_CON_SELECT_8BIT_MODE_2 HIWORD_UPDATE(1, 1, 0) +#define LVDS_CON_SELECT_8BIT_MODE_1 HIWORD_UPDATE(0, 1, 0) +#define RK618_IO_CON0 0x0088 +#define VIF1_SYNC_MODE_ENABLE HIWORD_UPDATE(1, 15, 15) +#define VIF1_SYNC_MODE_DISABLE HIWORD_UPDATE(0, 15, 15) +#define VIF0_SYNC_MODE_ENABLE HIWORD_UPDATE(1, 14, 14) +#define VIF0_SYNC_MODE_DISABLE HIWORD_UPDATE(0, 14, 14) +#define PORT2_OUTPUT_LVDS HIWORD_UPDATE(1, 11, 11) +#define PORT2_OUTPUT_TTL HIWORD_UPDATE(0, 11, 11) +#define PORT1_OUTPUT_TTL_DISABLE HIWORD_UPDATE(1, 10, 10) +#define PORT1_OUTPUT_TTL_ENABLE HIWORD_UPDATE(0, 10, 10) +#define PORT2_IO_PULL_DOWN_DISABLE HIWORD_UPDATE(1, 9, 9) +#define PORT2_IO_PULL_DOWN_ENABLE HIWORD_UPDATE(0, 9, 9) +#define PORT1_IO_PULL_DOWN_DISABLE HIWORD_UPDATE(1, 8, 8) +#define PORT1_IO_PULL_DOWN_ENABLE HIWORD_UPDATE(0, 8, 8) +#define PORT0_IO_PULL_DOWN_DISABLE HIWORD_UPDATE(1, 7, 7) +#define PORT0_IO_PULL_DOWN_ENABLE HIWORD_UPDATE(0, 7, 7) +#define HDMI_IO_PULL_UP_DISABLE HIWORD_UPDATE(1, 6, 6) +#define HDMI_IO_PULL_UP_ENABLE HIWORD_UPDATE(0, 6, 6) +#define I2C_IO_PULL_UP_DISABLE HIWORD_UPDATE(1, 2, 2) +#define I2C_IO_PULL_UP_ENABLE HIWORD_UPDATE(0, 2, 2) +#define INT_IO_PULL_UP HIWORD_UPDATE(1, 1, 1) +#define INT_IO_PULL_DOWN HIWORD_UPDATE(0, 1, 1) +#define CLKIN_IO_PULL_UP HIWORD_UPDATE(1, 0, 0) +#define CLKIN_IO_PULL_DOWN HIWORD_UPDATE(0, 0, 0) +#define RK618_IO_CON1 0x008c +#define PORT2_IO_SCHMITT_INPUT_ENABLE HIWORD_UPDATE(1, 9, 9) +#define PORT2_IO_SCHMITT_INPUT_DISABLE HIWORD_UPDATE(0, 9, 9) +#define PORT1_IO_SCHMITT_INPUT_ENABLE HIWORD_UPDATE(1, 8, 8) +#define PORT1_IO_SCHMITT_INPUT_DISABLE HIWORD_UPDATE(0, 8, 8) +#define PORT0_IO_SCHMITT_INPUT_ENABLE HIWORD_UPDATE(1, 7, 7) +#define PORT0_IO_SCHMITT_INPUT_DISABLE HIWORD_UPDATE(0, 7, 7) +#define HDMI_IO_SCHMITT_INPUT_ENABLE HIWORD_UPDATE(1, 6, 6) +#define HDMI_IO_SCHMITT_INPUT_DISABLE HIWORD_UPDATE(0, 6, 6) +#define I2C_IO_SCHMITT_INPUT_ENABLE HIWORD_UPDATE(1, 2, 2) +#define I2C_IO_SCHMITT_INPUT_DISABLE HIWORD_UPDATE(0, 2, 2) +#define INT_IO_SCHMITT_INPUT_ENABLE HIWORD_UPDATE(1, 1, 1) +#define INT_IO_SCHMITT_INPUT_DISABLE HIWORD_UPDATE(0, 1, 1) +#define CLKIN_IO_SCHMITT_INPUT_ENABLE HIWORD_UPDATE(1, 0, 0) +#define CLKIN_IO_SCHMITT_INPUT_DISABLE HIWORD_UPDATE(0, 0, 0) +#define RK618_MISC_CON 0x009c +#define HDMI_INT_STATUS BIT(20) +#define MIPI_INT_STATUS BIT(19) +#define MIPI_EDPI_HALT BIT(16) +#define HDMI_HSYNC_POL_INV BIT(15) +#define HDMI_VSYNC_POL_INV BIT(14) +#define HDMI_CLK_SEL_MASK GENMASK(13, 12) +#define HDMI_CLK_SEL_VIDEO_INF0_CLK UPDATE(2, 13, 12) +#define HDMI_CLK_SEL_SCALER_CLK UPDATE(1, 13, 12) +#define HDMI_CLK_SEL_VIDEO_INF1_CLK 0 +#define INT_ACTIVE_LOW BIT(5) +#define INT_ACTIVE_HIGH 0 +#define DOUBLE_CH_LVDS_DEN_POLARITY BIT(4) +#define DOUBLE_CH_LVDS_DEN_LOW BIT(4) +#define DOUBLE_CH_LVDS_DEN_HIGH 0 +#define DOUBLE_CH_LVDS_HSYNC_POLARITY BIT(3) +#define DOUBLE_CH_LVDS_HSYNC_LOW BIT(3) +#define DOUBLE_CH_LVDS_HSYNC_HIGH 0 +#define MIPI_DPICOLOM BIT(2) +#define MIPI_DPISHUTDN BIT(1) + +struct rk618 { + struct device *dev; + struct i2c_client *client; + struct clk *clkin; + struct regmap *regmap; + + struct regulator *supply; + struct gpio_desc *enable_gpio; + struct gpio_desc *reset_gpio; /* power on reset */ +}; + +#endif diff --git a/include/linux/mfd/rk808.h b/include/linux/mfd/rk808.h index 441b6ee72691..10f0ce092ea0 100644 --- a/include/linux/mfd/rk808.h +++ b/include/linux/mfd/rk808.h @@ -47,6 +47,49 @@ enum rk808_reg { RK808_ID_SWITCH2, }; +enum rk816_reg { + RK816_ID_DCDC1, + RK816_ID_DCDC2, + RK816_ID_DCDC3, + RK816_ID_DCDC4, + RK816_ID_LDO1, + RK816_ID_LDO2, + RK816_ID_LDO3, + RK816_ID_LDO4, + RK816_ID_LDO5, + RK816_ID_LDO6, +}; + +enum rk818_reg { + RK818_ID_DCDC1, + RK818_ID_DCDC2, + RK818_ID_DCDC3, + RK818_ID_DCDC4, + RK818_ID_BOOST, + RK818_ID_LDO1, + RK818_ID_LDO2, + RK818_ID_LDO3, + RK818_ID_LDO4, + RK818_ID_LDO5, + RK818_ID_LDO6, + RK818_ID_LDO7, + RK818_ID_LDO8, + RK818_ID_LDO9, + RK818_ID_SWITCH, + RK818_ID_HDMI_SWITCH, + RK818_ID_OTG_SWITCH, +}; + +enum rk805_reg { + RK805_ID_DCDC1, + RK805_ID_DCDC2, + RK805_ID_DCDC3, + RK805_ID_DCDC4, + RK805_ID_LDO1, + RK805_ID_LDO2, + RK805_ID_LDO3, +}; + #define RK808_SECONDS_REG 0x00 #define RK808_MINUTES_REG 0x01 #define RK808_HOURS_REG 0x02 @@ -65,6 +108,8 @@ enum rk808_reg { #define RK808_RTC_INT_REG 0x12 #define RK808_RTC_COMP_LSB_REG 0x13 #define RK808_RTC_COMP_MSB_REG 0x14 +#define RK808_ID_MSB 0x17 +#define RK808_ID_LSB 0x18 #define RK808_CLK32OUT_REG 0x20 #define RK808_VB_MON_REG 0x21 #define RK808_THERMAL_REG 0x22 @@ -115,6 +160,138 @@ enum rk808_reg { #define RK808_INT_STS_MSK_REG2 0x4f #define RK808_IO_POL_REG 0x50 +#define RK818_VB_MON_REG 0x21 +#define RK818_THERMAL_REG 0x22 +#define RK818_DCDC_EN_REG 0x23 +#define RK818_LDO_EN_REG 0x24 +#define RK818_SLEEP_SET_OFF_REG1 0x25 +#define RK818_SLEEP_SET_OFF_REG2 0x26 +#define RK818_DCDC_UV_STS_REG 0x27 +#define RK818_DCDC_UV_ACT_REG 0x28 +#define RK818_LDO_UV_STS_REG 0x29 +#define RK818_LDO_UV_ACT_REG 0x2a +#define RK818_DCDC_PG_REG 0x2b +#define RK818_LDO_PG_REG 0x2c +#define RK818_VOUT_MON_TDB_REG 0x2d +#define RK818_BUCK1_CONFIG_REG 0x2e +#define RK818_BUCK1_ON_VSEL_REG 0x2f +#define RK818_BUCK1_SLP_VSEL_REG 0x30 +#define RK818_BUCK2_CONFIG_REG 0x32 +#define RK818_BUCK2_ON_VSEL_REG 0x33 +#define RK818_BUCK2_SLP_VSEL_REG 0x34 +#define RK818_BUCK3_CONFIG_REG 0x36 +#define RK818_BUCK4_CONFIG_REG 0x37 +#define RK818_BUCK4_ON_VSEL_REG 0x38 +#define RK818_BUCK4_SLP_VSEL_REG 0x39 +#define RK818_BOOST_CONFIG_REG 0x3a +#define RK818_LDO1_ON_VSEL_REG 0x3b +#define RK818_LDO1_SLP_VSEL_REG 0x3c +#define RK818_LDO2_ON_VSEL_REG 0x3d +#define RK818_LDO2_SLP_VSEL_REG 0x3e +#define RK818_LDO3_ON_VSEL_REG 0x3f +#define RK818_LDO3_SLP_VSEL_REG 0x40 +#define RK818_LDO4_ON_VSEL_REG 0x41 +#define RK818_LDO4_SLP_VSEL_REG 0x42 +#define RK818_LDO5_ON_VSEL_REG 0x43 +#define RK818_LDO5_SLP_VSEL_REG 0x44 +#define RK818_LDO6_ON_VSEL_REG 0x45 +#define RK818_LDO6_SLP_VSEL_REG 0x46 +#define RK818_LDO7_ON_VSEL_REG 0x47 +#define RK818_LDO7_SLP_VSEL_REG 0x48 +#define RK818_LDO8_ON_VSEL_REG 0x49 +#define RK818_LDO8_SLP_VSEL_REG 0x4a +#define RK818_DEVCTRL_REG 0x4b +#define RK818_INT_STS_REG1 0X4c +#define RK818_INT_STS_MSK_REG1 0X4d +#define RK818_INT_STS_REG2 0X4e +#define RK818_INT_STS_MSK_REG2 0X4f +#define RK818_IO_POL_REG 0X50 +#define RK818_OTP_VDD_EN_REG 0x51 +#define RK818_H5V_EN_REG 0x52 +#define RK818_SLEEP_SET_OFF_REG3 0x53 +#define RK818_BOOST_LDO9_ON_VSEL_REG 0x54 +#define RK818_BOOST_LDO9_SLP_VSEL_REG 0x55 +#define RK818_BOOST_CTRL_REG 0x56 +#define RK818_DCDC_ILMAX_REG 0x90 +#define RK818_CHRG_COMP_REG 0x9a +#define RK818_SUP_STS_REG 0xa0 +#define RK818_USB_CTRL_REG 0xa1 +#define RK818_CHRG_CTRL_REG1 0xa3 +#define RK818_CHRG_CTRL_REG2 0xa4 +#define RK818_CHRG_CTRL_REG3 0xa5 +#define RK818_BAT_CTRL_REG 0xa6 +#define RK818_BAT_HTS_TS1_REG 0xa8 +#define RK818_BAT_LTS_TS1_REG 0xa9 +#define RK818_BAT_HTS_TS2_REG 0xaa +#define RK818_BAT_LTS_TS2_REG 0xab +#define RK818_TS_CTRL_REG 0xac +#define RK818_ADC_CTRL_REG 0xad +#define RK818_ON_SOURCE_REG 0xae +#define RK818_OFF_SOURCE_REG 0xaf +#define RK818_GGCON_REG 0xb0 +#define RK818_GGSTS_REG 0xb1 +#define RK818_FRAME_SMP_INTERV_REG 0xb2 +#define RK818_AUTO_SLP_CUR_THR_REG 0xb3 +#define RK818_GASCNT_CAL_REG3 0xb4 +#define RK818_GASCNT_CAL_REG2 0xb5 +#define RK818_GASCNT_CAL_REG1 0xb6 +#define RK818_GASCNT_CAL_REG0 0xb7 +#define RK818_GASCNT3_REG 0xb8 +#define RK818_GASCNT2_REG 0xb9 +#define RK818_GASCNT1_REG 0xba +#define RK818_GASCNT0_REG 0xbb +#define RK818_BAT_CUR_AVG_REGH 0xbc +#define RK818_BAT_CUR_AVG_REGL 0xbd +#define RK818_TS1_ADC_REGH 0xbe +#define RK818_TS1_ADC_REGL 0xbf +#define RK818_TS2_ADC_REGH 0xc0 +#define RK818_TS2_ADC_REGL 0xc1 +#define RK818_BAT_OCV_REGH 0xc2 +#define RK818_BAT_OCV_REGL 0xc3 +#define RK818_BAT_VOL_REGH 0xc4 +#define RK818_BAT_VOL_REGL 0xc5 +#define RK818_RELAX_ENTRY_THRES_REGH 0xc6 +#define RK818_RELAX_ENTRY_THRES_REGL 0xc7 +#define RK818_RELAX_EXIT_THRES_REGH 0xc8 +#define RK818_RELAX_EXIT_THRES_REGL 0xc9 +#define RK818_RELAX_VOL1_REGH 0xca +#define RK818_RELAX_VOL1_REGL 0xcb +#define RK818_RELAX_VOL2_REGH 0xcc +#define RK818_RELAX_VOL2_REGL 0xcd +#define RK818_BAT_CUR_R_CALC_REGH 0xce +#define RK818_BAT_CUR_R_CALC_REGL 0xcf +#define RK818_BAT_VOL_R_CALC_REGH 0xd0 +#define RK818_BAT_VOL_R_CALC_REGL 0xd1 +#define RK818_CAL_OFFSET_REGH 0xd2 +#define RK818_CAL_OFFSET_REGL 0xd3 +#define RK818_NON_ACT_TIMER_CNT_REG 0xd4 +#define RK818_VCALIB0_REGH 0xd5 +#define RK818_VCALIB0_REGL 0xd6 +#define RK818_VCALIB1_REGH 0xd7 +#define RK818_VCALIB1_REGL 0xd8 +#define RK818_IOFFSET_REGH 0xdd +#define RK818_IOFFSET_REGL 0xde +#define RK818_SOC_REG 0xe0 +#define RK818_REMAIN_CAP_REG3 0xe1 +#define RK818_REMAIN_CAP_REG2 0xe2 +#define RK818_REMAIN_CAP_REG1 0xe3 +#define RK818_REMAIN_CAP_REG0 0xe4 +#define RK818_UPDAT_LEVE_REG 0xe5 +#define RK818_NEW_FCC_REG3 0xe6 +#define RK818_NEW_FCC_REG2 0xe7 +#define RK818_NEW_FCC_REG1 0xe8 +#define RK818_NEW_FCC_REG0 0xe9 +#define RK818_NON_ACT_TIMER_CNT_SAVE_REG 0xea +#define RK818_OCV_VOL_VALID_REG 0xeb +#define RK818_REBOOT_CNT_REG 0xec +#define RK818_POFFSET_REG 0xed +#define RK818_MISC_MARK_REG 0xee +#define RK818_HALT_CNT_REG 0xef +#define RK818_CALC_REST_REGH 0xf0 +#define RK818_CALC_REST_REGL 0xf1 +#define RK818_SAVE_DATA19 0xf2 +#define RK818_NUM_REGULATORS 17 + /* IRQ Definitions */ #define RK808_IRQ_VOUT_LO 0 #define RK808_IRQ_VB_LO 1 @@ -162,12 +339,614 @@ enum rk808_reg { #define SWITCH2_EN BIT(6) #define SWITCH1_EN BIT(5) #define DEV_OFF_RST BIT(3) +#define DEV_OFF BIT(0) +#define RTC_STOP BIT(0) #define VB_LO_ACT BIT(4) #define VB_LO_SEL_3500MV (7 << 0) #define VOUT_LO_INT BIT(0) #define CLK32KOUT2_EN BIT(0) +#define H5V_EN_MASK BIT(0) +#define H5V_EN_ENABLE BIT(0) +#define REF_RDY_CTRL_MASK BIT(1) +#define REF_RDY_CTRL_ENABLE BIT(1) + +/*RK818_DCDC_EN_REG*/ +#define BUCK1_EN_MASK BIT(0) +#define BUCK2_EN_MASK BIT(1) +#define BUCK3_EN_MASK BIT(2) +#define BUCK4_EN_MASK BIT(3) +#define BOOST_EN_MASK BIT(4) +#define LDO9_EN_MASK BIT(5) +#define SWITCH_EN_MASK BIT(6) +#define OTG_EN_MASK BIT(7) + +#define BUCK1_EN_ENABLE BIT(0) +#define BUCK2_EN_ENABLE BIT(1) +#define BUCK3_EN_ENABLE BIT(2) +#define BUCK4_EN_ENABLE BIT(3) +#define BOOST_EN_ENABLE BIT(4) +#define LDO9_EN_ENABLE BIT(5) +#define SWITCH_EN_ENABLE BIT(6) +#define OTG_EN_ENABLE BIT(7) + +/* IRQ Definitions */ +#define RK818_IRQ_VOUT_LO 0 +#define RK818_IRQ_VB_LO 1 +#define RK818_IRQ_PWRON 2 +#define RK818_IRQ_PWRON_LP 3 +#define RK818_IRQ_HOTDIE 4 +#define RK818_IRQ_RTC_ALARM 5 +#define RK818_IRQ_RTC_PERIOD 6 +#define RK818_IRQ_USB_OV 7 +#define RK818_IRQ_PLUG_IN 8 +#define RK818_IRQ_PLUG_OUT 9 +#define RK818_IRQ_CHG_OK 10 +#define RK818_IRQ_CHG_TE 11 +#define RK818_IRQ_CHG_TS1 12 +#define RK818_IRQ_TS2 13 +#define RK818_IRQ_CHG_CVTLIM 14 +#define RK818_IRQ_DISCHG_ILIM 15 + +#define BUCK1_SLP_SET_MASK BIT(0) +#define BUCK2_SLP_SET_MASK BIT(1) +#define BUCK3_SLP_SET_MASK BIT(2) +#define BUCK4_SLP_SET_MASK BIT(3) +#define BOOST_SLP_SET_MASK BIT(4) +#define LDO9_SLP_SET_MASK BIT(5) +#define SWITCH_SLP_SET_MASK BIT(6) +#define OTG_SLP_SET_MASK BIT(7) + +#define BUCK1_SLP_SET_OFF BIT(0) +#define BUCK2_SLP_SET_OFF BIT(1) +#define BUCK3_SLP_SET_OFF BIT(2) +#define BUCK4_SLP_SET_OFF BIT(3) +#define BOOST_SLP_SET_OFF BIT(4) +#define LDO9_SLP_SET_OFF BIT(5) +#define SWITCH_SLP_SET_OFF BIT(6) +#define OTG_SLP_SET_OFF BIT(7) +#define OTG_BOOST_SLP_OFF (BOOST_SLP_SET_OFF | OTG_SLP_SET_OFF) + +#define BUCK1_SLP_SET_ON BIT(0) +#define BUCK2_SLP_SET_ON BIT(1) +#define BUCK3_SLP_SET_ON BIT(2) +#define BUCK4_SLP_SET_ON BIT(3) +#define BOOST_SLP_SET_ON BIT(4) +#define LDO9_SLP_SET_ON BIT(5) +#define SWITCH_SLP_SET_ON BIT(6) +#define OTG_SLP_SET_ON BIT(7) + +#define VOUT_LO_MASK BIT(0) +#define VB_LO_MASK BIT(1) +#define PWRON_MASK BIT(2) +#define PWRON_LP_MASK BIT(3) +#define HOTDIE_MASK BIT(4) +#define RTC_ALARM_MASK BIT(5) +#define RTC_PERIOD_MASK BIT(6) +#define USB_OV_MASK BIT(7) + +#define VOUT_LO_DISABLE BIT(0) +#define VB_LO_DISABLE BIT(1) +#define PWRON_DISABLE BIT(2) +#define PWRON_LP_DISABLE BIT(3) +#define HOTDIE_DISABLE BIT(4) +#define RTC_ALARM_DISABLE BIT(5) +#define RTC_PERIOD_DISABLE BIT(6) +#define USB_OV_INT_DISABLE BIT(7) + +#define VOUT_LO_ENABLE (0 << 0) +#define VB_LO_ENABLE (0 << 1) +#define PWRON_ENABLE (0 << 2) +#define PWRON_LP_ENABLE (0 << 3) +#define HOTDIE_ENABLE (0 << 4) +#define RTC_ALARM_ENABLE (0 << 5) +#define RTC_PERIOD_ENABLE (0 << 6) +#define USB_OV_INT_ENABLE (0 << 7) + +#define PLUG_IN_MASK BIT(0) +#define PLUG_OUT_MASK BIT(1) +#define CHGOK_MASK BIT(2) +#define CHGTE_MASK BIT(3) +#define CHGTS1_MASK BIT(4) +#define TS2_MASK BIT(5) +#define CHG_CVTLIM_MASK BIT(6) +#define DISCHG_ILIM_MASK BIT(7) + +#define PLUG_IN_DISABLE BIT(0) +#define PLUG_OUT_DISABLE BIT(1) +#define CHGOK_DISABLE BIT(2) +#define CHGTE_DISABLE BIT(3) +#define CHGTS1_DISABLE BIT(4) +#define TS2_DISABLE BIT(5) +#define CHG_CVTLIM_DISABLE BIT(6) +#define DISCHG_ILIM_DISABLE BIT(7) + +#define PLUG_IN_ENABLE BIT(0) +#define PLUG_OUT_ENABLE BIT(1) +#define CHGOK_ENABLE BIT(2) +#define CHGTE_ENABLE BIT(3) +#define CHGTS1_ENABLE BIT(4) +#define TS2_ENABLE BIT(5) +#define CHG_CVTLIM_ENABLE BIT(6) +#define DISCHG_ILIM_ENABLE BIT(7) + +/* IRQ Definitions */ +#define RK805_IRQ_VB_LOW 1 +#define RK805_IRQ_PWRON 2 +#define RK805_IRQ_PWRON_LP 3 +#define RK805_IRQ_HOTDIE 4 +#define RK805_IRQ_RTC_ALARM 5 +#define RK805_IRQ_RTC_PERIOD 6 + +/* + * When PMIC irq occurs, regmap-irq.c will traverse all PMIC child + * interrupts from low index 0 to high index, we give fall interrupt + * high priority to be called earlier than rise, so that it can be + * override by late rise event. This can helps to solve key release + * glitch which make a wrongly fall event immediately after rise. + */ +#define RK805_IRQ_PWRON_FALL 0 +#define RK805_IRQ_PWRON_RISE 7 + +#define RK805_IRQ_PWRON_RISE_MSK BIT(0) +#define RK805_IRQ_VB_LOW_MSK BIT(1) +#define RK805_IRQ_PWRON_MSK BIT(2) +#define RK805_IRQ_PWRON_LP_MSK BIT(3) +#define RK805_IRQ_HOTDIE_MSK BIT(4) +#define RK805_IRQ_RTC_ALARM_MSK BIT(5) +#define RK805_IRQ_RTC_PERIOD_MSK BIT(6) +#define RK805_IRQ_PWRON_FALL_MSK BIT(7) + +#define RK805_PWR_RISE_INT_STATUS BIT(0) +#define RK805_VB_LOW_INT_STATUS BIT(1) +#define RK805_PWRON_INT_STATUS BIT(2) +#define RK805_PWRON_LP_INT_STATUS BIT(3) +#define RK805_HOTDIE_INT_STATUS BIT(4) +#define RK805_ALARM_INT_STATUS BIT(5) +#define RK805_PERIOD_INT_STATUS BIT(6) +#define RK805_PWR_FALL_INT_STATUS BIT(7) + +/*INTERRUPT REGISTER*/ +#define RK805_INT_STS_REG 0x4C +#define RK805_INT_STS_MSK_REG 0x4D +#define RK805_GPIO_IO_POL_REG 0x50 +#define RK805_OUT_REG 0x52 +#define RK805_ON_SOURCE_REG 0xAE +#define RK805_OFF_SOURCE_REG 0xAF + +/*POWER CHANNELS ENABLE REGISTER*/ +#define RK805_DCDC_EN_REG 0x23 +#define RK805_SLP_DCDC_EN_REG 0x25 +#define RK805_SLP_LDO_EN_REG 0x26 +#define RK805_LDO_EN_REG 0x27 + +/*CONFIG REGISTER*/ +#define RK805_THERMAL_REG 0x22 + +/*BUCK AND LDO CONFIG REGISTER*/ +#define RK805_BUCK_LDO_SLP_LP_EN_REG 0x2A +#define RK805_BUCK1_CONFIG_REG 0x2E +#define RK805_BUCK1_ON_VSEL_REG 0x2F +#define RK805_BUCK1_SLP_VSEL_REG 0x30 +#define RK805_BUCK2_CONFIG_REG 0x32 +#define RK805_BUCK2_ON_VSEL_REG 0x33 +#define RK805_BUCK2_SLP_VSEL_REG 0x34 +#define RK805_BUCK3_CONFIG_REG 0x36 +#define RK805_BUCK4_CONFIG_REG 0x37 +#define RK805_BUCK4_ON_VSEL_REG 0x38 +#define RK805_BUCK4_SLP_VSEL_REG 0x39 +#define RK805_LDO1_ON_VSEL_REG 0x3B +#define RK805_LDO1_SLP_VSEL_REG 0x3C +#define RK805_LDO2_ON_VSEL_REG 0x3D +#define RK805_LDO2_SLP_VSEL_REG 0x3E +#define RK805_LDO3_ON_VSEL_REG 0x3F +#define RK805_LDO3_SLP_VSEL_REG 0x40 +#define RK805_OUT_REG 0x52 +#define RK805_ON_SOURCE_REG 0xAE +#define RK805_OFF_SOURCE_REG 0xAF +#define RK805_DCDC_VRP_REG 0x92 + +#define RK805_NUM_REGULATORS 7 + +#define RK805_PWRON_FALL_RISE_INT_EN 0x0 +#define RK805_PWRON_FALL_RISE_INT_MSK 0x81 + +/*VERSION REGISTER*/ +#define RK816_CHIP_NAME_REG 0x17 +#define RK816_CHIP_VER_REG 0x18 +#define RK816_OTP_VER_REG 0x19 +#define RK816_NUM_REGULATORS 10 + +/*POWER ON/OFF REGISTER*/ +#define RK816_VB_MON_REG 0x21 +#define RK816_THERMAL_REG 0x22 +#define RK816_PWRON_LP_INT_TIME_REG 0x47 +#define RK816_PWRON_DB_REG 0x48 +#define RK816_DEV_CTRL_REG 0x4B +#define RK816_ON_SOURCE_REG 0xAE +#define RK816_OFF_SOURCE_REG 0xAF + +/*POWER CHANNELS ENABLE REGISTER*/ +#define RK816_DCDC_EN_REG1 0x23 +#define RK816_DCDC_EN_REG2 0x24 +#define RK816_SLP_DCDC_EN_REG 0x25 +#define RK816_SLP_LDO_EN_REG 0x26 +#define RK816_LDO_EN_REG1 0x27 +#define RK816_LDO_EN_REG2 0x28 + +/*BUCK AND LDO CONFIG REGISTER*/ +#define RK816_BUCK1_CONFIG_REG 0x2E +#define RK816_BUCK1_ON_VSEL_REG 0x2F +#define RK816_BUCK1_SLP_VSEL_REG 0x30 +#define RK816_BUCK2_CONFIG_REG 0x32 +#define RK816_BUCK2_ON_VSEL_REG 0x33 +#define RK816_BUCK2_SLP_VSEL_REG 0x34 +#define RK816_BUCK3_CONFIG_REG 0x36 +#define RK816_BUCK4_CONFIG_REG 0x37 +#define RK816_BUCK4_ON_VSEL_REG 0x38 +#define RK816_BUCK4_SLP_VSEL_REG 0x39 +#define RK816_LDO1_ON_VSEL_REG 0x3B +#define RK816_LDO1_SLP_VSEL_REG 0x3C +#define RK816_LDO2_ON_VSEL_REG 0x3D +#define RK816_LDO2_SLP_VSEL_REG 0x3E +#define RK816_LDO3_ON_VSEL_REG 0x3F +#define RK816_LDO3_SLP_VSEL_REG 0x40 +#define RK816_LDO4_ON_VSEL_REG 0x41 +#define RK816_LDO4_SLP_VSEL_REG 0x42 +#define RK816_LDO5_ON_VSEL_REG 0x43 +#define RK816_LDO5_SLP_VSEL_REG 0x44 +#define RK816_LDO6_ON_VSEL_REG 0x45 +#define RK816_LDO6_SLP_VSEL_REG 0x46 + +/*CHARGER BOOST AND OTG REGISTER*/ +#define RK816_OTG_BUCK_LDO_CONFIG_REG 0x2A +#define RK816_CHRG_CONFIG_REG 0x2B +#define RK816_BOOST_ON_VESL_REG 0x54 +#define RK816_BOOST_SLP_VSEL_REG 0x55 +#define RK816_CHRG_BOOST_CONFIG_REG 0x9A +#define RK816_SUP_STS_REG 0xA0 +#define RK816_USB_CTRL_REG 0xA1 +#define RK816_CHRG_CTRL_REG1 0xA3 +#define RK816_CHRG_CTRL_REG2 0xA4 +#define RK816_CHRG_CTRL_REG3 0xA5 +#define RK816_BAT_CTRL_REG 0xA6 +#define RK816_BAT_HTS_TS_REG 0xA8 +#define RK816_BAT_LTS_TS_REG 0xA9 + +#define RK816_TS_CTRL_REG 0xAC +#define RK816_ADC_CTRL_REG 0xAD +#define RK816_GGCON_REG 0xB0 +#define RK816_GGSTS_REG 0xB1 +#define RK816_ZERO_CUR_ADC_REGH 0xB2 +#define RK816_ZERO_CUR_ADC_REGL 0xB3 +#define RK816_GASCNT_CAL_REG3 0xB4 +#define RK816_GASCNT_CAL_REG2 0xB5 +#define RK816_GASCNT_CAL_REG1 0xB6 +#define RK816_GASCNT_CAL_REG0 0xB7 +#define RK816_GASCNT_REG3 0xB8 +#define RK816_GASCNT_REG2 0xB9 +#define RK816_GASCNT_REG1 0xBA +#define RK816_GASCNT_REG0 0xBB +#define RK816_BAT_CUR_AVG_REGH 0xBC +#define RK816_BAT_CUR_AVG_REGL 0xBD +#define RK816_TS_ADC_REGH 0xBE +#define RK816_TS_ADC_REGL 0xBF +#define RK816_USB_ADC_REGH 0xC0 +#define RK816_USB_ADC_REGL 0xC1 +#define RK816_BAT_OCV_REGH 0xC2 +#define RK816_BAT_OCV_REGL 0xC3 +#define RK816_BAT_VOL_REGH 0xC4 +#define RK816_BAT_VOL_REGL 0xC5 +#define RK816_RELAX_ENTRY_THRES_REGH 0xC6 +#define RK816_RELAX_ENTRY_THRES_REGL 0xC7 +#define RK816_RELAX_EXIT_THRES_REGH 0xC8 +#define RK816_RELAX_EXIT_THRES_REGL 0xC9 +#define RK816_RELAX_VOL1_REGH 0xCA +#define RK816_RELAX_VOL1_REGL 0xCB +#define RK816_RELAX_VOL2_REGH 0xCC +#define RK816_RELAX_VOL2_REGL 0xCD +#define RK816_RELAX_CUR1_REGH 0xCE +#define RK816_RELAX_CUR1_REGL 0xCF +#define RK816_RELAX_CUR2_REGH 0xD0 +#define RK816_RELAX_CUR2_REGL 0xD1 +#define RK816_CAL_OFFSET_REGH 0xD2 +#define RK816_CAL_OFFSET_REGL 0xD3 +#define RK816_NON_ACT_TIMER_CNT_REG 0xD4 +#define RK816_VCALIB0_REGH 0xD5 +#define RK816_VCALIB0_REGL 0xD6 +#define RK816_VCALIB1_REGH 0xD7 +#define RK816_VCALIB1_REGL 0xD8 +#define RK816_FCC_GASCNT_REG3 0xD9 +#define RK816_FCC_GASCNT_REG2 0xDA +#define RK816_FCC_GASCNT_REG1 0xDB +#define RK816_FCC_GASCNT_REG0 0xDC +#define RK816_IOFFSET_REGH 0xDD +#define RK816_IOFFSET_REGL 0xDE +#define RK816_SLEEP_CON_SAMP_CUR_REG 0xDF + +/*DATA REGISTER*/ +#define RK816_SOC_REG 0xE0 +#define RK816_REMAIN_CAP_REG3 0xE1 +#define RK816_REMAIN_CAP_REG2 0xE2 +#define RK816_REMAIN_CAP_REG1 0xE3 +#define RK816_REMAIN_CAP_REG0 0xE4 +#define RK816_UPDATE_LEVE_REG 0xE5 +#define RK816_NEW_FCC_REG3 0xE6 +#define RK816_NEW_FCC_REG2 0xE7 +#define RK816_NEW_FCC_REG1 0xE8 +#define RK816_NEW_FCC_REG0 0xE9 +#define RK816_NON_ACT_TIMER_CNT_REG_SAVE 0xEA +#define RK816_OCV_VOL_VALID_REG 0xEB +#define RK816_REBOOT_CNT_REG 0xEC +#define RK816_PCB_IOFFSET_REG 0xED +#define RK816_MISC_MARK_REG 0xEE +#define RK816_HALT_CNT_REG 0xEF +#define RK816_CALC_REST_REGH 0xF0 +#define RK816_CALC_REST_REGL 0xF1 +#define DATA18_REG 0xF2 + +/*INTERRUPT REGISTER*/ +#define RK816_INT_STS_REG1 0x49 +#define RK816_INT_STS_MSK_REG1 0x4A +#define RK816_INT_STS_REG2 0x4C +#define RK816_INT_STS_MSK_REG2 0x4D +#define RK816_INT_STS_REG3 0x4E +#define RK816_INT_STS_MSK_REG3 0x4F +#define RK816_GPIO_IO_POL_REG 0x50 + +#define RK816_DATA18_REG 0xF2 + +/* IRQ Definitions */ +#define RK816_IRQ_PWRON_FALL 0 +#define RK816_IRQ_PWRON_RISE 1 +#define RK816_IRQ_VB_LOW 2 +#define RK816_IRQ_PWRON 3 +#define RK816_IRQ_PWRON_LP 4 +#define RK816_IRQ_HOTDIE 5 +#define RK816_IRQ_RTC_ALARM 6 +#define RK816_IRQ_RTC_PERIOD 7 +#define RK816_IRQ_USB_OV 8 +#define RK816_IRQ_PLUG_IN 9 +#define RK816_IRQ_PLUG_OUT 10 +#define RK816_IRQ_CHG_OK 11 +#define RK816_IRQ_CHG_TE 12 +#define RK816_IRQ_CHG_TS 13 +#define RK816_IRQ_CHG_CVTLIM 14 +#define RK816_IRQ_DISCHG_ILIM 15 + +#define RK816_IRQ_PWRON_FALL_MSK BIT(5) +#define RK816_IRQ_PWRON_RISE_MSK BIT(6) +#define RK816_IRQ_VB_LOW_MSK BIT(1) +#define RK816_IRQ_PWRON_MSK BIT(2) +#define RK816_IRQ_PWRON_LP_MSK BIT(3) +#define RK816_IRQ_HOTDIE_MSK BIT(4) +#define RK816_IRQ_RTC_ALARM_MSK BIT(5) +#define RK816_IRQ_RTC_PERIOD_MSK BIT(6) +#define RK816_IRQ_USB_OV_MSK BIT(7) +#define RK816_IRQ_PLUG_IN_MSK BIT(0) +#define RK816_IRQ_PLUG_OUT_MSK BIT(1) +#define RK816_IRQ_CHG_OK_MSK BIT(2) +#define RK816_IRQ_CHG_TE_MSK BIT(3) +#define RK816_IRQ_CHG_TS_MSK BIT(4) +#define RK816_IRQ_CHG_CVTLIM_MSK BIT(6) +#define RK816_IRQ_DISCHG_ILIM_MSK BIT(7) + +#define RK816_VBAT_LOW_2V8 0x00 +#define RK816_VBAT_LOW_2V9 0x01 +#define RK816_VBAT_LOW_3V0 0x02 +#define RK816_VBAT_LOW_3V1 0x03 +#define RK816_VBAT_LOW_3V2 0x04 +#define RK816_VBAT_LOW_3V3 0x05 +#define RK816_VBAT_LOW_3V4 0x06 +#define RK816_VBAT_LOW_3V5 0x07 +#define RK816_PWR_FALL_INT_STATUS (0x1 << 5) +#define RK816_PWR_RISE_INT_STATUS (0x1 << 6) +#define RK816_ALARM_INT_STATUS (0x1 << 5) +#define EN_VBAT_LOW_IRQ (0x1 << 4) +#define VBAT_LOW_ACT_MASK (0x1 << 4) +#define RTC_TIMER_ALARM_INT_MSK (0x3 << 2) +#define RTC_TIMER_ALARM_INT_DIS (0x0 << 2) +#define RTC_PERIOD_ALARM_INT_MSK (0x3 << 5) +#define RTC_PERIOD_ALARM_INT_ST (0x3 << 5) +#define RTC_PERIOD_ALARM_INT_DIS (0x3 << 5) +#define RTC_PERIOD_ALARM_INT_EN (0x9f) +#define REG_WRITE_MSK 0xff +#define BUCK4_MAX_ILIMIT 0x2c +#define BUCK_RATE_MSK (0x3 << 3) +#define BUCK_RATE_12_5MV_US (0x2 << 3) +#define ALL_INT_FLAGS_ST 0xff +#define PLUGIN_OUT_INT_EN 0xfc +#define RK816_PWRON_FALL_RISE_INT_EN 0x9f +#define BUCK1_2_IMAX_MAX (0x3 << 6) +#define BUCK3_4_IMAX_MAX (0x3 << 3) +#define BOOST_DISABLE ((0x1 << 5) | (0x0 << 1)) +#define BUCK4_VRP_3PERCENT 0xc0 +#define RK816_BUCK_DVS_CONFIRM (0x1 << 7) +#define RK816_TYPE_ES2 0x05 +#define RK816_CHIP_VERSION_MASK 0x0f + +#define TEMP105C 0x08 +#define TEMP115C 0x0c +#define TEMP_HOTDIE_MSK 0x0c +#define SLP_SD_MSK (0x3 << 2) +#define SHUTDOWN_FUN (0x2 << 2) +#define SLEEP_FUN (0x1 << 2) +#define RK8XX_ID_MSK 0xfff0 +#define PWM_MODE_MSK BIT(7) +#define FPWM_MODE BIT(7) +#define AUTO_PWM_MODE 0 +#define REGS_WMSK 0xf0 + +enum rk817_reg_id { + RK817_ID_DCDC1 = 0, + RK817_ID_DCDC2, + RK817_ID_DCDC3, + RK817_ID_DCDC4, + RK817_ID_LDO1, + RK817_ID_LDO2, + RK817_ID_LDO3, + RK817_ID_LDO4, + RK817_ID_LDO5, + RK817_ID_LDO6, + RK817_ID_LDO7, + RK817_ID_LDO8, + RK817_ID_LDO9, + RK817_ID_BOOST, + RK817_ID_BOOST_OTG_SW, + RK817_NUM_REGULATORS +}; + +enum rk809_reg_id { + RK809_ID_DCDC5 = RK817_ID_BOOST, + RK809_ID_SW1, + RK809_ID_SW2, + RK809_NUM_REGULATORS +}; + +#define RK817_SECONDS_REG 0x00 +#define RK817_MINUTES_REG 0x01 +#define RK817_HOURS_REG 0x02 +#define RK817_DAYS_REG 0x03 +#define RK817_MONTHS_REG 0x04 +#define RK817_YEARS_REG 0x05 +#define RK817_WEEKS_REG 0x06 +#define RK817_ALARM_SECONDS_REG 0x07 +#define RK817_ALARM_MINUTES_REG 0x08 +#define RK817_ALARM_HOURS_REG 0x09 +#define RK817_ALARM_DAYS_REG 0x0a +#define RK817_ALARM_MONTHS_REG 0x0b +#define RK817_ALARM_YEARS_REG 0x0c +#define RK817_RTC_CTRL_REG 0xd +#define RK817_RTC_STATUS_REG 0xe +#define RK817_RTC_INT_REG 0xf +#define RK817_RTC_COMP_LSB_REG 0x10 +#define RK817_RTC_COMP_MSB_REG 0x11 + +#define RK817_POWER_EN_REG(i) (0xb1 + (i)) +#define RK817_POWER_SLP_EN_REG(i) (0xb5 + (i)) + +#define RK817_POWER_CONFIG (0xb9) + +#define RK817_BUCK_CONFIG_REG(i) (0xba + (i) * 3) + +#define RK817_BUCK1_ON_VSEL_REG 0xBB +#define RK817_BUCK1_SLP_VSEL_REG 0xBC + +#define RK817_BUCK2_CONFIG_REG 0xBD +#define RK817_BUCK2_ON_VSEL_REG 0xBE +#define RK817_BUCK2_SLP_VSEL_REG 0xBF + +#define RK817_BUCK3_CONFIG_REG 0xC0 +#define RK817_BUCK3_ON_VSEL_REG 0xC1 +#define RK817_BUCK3_SLP_VSEL_REG 0xC2 + +#define RK817_BUCK4_CONFIG_REG 0xC3 +#define RK817_BUCK4_ON_VSEL_REG 0xC4 +#define RK817_BUCK4_SLP_VSEL_REG 0xC5 + +#define RK817_LDO_ON_VSEL_REG(idx) (0xcc + (idx) * 2) +#define RK817_BOOST_OTG_CFG (0xde) + +#define RK817_ID_MSB 0xed +#define RK817_ID_LSB 0xee + +#define RK817_SYS_STS 0xf0 +#define RK817_SYS_CFG(i) (0xf1 + (i)) + +#define RK817_ON_SOURCE_REG 0xf5 +#define RK817_OFF_SOURCE_REG 0xf6 + +/* INTERRUPT REGISTER */ +#define RK817_INT_STS_REG0 0xf8 +#define RK817_INT_STS_MSK_REG0 0xf9 +#define RK817_INT_STS_REG1 0xfa +#define RK817_INT_STS_MSK_REG1 0xfb +#define RK817_INT_STS_REG2 0xfc +#define RK817_INT_STS_MSK_REG2 0xfd +#define RK817_GPIO_INT_CFG 0xfe + +/* IRQ Definitions */ +#define RK817_IRQ_PWRON_FALL 0 +#define RK817_IRQ_PWRON_RISE 1 +#define RK817_IRQ_PWRON 2 +#define RK817_IRQ_PWMON_LP 3 +#define RK817_IRQ_HOTDIE 4 +#define RK817_IRQ_RTC_ALARM 5 +#define RK817_IRQ_RTC_PERIOD 6 +#define RK817_IRQ_VB_LO 7 +#define RK817_IRQ_PLUG_IN (8 + 0) +#define RK817_IRQ_PLUG_OUT (8 + 1) +#define RK817_IRQ_CHRG_TERM (8 + 2) +#define RK817_IRQ_CHRG_TIME (8 + 3) +#define RK817_IRQ_CHRG_TS (8 + 4) +#define RK817_IRQ_USB_OV (8 + 5) +#define RK817_IRQ_CHRG_IN_CLMP (8 + 6) +#define RK817_IRQ_BAT_DIS_ILIM (8 + 7) +#define RK817_IRQ_GATE_GPIO (16 + 0) +#define RK817_IRQ_TS_GPIO (16 + 1) +#define RK817_IRQ_CODEC_PD (16 + 2) +#define RK817_IRQ_CODEC_PO (16 + 3) +#define RK817_IRQ_CLASSD_MUTE_DONE (16 + 4) +#define RK817_IRQ_CLASSD_OCP (16 + 5) +#define RK817_IRQ_BAT_OVP (16 + 6) +#define RK817_IRQ_CHRG_BAT_HI (16 + 7) +#define RK817_IRQ_END (RK817_IRQ_CHRG_BAT_HI + 1) + +/* + * rtc_ctrl 0xd + * same as 808, except bit4 + */ +#define RK817_RTC_CTRL_RSV4 BIT(4) + +/* power config 0xb9 */ +#define RK817_BUCK3_FB_RES_MSK BIT(6) +#define RK817_BUCK3_FB_RES_INTER BIT(6) +#define RK817_BUCK3_FB_RES_EXT 0 + +/* buck config 0xba */ +#define RK817_RAMP_RATE_OFFSET 6 +#define RK817_RAMP_RATE_MASK (0x3 << RK817_RAMP_RATE_OFFSET) +#define RK817_RAMP_RATE_3MV_PER_US (0x0 << RK817_RAMP_RATE_OFFSET) +#define RK817_RAMP_RATE_6_3MV_PER_US (0x1 << RK817_RAMP_RATE_OFFSET) +#define RK817_RAMP_RATE_12_5MV_PER_US (0x2 << RK817_RAMP_RATE_OFFSET) +#define RK817_RAMP_RATE_25MV_PER_US (0x3 << RK817_RAMP_RATE_OFFSET) + +/* sys_cfg1 0xf2 */ +#define RK817_HOTDIE_TEMP_MSK (0x3 << 4) +#define RK817_HOTDIE_85 (0x0 << 4) +#define RK817_HOTDIE_95 (0x1 << 4) +#define RK817_HOTDIE_105 (0x2 << 4) +#define RK817_HOTDIE_115 (0x3 << 4) + +#define RK817_TSD_TEMP_MSK BIT(6) +#define RK817_TSD_140 0 +#define RK817_TSD_160 BIT(6) + +#define RK817_CLK32KOUT2_EN BIT(7) + +/* sys_cfg3 0xf4 */ +#define RK817_SLPPIN_FUNC_MSK (0x3 << 3) +#define SLPPIN_NULL_FUN (0x0 << 3) +#define SLPPIN_SLP_FUN (0x1 << 3) +#define SLPPIN_DN_FUN (0x2 << 3) +#define SLPPIN_RST_FUN (0x3 << 3) + +#define RK817_RST_FUNC_MSK (0x3 << 6) +#define RK817_RST_FUNC_SFT (6) +#define RK817_RST_FUNC_CNT (3) +#define RK817_RST_FUNC_DEV (0) /* reset the dev */ +#define RK817_RST_FUNC_REG (0x1 << 6) /* reset the reg only */ + +#define RK817_SLPPOL_MSK BIT(5) +#define RK817_SLPPOL_H BIT(5) +#define RK817_SLPPOL_L (0) + +/* gpio&int 0xfe */ +#define RK817_INT_POL_MSK BIT(1) +#define RK817_INT_POL_H BIT(1) +#define RK817_INT_POL_L 0 +#define RK809_BUCK5_CONFIG(i) (RK817_BOOST_OTG_CFG + (i) * 1) enum { BUCK_ILMIN_50MA, @@ -191,9 +970,29 @@ enum { BOOST_ILMIN_250MA, }; +struct rk808_pin_info { + struct pinctrl *p; + struct pinctrl_state *reset; + struct pinctrl_state *power_off; + struct pinctrl_state *sleep; +}; + struct rk808 { struct i2c_client *i2c; struct regmap_irq_chip_data *irq_data; + struct regmap_irq_chip_data *battery_irq_data; struct regmap *regmap; + long variant; + struct rk808_pin_info *pins; }; + +enum { + RK805_ID = 0x8050, + RK808_ID = 0x0000, + RK809_ID = 0x8090, + RK816_ID = 0x8160, + RK817_ID = 0x8170, + RK818_ID = 0x8180, +}; + #endif /* __LINUX_REGULATOR_rk808_H */ diff --git a/include/linux/mma7660.h b/include/linux/mma7660.h new file mode 100644 index 000000000000..8f30ce6f3d3f --- /dev/null +++ b/include/linux/mma7660.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Definitions for mma7660 compass chip. + */ +#ifndef MMA7660_H +#define MMA7660_H + +#include <linux/ioctl.h> + + + + +/* Default register settings */ +#define RBUFF_SIZE 12 /* Rx buffer size */ + + +#define MMA7660_REG_X_OUT 0x0 +#define MMA7660_REG_Y_OUT 0x1 +#define MMA7660_REG_Z_OUT 0x2 +#define MMA7660_REG_TILT 0x3 +#define MMA7660_REG_SRST 0x4 +#define MMA7660_REG_SPCNT 0x5 +#define MMA7660_REG_INTSU 0x6 +#define MMA7660_REG_MODE 0x7 +#define MMA7660_REG_SR 0x8 +#define MMA7660_REG_PDET 0x9 +#define MMA7660_REG_PD 0xa + + +#define MMAIO 0xA1 + +/* IOCTLs for MMA7660 library */ +#define ECS_IOCTL_INIT _IO(MMAIO, 0x01) +#define ECS_IOCTL_RESET _IO(MMAIO, 0x04) +#define ECS_IOCTL_CLOSE _IO(MMAIO, 0x02) +#define ECS_IOCTL_START _IO(MMAIO, 0x03) +#define ECS_IOCTL_GETDATA _IOR(MMAIO, 0x08, char[RBUFF_SIZE+1]) + +/* IOCTLs for APPs */ +#define ECS_IOCTL_APP_SET_RATE _IOW(MMAIO, 0x10, char) + + +/*rate*/ +#define MMA7660_RATE_1 1 +#define MMA7660_RATE_2 2 +#define MMA7660_RATE_4 4 +#define MMA7660_RATE_8 8 +#define MMA7660_RATE_16 16 +#define MMA7660_RATE_32 32 +#define MMA7660_RATE_64 64 +#define MMA7660_RATE_120 128 + +/*status*/ +#define MMA7660_OPEN 1 +#define MMA7660_CLOSE 0 + + + +#define MMA7660_IIC_ADDR 0x98 +#define MMA7660_REG_LEN 11 +#define MMA7660_RANGE 2000000 +#define MMA7660_PRECISION 6 +#define MMA7660_BOUNDARY (0x1 << (MMA7660_PRECISION - 1)) +#define MMA7660_GRAVITY_STEP MMA7660_RANGE/MMA7660_BOUNDARY +#define MMA7660_TOTAL_TIME 10 + + + +struct mma7660_platform_data { + int reset; + int clk_on; + int intr; +}; + +struct mma7660_data { + char status; + char curr_tate; + struct input_dev *input_dev; + struct i2c_client *client; + struct work_struct work; + struct delayed_work delaywork; /*report second event*/ +}; + +struct mma7660_axis { + int x; + int y; + int z; +}; + +#define GSENSOR_DEV_PATH "/dev/mma7660_daemon" + + +#endif + diff --git a/include/linux/mma8452.h b/include/linux/mma8452.h new file mode 100644 index 000000000000..b97d2900d833 --- /dev/null +++ b/include/linux/mma8452.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Definitions for mma8452 compass chip. + */ +#ifndef MMA8452_H +#define MMA8452_H + +#include <linux/ioctl.h> + +/* Default register settings */ +#define RBUFF_SIZE 12 /* Rx buffer size */ + +#define MMA8452_REG_STATUS 0x0 //RO +#define MMA8452_REG_X_OUT_MSB 0x1 //RO +#define MMA8452_REG_X_OUT_LSB 0x2 //RO +#define MMA8452_REG_Y_OUT_MSB 0x3 //RO +#define MMA8452_REG_Y_OUT_LSB 0x4 //RO +#define MMA8452_REG_Z_OUT_MSB 0x5 //RO +#define MMA8452_REG_Z_OUT_LSB 0x6 //RO +#define MMA8452_REG_F_SETUP 0x9 //RW + +#define MMA8452_REG_SYSMOD 0xB //RO +#define MMA8452_REG_INTSRC 0xC //RO +#define MMA8452_REG_WHO_AM_I 0xD //RO +#define MMA8452_REG_XYZ_DATA_CFG 0xE //RW +#define MMA8452_REG_HP_FILTER_CUTOFF 0xF //RW +#define MMA8452_REG_PL_STATUS 0x10 //RO +#define MMA8452_REG_PL_CFG 0x11 //RW +#define MMA8452_REG_PL_COUNT 0x12 //RW +#define MMA8452_REG_PL_BF_ZCOMP 0x13 //RW +#define MMA8452_REG_P_L_THS_REG 0x14 //RW +#define MMA8452_REG_FF_MT_CFG 0x15 //RW +#define MMA8452_REG_FF_MT_SRC 0x16 //RO +#define MMA8452_REG_FF_MT_THS 0x17 //RW +#define MMA8452_REG_FF_MT_COUNT 0x18 //RW +#define MMA8452_REG_TRANSIENT_CFG 0x1D //RW +#define MMA8452_REG_TRANSIENT_SRC 0x1E //RO +#define MMA8452_REG_TRANSIENT_THS 0x1F //RW +#define MMA8452_REG_TRANSIENT_COUNT 0x20 //RW +#define MMA8452_REG_PULSE_CFG 0x21 //RW +#define MMA8452_REG_PULSE_SRC 0x22 //RO +#define MMA8452_REG_PULSE_THSX 0x23 //RW +#define MMA8452_REG_PULSE_THSY 0x24 //RW +#define MMA8452_REG_PULSE_THSZ 0x25 //RW +#define MMA8452_REG_PULSE_TMLT 0x26 //RW +#define MMA8452_REG_PULSE_LTCY 0x27 //RW +#define MMA8452_REG_PULSE_WIND 0x28 //RW +#define MMA8452_REG_ASLP_COUNT 0x29 //RW +#define MMA8452_REG_CTRL_REG1 0x2A //RW +#define MMA8452_REG_CTRL_REG2 0x2B //RW +#define MMA8452_REG_CTRL_REG3 0x2C //RW +#define MMA8452_REG_CTRL_REG4 0x2D //RW +#define MMA8452_REG_CTRL_REG5 0x2E //RW +#define MMA8452_REG_OFF_X 0x2F //RW +#define MMA8452_REG_OFF_Y 0x30 //RW +#define MMA8452_REG_OFF_Z 0x31 //RW + +#define MMAIO 0xA1 + +/* IOCTLs for MMA8452 library */ +#define MMA_IOCTL_INIT _IO(MMAIO, 0x01) +#define MMA_IOCTL_RESET _IO(MMAIO, 0x04) +#define MMA_IOCTL_CLOSE _IO(MMAIO, 0x02) +#define MMA_IOCTL_START _IO(MMAIO, 0x03) +#define MMA_IOCTL_GETDATA _IOR(MMAIO, 0x08, char[RBUFF_SIZE+1]) + +/* IOCTLs for APPs */ +#define MMA_IOCTL_APP_SET_RATE _IOW(MMAIO, 0x10, char) + + +/*rate*/ +#define MMA8452_RATE_800 0 +#define MMA8452_RATE_400 1 +#define MMA8452_RATE_200 2 +#define MMA8452_RATE_100 3 +#define MMA8452_RATE_50 4 +#define MMA8452_RATE_12P5 5 +#define MMA8452_RATE_6P25 6 +#define MMA8452_RATE_1P56 7 +#define MMA8452_RATE_SHIFT 3 + + +#define MMA8452_ASLP_RATE_50 0 +#define MMA8452_ASLP_RATE_12P5 1 +#define MMA8452_ASLP_RATE_6P25 2 +#define MMA8452_ASLP_RATE_1P56 3 +#define MMA8452_ASLP_RATE_SHIFT 6 + +/*Auto-adapt mma845x series*/ +/*Modified by Yick @ROCKCHIP + xieyi@rockchips.com*/ +/* + Range: unit(ug 1g=1 000 000 ug) + option(2g,4g,8g) + G would be defined on android HAL + Precision: bit wide of valid data + Boundary: Max positive count + Gravity_step: gravity value indicated by per count + */ +#define FREAD_MASK 0 /* enabled(1<<1) only if reading MSB 8bits*/ +#define MMA845X_RANGE 2000000 +/* mma8451 */ +#define MMA8451_PRECISION 14 +#define MMA8451_BOUNDARY (0x1 << (MMA8451_PRECISION - 1)) +#define MMA8451_GRAVITY_STEP MMA845X_RANGE / MMA8451_BOUNDARY + +/* mma8452 */ +#define MMA8452_PRECISION 12 +#define MMA8452_BOUNDARY (0x1 << (MMA8452_PRECISION - 1)) +#define MMA8452_GRAVITY_STEP MMA845X_RANGE / MMA8452_BOUNDARY + +/* mma8453 */ +#define MMA8453_PRECISION 10 +#define MMA8453_BOUNDARY (0x1 << (MMA8453_PRECISION - 1)) +#define MMA8453_GRAVITY_STEP MMA845X_RANGE / MMA8453_BOUNDARY + +/*End of precision adaption*/ + +#define MMA8452_TOTAL_TIME 10 + +#define ACTIVE_MASK 1 + +/*status*/ +#define MMA8452_SUSPEND 2 +#define MMA8452_OPEN 1 +#define MMA8452_CLOSE 0 + +#define MMA8452_REG_LEN 11 + +struct mma8452_axis { + int x; + int y; + int z; +}; + +#define GSENSOR_DEV_PATH "/dev/mma8452_daemon" + +#endif + diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h index 8f23fb2c5ed2..fca73a076ec0 100644 --- a/include/linux/mmc/card.h +++ b/include/linux/mmc/card.h @@ -95,6 +95,7 @@ struct mmc_ext_csd { u8 raw_partition_support; /* 160 */ u8 raw_rpmb_size_mult; /* 168 */ u8 raw_erased_mem_count; /* 181 */ + u8 strobe_support; /* 184 */ u8 raw_ext_csd_structure; /* 194 */ u8 raw_card_type; /* 196 */ u8 raw_driver_strength; /* 197 */ diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h index 7776afb0ffa5..0cf1b2a2161b 100644 --- a/include/linux/mmc/dw_mmc.h +++ b/include/linux/mmc/dw_mmc.h @@ -110,6 +110,7 @@ struct dw_mci_dma_slave { * @irq_flags: The flags to be passed to request_irq. * @irq: The irq value to be passed to request_irq. * @sdio_id0: Number of slot0 in the SDIO interrupt registers. + * @cto_timer: Timer for broken command transfer over scheme. * @dto_timer: Timer for broken data transfer over scheme. * * Locking @@ -220,7 +221,9 @@ struct dw_mci { int sdio_id0; struct timer_list cmd11_timer; + struct timer_list cto_timer; struct timer_list dto_timer; + struct timer_list xfer_timer; }; /* DMA ops for Internal/External DMAC interface */ @@ -245,6 +248,7 @@ struct dw_mci_dma_ops { #define DW_MCI_QUIRK_BROKEN_CARD_DETECTION BIT(3) /* Timer for broken data transfer over scheme */ #define DW_MCI_QUIRK_BROKEN_DTO BIT(4) +#define DW_MCI_QUIRK_BROKEN_XFER BIT(5) struct dma_pdata; diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 46e91d4fce7e..35e0a013e466 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -20,6 +20,7 @@ #include <linux/mmc/core.h> #include <linux/mmc/card.h> +#include <linux/mmc/mmc.h> #include <linux/mmc/pm.h> struct mmc_ios { @@ -78,6 +79,8 @@ struct mmc_ios { #define MMC_SET_DRIVER_TYPE_A 1 #define MMC_SET_DRIVER_TYPE_C 2 #define MMC_SET_DRIVER_TYPE_D 3 + + bool enhanced_strobe; /* hs400 enhanced strobe selection */ }; struct mmc_host_ops { @@ -127,12 +130,15 @@ struct mmc_host_ops { /* Check if the card is pulling dat[0:3] low */ int (*card_busy)(struct mmc_host *host); + int (*set_sdio_status)(struct mmc_host *host, int val); /* The tuning command opcode value is different for SD and eMMC cards */ int (*execute_tuning)(struct mmc_host *host, u32 opcode); /* Prepare HS400 target operating frequency depending host driver */ int (*prepare_hs400_tuning)(struct mmc_host *host, struct mmc_ios *ios); + /* Prepare enhanced strobe depending host driver */ + void (*hs400_enhanced_strobe)(struct mmc_host *host, struct mmc_ios *ios); int (*select_drive_strength)(struct mmc_card *card, unsigned int max_dtr, int host_drv, int card_drv, int *drv_type); @@ -290,9 +296,15 @@ struct mmc_host { #define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V) #define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17) #define MMC_CAP2_NO_WRITE_PROTECT (1 << 18) /* No physical write protect pin, assume that card is always read-write */ +#define MMC_CAP2_HS400_ES (1 << 20) /* Host supports enhanced strobe */ mmc_pm_flag_t pm_caps; /* supported pm features */ + u32 restrict_caps; /* Indicate slot specific card type */ +#define RESTRICT_CARD_TYPE_SD (1 << 0) /* Can support Secure-Digital Card */ +#define RESTRICT_CARD_TYPE_SDIO (1 << 1) /* Can support Secure-Digital I/O Card or Combo-Mem */ +#define RESTRICT_CARD_TYPE_EMMC (1 << 2) /* Can support embedded Multi-Media Card */ + /* host specific block data */ unsigned int max_seg_size; /* see blk_queue_max_segment_size */ unsigned short max_segs; /* see blk_queue_max_segments */ @@ -490,7 +502,12 @@ static inline int mmc_host_uhs(struct mmc_host *host) return host->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | - MMC_CAP_UHS_DDR50); + MMC_CAP_UHS_DDR50) && host->caps & MMC_CAP_4_BIT_DATA; +} + +static inline int mmc_host_hs400_enhanced_strobe(struct mmc_host *host) +{ + return host->caps2 & MMC_CAP2_HS400_ES; } static inline int mmc_host_packed_wr(struct mmc_host *host) @@ -525,6 +542,11 @@ static inline bool mmc_card_hs400(struct mmc_card *card) return card->host->ios.timing == MMC_TIMING_MMC_HS400; } +static inline bool mmc_card_hs400es(struct mmc_card *card) +{ + return card->host->ios.enhanced_strobe; +} + void mmc_retune_timer_stop(struct mmc_host *host); static inline void mmc_retune_needed(struct mmc_host *host) @@ -539,4 +561,7 @@ static inline void mmc_retune_recheck(struct mmc_host *host) host->retune_now = 1; } +void mmc_retune_enable(struct mmc_host *host); +void mmc_retune_disable(struct mmc_host *host); + #endif /* LINUX_MMC_HOST_H */ diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h index 2c6b1d45626e..a034d07c218d 100644 --- a/include/linux/mmc/mmc.h +++ b/include/linux/mmc/mmc.h @@ -297,6 +297,7 @@ struct _mmc_csd { #define EXT_CSD_PART_CONFIG 179 /* R/W */ #define EXT_CSD_ERASED_MEM_CONT 181 /* RO */ #define EXT_CSD_BUS_WIDTH 183 /* R/W */ +#define EXT_CSD_STROBE_SUPPORT 184 /* RO */ #define EXT_CSD_HS_TIMING 185 /* R/W */ #define EXT_CSD_POWER_CLASS 187 /* R/W */ #define EXT_CSD_REV 192 /* RO */ @@ -383,12 +384,14 @@ struct _mmc_csd { #define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.2V */ #define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \ EXT_CSD_CARD_TYPE_HS400_1_2V) +#define EXT_CSD_CARD_TYPE_HS400ES (1<<8) /* Card can run at HS400ES */ #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ +#define EXT_CSD_BUS_WIDTH_STROBE BIT(7) /* Enhanced strobe mode */ #define EXT_CSD_TIMING_BC 0 /* Backwards compatility */ #define EXT_CSD_TIMING_HS 1 /* High speed */ diff --git a/include/linux/mpu.h b/include/linux/mpu.h new file mode 100755 index 000000000000..f47496239366 --- /dev/null +++ b/include/linux/mpu.h @@ -0,0 +1,123 @@ +/* +* Copyright (C) 2012 Invensense, Inc. +* +* This software is licensed under the terms of the GNU General Public +* License version 2, as published by the Free Software Foundation, and +* may be copied, distributed, and modified under those terms. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef __MPU_H_ +#define __MPU_H_ + +#ifdef __KERNEL__ +#include <linux/types.h> +#include <linux/ioctl.h> +#endif + +enum secondary_slave_type { + SECONDARY_SLAVE_TYPE_NONE, + SECONDARY_SLAVE_TYPE_ACCEL, + SECONDARY_SLAVE_TYPE_COMPASS, + SECONDARY_SLAVE_TYPE_PRESSURE, + SECONDARY_SLAVE_TYPE_ALS, + + SECONDARY_SLAVE_TYPE_TYPES +}; + +enum ext_slave_id { + ID_INVALID = 0, + GYRO_ID_MPU3050, + GYRO_ID_MPU6050A2, + GYRO_ID_MPU6050B1, + GYRO_ID_MPU6050B1_NO_ACCEL, + GYRO_ID_ITG3500, + + ACCEL_ID_LIS331, + ACCEL_ID_LSM303DLX, + ACCEL_ID_LIS3DH, + ACCEL_ID_KXSD9, + ACCEL_ID_KXTF9, + ACCEL_ID_BMA150, + ACCEL_ID_BMA222, + ACCEL_ID_BMA250, + ACCEL_ID_ADXL34X, + ACCEL_ID_MMA8450, + ACCEL_ID_MMA845X, + ACCEL_ID_MPU6050, + + COMPASS_ID_AK8963, + COMPASS_ID_AK8975, + COMPASS_ID_AK8972, + COMPASS_ID_AMI30X, + COMPASS_ID_AMI306, + COMPASS_ID_YAS529, + COMPASS_ID_YAS530, + COMPASS_ID_HMC5883, + COMPASS_ID_LSM303DLH, + COMPASS_ID_LSM303DLM, + COMPASS_ID_MMC314X, + COMPASS_ID_HSCDTD002B, + COMPASS_ID_HSCDTD004A, + COMPASS_ID_MLX90399, + COMPASS_ID_AK09911, + COMPASS_ID_AK09912, + COMPASS_ID_ST480M, + + PRESSURE_ID_BMP085, + PRESSURE_ID_BMP280, + + ALS_ID_APDS_9900, + ALS_ID_APDS_9930, +}; + +#define INV_PROD_KEY(ver, rev) (ver * 100 + rev) +/** + * struct mpu_platform_data - Platform data for the mpu driver + * @int_config: Bits [7:3] of the int config register. + * @level_shifter: 0: VLogic, 1: VDD + * @orientation: Orientation matrix of the gyroscope + * @sec_slave_type: secondary slave device type, can be compass, accel, etc + * @sec_slave_id: id of the secondary slave device + * @secondary_i2c_address: secondary device's i2c address + * @secondary_orientation: secondary device's orientation matrix + * @aux_slave_type: auxiliary slave. Another slave device type + * @aux_slave_id: auxiliary slave ID. + * @aux_i2c_addr: auxiliary device I2C address. + * @read_only_slave_type: read only slave type. + * @read_only_slave_id: read only slave device ID. + * @read_only_i2c_addr: read only slave device address. + * + * Contains platform specific information on how to configure the MPU3050 to + * work on this platform. The orientation matricies are 3x3 rotation matricies + * that are applied to the data to rotate from the mounting orientation to the + * platform orientation. The values must be one of 0, 1, or -1 and each row and + * column should have exactly 1 non-zero value. + */ +struct mpu_platform_data { + __u8 int_config; + __u8 level_shifter; + __s8 orientation[9]; + enum secondary_slave_type sec_slave_type; + enum ext_slave_id sec_slave_id; + __u16 secondary_i2c_addr; + __s8 secondary_orientation[9]; + enum secondary_slave_type aux_slave_type; + enum ext_slave_id aux_slave_id; + __u16 aux_i2c_addr; + enum secondary_slave_type read_only_slave_type; + enum ext_slave_id read_only_slave_id; + __u16 read_only_i2c_addr; +#ifdef CONFIG_DTS_INV_MPU_IIO + int (*power_on)(struct mpu_platform_data *); + int (*power_off)(struct mpu_platform_data *); + struct regulator *vdd_ana; + struct regulator *vdd_i2c; +#endif +}; + +#endif /* __MPU_H_ */ diff --git a/include/linux/mpu6500.h b/include/linux/mpu6500.h new file mode 100644 index 000000000000..2b45884a724b --- /dev/null +++ b/include/linux/mpu6500.h @@ -0,0 +1,239 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Definitions for mma8452 compass chip. + */ +#ifndef __MPU6500_H +#define __MPU6500_H + +#include <linux/ioctl.h> +/**add***/ +#define MPU6500_PRECISION 16 +#define MPU6500_RANGE 2000000 + +#define MPU6500_SMPLRT_DIV 0x19 +#define MPU6500_CONFIG 0x1A +#define MPU6500_GYRO_CONFIG 0x1B +#define MPU6500_ACCEL_CONFIG 0x1C +#define MPU6500_ACCEL_CONFIG2 0x1D +#define MPU6500_LP_ACCEL_ODR 0x1E +#define MPU6500_WOM_THRESH 0x1F +#define MPU6500_FIFO_EN 0x23 +#define MPU6500_INT_PIN_CFG 0x37 +#define MPU6500_INT_ENABLE 0x38 +#define MPU6500_DMP_INT_STATUS 0x39 +#define MPU6500_INT_STATUS 0x3A +#define MPU6500_ACCEL_XOUT_H 0x3B +#define MPU6500_TEMP_OUT_H 0x41 +#define MPU6500_GYRO_XOUT_H 0x43 +#define MPU6500_ACCEL_INTEL_CTRL 0x69 +#define MPU6500_USER_CTRL 0x6A +#define MPU6500_PWR_MGMT_1 0x6B +#define MPU6500_PWR_MGMT_2 0x6C +#define MPU6500_PRGM_STRT_ADDRH 0x70 +#define MPU6500_FIFO_COUNTH 0x72 +#define MPU6500_FIFO_R_W 0x74 +#define MPU6500_WHOAMI 0x75 + +#define MPU6500_DEVICE_ID 0x70 +/*------------------------------ + MPU6500_CONFIG +--------------------------------*/ +#define DLPF_CFG_250HZ 0x00 +#define DLPF_CFG_184HZ 0x01 +#define DLPF_CFG_98HZ 0x02 +#define DLPF_CFG_41HZ 0x03 +#define DLPF_CFG_20HZ 0x04 +#define DLPF_CFG_10HZ 0x05 +#define DLPF_CFG_5HZ 0x06 +#define DLPF_CFG_3600HZ 0x07 +#define EXT_SYNC_SET_TEMP 0x08 +#define EXT_SYNC_SET_GYRO_X 0x10 +#define EXT_SYNC_SET_GYRO_Y 0x18 +#define EXT_SYNC_SET_GYRO_Z 0x20 +#define EXT_SYNC_SET_ACCEL_X 0x28 +#define EXT_SYNC_SET_ACCEL_Y 0x30 +#define EXT_SYNC_SET_ACCEL_Z 0x38 + + +/*------------------------------ + MPU6500_GYRO_CONFIG +--------------------------------*/ +#define GFSR_250DPS (0 <<3) +#define GFSR_500DPS (1 <<3) +#define GFSR_1000DPS (2 <<3) +#define GFSR_2000DPS (3 <<3) + +/*------------------------------ + MPU6500_ACCEL_CONFIG +--------------------------------*/ +#define AFSR_2G (0 <<3) +#define AFSR_4G (1 <<3) +#define AFSR_8G (2 <<3) +#define AFSR_16G (3 <<3) + + +/*------------------------------ + MPU6500_ACCEL_CONFIG2 +--------------------------------*/ +#define A_DLPF_CFG_460HZ 0x00 +#define A_DLPF_CFG_184HZ 0x01 +#define A_DLPF_CFG_92HZ 0x02 +#define A_DLPF_CFG_41HZ 0x03 +#define A_DLPF_CFG_20HZ 0x04 +#define A_DLPF_CFG_10HZ 0x05 +#define A_DLPF_CFG_5HZ 0x06 +//#define A_DLPF_CFG_460HZ 0x07 +#define BIT_FIFO_SIZE_1K 0x40 +#define BIT_ACCEL_FCHOICE_B 0x08 + + +/*------------------------------ + MPU6500_LP_ACCEL_ODR +--------------------------------*/ +#define LPA_CLK_P24HZ 0x0 +#define LPA_CLK_P49HZ 0x1 +#define LPA_CLK_P98HZ 0x2 +#define LPA_CLK_1P95HZ 0x3 +#define LPA_CLK_3P91HZ 0x4 +#define LPA_CLK_7P81HZ 0x5 +#define LPA_CLK_15P63HZ 0x6 +#define LPA_CLK_31P25HZ 0x7 +#define LPA_CLK_62P50HZ 0x8 +#define LPA_CLK_125HZ 0x9 +#define LPA_CLK_250HZ 0xa +#define LPA_CLK_500HZ 0xb + + +/*------------------------------ + MPU6500_PWR_MGMT_1 +--------------------------------*/ +#define BIT_H_RESET (1<<7) +#define BIT_SLEEP (1<<6) +#define BIT_CYCLE (1<<5) +#define BIT_GYRO_STANDBY (1<<4) +#define BIT_PD_PTAT (1<<3) +#define BIT_CLKSEL (1<<0) + +#define CLKSEL_INTERNAL 0 +#define CLKSEL_PLL 1 + +/*------------------------------ + MPU6500_PWR_MGMT_2 +--------------------------------*/ +#define BIT_ACCEL_STBY 0x38 +#define BIT_GYRO_STBY 0x07 +#define BITS_LPA_WAKE_CTRL 0xC0 +#define BITS_LPA_WAKE_1HZ 0x00 +#define BITS_LPA_WAKE_2HZ 0x40 +#define BITS_LPA_WAKE_20HZ 0x80 + +#define MPU6500_PWRM1_SLEEP 0x40 +#define MPU6500_PWRM1_GYRO_STANDBY 0x10 +#define MPU6500_PWRM2_ACCEL_DISABLE 0x38 +#define MPU6500_PWRM2_GYRO_DISABLE 0x07 + +/*------------------------------ + MPU6500_ACCEL_INTEL_CTRL +--------------------------------*/ +#define BIT_ACCEL_INTEL_EN 0x80 +#define BIT_ACCEL_INTEL_MODE 0x40 + + +/*------------------------------ + MPU6500_USER_CTRL +--------------------------------*/ +#define BIT_FIFO_RST 0x04 +#define BIT_DMP_RST 0x08 +#define BIT_I2C_MST_EN 0x20 +#define BIT_FIFO_EN 0x40 +#define BIT_DMP_EN 0x80 + + +/*------------------------------ + MPU6500_FIFO_EN +--------------------------------*/ +#define BIT_ACCEL_OUT 0x08 +#define BITS_GYRO_OUT 0x70 + + +/*------------------------------ + MPU6500_INT_PIN_CFG +--------------------------------*/ +#define BIT_BYPASS_EN 0x2 + +/*------------------------------ + MPU6500_INT_EN/INT_STATUS +--------------------------------*/ +#define BIT_FIFO_OVERLOW 0x80 +#define BIT_MOT_INT 0x40 +#define BIT_MPU_RDY 0x04 +#define BIT_DMP_INT 0x02 +#define BIT_RAW_RDY 0x01 + + +#define DMP_START_ADDR 0x400 + + + +#define AXIS_NUM 3 +#define AXIS_ADC_BYTE 2 +#define SENSOR_PACKET (AXIS_NUM * AXIS_ADC_BYTE) + + + + + +/* + self-test parameter +*/ + +#define DEF_ST_PRECISION 1000 +#define DEF_ST_MPU6500_ACCEL_LPF 2 +#define DEF_STABLE_TIME_ST 50 +#define DEF_SELFTEST_GYRO_FS (0 << 3) +#define DEF_SELFTEST_ACCEL_FS (2 << 3) +#define DEF_SELFTEST_6500_ACCEL_FS (0 << 3) +#define DEF_SW_SELFTEST_GYRO_FS GFSR_2000DPS +#define DEF_SW_SELFTEST_SENSITIVITY \ + (2000*DEF_ST_PRECISION)/32768 + +#define DEF_SW_SELFTEST_SAMPLE_COUNT 75 +#define DEF_SW_SELFTEST_SAMPLE_TIME 75 +#define DEF_SW_ACCEL_CAL_SAMPLE_TIME 50 +#define DEF_SW_SKIP_COUNT 10 + +#define DEF_ST_6500_STABLE_TIME 20 +#define BYTES_PER_SENSOR (6) +#define DEF_SELFTEST_SAMPLE_RATE 0 +#define DEF_GYRO_WAIT_TIME 50 +#define THREE_AXIS (3) +#define INIT_ST_SAMPLES 200 +#define FIFO_COUNT_BYTE (2) +#define DEF_ST_TRY_TIMES 2 +#define REG_6500_XG_ST_DATA 0x0 +#define REG_6500_XA_ST_DATA 0xD +#define BITS_SELF_TEST_EN 0xE0 + +#define DEF_ST_SCALE (1L << 15) + +/*---- MPU6500 Self Test Pass/Fail Criteria ----*/ +/* Gyro Offset Max Value (dps) */ +#define DEF_GYRO_OFFSET_MAX 20 +/* Gyro Self Test Absolute Limits ST_AL (dps) */ +#define DEF_GYRO_ST_AL 60 +/* Accel Self Test Absolute Limits ST_AL (mg) */ +#define DEF_ACCEL_ST_AL_MIN 225 +#define DEF_ACCEL_ST_AL_MAX 675 +#define DEF_6500_ACCEL_ST_SHIFT_DELTA 500 +#define DEF_6500_GYRO_CT_SHIFT_DELTA 500 +#define DEF_ST_MPU6500_ACCEL_LPF 2 +#define DEF_ST_6500_ACCEL_FS_MG 2000UL +#define DEF_SELFTEST_6500_ACCEL_FS (0 << 3) + +#define DEF_SELFTEST_GYRO_SENS (32768 / 250) + + +#define GSENSOR_DEV_PATH "/dev/mma8452_daemon" + +#endif + diff --git a/include/linux/mpu6880.h b/include/linux/mpu6880.h new file mode 100644 index 000000000000..a0cb445c531e --- /dev/null +++ b/include/linux/mpu6880.h @@ -0,0 +1,239 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Definitions for mma8452 compass chip. + */ +#ifndef __MPU6880_H +#define __MPU6880_H + +#include <linux/ioctl.h> +/**add***/ +#define MPU6880_PRECISION 16 +#define MPU6880_RANGE 2000000 + +#define MPU6880_SMPLRT_DIV 0x19 +#define MPU6880_CONFIG 0x1A +#define MPU6880_GYRO_CONFIG 0x1B +#define MPU6880_ACCEL_CONFIG 0x1C +#define MPU6880_ACCEL_CONFIG2 0x1D +#define MPU6880_LP_ACCEL_ODR 0x1E +#define MPU6880_WOM_THRESH 0x1F +#define MPU6880_FIFO_EN 0x23 +#define MPU6880_INT_PIN_CFG 0x37 +#define MPU6880_INT_ENABLE 0x38 +#define MPU6880_DMP_INT_STATUS 0x39 +#define MPU6880_INT_STATUS 0x3A +#define MPU6880_ACCEL_XOUT_H 0x3B +#define MPU6880_TEMP_OUT_H 0x41 +#define MPU6880_GYRO_XOUT_H 0x43 +#define MPU6880_ACCEL_INTEL_CTRL 0x69 +#define MPU6880_USER_CTRL 0x6A +#define MPU6880_PWR_MGMT_1 0x6B +#define MPU6880_PWR_MGMT_2 0x6C +#define MPU6880_PRGM_STRT_ADDRH 0x70 +#define MPU6880_FIFO_COUNTH 0x72 +#define MPU6880_FIFO_R_W 0x74 +#define MPU6880_WHOAMI 0x75 + +#define MPU6880_DEVICE_ID 0x78 +/*------------------------------ + MPU6880_CONFIG +--------------------------------*/ +#define DLPF_CFG_250HZ 0x00 +#define DLPF_CFG_184HZ 0x01 +#define DLPF_CFG_98HZ 0x02 +#define DLPF_CFG_41HZ 0x03 +#define DLPF_CFG_20HZ 0x04 +#define DLPF_CFG_10HZ 0x05 +#define DLPF_CFG_5HZ 0x06 +#define DLPF_CFG_3600HZ 0x07 +#define EXT_SYNC_SET_TEMP 0x08 +#define EXT_SYNC_SET_GYRO_X 0x10 +#define EXT_SYNC_SET_GYRO_Y 0x18 +#define EXT_SYNC_SET_GYRO_Z 0x20 +#define EXT_SYNC_SET_ACCEL_X 0x28 +#define EXT_SYNC_SET_ACCEL_Y 0x30 +#define EXT_SYNC_SET_ACCEL_Z 0x38 + + +/*------------------------------ + MPU6880_GYRO_CONFIG +--------------------------------*/ +#define GFSR_250DPS (0 <<3) +#define GFSR_500DPS (1 <<3) +#define GFSR_1000DPS (2 <<3) +#define GFSR_2000DPS (3 <<3) + +/*------------------------------ + MPU6880_ACCEL_CONFIG +--------------------------------*/ +#define AFSR_2G (0 <<3) +#define AFSR_4G (1 <<3) +#define AFSR_8G (2 <<3) +#define AFSR_16G (3 <<3) + + +/*------------------------------ + MPU6880_ACCEL_CONFIG2 +--------------------------------*/ +#define A_DLPF_CFG_460HZ 0x00 +#define A_DLPF_CFG_184HZ 0x01 +#define A_DLPF_CFG_92HZ 0x02 +#define A_DLPF_CFG_41HZ 0x03 +#define A_DLPF_CFG_20HZ 0x04 +#define A_DLPF_CFG_10HZ 0x05 +#define A_DLPF_CFG_5HZ 0x06 +//#define A_DLPF_CFG_460HZ 0x07 +#define BIT_FIFO_SIZE_1K 0x40 +#define BIT_ACCEL_FCHOICE_B 0x08 + + +/*------------------------------ + MPU6880_LP_ACCEL_ODR +--------------------------------*/ +#define LPA_CLK_P24HZ 0x0 +#define LPA_CLK_P49HZ 0x1 +#define LPA_CLK_P98HZ 0x2 +#define LPA_CLK_1P95HZ 0x3 +#define LPA_CLK_3P91HZ 0x4 +#define LPA_CLK_7P81HZ 0x5 +#define LPA_CLK_15P63HZ 0x6 +#define LPA_CLK_31P25HZ 0x7 +#define LPA_CLK_62P50HZ 0x8 +#define LPA_CLK_125HZ 0x9 +#define LPA_CLK_250HZ 0xa +#define LPA_CLK_500HZ 0xb + + +/*------------------------------ + MPU6880_PWR_MGMT_1 +--------------------------------*/ +#define BIT_H_RESET (1<<7) +#define BIT_SLEEP (1<<6) +#define BIT_CYCLE (1<<5) +#define BIT_GYRO_STANDBY (1<<4) +#define BIT_PD_PTAT (1<<3) +#define BIT_CLKSEL (1<<0) + +#define CLKSEL_INTERNAL 0 +#define CLKSEL_PLL 1 + +/*------------------------------ + MPU6880_PWR_MGMT_2 +--------------------------------*/ +#define BIT_ACCEL_STBY 0x38 +#define BIT_GYRO_STBY 0x07 +#define BITS_LPA_WAKE_CTRL 0xC0 +#define BITS_LPA_WAKE_1HZ 0x00 +#define BITS_LPA_WAKE_2HZ 0x40 +#define BITS_LPA_WAKE_20HZ 0x80 + +#define MPU6880_PWRM1_SLEEP 0x40 +#define MPU6880_PWRM1_GYRO_STANDBY 0x10 +#define MPU6880_PWRM2_ACCEL_DISABLE 0x38 +#define MPU6880_PWRM2_GYRO_DISABLE 0x07 + +/*------------------------------ + MPU6880_ACCEL_INTEL_CTRL +--------------------------------*/ +#define BIT_ACCEL_INTEL_EN 0x80 +#define BIT_ACCEL_INTEL_MODE 0x40 + + +/*------------------------------ + MPU6880_USER_CTRL +--------------------------------*/ +#define BIT_FIFO_RST 0x04 +#define BIT_DMP_RST 0x08 +#define BIT_I2C_MST_EN 0x20 +#define BIT_FIFO_EN 0x40 +#define BIT_DMP_EN 0x80 + + +/*------------------------------ + MPU6880_FIFO_EN +--------------------------------*/ +#define BIT_ACCEL_OUT 0x08 +#define BITS_GYRO_OUT 0x70 + + +/*------------------------------ + MPU6880_INT_PIN_CFG +--------------------------------*/ +#define BIT_BYPASS_EN 0x2 + +/*------------------------------ + MPU6880_INT_EN/INT_STATUS +--------------------------------*/ +#define BIT_FIFO_OVERLOW 0x80 +#define BIT_MOT_INT 0x40 +#define BIT_MPU_RDY 0x04 +#define BIT_DMP_INT 0x02 +#define BIT_RAW_RDY 0x01 + + +#define DMP_START_ADDR 0x400 + + + +#define AXIS_NUM 3 +#define AXIS_ADC_BYTE 2 +#define SENSOR_PACKET (AXIS_NUM * AXIS_ADC_BYTE) + + + + + +/* + self-test parameter +*/ + +#define DEF_ST_PRECISION 1000 +#define DEF_ST_MPU6500_ACCEL_LPF 2 +#define DEF_STABLE_TIME_ST 50 +#define DEF_SELFTEST_GYRO_FS (0 << 3) +#define DEF_SELFTEST_ACCEL_FS (2 << 3) +#define DEF_SELFTEST_6500_ACCEL_FS (0 << 3) +#define DEF_SW_SELFTEST_GYRO_FS GFSR_2000DPS +#define DEF_SW_SELFTEST_SENSITIVITY \ + (2000*DEF_ST_PRECISION)/32768 + +#define DEF_SW_SELFTEST_SAMPLE_COUNT 75 +#define DEF_SW_SELFTEST_SAMPLE_TIME 75 +#define DEF_SW_ACCEL_CAL_SAMPLE_TIME 50 +#define DEF_SW_SKIP_COUNT 10 + +#define DEF_ST_6500_STABLE_TIME 20 +#define BYTES_PER_SENSOR (6) +#define DEF_SELFTEST_SAMPLE_RATE 0 +#define DEF_GYRO_WAIT_TIME 50 +#define THREE_AXIS (3) +#define INIT_ST_SAMPLES 200 +#define FIFO_COUNT_BYTE (2) +#define DEF_ST_TRY_TIMES 2 +#define REG_6500_XG_ST_DATA 0x0 +#define REG_6500_XA_ST_DATA 0xD +#define BITS_SELF_TEST_EN 0xE0 + +#define DEF_ST_SCALE (1L << 15) + +/*---- MPU6500 Self Test Pass/Fail Criteria ----*/ +/* Gyro Offset Max Value (dps) */ +#define DEF_GYRO_OFFSET_MAX 20 +/* Gyro Self Test Absolute Limits ST_AL (dps) */ +#define DEF_GYRO_ST_AL 60 +/* Accel Self Test Absolute Limits ST_AL (mg) */ +#define DEF_ACCEL_ST_AL_MIN 225 +#define DEF_ACCEL_ST_AL_MAX 675 +#define DEF_6500_ACCEL_ST_SHIFT_DELTA 500 +#define DEF_6500_GYRO_CT_SHIFT_DELTA 500 +#define DEF_ST_MPU6500_ACCEL_LPF 2 +#define DEF_ST_6500_ACCEL_FS_MG 2000UL +#define DEF_SELFTEST_6500_ACCEL_FS (0 << 3) + +#define DEF_SELFTEST_GYRO_SENS (32768 / 250) + + +#define GSENSOR_DEV_PATH "/dev/mma8452_daemon" + +#endif + diff --git a/include/linux/nvmem-provider.h b/include/linux/nvmem-provider.h index 0b68caff1b3c..cd93416d762e 100644 --- a/include/linux/nvmem-provider.h +++ b/include/linux/nvmem-provider.h @@ -14,6 +14,10 @@ struct nvmem_device; struct nvmem_cell_info; +typedef int (*nvmem_reg_read_t)(void *priv, unsigned int offset, + void *val, size_t bytes); +typedef int (*nvmem_reg_write_t)(void *priv, unsigned int offset, + void *val, size_t bytes); struct nvmem_config { struct device *dev; @@ -23,6 +27,16 @@ struct nvmem_config { const struct nvmem_cell_info *cells; int ncells; bool read_only; + bool root_only; + nvmem_reg_read_t reg_read; + nvmem_reg_write_t reg_write; + int size; + int word_size; + int stride; + void *priv; + /* To be only used by old driver/misc/eeprom drivers */ + bool compat; + struct device *base_dev; }; #if IS_ENABLED(CONFIG_NVMEM) @@ -43,5 +57,4 @@ static inline int nvmem_unregister(struct nvmem_device *nvmem) } #endif /* CONFIG_NVMEM */ - #endif /* ifndef _LINUX_NVMEM_PROVIDER_H */ diff --git a/include/linux/of.h b/include/linux/of.h index d9371c9cd88a..197e09b0bc8e 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -83,10 +83,12 @@ struct of_reconfig_data { /* initialize a node */ extern struct kobj_type of_node_ktype; +extern const struct fwnode_operations of_fwnode_ops; static inline void of_node_init(struct device_node *node) { kobject_init(&node->kobj, &of_node_ktype); node->fwnode.type = FWNODE_OF; + node->fwnode.ops = &of_fwnode_ops; } /* true when node is initialized */ @@ -133,7 +135,7 @@ void of_core_init(void); static inline bool is_of_node(struct fwnode_handle *fwnode) { - return fwnode && fwnode->type == FWNODE_OF; + return !IS_ERR_OR_NULL(fwnode) && fwnode->type == FWNODE_OF; } static inline struct device_node *to_of_node(struct fwnode_handle *fwnode) @@ -142,6 +144,14 @@ static inline struct device_node *to_of_node(struct fwnode_handle *fwnode) container_of(fwnode, struct device_node, fwnode) : NULL; } +#define of_fwnode_handle(node) \ + ({ \ + typeof(node) __of_fwnode_handle_node = (node); \ + \ + __of_fwnode_handle_node ? \ + &__of_fwnode_handle_node->fwnode : NULL; \ + }) + static inline bool of_have_populated_dt(void) { return of_root != NULL; @@ -221,13 +231,6 @@ static inline unsigned long of_read_ulong(const __be32 *cell, int size) #define OF_ROOT_NODE_SIZE_CELLS_DEFAULT 1 #endif -/* Default string compare functions, Allow arch asm/prom.h to override */ -#if !defined(of_compat_cmp) -#define of_compat_cmp(s1, s2, l) strcasecmp((s1), (s2)) -#define of_prop_cmp(s1, s2) strcmp((s1), (s2)) -#define of_node_cmp(s1, s2) strcasecmp((s1), (s2)) -#endif - #define OF_IS_DYNAMIC(x) test_bit(OF_DYNAMIC, &x->_flags) #define OF_MARK_DYNAMIC(x) set_bit(OF_DYNAMIC, &x->_flags) @@ -283,20 +286,24 @@ extern int of_property_count_elems_of_size(const struct device_node *np, extern int of_property_read_u32_index(const struct device_node *np, const char *propname, u32 index, u32 *out_value); -extern int of_property_read_u8_array(const struct device_node *np, - const char *propname, u8 *out_values, size_t sz); -extern int of_property_read_u16_array(const struct device_node *np, - const char *propname, u16 *out_values, size_t sz); -extern int of_property_read_u32_array(const struct device_node *np, - const char *propname, - u32 *out_values, - size_t sz); +extern int of_property_read_variable_u8_array(const struct device_node *np, + const char *propname, u8 *out_values, + size_t sz_min, size_t sz_max); +extern int of_property_read_variable_u16_array(const struct device_node *np, + const char *propname, u16 *out_values, + size_t sz_min, size_t sz_max); +extern int of_property_read_variable_u32_array(const struct device_node *np, + const char *propname, + u32 *out_values, + size_t sz_min, + size_t sz_max); extern int of_property_read_u64(const struct device_node *np, const char *propname, u64 *out_value); -extern int of_property_read_u64_array(const struct device_node *np, - const char *propname, - u64 *out_values, - size_t sz); +extern int of_property_read_variable_u64_array(const struct device_node *np, + const char *propname, + u64 *out_values, + size_t sz_min, + size_t sz_max); extern int of_property_read_string(struct device_node *np, const char *propname, @@ -358,6 +365,122 @@ extern int of_detach_node(struct device_node *); #define of_match_ptr(_ptr) (_ptr) +/** + * of_property_read_u8_array - Find and read an array of u8 from a property. + * + * @np: device node from which the property value is to be read. + * @propname: name of the property to be searched. + * @out_values: pointer to return value, modified only if return value is 0. + * @sz: number of array elements to read + * + * Search for a property in a device node and read 8-bit value(s) from + * it. Returns 0 on success, -EINVAL if the property does not exist, + * -ENODATA if property does not have a value, and -EOVERFLOW if the + * property data isn't large enough. + * + * dts entry of array should be like: + * property = /bits/ 8 <0x50 0x60 0x70>; + * + * The out_values is modified only if a valid u8 value can be decoded. + */ +static inline int of_property_read_u8_array(const struct device_node *np, + const char *propname, + u8 *out_values, size_t sz) +{ + int ret = of_property_read_variable_u8_array(np, propname, out_values, + sz, 0); + if (ret >= 0) + return 0; + else + return ret; +} + +/** + * of_property_read_u16_array - Find and read an array of u16 from a property. + * + * @np: device node from which the property value is to be read. + * @propname: name of the property to be searched. + * @out_values: pointer to return value, modified only if return value is 0. + * @sz: number of array elements to read + * + * Search for a property in a device node and read 16-bit value(s) from + * it. Returns 0 on success, -EINVAL if the property does not exist, + * -ENODATA if property does not have a value, and -EOVERFLOW if the + * property data isn't large enough. + * + * dts entry of array should be like: + * property = /bits/ 16 <0x5000 0x6000 0x7000>; + * + * The out_values is modified only if a valid u16 value can be decoded. + */ +static inline int of_property_read_u16_array(const struct device_node *np, + const char *propname, + u16 *out_values, size_t sz) +{ + int ret = of_property_read_variable_u16_array(np, propname, out_values, + sz, 0); + if (ret >= 0) + return 0; + else + return ret; +} + +/** + * of_property_read_u32_array - Find and read an array of 32 bit integers + * from a property. + * + * @np: device node from which the property value is to be read. + * @propname: name of the property to be searched. + * @out_values: pointer to return value, modified only if return value is 0. + * @sz: number of array elements to read + * + * Search for a property in a device node and read 32-bit value(s) from + * it. Returns 0 on success, -EINVAL if the property does not exist, + * -ENODATA if property does not have a value, and -EOVERFLOW if the + * property data isn't large enough. + * + * The out_values is modified only if a valid u32 value can be decoded. + */ +static inline int of_property_read_u32_array(const struct device_node *np, + const char *propname, + u32 *out_values, size_t sz) +{ + int ret = of_property_read_variable_u32_array(np, propname, out_values, + sz, 0); + if (ret >= 0) + return 0; + else + return ret; +} + +/** + * of_property_read_u64_array - Find and read an array of 64 bit integers + * from a property. + * + * @np: device node from which the property value is to be read. + * @propname: name of the property to be searched. + * @out_values: pointer to return value, modified only if return value is 0. + * @sz: number of array elements to read + * + * Search for a property in a device node and read 64-bit value(s) from + * it. Returns 0 on success, -EINVAL if the property does not exist, + * -ENODATA if property does not have a value, and -EOVERFLOW if the + * property data isn't large enough. + * + * The out_values is modified only if a valid u64 value can be decoded. + */ +static inline int of_property_read_u64_array(const struct device_node *np, + const char *propname, + u64 *out_values, size_t sz) +{ + int ret = of_property_read_variable_u64_array(np, propname, out_values, + sz, 0); + if (ret >= 0) + return 0; + else + return ret; +} + /* * struct property *prop; * const __be32 *p; @@ -459,6 +582,8 @@ static inline struct device_node *of_find_node_with_property( return NULL; } +#define of_fwnode_handle(node) NULL + static inline bool of_have_populated_dt(void) { return false; @@ -684,6 +809,13 @@ static inline void of_property_clear_flag(struct property *p, unsigned long flag #define of_match_node(_matches, _node) NULL #endif /* CONFIG_OF */ +/* Default string compare functions, Allow arch asm/prom.h to override */ +#if !defined(of_compat_cmp) +#define of_compat_cmp(s1, s2, l) strcasecmp((s1), (s2)) +#define of_prop_cmp(s1, s2) strcmp((s1), (s2)) +#define of_node_cmp(s1, s2) strcasecmp((s1), (s2)) +#endif + #if defined(CONFIG_OF) && defined(CONFIG_NUMA) extern int of_node_to_nid(struct device_node *np); #else diff --git a/include/linux/of_graph.h b/include/linux/of_graph.h index f8bcd0e21a26..6f2f6bcd4c55 100644 --- a/include/linux/of_graph.h +++ b/include/linux/of_graph.h @@ -50,6 +50,8 @@ struct device_node *of_graph_get_endpoint_by_regs( struct device_node *of_graph_get_remote_port_parent( const struct device_node *node); struct device_node *of_graph_get_remote_port(const struct device_node *node); +struct device_node *of_graph_get_remote_node(const struct device_node *node, + u32 port, u32 endpoint); #else static inline int of_graph_parse_endpoint(const struct device_node *node, @@ -88,6 +90,12 @@ static inline struct device_node *of_graph_get_remote_port( { return NULL; } +static inline struct device_node *of_graph_get_remote_node( + const struct device_node *node, + u32 port, u32 endpoint) +{ + return NULL; +} #endif /* CONFIG_OF */ diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h index 2c51ee78b1c0..7a6fd1c2e074 100644 --- a/include/linux/of_pci.h +++ b/include/linux/of_pci.h @@ -16,6 +16,7 @@ int of_pci_get_devfn(struct device_node *np); int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin); int of_pci_parse_bus_range(struct device_node *node, struct resource *res); int of_get_pci_domain_nr(struct device_node *node); +int of_pci_get_max_link_speed(struct device_node *node); void of_pci_check_probe_only(void); #else static inline int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args *out_irq) @@ -52,6 +53,12 @@ of_get_pci_domain_nr(struct device_node *node) return -1; } +static inline int +of_pci_get_max_link_speed(struct device_node *node) +{ + return -EINVAL; +} + static inline void of_pci_check_probe_only(void) { } #endif diff --git a/include/linux/pci.h b/include/linux/pci.h index 5f37614f2451..f6c1d9719338 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1132,9 +1132,12 @@ void pci_add_resource(struct list_head *resources, struct resource *res); void pci_add_resource_offset(struct list_head *resources, struct resource *res, resource_size_t offset); void pci_free_resource_list(struct list_head *resources); -void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags); +void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, + unsigned int flags); struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); void pci_bus_remove_resources(struct pci_bus *bus); +int devm_request_pci_bus_resources(struct device *dev, + struct list_head *resources); #define pci_bus_for_each_resource(bus, res, i) \ for (i = 0; \ @@ -1153,6 +1156,7 @@ int __must_check pci_bus_alloc_resource(struct pci_bus *bus, int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); +void pci_unmap_iospace(struct resource *res); static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) { diff --git a/include/linux/phy.h b/include/linux/phy.h index dbfd5ce9350f..b0cef11769f3 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -623,14 +623,12 @@ static inline int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum) * phy_read_mmd_indirect - reads data from the MMD registers * @phydev: The PHY device bus * @prtad: MMD Address - * @devad: MMD DEVAD * @addr: PHY address on the MII bus * * Description: it reads data from the MMD registers (clause 22 to access to * clause 45) of the specified phy address. */ -int phy_read_mmd_indirect(struct phy_device *phydev, int prtad, - int devad, int addr); +int phy_read_mmd_indirect(struct phy_device *phydev, int prtad, int devad); /** * phy_read - Convenience function for reading a given PHY register @@ -740,14 +738,13 @@ static inline int phy_write_mmd(struct phy_device *phydev, int devad, * @phydev: The PHY device * @prtad: MMD Address * @devad: MMD DEVAD - * @addr: PHY address on the MII bus * @data: data to write in the MMD register * * Description: Write data from the MMD registers of the specified * phy address. */ void phy_write_mmd_indirect(struct phy_device *phydev, int prtad, - int devad, int addr, u32 data); + int devad, u32 data); struct phy_device *phy_device_create(struct mii_bus *bus, int addr, int phy_id, bool is_c45, @@ -782,6 +779,12 @@ static inline int phy_read_status(struct phy_device *phydev) return phydev->drv->read_status(phydev); } +#define phydev_err(_phydev, format, args...) \ + dev_err(&_phydev->dev, format, ##args) + +#define phydev_dbg(_phydev, format, args...) \ + dev_dbg(&_phydev->dev, format, ##args) + int genphy_config_init(struct phy_device *phydev); int genphy_setup_forced(struct phy_device *phydev); int genphy_restart_aneg(struct phy_device *phydev); diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index 8cf05e341cff..43b2da6f4be2 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -22,12 +22,24 @@ struct phy; +enum phy_mode { + PHY_MODE_INVALID, + PHY_MODE_PCIE_EP, + PHY_MODE_PCIE_RC, + PHY_MODE_USB_HOST, + PHY_MODE_USB_DEVICE, + PHY_MODE_USB_OTG, +}; + /** * struct phy_ops - set of function pointers for performing phy operations * @init: operation to be performed for initializing phy * @exit: operation to be performed while exiting * @power_on: powering on the phy * @power_off: powering off the phy + * @set_mode: set the mode of the phy + * @reset: resetting the phy + * @cp_test: prepare for the phy compliance test * @owner: the module owner containing the ops */ struct phy_ops { @@ -35,6 +47,9 @@ struct phy_ops { int (*exit)(struct phy *phy); int (*power_on)(struct phy *phy); int (*power_off)(struct phy *phy); + int (*set_mode)(struct phy *phy, enum phy_mode mode); + int (*reset)(struct phy *phy); + int (*cp_test)(struct phy *phy); struct module *owner; }; @@ -119,6 +134,9 @@ int phy_init(struct phy *phy); int phy_exit(struct phy *phy); int phy_power_on(struct phy *phy); int phy_power_off(struct phy *phy); +int phy_set_mode(struct phy *phy, enum phy_mode mode); +int phy_reset(struct phy *phy); +int phy_cp_test(struct phy *phy); static inline int phy_get_bus_width(struct phy *phy) { return phy->attrs.bus_width; @@ -224,6 +242,27 @@ static inline int phy_power_off(struct phy *phy) return -ENOSYS; } +static inline int phy_set_mode(struct phy *phy, enum phy_mode mode) +{ + if (!phy) + return 0; + return -ENOSYS; +} + +static inline int phy_reset(struct phy *phy) +{ + if (!phy) + return 0; + return -ENOSYS; +} + +static inline int phy_cp_test(struct phy *phy) +{ + if (!phy) + return 0; + return -ENOSYS; +} + static inline int phy_get_bus_width(struct phy *phy) { return -ENOSYS; diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h index 9ba59fcba549..a42e57da270d 100644 --- a/include/linux/pinctrl/pinctrl.h +++ b/include/linux/pinctrl/pinctrl.h @@ -144,6 +144,12 @@ struct pinctrl_desc { extern struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc, struct device *dev, void *driver_data); extern void pinctrl_unregister(struct pinctrl_dev *pctldev); +extern struct pinctrl_dev *devm_pinctrl_register(struct device *dev, + struct pinctrl_desc *pctldesc, + void *driver_data); +extern void devm_pinctrl_unregister(struct device *dev, + struct pinctrl_dev *pctldev); + extern bool pin_is_valid(struct pinctrl_dev *pctldev, int pin); extern void pinctrl_add_gpio_range(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range); diff --git a/include/linux/platform_data/rk_isp10_platform.h b/include/linux/platform_data/rk_isp10_platform.h new file mode 100644 index 000000000000..858d9959aadd --- /dev/null +++ b/include/linux/platform_data/rk_isp10_platform.h @@ -0,0 +1,196 @@ +/* + ************************************************************************* + * Rockchip driver for CIF ISP 1.0 + * (Based on Intel driver for sofiaxxx) + * + * Copyright (C) 2015 Intel Mobile Communications GmbH + * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + ************************************************************************* + */ +#ifndef _CIF_ISP10_PLATFORM_H +#define _CIF_ISP10_PLATFORM_H +#include <linux/videodev2.h> + +#define CIF_ISP10_SOC_RK3288 "rk3288" +#define CIF_ISP10_SOC_RK3368 "rk3368" +#define CIF_ISP10_SOC_RK3399 "rk3399" + +#define DRIVER_NAME "rkisp10" +#define ISP_VDEV_NAME DRIVER_NAME "_ispdev" +#define SP_VDEV_NAME DRIVER_NAME "_selfpath" +#define MP_VDEV_NAME DRIVER_NAME "_mainpath" +#define DMA_VDEV_NAME DRIVER_NAME "_dmapath" + +enum pltfrm_cam_signal_polarity { + PLTFRM_CAM_SIGNAL_HIGH_LEVEL = 0, + PLTFRM_CAM_SIGNAL_LOW_LEVEL = 1, +}; + +enum pltfrm_cam_sample_type { + PLTFRM_CAM_SDR_NEG_EDG = 0x10000001, + PLTFRM_CAM_SDR_POS_EDG = 0x10000002, + PLTFRM_CAM_DDR = 0x20000000 +}; + +enum pltfrm_cam_itf_type { + PLTFRM_CAM_ITF_MIPI = 0x10000000, + PLTFRM_CAM_ITF_BT601_8 = 0x20000071, + PLTFRM_CAM_ITF_BT656_8 = 0x20000072, + PLTFRM_CAM_ITF_BT601_10 = 0x20000091, + PLTFRM_CAM_ITF_BT656_10 = 0x20000092, + PLTFRM_CAM_ITF_BT601_12 = 0x200000B1, + PLTFRM_CAM_ITF_BT656_12 = 0x200000B2, + PLTFRM_CAM_ITF_BT601_16 = 0x200000F1, + PLTFRM_CAM_ITF_BT656_16 = 0x200000F2, + PLTFRM_CAM_ITF_BT656_8I = 0x20000172 +}; + +#define PLTFRM_CAM_ITF_MAIN_MASK 0xf0000000 +#define PLTFRM_CAM_ITF_SUB_MASK 0x0000000f +#define PLTFRM_CAM_ITF_DVP_BW_MASK 0x000000f0 +#define PLTFRM_CAM_ITF_INTERLACE_MASK 0x00000100 + +#define PLTFRM_CAM_ITF_IS_MIPI(a) \ + (((a) & PLTFRM_CAM_ITF_MAIN_MASK) == 0x10000000) +#define PLTFRM_CAM_ITF_IS_DVP(a) \ + (((a) & PLTFRM_CAM_ITF_MAIN_MASK) == 0x20000000) +#define PLTFRM_CAM_ITF_IS_BT656(a) (PLTFRM_CAM_ITF_IS_DVP(a) &&\ + (((a) & PLTFRM_CAM_ITF_SUB_MASK) == 0x02)) +#define PLTFRM_CAM_ITF_IS_BT601(a) (PLTFRM_CAM_ITF_IS_DVP(a) &&\ + (((a) & PLTFRM_CAM_ITF_SUB_MASK) == 0x01)) +#define PLTFRM_CAM_ITF_DVP_BW(a) \ + ((((a) & PLTFRM_CAM_ITF_DVP_BW_MASK) >> 4) + 1) +#define PLTFRM_CAM_ITF_INTERLACE(a) \ + (((a) & PLTFRM_CAM_ITF_INTERLACE_MASK) == 0x00000100) + +struct pltfrm_cam_mipi_config { + u32 dphy_index; + u32 vc; + u32 nb_lanes; + u32 bit_rate; +}; + +struct pltfrm_cam_dvp_config { + enum pltfrm_cam_signal_polarity vsync; + enum pltfrm_cam_signal_polarity hsync; + enum pltfrm_cam_sample_type pclk; +}; + +struct pltfrm_cam_itf { + enum pltfrm_cam_itf_type type; + + union { + struct pltfrm_cam_mipi_config mipi; + struct pltfrm_cam_dvp_config dvp; + } cfg; + unsigned int mclk_hz; +}; + +#define PLTFRM_CAM_ITF_MIPI_CFG(v, nb, br, mk)\ + .itf_cfg = {\ + .type = PLTFRM_CAM_ITF_MIPI,\ + .cfg = {\ + .mipi = {\ + .dphy_index = 0,\ + .vc = v,\ + .nb_lanes = nb,\ + .bit_rate = br,\ + } \ + },\ + .mclk_hz = mk\ + } +#define PLTFRM_CAM_ITF_DVP_CFG(ty, vs, hs, ck, mk)\ + .itf_cfg = {\ + .type = ty,\ + .cfg = {\ + .dvp = {\ + .vsync = vs,\ + .hsync = hs,\ + .pclk = ck,\ + } \ + },\ + .mclk_hz = mk\ + } + +#define PLTFRM_CIFCAM_IOCTL_INTERNAL_BASE 0x00 +#define PLTFRM_CIFCAM_G_ITF_CFG \ + (PLTFRM_CIFCAM_IOCTL_INTERNAL_BASE + 1) +#define PLTFRM_CIFCAM_G_DEFRECT \ + (PLTFRM_CIFCAM_IOCTL_INTERNAL_BASE + 2) +#define PLTFRM_CIFCAM_ATTACH \ + (PLTFRM_CIFCAM_IOCTL_INTERNAL_BASE + 3) +#define PLTFRM_CIFCAM_SET_VCM_POS \ + (PLTFRM_CIFCAM_IOCTL_INTERNAL_BASE + 4) +#define PLTFRM_CIFCAM_GET_VCM_POS \ + (PLTFRM_CIFCAM_IOCTL_INTERNAL_BASE + 5) +#define PLTFRM_CIFCAM_GET_VCM_MOVE_RES \ + (PLTFRM_CIFCAM_IOCTL_INTERNAL_BASE + 6) + +struct pltfrm_cam_vcm_tim { + struct timeval vcm_start_t; + struct timeval vcm_end_t; +}; + +struct pltfrm_cam_defrect { + unsigned int width; + unsigned int height; + struct v4l2_rect defrect; +}; + +enum pltfrm_soc_cfg_cmd { + PLTFRM_MCLK_CFG = 0, + PLTFRM_MIPI_DPHY_CFG, + + PLTFRM_CLKEN, + PLTFRM_CLKDIS, + PLTFRM_CLKRST, + + PLTFRM_SOC_INIT +}; + +enum pltfrm_soc_io_voltage { + PLTFRM_IO_1V8 = 0, + PLTFRM_IO_3V3 = 1 +}; + +enum pltfrm_soc_drv_strength { + PLTFRM_DRV_STRENGTH_0 = 0, + PLTFRM_DRV_STRENGTH_1 = 1, + PLTFRM_DRV_STRENGTH_2 = 2, + PLTFRM_DRV_STRENGTH_3 = 3 + +}; + +struct pltfrm_soc_init_para { + struct platform_device *pdev; + void __iomem *isp_base; +}; + +struct pltfrm_soc_mclk_para { + enum pltfrm_soc_io_voltage io_voltage; + enum pltfrm_soc_drv_strength drv_strength; +}; + +struct pltfrm_soc_cfg_para { + enum pltfrm_soc_cfg_cmd cmd; + void **isp_config; + void *cfg_para; +}; + +struct pltfrm_soc_cfg { + char name[32]; + void *isp_config; + int (*soc_cfg)(struct pltfrm_soc_cfg_para *cfg); +}; + +int pltfrm_rk3288_cfg(struct pltfrm_soc_cfg_para *cfg); +int pltfrm_rk3399_cfg(struct pltfrm_soc_cfg_para *cfg); + + +#endif diff --git a/include/linux/platform_data/rk_isp10_platform_camera_module.h b/include/linux/platform_data/rk_isp10_platform_camera_module.h new file mode 100644 index 000000000000..41c6c03dd488 --- /dev/null +++ b/include/linux/platform_data/rk_isp10_platform_camera_module.h @@ -0,0 +1,169 @@ +/* + ************************************************************************* + * Rockchip driver for CIF ISP 1.0 + * (Based on Intel driver for sofiaxxx) + * + * Copyright (C) 2015 Intel Mobile Communications GmbH + * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + ************************************************************************* + */ + +#ifndef PLATFORM_CAMERA_MODULE_H +#define PLATFORM_CAMERA_MODULE_H +#include <linux/videodev2.h> + +#define PLTFRM_CAMERA_MODULE_REG_CODE_MASK 0xff +#define PLTFRM_CAMERA_MODULE_REG_LEN_BIT 8 +#define PLTFRM_CAMERA_MODULE_REG_LEN_MASK (0x03 << PLTFRM_CAMERA_MODULE_REG_LEN_BIT) +#define PLTFRM_CAMERA_MODULE_REG_LEN(flag) \ + (((flag & PLTFRM_CAMERA_MODULE_REG_LEN_MASK) >> PLTFRM_CAMERA_MODULE_REG_LEN_BIT) + 1) + +#define PLTFRM_CAMERA_MODULE_DATA_LEN_BIT 10 +#define PLTFRM_CAMERA_MODULE_DATA_LEN_MASK (0x03 << PLTFRM_CAMERA_MODULE_DATA_LEN_BIT) +#define PLTFRM_CAMERA_MODULE_DATA_LEN(flag) \ + (((flag & PLTFRM_CAMERA_MODULE_DATA_LEN_MASK) >> PLTFRM_CAMERA_MODULE_DATA_LEN_BIT) + 1) + +#define PLTFRM_CAMERA_MODULE_WR_CONTINUE_MASK 0x1000 +#define PLTFRM_CAMERA_MODULE_WR_CONTINUE 0x0000 +#define PLTFRM_CAMERA_MODULE_WR_SINGLE 0x1000 + +#define PLTFRM_CAMERA_MODULE_RD_CONTINUE_MASK 0x2000 +#define PLTFRM_CAMERA_MODULE_RD_CONTINUE 0x2000 +#define PLTFRM_CAMERA_MODULE_RD_SINGLE 0x0000 + +#define PLTFRM_CAMERA_MODULE_REG1_TYPE_DATA1 0x000 +#define PLTFRM_CAMERA_MODULE_REG2_TYPE_DATA1 0x100 +#define PLTFRM_CAMERA_MODULE_REG1_TYPE_DATA2 0x400 +#define PLTFRM_CAMERA_MODULE_REG2_TYPE_DATA2 0x500 + +#define PLTFRM_CAMERA_MODULE_REG_TYPE_DATA PLTFRM_CAMERA_MODULE_REG2_TYPE_DATA1 +#define PLTFRM_CAMERA_MODULE_REG_TYPE_TIMEOUT 0x01 +#define PLTFRM_CAMERA_MODULE_REG_TYPE_DATA_SINGLE 0x1100 + +#define PLTFRM_CAMERA_MODULE_MIRROR_BIT 0 +#define PLTFRM_CAMERA_MODULE_FLIP_BIT 1 +#define PLTFRM_CAMERA_MODULE_IS_MIRROR(a) \ + ((a & PLTFRM_CAMERA_MODULE_MIRROR_BIT) == PLTFRM_CAMERA_MODULE_MIRROR_BIT) +#define PLTFRM_CAMERA_MODULE_IS_FLIP(a) \ + ((a & PLTFRM_CAMERA_MODULE_FLIP_BIT) == PLTFRM_CAMERA_MODULE_FLIP_BIT) + +extern const char *PLTFRM_CAMERA_MODULE_PIN_PD; +extern const char *PLTFRM_CAMERA_MODULE_PIN_PWR; +extern const char *PLTFRM_CAMERA_MODULE_PIN_FLASH; +extern const char *PLTFRM_CAMERA_MODULE_PIN_TORCH; +extern const char *PLTFRM_CAMERA_MODULE_PIN_RESET; +extern const char *PLTFRM_CAMERA_MODULE_PIN_VSYNC; + +enum pltfrm_camera_module_pin_state { + PLTFRM_CAMERA_MODULE_PIN_STATE_INACTIVE = 0, + PLTFRM_CAMERA_MODULE_PIN_STATE_ACTIVE = 1 +}; + +struct pltfrm_camera_module_reg { + u32 flag; + u16 reg; + u16 val; +}; + +struct pltfrm_camera_module_reg_table { + u32 reg_table_num_entries; + struct pltfrm_camera_module_reg *reg_table; +}; + +int pltfrm_camera_module_set_pm_state( + struct v4l2_subdev *sd, + int on); + +int pltfrm_camera_module_set_pin_state( + struct v4l2_subdev *sd, + const char *pin, + enum pltfrm_camera_module_pin_state state); + +int pltfrm_camera_module_get_pin_state( + struct v4l2_subdev *sd, + const char *pin); + +int pltfrm_camera_module_s_power( + struct v4l2_subdev *sd, + int on); + +int pltfrm_camera_module_patch_config( + struct v4l2_subdev *sd, + struct v4l2_mbus_framefmt *frm_fmt, + struct v4l2_subdev_frame_interval *frm_intrvl); + +struct v4l2_subdev *pltfrm_camera_module_get_af_ctrl( + struct v4l2_subdev *sd); + +struct v4l2_subdev *pltfrm_camera_module_get_fl_ctrl( + struct v4l2_subdev *sd); + +char *pltfrm_camera_module_get_flash_driver_name( + struct v4l2_subdev *sd); + +int pltfrm_camera_module_init( + struct v4l2_subdev *sd, + void **pldata); + +void pltfrm_camera_module_release( + struct v4l2_subdev *sd); + +int pltfrm_camera_module_read_reg(struct v4l2_subdev *sd, + u16 data_length, + u16 reg, + u32 *val); + +int pltfrm_superpix_camera_module_read_reg(struct v4l2_subdev *sd, + u16 data_length, + u8 reg, + u8 *val); + +int pltfrm_camera_module_write_reg(struct v4l2_subdev *sd, + u16 reg, u8 val); + +int pltfrm_camera_module_read_reg_ex(struct v4l2_subdev *sd, + u16 data_length, + u32 flag, + u16 reg, + u32 *val); + +int pltfrm_camera_module_write_reg_ex(struct v4l2_subdev *sd, + u32 flag, u16 reg, u16 val); + +int pltfrm_camera_module_write_reglist( + struct v4l2_subdev *sd, + const struct pltfrm_camera_module_reg reglist[], + int len); + +long pltfrm_camera_module_ioctl(struct v4l2_subdev *sd, + unsigned int cmd, + void *arg); + +const char *pltfrm_dev_string(struct v4l2_subdev *sd); + +int pltfrm_camera_module_get_flip_mirror( + struct v4l2_subdev *sd); + +int pltfrm_camera_module_pix_fmt2csi2_dt(int src_pix_fmt); + +#define pltfrm_camera_module_pr_debug(dev, fmt, arg...) \ + pr_debug("%s.%s: " fmt, \ + pltfrm_dev_string(dev), __func__, ## arg) +#define pltfrm_camera_module_pr_info(dev, fmt, arg...) \ + pr_info("%s.%s: " fmt, \ + pltfrm_dev_string(dev), __func__, ## arg) +#define pltfrm_camera_module_pr_warn(dev, fmt, arg...) \ + pr_warn("%s.%s WARN: " fmt, \ + pltfrm_dev_string(dev), __func__, ## arg) +#define pltfrm_camera_module_pr_err(dev, fmt, arg...) \ + pr_err("%s.%s(%d) ERR: " fmt, \ + pltfrm_dev_string(dev), __func__, __LINE__, \ + ## arg) + +#endif diff --git a/include/linux/platform_data/spi-rockchip.h b/include/linux/platform_data/spi-rockchip.h new file mode 100755 index 000000000000..4b588739b5b6 --- /dev/null +++ b/include/linux/platform_data/spi-rockchip.h @@ -0,0 +1,79 @@ +/* include/linux/platform_data/spi-rockchip.h + * + * Copyright (C) 2014 Rockchip Electronics Ltd. + * luowei <lw@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ROCKCHIP_PLAT_SPI_H +#define __ROCKCHIP_PLAT_SPI_H + +#include <linux/dmaengine.h> + +struct platform_device; + +/** + * struct rockchip_spi_csinfo - ChipSelect description + * @fb_delay: Slave specific feedback delay. + * Refer to FB_CLK_SEL register definition in SPI chapter. + * @line: Custom 'identity' of the CS line. + * + * This is per SPI-Slave Chipselect information. + * Allocate and initialize one in machine init code and make the + * spi_board_info.controller_data point to it. + */ +struct rockchip_spi_csinfo { + u8 fb_delay; + unsigned line; +}; + +/** + * struct rockchip_spi_info - SPI Controller defining structure + * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field. + * @num_cs: Number of CS this controller emulates. + * @cfg_gpio: Configure pins for this SPI controller. + */ +struct rockchip_spi_info { + int src_clk_nr; + int spi_freq; + int num_cs; + int bus_num; + int (*cfg_gpio)(void); + dma_filter_fn filter; + + u8 transfer_mode;/*full or half duplex*/ + u8 poll_mode; /* 0 for contoller polling mode */ + u8 type; /* SPI/SSP/Micrwire */ + u8 enable_dma; + u8 slave_enable; +}; + +/** + * rockchip_spi_set_platdata - SPI Controller configure callback by the board + * initialization code. + * @cfg_gpio: Pointer to gpio setup function. + * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks. + * @num_cs: Number of elements in the 'cs' array. + * + * Call this from machine init code for each SPI Controller that + * has some chips attached to it. + */ +extern void rockchip_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, + int num_cs); +extern void rockchip_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, + int num_cs); +extern void rockchip_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, + int num_cs); + +/* defined by architecture to configure gpio */ +extern int rockchip_spi0_cfg_gpio(void); +extern int rockchip_spi1_cfg_gpio(void); +extern int rockchip_spi2_cfg_gpio(void); + +extern struct rockchip_spi_info rockchip_spi0_pdata; +extern struct rockchip_spi_info rockchip_spi1_pdata; +extern struct rockchip_spi_info rockchip_spi2_pdata; +#endif /* __ROCKCHIP_PLAT_SPI_H */ diff --git a/include/linux/platform_data/sram.h b/include/linux/platform_data/sram.h new file mode 100644 index 000000000000..38db9ae07308 --- /dev/null +++ b/include/linux/platform_data/sram.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _LINUX_SRAM_H +#define _LINUX_SRAM_H + +struct sram_platform_data { + bool map_exec; +}; + +#endif diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h index cccaf4a29e9f..33f5e8d95786 100644 --- a/include/linux/pm_opp.h +++ b/include/linux/pm_opp.h @@ -22,6 +22,7 @@ struct device; enum dev_pm_opp_event { OPP_EVENT_ADD, OPP_EVENT_REMOVE, OPP_EVENT_ENABLE, OPP_EVENT_DISABLE, + OPP_EVENT_ADJUST_VOLTAGE, }; #if defined(CONFIG_PM_OPP) @@ -65,6 +66,7 @@ void dev_pm_opp_put_prop_name(struct device *dev); int dev_pm_opp_set_regulator(struct device *dev, const char *name); void dev_pm_opp_put_regulator(struct device *dev); int dev_pm_opp_set_rate(struct device *dev, unsigned long target_freq); +int dev_pm_opp_check_rate_volt(struct device *dev, bool force); #else static inline unsigned long dev_pm_opp_get_voltage(struct dev_pm_opp *opp) { @@ -178,6 +180,11 @@ static inline int dev_pm_opp_set_rate(struct device *dev, unsigned long target_f return -EINVAL; } +static inline int dev_pm_opp_check_rate_volt(struct device *dev, bool force) +{ + return -EINVAL; +} + #endif /* CONFIG_PM_OPP */ #if defined(CONFIG_PM_OPP) && defined(CONFIG_OF) diff --git a/include/linux/power/bq25700-charge.h b/include/linux/power/bq25700-charge.h new file mode 100644 index 000000000000..5e7d3e40d2ea --- /dev/null +++ b/include/linux/power/bq25700-charge.h @@ -0,0 +1,20 @@ +/* + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __CHARGER_BQ25700_H_ +#define __CHARGER_BQ25700_H_ + +#define CHARGER_CURRENT_EVENT 0x01 +#define INPUT_CURRENT_EVENT 0x02 + +void bq25700_charger_set_current(unsigned long event, int current_value); + +#endif /* __CHARGER_BQ25700_H_ */ diff --git a/include/linux/power/cw2015_battery.h b/include/linux/power/cw2015_battery.h new file mode 100644 index 000000000000..938dda818e72 --- /dev/null +++ b/include/linux/power/cw2015_battery.h @@ -0,0 +1,118 @@ +/* + * Fuel gauge driver for CellWise 2013 / 2015 + * + * Copyright (C) 2012, RockChip + * + * Authors: xuhuicong <xhc@rock-chips.com> + * + * Based on rk30_adc_battery.c + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef CW2015_BATTERY_H +#define CW2015_BATTERY_H + +#define SIZE_BATINFO 64 + +#define CW2015_GPIO_HIGH 1 +#define CW2015_GPIO_LOW 0 + +#define REG_VERSION 0x0 +#define REG_VCELL 0x2 +#define REG_SOC 0x4 +#define REG_RRT_ALERT 0x6 +#define REG_CONFIG 0x8 +#define REG_MODE 0xA +#define REG_BATINFO 0x10 + +#define MODE_SLEEP_MASK (0x3<<6) +#define MODE_SLEEP (0x3<<6) +#define MODE_NORMAL (0x0<<6) +#define MODE_QUICK_START (0x3<<4) +#define MODE_RESTART (0xf<<0) + +#define CONFIG_UPDATE_FLG (0x1<<1) +#define ATHD (0x0<<3) + +#define CW_I2C_SPEED 100000 +#define BATTERY_UP_MAX_CHANGE (420 * 1000) +#define BATTERY_DOWN_MAX_CHANGE (120 * 1000) +#define BATTERY_DOWN_CHANGE 60 +#define BATTERY_DOWN_MIN_CHANGE_RUN 30 +#define BATTERY_DOWN_MIN_CHANGE_SLEEP 1800 +#define BATTERY_JUMP_TO_ZERO (30 * 1000) +#define BATTERY_CAPACITY_ERROR (40 * 1000) +#define BATTERY_CHARGING_ZERO (1800 * 1000) + +#define DOUBLE_SERIES_BATTERY 0 + +#define CHARGING_ON 1 +#define NO_CHARGING 0 + +#define BATTERY_DOWN_MAX_CHANGE_RUN_AC_ONLINE 3600 + +#define NO_STANDARD_AC_BIG_CHARGE_MODE 1 +/* #define SYSTEM_SHUTDOWN_VOLTAGE 3400000 */ +#define BAT_LOW_INTERRUPT 1 + +#define USB_CHARGER_MODE 1 +#define AC_CHARGER_MODE 2 +#define CW_QUICKSTART 0 + +#define TIMER_MS_COUNTS 1000 +#define DEFAULT_MONITOR_SEC 8 + +/* virtual params */ +#define VIRTUAL_CURRENT 1000 +#define VIRTUAL_VOLTAGE 3888 +#define VIRTUAL_SOC 66 +#define VIRTUAL_PRESET 1 +#define VIRTUAL_TEMPERATURE 188 +#define VIRTUAL_TIME2EMPTY 60 +#define VIRTUAL_STATUS POWER_SUPPLY_STATUS_CHARGING + +enum bat_mode { + MODE_BATTARY = 0, + MODE_VIRTUAL, +}; + +struct cw_bat_platform_data { + int divider_res1; + int divider_res2; + u32 *cw_bat_config_info; +}; + +struct cw_battery { + struct i2c_client *client; + struct workqueue_struct *battery_workqueue; + struct delayed_work battery_delay_work; + struct cw_bat_platform_data plat_data; + + struct power_supply *rk_bat; + + struct power_supply *chrg_usb_psy; + struct power_supply *chrg_ac_psy; + +#ifdef CONFIG_PM + struct timespec suspend_time_before; + struct timespec after; + int suspend_resume_mark; +#endif + int charger_mode; + int capacity; + int voltage; + int status; + int time_to_empty; + int alt; + u32 monitor_sec; + u32 bat_mode; + int bat_change; + bool dual_battery; + int charge_count; +}; + +#endif diff --git a/include/linux/power/rk_usbbc.h b/include/linux/power/rk_usbbc.h new file mode 100644 index 000000000000..45f7128b3a69 --- /dev/null +++ b/include/linux/power/rk_usbbc.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __RK_USBBC_H +#define __RK_USBBC_H + +/* USB Charger Types */ +enum bc_port_type{ + USB_BC_TYPE_DISCNT = 0, + USB_BC_TYPE_SDP, + USB_BC_TYPE_DCP, + USB_BC_TYPE_CDP, + USB_BC_TYPE_UNKNOW, + USB_OTG_POWER_ON, + USB_OTG_POWER_OFF, + USB_BC_TYPE_MAX, +}; + +/*********************************** + * USB Port Type + * 0 : Disconnect + * 1 : SDP - pc + * 2 : DCP - charger + * 3 : CDP - pc with big currect charge + ************************************/ +#ifdef CONFIG_DWC_OTG_310 +extern int dwc_otg_check_dpdm(bool wait); +extern int rk_bc_detect_notifier_register(struct notifier_block *nb, + enum bc_port_type *type); +extern int rk_bc_detect_notifier_unregister(struct notifier_block *nb); +#else +static inline int dwc_otg_check_dpdm(bool wait) { return USB_BC_TYPE_DISCNT; } + +static inline int rk_bc_detect_notifier_register(struct notifier_block *nb, + enum bc_port_type *type) +{ + return -EINVAL; +} + +static inline int rk_bc_detect_notifier_unregister(struct notifier_block *nb) +{ + return -EINVAL; +} +#endif + +#endif diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h index 1c075892c6fd..3241026e49f6 100644 --- a/include/linux/power_supply.h +++ b/include/linux/power_supply.h @@ -170,6 +170,7 @@ enum power_supply_type { POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */ POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */ POWER_SUPPLY_TYPE_USB_ACA, /* Accessory Charger Adapters */ + POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */ }; enum power_supply_notifier_events { @@ -253,6 +254,7 @@ struct power_supply { struct delayed_work deferred_register_work; spinlock_t changed_lock; bool changed; + bool initialized; atomic_t use_cnt; #ifdef CONFIG_THERMAL struct thermal_zone_device *tzd; diff --git a/include/linux/property.h b/include/linux/property.h index 0a3705a7c9f2..935ce0a6df15 100644 --- a/include/linux/property.h +++ b/include/linux/property.h @@ -49,6 +49,9 @@ int device_property_read_string(struct device *dev, const char *propname, int device_property_match_string(struct device *dev, const char *propname, const char *string); +struct fwnode_handle *dev_fwnode(struct device *dev); + +bool fwnode_device_is_available(struct fwnode_handle *fwnode); bool fwnode_property_present(struct fwnode_handle *fwnode, const char *propname); int fwnode_property_read_u8_array(struct fwnode_handle *fwnode, const char *propname, u8 *val, @@ -69,14 +72,33 @@ int fwnode_property_read_string(struct fwnode_handle *fwnode, const char *propname, const char **val); int fwnode_property_match_string(struct fwnode_handle *fwnode, const char *propname, const char *string); +int fwnode_property_get_reference_args(struct fwnode_handle *fwnode, + const char *prop, const char *nargs_prop, + unsigned int nargs, unsigned int index, + struct fwnode_reference_args *args); + +struct fwnode_handle *fwnode_get_parent(struct fwnode_handle *fwnode); +struct fwnode_handle *fwnode_get_next_parent(struct fwnode_handle *fwnode); +struct fwnode_handle *fwnode_get_next_child_node(struct fwnode_handle *fwnode, + struct fwnode_handle *child); + +#define fwnode_for_each_child_node(fwnode, child) \ + for (child = fwnode_get_next_child_node(fwnode, NULL); child; \ + child = fwnode_get_next_child_node(fwnode, child)) struct fwnode_handle *device_get_next_child_node(struct device *dev, struct fwnode_handle *child); -#define device_for_each_child_node(dev, child) \ - for (child = device_get_next_child_node(dev, NULL); child; \ +#define device_for_each_child_node(dev, child) \ + for (child = device_get_next_child_node(dev, NULL); child; \ child = device_get_next_child_node(dev, child)) +struct fwnode_handle *fwnode_get_named_child_node(struct fwnode_handle *fwnode, + const char *childname); +struct fwnode_handle *device_get_named_child_node(struct device *dev, + const char *childname); + +void fwnode_handle_get(struct fwnode_handle *fwnode); void fwnode_handle_put(struct fwnode_handle *fwnode); unsigned int device_get_child_node_count(struct device *dev); @@ -144,22 +166,35 @@ static inline int fwnode_property_read_u64(struct fwnode_handle *fwnode, /** * struct property_entry - "Built-in" device property representation. * @name: Name of the property. - * @type: Type of the property. - * @nval: Number of items of type @type making up the value. - * @value: Value of the property (an array of @nval items of type @type). + * @length: Length of data making up the value. + * @is_array: True when the property is an array. + * @is_string: True when property is a string. + * @pointer: Pointer to the property (an array of items of the given type). + * @value: Value of the property (when it is a single item of the given type). */ struct property_entry { const char *name; - enum dev_prop_type type; - size_t nval; + size_t length; + bool is_array; + bool is_string; union { - void *raw_data; - u8 *u8_data; - u16 *u16_data; - u32 *u32_data; - u64 *u64_data; - const char **str; - } value; + union { + void *raw_data; + u8 *u8_data; + u16 *u16_data; + u32 *u32_data; + u64 *u64_data; + const char **str; + } pointer; + union { + unsigned long long raw_data; + u8 u8_data; + u16 u16_data; + u32 u32_data; + u64 u64_data; + const char *str; + } value; + }; }; /** @@ -172,7 +207,8 @@ struct property_set { struct property_entry *properties; }; -void device_add_property_set(struct device *dev, struct property_set *pset); +int device_add_property_set(struct device *dev, const struct property_set *pset); +void device_remove_property_set(struct device *dev); bool device_dma_supported(struct device *dev); @@ -182,4 +218,20 @@ int device_get_phy_mode(struct device *dev); void *device_get_mac_address(struct device *dev, char *addr, int alen); +struct fwnode_handle *fwnode_graph_get_next_endpoint( + struct fwnode_handle *fwnode, struct fwnode_handle *prev); +struct fwnode_handle * +fwnode_graph_get_port_parent(struct fwnode_handle *fwnode); +struct fwnode_handle *fwnode_graph_get_remote_port_parent( + struct fwnode_handle *fwnode); +struct fwnode_handle *fwnode_graph_get_remote_port( + struct fwnode_handle *fwnode); +struct fwnode_handle *fwnode_graph_get_remote_endpoint( + struct fwnode_handle *fwnode); +struct fwnode_handle *fwnode_graph_get_remote_node(struct fwnode_handle *fwnode, + u32 port, u32 endpoint); + +int fwnode_graph_parse_endpoint(struct fwnode_handle *fwnode, + struct fwnode_endpoint *endpoint); + #endif /* _LINUX_PROPERTY_H_ */ diff --git a/include/linux/pwm.h b/include/linux/pwm.h index aa8736d5b2f3..2c6c5114c089 100644 --- a/include/linux/pwm.h +++ b/include/linux/pwm.h @@ -5,59 +5,9 @@ #include <linux/mutex.h> #include <linux/of.h> -struct pwm_device; +struct pwm_capture; struct seq_file; -#if IS_ENABLED(CONFIG_PWM) -/* - * pwm_request - request a PWM device - */ -struct pwm_device *pwm_request(int pwm_id, const char *label); - -/* - * pwm_free - free a PWM device - */ -void pwm_free(struct pwm_device *pwm); - -/* - * pwm_config - change a PWM device configuration - */ -int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns); - -/* - * pwm_enable - start a PWM output toggling - */ -int pwm_enable(struct pwm_device *pwm); - -/* - * pwm_disable - stop a PWM output toggling - */ -void pwm_disable(struct pwm_device *pwm); -#else -static inline struct pwm_device *pwm_request(int pwm_id, const char *label) -{ - return ERR_PTR(-ENODEV); -} - -static inline void pwm_free(struct pwm_device *pwm) -{ -} - -static inline int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) -{ - return -EINVAL; -} - -static inline int pwm_enable(struct pwm_device *pwm) -{ - return -EINVAL; -} - -static inline void pwm_disable(struct pwm_device *pwm) -{ -} -#endif - struct pwm_chip; /** @@ -74,10 +24,41 @@ enum pwm_polarity { PWM_POLARITY_INVERSED, }; +/** + * struct pwm_args - board-dependent PWM arguments + * @period: reference period + * @polarity: reference polarity + * + * This structure describes board-dependent arguments attached to a PWM + * device. These arguments are usually retrieved from the PWM lookup table or + * device tree. + * + * Do not confuse this with the PWM state: PWM arguments represent the initial + * configuration that users want to use on this PWM device rather than the + * current PWM hardware state. + */ +struct pwm_args { + unsigned int period; + enum pwm_polarity polarity; +}; + enum { PWMF_REQUESTED = 1 << 0, - PWMF_ENABLED = 1 << 1, - PWMF_EXPORTED = 1 << 2, + PWMF_EXPORTED = 1 << 1, +}; + +/* + * struct pwm_state - state of a PWM channel + * @period: PWM period (in nanoseconds) + * @duty_cycle: PWM duty cycle (in nanoseconds) + * @polarity: PWM polarity + * @enabled: PWM enabled status + */ +struct pwm_state { + unsigned int period; + unsigned int duty_cycle; + enum pwm_polarity polarity; + bool enabled; }; /** @@ -88,10 +69,8 @@ enum { * @pwm: global index of the PWM device * @chip: PWM chip providing this PWM device * @chip_data: chip-private data associated with the PWM device - * @lock: used to serialize accesses to the PWM device where necessary - * @period: period of the PWM signal (in nanoseconds) - * @duty_cycle: duty cycle of the PWM signal (in nanoseconds) - * @polarity: polarity of the PWM signal + * @args: PWM arguments + * @state: curent PWM channel state */ struct pwm_device { const char *label; @@ -100,48 +79,162 @@ struct pwm_device { unsigned int pwm; struct pwm_chip *chip; void *chip_data; - struct mutex lock; - unsigned int period; - unsigned int duty_cycle; - enum pwm_polarity polarity; + struct pwm_args args; + struct pwm_state state; }; +/** + * pwm_get_state() - retrieve the current PWM state + * @pwm: PWM device + * @state: state to fill with the current PWM state + */ +static inline void pwm_get_state(const struct pwm_device *pwm, + struct pwm_state *state) +{ + *state = pwm->state; +} + static inline bool pwm_is_enabled(const struct pwm_device *pwm) { - return test_bit(PWMF_ENABLED, &pwm->flags); + struct pwm_state state; + + pwm_get_state(pwm, &state); + + return state.enabled; } static inline void pwm_set_period(struct pwm_device *pwm, unsigned int period) { if (pwm) - pwm->period = period; + pwm->state.period = period; } static inline unsigned int pwm_get_period(const struct pwm_device *pwm) { - return pwm ? pwm->period : 0; + struct pwm_state state; + + pwm_get_state(pwm, &state); + + return state.period; } static inline void pwm_set_duty_cycle(struct pwm_device *pwm, unsigned int duty) { if (pwm) - pwm->duty_cycle = duty; + pwm->state.duty_cycle = duty; } static inline unsigned int pwm_get_duty_cycle(const struct pwm_device *pwm) { - return pwm ? pwm->duty_cycle : 0; + struct pwm_state state; + + pwm_get_state(pwm, &state); + + return state.duty_cycle; } -/* - * pwm_set_polarity - configure the polarity of a PWM signal +static inline enum pwm_polarity pwm_get_polarity(const struct pwm_device *pwm) +{ + struct pwm_state state; + + pwm_get_state(pwm, &state); + + return state.polarity; +} + +static inline void pwm_get_args(const struct pwm_device *pwm, + struct pwm_args *args) +{ + *args = pwm->args; +} + +/** + * pwm_init_state() - prepare a new state to be applied with pwm_apply_state() + * @pwm: PWM device + * @state: state to fill with the prepared PWM state + * + * This functions prepares a state that can later be tweaked and applied + * to the PWM device with pwm_apply_state(). This is a convenient function + * that first retrieves the current PWM state and the replaces the period + * and polarity fields with the reference values defined in pwm->args. + * Once the function returns, you can adjust the ->enabled and ->duty_cycle + * fields according to your needs before calling pwm_apply_state(). + * + * ->duty_cycle is initially set to zero to avoid cases where the current + * ->duty_cycle value exceed the pwm_args->period one, which would trigger + * an error if the user calls pwm_apply_state() without adjusting ->duty_cycle + * first. */ -int pwm_set_polarity(struct pwm_device *pwm, enum pwm_polarity polarity); +static inline void pwm_init_state(const struct pwm_device *pwm, + struct pwm_state *state) +{ + struct pwm_args args; -static inline enum pwm_polarity pwm_get_polarity(const struct pwm_device *pwm) + /* First get the current state. */ + pwm_get_state(pwm, state); + + /* Then fill it with the reference config */ + pwm_get_args(pwm, &args); + + state->period = args.period; + state->polarity = args.polarity; + state->duty_cycle = 0; +} + +/** + * pwm_get_relative_duty_cycle() - Get a relative duty cycle value + * @state: PWM state to extract the duty cycle from + * @scale: target scale of the relative duty cycle + * + * This functions converts the absolute duty cycle stored in @state (expressed + * in nanosecond) into a value relative to the period. + * + * For example if you want to get the duty_cycle expressed in percent, call: + * + * pwm_get_state(pwm, &state); + * duty = pwm_get_relative_duty_cycle(&state, 100); + */ +static inline unsigned int +pwm_get_relative_duty_cycle(const struct pwm_state *state, unsigned int scale) { - return pwm ? pwm->polarity : PWM_POLARITY_NORMAL; + if (!state->period) + return 0; + + return DIV_ROUND_CLOSEST_ULL((u64)state->duty_cycle * scale, + state->period); +} + +/** + * pwm_set_relative_duty_cycle() - Set a relative duty cycle value + * @state: PWM state to fill + * @duty_cycle: relative duty cycle value + * @scale: scale in which @duty_cycle is expressed + * + * This functions converts a relative into an absolute duty cycle (expressed + * in nanoseconds), and puts the result in state->duty_cycle. + * + * For example if you want to configure a 50% duty cycle, call: + * + * pwm_init_state(pwm, &state); + * pwm_set_relative_duty_cycle(&state, 50, 100); + * pwm_apply_state(pwm, &state); + * + * This functions returns -EINVAL if @duty_cycle and/or @scale are + * inconsistent (@scale == 0 or @duty_cycle > @scale). + */ +static inline int +pwm_set_relative_duty_cycle(struct pwm_state *state, unsigned int duty_cycle, + unsigned int scale) +{ + if (!scale || duty_cycle > scale) + return -EINVAL; + + state->duty_cycle = DIV_ROUND_CLOSEST_ULL((u64)duty_cycle * + state->period, + scale); + + return 0; } /** @@ -150,8 +243,16 @@ static inline enum pwm_polarity pwm_get_polarity(const struct pwm_device *pwm) * @free: optional hook for freeing a PWM * @config: configure duty cycles and period length for this PWM * @set_polarity: configure the polarity of this PWM + * @capture: capture and report PWM signal * @enable: enable PWM output toggling * @disable: disable PWM output toggling + * @apply: atomically apply a new PWM config. The state argument + * should be adjusted with the real hardware config (if the + * approximate the period or duty_cycle value, state should + * reflect it) + * @get_state: get the current PWM state. This function is only + * called once per PWM device when the PWM chip is + * registered. * @dbg_show: optional routine to show contents in debugfs * @owner: helps prevent removal of modules exporting active PWMs */ @@ -162,8 +263,14 @@ struct pwm_ops { int duty_ns, int period_ns); int (*set_polarity)(struct pwm_chip *chip, struct pwm_device *pwm, enum pwm_polarity polarity); + int (*capture)(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_capture *result, unsigned long timeout); int (*enable)(struct pwm_chip *chip, struct pwm_device *pwm); void (*disable)(struct pwm_chip *chip, struct pwm_device *pwm); + int (*apply)(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state); + void (*get_state)(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state); #ifdef CONFIG_DEBUG_FS void (*dbg_show)(struct pwm_chip *chip, struct seq_file *s); #endif @@ -198,7 +305,130 @@ struct pwm_chip { bool can_sleep; }; +/** + * struct pwm_capture - PWM capture data + * @period: period of the PWM signal (in nanoseconds) + * @duty_cycle: duty cycle of the PWM signal (in nanoseconds) + */ +struct pwm_capture { + unsigned int period; + unsigned int duty_cycle; +}; + #if IS_ENABLED(CONFIG_PWM) +/* PWM user APIs */ +struct pwm_device *pwm_request(int pwm_id, const char *label); +void pwm_free(struct pwm_device *pwm); +int pwm_apply_state(struct pwm_device *pwm, struct pwm_state *state); +int pwm_adjust_config(struct pwm_device *pwm); + +/** + * pwm_config() - change a PWM device configuration + * @pwm: PWM device + * @duty_ns: "on" time (in nanoseconds) + * @period_ns: duration (in nanoseconds) of one cycle + * + * Returns: 0 on success or a negative error code on failure. + */ +static inline int pwm_config(struct pwm_device *pwm, int duty_ns, + int period_ns) +{ + struct pwm_state state; + + if (!pwm) + return -EINVAL; + + if (duty_ns < 0 || period_ns < 0) + return -EINVAL; + + pwm_get_state(pwm, &state); + if (state.duty_cycle == duty_ns && state.period == period_ns) + return 0; + + state.duty_cycle = duty_ns; + state.period = period_ns; + return pwm_apply_state(pwm, &state); +} + +/** + * pwm_set_polarity() - configure the polarity of a PWM signal + * @pwm: PWM device + * @polarity: new polarity of the PWM signal + * + * Note that the polarity cannot be configured while the PWM device is + * enabled. + * + * Returns: 0 on success or a negative error code on failure. + */ +static inline int pwm_set_polarity(struct pwm_device *pwm, + enum pwm_polarity polarity) +{ + struct pwm_state state; + + if (!pwm) + return -EINVAL; + + pwm_get_state(pwm, &state); + if (state.polarity == polarity) + return 0; + + /* + * Changing the polarity of a running PWM without adjusting the + * dutycycle/period value is a bit risky (can introduce glitches). + * Return -EBUSY in this case. + * Note that this is allowed when using pwm_apply_state() because + * the user specifies all the parameters. + */ + if (state.enabled) + return -EBUSY; + + state.polarity = polarity; + return pwm_apply_state(pwm, &state); +} + +/** + * pwm_enable() - start a PWM output toggling + * @pwm: PWM device + * + * Returns: 0 on success or a negative error code on failure. + */ +static inline int pwm_enable(struct pwm_device *pwm) +{ + struct pwm_state state; + + if (!pwm) + return -EINVAL; + + pwm_get_state(pwm, &state); + if (state.enabled) + return 0; + + state.enabled = true; + return pwm_apply_state(pwm, &state); +} + +/** + * pwm_disable() - stop a PWM output toggling + * @pwm: PWM device + */ +static inline void pwm_disable(struct pwm_device *pwm) +{ + struct pwm_state state; + + if (!pwm) + return; + + pwm_get_state(pwm, &state); + if (!state.enabled) + return; + + state.enabled = false; + pwm_apply_state(pwm, &state); +} + +/* PWM provider APIs */ +int pwm_capture(struct pwm_device *pwm, struct pwm_capture *result, + unsigned long timeout); int pwm_set_chip_data(struct pwm_device *pwm, void *data); void *pwm_get_chip_data(struct pwm_device *pwm); @@ -224,6 +454,54 @@ void devm_pwm_put(struct device *dev, struct pwm_device *pwm); bool pwm_can_sleep(struct pwm_device *pwm); #else +static inline struct pwm_device *pwm_request(int pwm_id, const char *label) +{ + return ERR_PTR(-ENODEV); +} + +static inline void pwm_free(struct pwm_device *pwm) +{ +} + +static inline int pwm_apply_state(struct pwm_device *pwm, + const struct pwm_state *state) +{ + return -ENOTSUPP; +} + +static inline int pwm_adjust_config(struct pwm_device *pwm) +{ + return -ENOTSUPP; +} + +static inline int pwm_config(struct pwm_device *pwm, int duty_ns, + int period_ns) +{ + return -EINVAL; +} + +static inline int pwm_capture(struct pwm_device *pwm, + struct pwm_capture *result, + unsigned long timeout) +{ + return -EINVAL; +} + +static inline int pwm_set_polarity(struct pwm_device *pwm, + enum pwm_polarity polarity) +{ + return -ENOTSUPP; +} + +static inline int pwm_enable(struct pwm_device *pwm) +{ + return -EINVAL; +} + +static inline void pwm_disable(struct pwm_device *pwm) +{ +} + static inline int pwm_set_chip_data(struct pwm_device *pwm, void *data) { return -EINVAL; @@ -295,6 +573,38 @@ static inline bool pwm_can_sleep(struct pwm_device *pwm) } #endif +static inline void pwm_apply_args(struct pwm_device *pwm) +{ + struct pwm_state state = { }; + + /* + * PWM users calling pwm_apply_args() expect to have a fresh config + * where the polarity and period are set according to pwm_args info. + * The problem is, polarity can only be changed when the PWM is + * disabled. + * + * PWM drivers supporting hardware readout may declare the PWM device + * as enabled, and prevent polarity setting, which changes from the + * existing behavior, where all PWM devices are declared as disabled + * at startup (even if they are actually enabled), thus authorizing + * polarity setting. + * + * To fulfill this requirement, we apply a new state which disables + * the PWM device and set the reference period and polarity config. + * + * Note that PWM users requiring a smooth handover between the + * bootloader and the kernel (like critical regulators controlled by + * PWM devices) will have to switch to the atomic API and avoid calling + * pwm_apply_args(). + */ + + state.enabled = false; + state.polarity = pwm->args.polarity; + state.period = pwm->args.period; + + pwm_apply_state(pwm, &state); +} + struct pwm_lookup { struct list_head list; const char *provider; diff --git a/include/linux/reboot.h b/include/linux/reboot.h index a7ff409f386d..2f3bc9a0d84f 100644 --- a/include/linux/reboot.h +++ b/include/linux/reboot.h @@ -42,6 +42,10 @@ extern int register_restart_handler(struct notifier_block *); extern int unregister_restart_handler(struct notifier_block *); extern void do_kernel_restart(char *cmd); +extern int register_i2c_restart_handler(struct notifier_block *); +extern int unregister_i2c_restart_handler(struct notifier_block *); +extern void do_kernel_i2c_restart(char *cmd); + /* * Architecture-specific implementations of sys_reboot commands. */ diff --git a/include/linux/regmap.h b/include/linux/regmap.h index d68bb402120e..d47154cd6dd1 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -784,6 +784,45 @@ int regmap_fields_update_bits(struct regmap_field *field, unsigned int id, unsigned int mask, unsigned int val); /** + * regmap_read_poll_timeout - Poll until a condition is met or a timeout occurs + * @map: Regmap to read from + * @addr: Address to poll + * @val: Unsigned integer variable to read the value into + * @cond: Break condition (usually involving @val) + * @sleep_us: Maximum time to sleep between reads in us (0 + * tight-loops). Should be less than ~20ms since usleep_range + * is used (see Documentation/timers/timers-howto.txt). + * @timeout_us: Timeout in us, 0 means never timeout + * + * Returns 0 on success and -ETIMEDOUT upon a timeout or the regmap_read + * error return value in case of a error read. In the two former cases, + * the last read value at @addr is stored in @val. Must not be called + * from atomic context if sleep_us or timeout_us are used. + * + * This is modelled after the readx_poll_timeout macros in linux/iopoll.h. + */ +#define regmap_read_poll_timeout(map, addr, val, cond, sleep_us, timeout_us) \ +({ \ + ktime_t timeout = ktime_add_us(ktime_get(), timeout_us); \ + int ret; \ + might_sleep_if(sleep_us); \ + for (;;) { \ + ret = regmap_read((map), (addr), &(val)); \ + if (ret) \ + break; \ + if (cond) \ + break; \ + if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) { \ + ret = regmap_read((map), (addr), &(val)); \ + break; \ + } \ + if (sleep_us) \ + usleep_range((sleep_us >> 2) + 1, sleep_us); \ + } \ + ret ?: ((cond) ? 0 : -ETIMEDOUT); \ +}) + +/** * Description of an IRQ for the generic regmap irq_chip. * * @reg_offset: Offset of the status/mask register within the bank diff --git a/include/linux/regulator/consumer.h b/include/linux/regulator/consumer.h index 9e0e76992be0..48603506f8de 100644 --- a/include/linux/regulator/consumer.h +++ b/include/linux/regulator/consumer.h @@ -140,6 +140,8 @@ struct regulator; * * @supply: The name of the supply. Initialised by the user before * using the bulk regulator APIs. + * @optional: The supply should be considered optional. Initialised by the user + * before using the bulk regulator APIs. * @consumer: The regulator consumer for the supply. This will be managed * by the bulk API. * @@ -149,6 +151,7 @@ struct regulator; */ struct regulator_bulk_data { const char *supply; + bool optional; struct regulator *consumer; /* private: Internal use */ diff --git a/include/linux/regulator/driver.h b/include/linux/regulator/driver.h index 9c2903e58adb..2f890c611ecb 100644 --- a/include/linux/regulator/driver.h +++ b/include/linux/regulator/driver.h @@ -93,6 +93,8 @@ struct regulator_linear_range { * @get_current_limit: Get the configured limit for a current-limited regulator. * @set_input_current_limit: Configure an input limit. * + * @set_active_discharge: Set active discharge enable/disable of regulators. + * * @set_mode: Set the configured operating mode for the regulator. * @get_mode: Get the configured operating mode for the regulator. * @get_status: Return actual (not as-configured) status of regulator, as a @@ -108,10 +110,14 @@ struct regulator_linear_range { * stabilise after being enabled, in microseconds. * @set_ramp_delay: Set the ramp delay for the regulator. The driver should * select ramp delay equal to or less than(closest) ramp_delay. + * @set_voltage_time: Time taken for the regulator voltage output voltage + * to stabilise after being set to a new value, in microseconds. + * The function receives the from and to voltage as input, it + * should return the worst case. * @set_voltage_time_sel: Time taken for the regulator voltage output voltage * to stabilise after being set to a new value, in microseconds. - * The function provides the from and to voltage selector, the - * function should return the worst case. + * The function receives the from and to voltage selector as + * input, it should return the worst case. * @set_soft_start: Enable soft start for the regulator. * * @set_suspend_voltage: Set the voltage for the regulator when the system @@ -149,6 +155,7 @@ struct regulator_ops { int (*set_input_current_limit) (struct regulator_dev *, int lim_uA); int (*set_over_current_protection) (struct regulator_dev *); + int (*set_active_discharge) (struct regulator_dev *, bool enable); /* enable/disable regulator */ int (*enable) (struct regulator_dev *); @@ -162,6 +169,8 @@ struct regulator_ops { /* Time taken to enable or set voltage on the regulator */ int (*enable_time) (struct regulator_dev *); int (*set_ramp_delay) (struct regulator_dev *, int ramp_delay); + int (*set_voltage_time) (struct regulator_dev *, int old_uV, + int new_uV); int (*set_voltage_time_sel) (struct regulator_dev *, unsigned int old_selector, unsigned int new_selector); @@ -266,6 +275,14 @@ enum regulator_type { * @bypass_mask: Mask for control when using regmap set_bypass * @bypass_val_on: Enabling value for control when using regmap set_bypass * @bypass_val_off: Disabling value for control when using regmap set_bypass + * @active_discharge_off: Enabling value for control when using regmap + * set_active_discharge + * @active_discharge_on: Disabling value for control when using regmap + * set_active_discharge + * @active_discharge_mask: Mask for control when using regmap + * set_active_discharge + * @active_discharge_reg: Register for control when using regmap + * set_active_discharge * * @enable_time: Time taken for initial enable of regulator (in uS). * @off_on_delay: guard time (in uS), before re-enabling a regulator @@ -313,6 +330,10 @@ struct regulator_desc { unsigned int bypass_mask; unsigned int bypass_val_on; unsigned int bypass_val_off; + unsigned int active_discharge_on; + unsigned int active_discharge_off; + unsigned int active_discharge_mask; + unsigned int active_discharge_reg; unsigned int enable_time; @@ -399,6 +420,7 @@ struct regulator_dev { /* time when this regulator was disabled last time */ unsigned long last_off_jiffy; + struct regulator *debug_consumer; }; struct regulator_dev * @@ -445,6 +467,8 @@ int regulator_set_voltage_time_sel(struct regulator_dev *rdev, int regulator_set_bypass_regmap(struct regulator_dev *rdev, bool enable); int regulator_get_bypass_regmap(struct regulator_dev *rdev, bool *enable); +int regulator_set_active_discharge_regmap(struct regulator_dev *rdev, + bool enable); void *regulator_get_init_drvdata(struct regulator_init_data *reg_init_data); #endif diff --git a/include/linux/regulator/fan53555.h b/include/linux/regulator/fan53555.h index f13880e84d85..4e8184c5e804 100644 --- a/include/linux/regulator/fan53555.h +++ b/include/linux/regulator/fan53555.h @@ -56,6 +56,7 @@ struct fan53555_platform_data { unsigned int slew_rate; /* Sleep VSEL ID */ unsigned int sleep_vsel_id; + struct gpio_desc *vsel_gpio; }; #endif /* __FAN53555_H__ */ diff --git a/include/linux/regulator/machine.h b/include/linux/regulator/machine.h index a1067d0b3991..07e913c791aa 100644 --- a/include/linux/regulator/machine.h +++ b/include/linux/regulator/machine.h @@ -42,6 +42,13 @@ struct regulator; #define REGULATOR_CHANGE_DRMS 0x10 #define REGULATOR_CHANGE_BYPASS 0x20 +/* Regulator active discharge flags */ +enum regulator_active_discharge { + REGULATOR_ACTIVE_DISCHARGE_DEFAULT, + REGULATOR_ACTIVE_DISCHARGE_DISABLE, + REGULATOR_ACTIVE_DISCHARGE_ENABLE, +}; + /** * struct regulator_state - regulator state during low power system states * @@ -73,6 +80,9 @@ struct regulator_state { * @uV_offset: Offset applied to voltages from consumer to compensate for * voltage drops. * + * @early_min_uV: Minimum voltage during system startup, make sure we select + * a voltage that suits the needs of all regulator consumers. + * * @min_uA: Smallest current consumers may set. * @max_uA: Largest current consumers may set. * @ilim_uA: Maximum input current. @@ -100,6 +110,15 @@ struct regulator_state { * @initial_state: Suspend state to set by default. * @initial_mode: Mode to set at startup. * @ramp_delay: Time to settle down after voltage change (unit: uV/us) + * @settling_time: Time to settle down after voltage change when voltage + * change is non-linear (unit: microseconds). + * @settling_time_up: Time to settle down after voltage increase when voltage + * change is non-linear (unit: microseconds). + * @settling_time_down : Time to settle down after voltage decrease when + * voltage change is non-linear (unit: microseconds). + * @active_discharge: Enable/disable active discharge. The enum + * regulator_active_discharge values are used for + * initialisation. * @enable_time: Turn-on time of the rails (unit: microseconds) */ struct regulation_constraints { @@ -110,6 +129,9 @@ struct regulation_constraints { int min_uV; int max_uV; + /* Minimum voltage during system startup */ + int early_min_uV; + int uV_offset; /* current output range (inclusive) - for current control */ @@ -138,8 +160,13 @@ struct regulation_constraints { unsigned int initial_mode; unsigned int ramp_delay; + unsigned int settling_time; + unsigned int settling_time_up; + unsigned int settling_time_down; unsigned int enable_time; + unsigned int active_discharge; + /* constraint flags */ unsigned always_on:1; /* regulator never off when system is on */ unsigned boot_on:1; /* bootloader/firmware enabled regulator */ diff --git a/include/linux/rfkill-bt.h b/include/linux/rfkill-bt.h new file mode 100755 index 000000000000..c4174b156580 --- /dev/null +++ b/include/linux/rfkill-bt.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2011, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + + +#ifndef __RFKILL_GPIO_H +#define __RFKILL_GPIO_H + +#include <linux/types.h> +#include <linux/rfkill.h> +#include <linux/clk.h> + +#define RFKILL_RK_GPIO_NAME_SIZE 64 + +//struct rfkill_rk_iomux { +// char *name; +// int fgpio; +// int fmux; +//}; + +struct rfkill_rk_gpio { + int io; + char name[RFKILL_RK_GPIO_NAME_SIZE]; + int enable; // disable = !enable + struct pinctrl_state *gpio_state; + struct pinctrl_state *default_state; +}; + +struct rfkill_rk_irq { + char name[RFKILL_RK_GPIO_NAME_SIZE]; + struct rfkill_rk_gpio gpio; + int irq; +}; + +/** + * struct rfkill_rk_platform_data - platform data for rfkill gpio device. + * for unused gpio's, the expected value is -1. + * @name: name for the gpio rf kill instance + * @reset_gpio: GPIO which is used for reseting rfkill switch + * @shutdown_gpio: GPIO which is used for shutdown of rfkill switch + */ + +struct rfkill_rk_platform_data { + char *name; + enum rfkill_type type; + bool power_toggle; + struct pinctrl *pinctrl; + struct rfkill_rk_gpio poweron_gpio; + struct rfkill_rk_gpio reset_gpio; + struct rfkill_rk_gpio wake_gpio; // Host wake or sleep BT + struct rfkill_rk_irq wake_host_irq; // BT wakeup host + struct rfkill_rk_gpio rts_gpio; + struct clk *ext_clk; +}; + +int rfkill_get_bt_power_state(int *power, bool *toggle); + +#endif /* __RFKILL_GPIO_H */ + diff --git a/include/linux/rfkill-wlan.h b/include/linux/rfkill-wlan.h new file mode 100644 index 000000000000..2cead6d09a15 --- /dev/null +++ b/include/linux/rfkill-wlan.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __PLAT_BOARD_H +#define __PLAT_BOARD_H + +#include <linux/types.h> +#include <linux/init.h> +#include <linux/device.h> +#include <linux/clk.h> + +struct rksdmmc_iomux { + char *name; //set the MACRO of gpio + int fgpio; + int fmux; +}; + +struct rksdmmc_gpio { + int io; //set the address of gpio + char name[64]; // + int enable; // disable = !enable //set the default value,i.e,GPIO_HIGH or GPIO_LOW + struct rksdmmc_iomux iomux; +}; + +struct rksdmmc_pmu { + bool power_ctrl_by_pmu; + char pmu_regulator[20]; + int enable; +}; + +struct rksdmmc_gpio_wifi_moudle { + int sdio_vol; //sdio reference voltage + bool vref_ctrl_enble; + bool wifi_power_remain; + struct rksdmmc_pmu mregulator; + struct rksdmmc_pmu ioregulator; + struct rksdmmc_gpio vbat_n; + struct rksdmmc_gpio power_n; //PMU_EN + struct rksdmmc_gpio reset_n; //SYSRET_B, DAIRST + struct rksdmmc_gpio vddio; + struct rksdmmc_gpio bgf_int_b; + struct rksdmmc_gpio wifi_int_b; + struct rksdmmc_gpio gps_sync; + struct rksdmmc_gpio ANTSEL2; //pin5--ANTSEL2 + struct rksdmmc_gpio ANTSEL3; //pin6--ANTSEL3 + struct rksdmmc_gpio GPS_LAN; //pin33--GPS_LAN + struct regmap *grf; + struct clk *ext_clk; +}; + +enum { + WIFI_RK901, + WIFI_RK903, + WIFI_AP6181, + WIFI_AP6210, + WIFI_AP6212, + WIFI_AP6234, + WIFI_AP6255, + WIFI_AP6330, + WIFI_AP6335, + WIFI_AP6354, + WIFI_AP6441, + WIFI_AP6476, + WIFI_AP6493, + WIFI_AP6XXX_SERIES, + WIFI_RTL8188EU, + WIFI_RTL8192DU, + WIFI_RTL8723AS, + WIFI_RTL8723BS, + WIFI_RTL8723BS_VQ0, + WIFI_RTL8723CS, + WIFI_RTL8723DS, + WIFI_RTL8723BU, + WIFI_RTL8723AU, + WIFI_RTL8189ES, + WIFI_RTL8189FS, + WIFI_RTL8812AU, + WIFI_RTL_SERIES, + WIFI_ESP8089, + WIFI_MVL88W8977, + WIFI_SSV6051, + TYPE_MAX, +}; + +int rfkill_get_wifi_power_state(int *power, int *vref_ctrl_enable); +void *rockchip_mem_prealloc(int section, unsigned long size); +int rockchip_wifi_ref_voltage(int on); +int rockchip_wifi_power(int on); +int rockchip_wifi_set_carddetect(int val); +int rockchip_wifi_get_oob_irq(void); +int rockchip_wifi_get_oob_irq_flag(void); +int rockchip_wifi_reset(int on); +int rockchip_wifi_mac_addr(unsigned char *buf); +void *rockchip_wifi_country_code(char *ccode); +#endif diff --git a/include/linux/rk_fb.h b/include/linux/rk_fb.h new file mode 100755 index 000000000000..944d997b38ec --- /dev/null +++ b/include/linux/rk_fb.h @@ -0,0 +1,851 @@ +/* drivers/video/rk_fb.h + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ARCH_ARM_MACH_RK30_FB_H +#define __ARCH_ARM_MACH_RK30_FB_H + +#include <linux/fb.h> +#include <linux/platform_device.h> +#include <linux/completion.h> +#include <linux/spinlock.h> +#include <asm/atomic.h> +#include <linux/rk_screen.h> +#if defined(CONFIG_OF) +#include <dt-bindings/display/rk_fb.h> +#endif +#include "../../drivers/staging/android/sw_sync.h" +#include <linux/file.h> +#include <linux/kthread.h> +#include <linux/pm_runtime.h> +#include <linux/version.h> + + +#define RK30_MAX_LCDC_SUPPORT 2 +#define RK30_MAX_LAYER_SUPPORT 5 +#define RK_MAX_FB_SUPPORT 5 +#define RK_WIN_MAX_AREA 4 +#define RK_MAX_BUF_NUM 11 + +#define FB0_IOCTL_STOP_TIMER_FLUSH 0x6001 +#define FB0_IOCTL_SET_PANEL 0x6002 + +#ifdef CONFIG_FB_WIMO +#define FB_WIMO_FLAG +#endif +#ifdef FB_WIMO_FLAG +#define FB0_IOCTL_SET_BUF 0x6017 +#define FB0_IOCTL_COPY_CURBUF 0x6018 +#define FB0_IOCTL_CLOSE_BUF 0x6019 +#endif + +#define RK_FBIOGET_PANEL_SIZE 0x5001 +#define RK_FBIOSET_YUV_ADDR 0x5002 +#define RK_FBIOGET_SCREEN_STATE 0X4620 +#define RK_FBIOGET_16OR32 0X4621 +#define RK_FBIOGET_IDLEFBUff_16OR32 0X4622 +#define RK_FBIOSET_COMPOSE_LAYER_COUNTS 0X4623 +#define RK_FBIOSET_HWC_ADDR 0x4624 + +#define RK_FBIOGET_DMABUF_FD 0x5003 +#define RK_FBIOSET_DMABUF_FD 0x5004 +#define RK_FB_IOCTL_SET_I2P_ODD_ADDR 0x5005 +#define RK_FB_IOCTL_SET_I2P_EVEN_ADDR 0x5006 +#define RK_FBIOSET_OVERLAY_STA 0x5018 +#define RK_FBIOGET_OVERLAY_STA 0X4619 +#define RK_FBIOSET_ENABLE 0x5019 +#define RK_FBIOGET_ENABLE 0x5020 +#define RK_FBIOSET_CONFIG_DONE 0x4628 +#define RK_FBIOSET_VSYNC_ENABLE 0x4629 +#define RK_FBIOPUT_NUM_BUFFERS 0x4625 +#define RK_FBIOPUT_COLOR_KEY_CFG 0x4626 +#define RK_FBIOGET_DSP_ADDR 0x4630 +#define RK_FBIOGET_LIST_STA 0X4631 +#define RK_FBIOGET_IOMMU_STA 0x4632 +#define RK_FBIOSET_CLEAR_FB 0x4633 + + +/**rk fb events**/ +#define RK_LF_STATUS_FC 0xef +#define RK_LF_STATUS_FR 0xee +#define RK_LF_STATUS_NC 0xfe +#define RK_LF_MAX_TIMEOUT (1600000UL << 6) //>0.64s + +/** +* pixel align value for gpu,align as 64 bytes in an odd number of times +*/ +#define ALIGN_PIXEL_64BYTE_RGB565 32 /* 64/2*/ +#define ALIGN_PIXEL_64BYTE_RGB8888 16 /* 64/4*/ +#define ALIGN_N_TIMES(x, align) (((x) % (align) == 0) ? (x) : (((x) + ((align) - 1)) & (~((align) - 1)))) +#define ALIGN_ODD_TIMES(x, align) (((x) % ((align) * 2) == 0) ? ((x) + (align)) : (x)) +#define ALIGN_64BYTE_ODD_TIMES(x, align) ALIGN_ODD_TIMES(ALIGN_N_TIMES(x, align), align) + +#define DUMP_FRAME_NUM 3 + +//#define USE_ION_MMU 1 +#if defined(CONFIG_ION_ROCKCHIP) +extern struct ion_client *rockchip_ion_client_create(const char *name); +#endif + +extern int rk_fb_poll_prmry_screen_vblank(void); +extern u32 rk_fb_get_prmry_screen_ft(void); +extern u32 rk_fb_get_prmry_screen_vbt(void); +extern u64 rk_fb_get_prmry_screen_framedone_t(void); +extern int rk_fb_set_prmry_screen_status(int status); +extern bool rk_fb_poll_wait_frame_complete(void); + +enum { + CSC_BT601, + CSC_BT709, + CSC_BT2020, +}; +#define CSC_SHIFT 6 +#define CSC_MASK (0x3 << CSC_SHIFT) +#define CSC_FORMAT(x) (((x) & CSC_MASK) >> CSC_SHIFT) + +#define BT601(x) ((CSC_BT601 << CSC_SHIFT) | ((x) & ~CSC_MASK)) +#define BT709(x) ((CSC_BT709 << CSC_SHIFT) | ((x) & ~CSC_MASK)) +#define BT2020(x) ((CSC_BT2020 << CSC_SHIFT) | ((x) & ~CSC_MASK)) + +enum { + SDR_DATA, + HDR_DATA, +}; + +/** + * pixel format definitions,this is copy from android/system/core/include/system/graphics.h + */ +enum { + HAL_PIXEL_FORMAT_RGBA_8888 = 1, + HAL_PIXEL_FORMAT_RGBX_8888 = 2, + HAL_PIXEL_FORMAT_RGB_888 = 3, + HAL_PIXEL_FORMAT_RGB_565 = 4, + HAL_PIXEL_FORMAT_BGRA_8888 = 5, + HAL_PIXEL_FORMAT_RGBA_5551 = 6, + HAL_PIXEL_FORMAT_RGBA_4444 = 7, + + /* 0x8 - 0xFF range unavailable */ + + /* + * 0x100 - 0x1FF + * + * This range is reserved for pixel formats that are specific to the HAL + * implementation. Implementations can use any value in this range to + * communicate video pixel formats between their HAL modules. These formats + * must not have an alpha channel. Additionally, an EGLimage created from a + * gralloc buffer of one of these formats must be supported for use with the + * GL_OES_EGL_image_external OpenGL ES extension. + */ + + /* + * Android YUV format: + * + * This format is exposed outside of the HAL to software decoders and + * applications. EGLImageKHR must support it in conjunction with the + * OES_EGL_image_external extension. + * + * YV12 is a 4:2:0 YCrCb planar format comprised of a WxH Y plane followed + * by (W/2) x (H/2) Cr and Cb planes. + * + * This format assumes + * - an even width + * - an even height + * - a horizontal stride multiple of 16 pixels + * - a vertical stride equal to the height + * + * y_size = stride * height + * c_size = ALIGN(stride/2, 16) * height/2 + * size = y_size + c_size * 2 + * cr_offset = y_size + * cb_offset = y_size + c_size + * + */ + HAL_PIXEL_FORMAT_YV12 = 0x32315659, // YCrCb 4:2:0 Planar + + /* Legacy formats (deprecated), used by ImageFormat.java */ + + /* + * YCbCr format default is BT601. + */ + HAL_PIXEL_FORMAT_YCbCr_422_SP = 0x10, // NV16 + HAL_PIXEL_FORMAT_YCrCb_420_SP = 0x11, // NV21 + HAL_PIXEL_FORMAT_YCbCr_422_I = 0x14, // YUY2 + HAL_PIXEL_FORMAT_YCrCb_NV12 = 0x20, // YUY2 + HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO = 0x21, // YUY2 + + HAL_PIXEL_FORMAT_YCrCb_NV12_10 = 0x22, // YUV420_1obit + HAL_PIXEL_FORMAT_YCbCr_422_SP_10 = 0x23, // YUV422_1obit + HAL_PIXEL_FORMAT_YCrCb_444_SP_10 = 0x24, //YUV444_1obit + + HAL_PIXEL_FORMAT_YCrCb_444 = 0x25, //yuv444 + HAL_PIXEL_FORMAT_FBDC_RGB565 = 0x26, + HAL_PIXEL_FORMAT_FBDC_U8U8U8U8 = 0x27, /*ARGB888*/ + HAL_PIXEL_FORMAT_FBDC_U8U8U8 = 0x28, /*RGBP888*/ + HAL_PIXEL_FORMAT_FBDC_RGBA888 = 0x29, /*ABGR888*/ + HAL_PIXEL_FORMAT_BGRX_8888 = 0x30, + HAL_PIXEL_FORMAT_BGR_888 = 0x31, + HAL_PIXEL_FORMAT_BGR_565 = 0x32, + + HAL_PIXEL_FORMAT_YUYV422 = 0x33, + HAL_PIXEL_FORMAT_YUYV420 = 0x34, + HAL_PIXEL_FORMAT_UYVY422 = 0x35, + HAL_PIXEL_FORMAT_UYVY420 = 0x36, + + HAL_PIXEL_FORMAT_YCrCb_NV12_BT709 = + BT709(HAL_PIXEL_FORMAT_YCrCb_NV12), + HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO_BT709 = + BT709(HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO), + HAL_PIXEL_FORMAT_YCbCr_422_SP_BT709 = + BT709(HAL_PIXEL_FORMAT_YCbCr_422_SP), + HAL_PIXEL_FORMAT_YCrCb_444_BT709 = + BT709(HAL_PIXEL_FORMAT_YCrCb_444), + + HAL_PIXEL_FORMAT_YCrCb_NV12_10_BT709 = + BT709(HAL_PIXEL_FORMAT_YCrCb_NV12_10), + HAL_PIXEL_FORMAT_YCbCr_422_SP_10_BT709 = + BT709(HAL_PIXEL_FORMAT_YCbCr_422_SP_10), + HAL_PIXEL_FORMAT_YCrCb_420_SP_10_BT709 = + BT709(HAL_PIXEL_FORMAT_YCrCb_444_SP_10), + + HAL_PIXEL_FORMAT_YCrCb_NV12_10_BT2020 = + BT2020(HAL_PIXEL_FORMAT_YCrCb_NV12_10), + HAL_PIXEL_FORMAT_YCbCr_422_SP_10_BT2020 = + BT2020(HAL_PIXEL_FORMAT_YCbCr_422_SP_10), + HAL_PIXEL_FORMAT_YCrCb_420_SP_10_BT2020 = + BT2020(HAL_PIXEL_FORMAT_YCrCb_444_SP_10), +}; + +//display data format +enum data_format { + ARGB888,/*don't update and insert other format*/ + RGB888, /*don't update and insert other format*/ + RGB565, /*don't update and insert other format*/ + BGR888, + XRGB888, + XBGR888, + ABGR888, + BGR565, + FBDC_RGB_565, + FBDC_ARGB_888, + FBDC_RGBX_888, + FBDC_ABGR_888, + YUV420, + YUV422, + YUV444, + YUV420_A, + YUV422_A, + YUV444_A, + YUV420_NV21, + YUYV422, + YUYV420, + UYVY422, + UYVY420 +}; +#define IS_YUV_FMT(fmt) ((fmt >= YUV420) ? 1 : 0) +#define IS_RGB_FMT(fmt) ((fmt < YUV420) ? 1 : 0) +#define IS_FBDC_FMT(fmt) \ + (((fmt >= FBDC_RGB_565) && (fmt <= FBDC_ABGR_888)) ? 1 : 0) + +enum +{ + SCALE_NONE = 0x0, + SCALE_UP = 0x1, + SCALE_DOWN = 0x2 +}; + +typedef enum { + BRIGHTNESS = 0x0, + CONTRAST = 0x1, + SAT_CON = 0x2 +} bcsh_bcs_mode; + +typedef enum { + H_SIN = 0x0, + H_COS = 0x1 +} bcsh_hue_mode; + +typedef enum { + SCREEN_PREPARE_DDR_CHANGE = 0x0, + SCREEN_UNPREPARE_DDR_CHANGE, +} screen_status; + +typedef enum { + GET_PAGE_FAULT = 0x0, + CLR_PAGE_FAULT = 0x1, + UNMASK_PAGE_FAULT = 0x2, + UPDATE_CABC_PWM = 0x3, + SET_DSP_MIRROR = 0x4 +} extern_func; + +enum rk_vop_feature { + SUPPORT_VOP_IDENTIFY = BIT(0), + SUPPORT_IFBDC = BIT(1), + SUPPORT_AFBDC = BIT(2), + SUPPORT_WRITE_BACK = BIT(3), + SUPPORT_YUV420_OUTPUT = BIT(4) +}; + +struct rk_vop_property { + u32 feature; + u32 max_output_x; + u32 max_output_y; +}; + +enum rk_win_feature { + SUPPORT_WIN_IDENTIFY = BIT(0), + SUPPORT_HW_EXIST = BIT(1), + SUPPORT_SCALE = BIT(2), + SUPPORT_YUV = BIT(3), + SUPPORT_YUV10BIT = BIT(4), + SUPPORT_MULTI_AREA = BIT(5), + SUPPORT_HWC_LAYER = BIT(6) +}; + +struct rk_win_property { + u32 feature; + u32 max_input_x; + u32 max_input_y; +}; + +struct rk_fb_rgb { + struct fb_bitfield red; + struct fb_bitfield green; + struct fb_bitfield blue; + struct fb_bitfield transp; +}; + +struct rk_fb_frame_time { + u64 last_framedone_t; + u64 framedone_t; + u32 ft; +}; + +struct rk_fb_vsync { + wait_queue_head_t wait; + ktime_t timestamp; + int active; + bool irq_stop; + int irq_refcount; + struct mutex irq_lock; + struct task_struct *thread; +}; + +struct color_key_cfg { + u32 win0_color_key_cfg; + u32 win1_color_key_cfg; + u32 win2_color_key_cfg; +}; + +struct pwr_ctr { + char name[32]; + int type; + int is_rst; + int gpio; + int atv_val; + const char *rgl_name; + int volt; + int delay; +}; + +struct rk_disp_pwr_ctr_list { + struct list_head list; + struct pwr_ctr pwr_ctr; +}; + +typedef enum _TRSP_MODE { + TRSP_CLOSE = 0, + TRSP_FMREG, + TRSP_FMREGEX, + TRSP_FMRAM, + TRSP_FMRAMEX, + TRSP_MASK, + TRSP_INVAL +} TRSP_MODE; + +struct rk_lcdc_post_cfg { + u32 xpos; + u32 ypos; + u32 xsize; + u32 ysize; +}; + +struct rk_fb_wb_cfg { + u8 data_format; + short ion_fd; + u32 phy_addr; + u16 xsize; + u16 ysize; + u8 reserved0; + u32 reversed1; +}; + +struct rk_lcdc_bcsh { + bool enable; + u16 brightness; + u16 contrast; + u16 sat_con; + u16 sin_hue; + u16 cos_hue; +}; + +struct rk_lcdc_win_area { + bool state; + enum data_format format; + u8 data_space; /* SDR or HDR */ + u8 fmt_cfg; + u8 yuyv_fmt; + u8 swap_rb; + u8 swap_uv; + u32 y_offset; /*yuv/rgb offset -->LCDC_WINx_YRGB_MSTx*/ + u32 c_offset; /*cb cr offset--->LCDC_WINx_CBR_MSTx*/ + u16 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/ + u16 ypos; + u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/ + u16 ysize; + u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/ + u16 yact; + u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/ + u16 yvir; + u16 xoff; /*mem offset*/ + u16 yoff; + unsigned long smem_start; + unsigned long cbr_start; /*Cbr memory start address*/ +#if defined(CONFIG_ION_ROCKCHIP) + struct ion_handle *ion_hdl; + int dma_buf_fd; + struct dma_buf *dma_buf; +#endif + u16 dsp_stx; + u16 dsp_sty; + u16 y_vir_stride; + u16 uv_vir_stride; + u32 y_addr; + u32 uv_addr; + + u8 fbdc_en; + u8 fbdc_cor_en; + u8 fbdc_data_format; + u8 fbdc_dsp_width_ratio; + u8 fbdc_fmt_cfg; + u16 fbdc_mb_vir_width; + u16 fbdc_mb_vir_height; + u16 fbdc_mb_width; + u16 fbdc_mb_height; + u16 fbdc_mb_xst; + u16 fbdc_mb_yst; + u16 fbdc_num_tiles; + u16 fbdc_cmp_index_init; +}; + + +struct rk_lcdc_win { + char name[5]; + int id; + struct rk_win_property property; + bool state; /*on or off*/ + bool last_state; /*on or off*/ + u32 pseudo_pal[16]; + int z_order; /*win sel layer*/ + u8 fmt_10; + u8 colorspace; + u32 reserved; + u32 area_num; + u32 scale_yrgb_x; + u32 scale_yrgb_y; + u32 scale_cbcr_x; + u32 scale_cbcr_y; + bool support_3d; + + u8 win_lb_mode; + + u8 bic_coe_el; + u8 yrgb_hor_scl_mode;//h 01:scale up ;10:down + u8 yrgb_ver_scl_mode;//v 01:scale up ;10:down + u8 yrgb_hsd_mode;//h scale down mode + u8 yrgb_vsu_mode;//v scale up mode + u8 yrgb_vsd_mode;//v scale down mode + u8 cbr_hor_scl_mode; + u8 cbr_ver_scl_mode; + u8 cbr_hsd_mode; + u8 cbr_vsu_mode; + u8 cbr_vsd_mode; + u8 vsd_yrgb_gt4; + u8 vsd_yrgb_gt2; + u8 vsd_cbr_gt4; + u8 vsd_cbr_gt2; + + u8 alpha_en; + u8 alpha_mode; + u16 g_alpha_val; + u32 color_key_val; + u8 csc_mode; + u8 xmirror; + u8 ymirror; + + struct rk_lcdc_win_area area[RK_WIN_MAX_AREA]; + struct rk_lcdc_post_cfg post_cfg; +}; + +struct rk_lcdc_driver; + +struct rk_fb_trsm_ops { + int (*enable)(void); + int (*disable)(void); + int (*dsp_pwr_on) (void); + int (*dsp_pwr_off) (void); + void (*refresh)(unsigned int xpos, unsigned int ypos, + unsigned int xsize, unsigned int ysize); +}; + +struct rk_lcdc_drv_ops { + int (*open) (struct rk_lcdc_driver *dev_drv, int layer_id, bool open); + int (*win_direct_en)(struct rk_lcdc_driver *dev_drv, int win_id, int en); + int (*init_lcdc) (struct rk_lcdc_driver *dev_drv); + int (*ioctl) (struct rk_lcdc_driver *dev_drv, unsigned int cmd, + unsigned long arg, int layer_id); + int (*suspend) (struct rk_lcdc_driver *dev_drv); + int (*resume) (struct rk_lcdc_driver *dev_drv); + int (*blank) (struct rk_lcdc_driver *dev_drv, int layer_id, + int blank_mode); + int (*set_par) (struct rk_lcdc_driver *dev_drv, int layer_id); + int (*pan_display) (struct rk_lcdc_driver *dev_drv, int layer_id); + int (*direct_set_addr)(struct rk_lcdc_driver *drv, int win_id, u32 addr); + int (*lcdc_reg_update) (struct rk_lcdc_driver *dev_drv); + ssize_t(*get_disp_info) (struct rk_lcdc_driver *dev_drv, char *buf, + int layer_id); + int (*load_screen) (struct rk_lcdc_driver *dev_drv, bool initscreen); + int (*get_dspbuf_info) (struct rk_lcdc_driver *dev_drv, + u16 *xact, u16 *yact, int *format, + u32 *dsp_addr, int *ymirror); + int (*post_dspbuf)(struct rk_lcdc_driver *dev_drv, u32 rgb_mst, + int format, u16 xact, u16 yact, u16 xvir, + int ymirror); + + int (*get_win_state) (struct rk_lcdc_driver *dev_drv, int layer_id, int area_id); + int (*ovl_mgr) (struct rk_lcdc_driver *dev_drv, int swap, bool set); /*overlay manager*/ + int (*fps_mgr) (struct rk_lcdc_driver *dev_drv, int fps, bool set); + int (*fb_get_win_id) (struct rk_lcdc_driver *dev_drv, const char *id); /*find layer for fb*/ + int (*fb_win_remap) (struct rk_lcdc_driver *dev_drv, + u16 fb_win_map_order); + int (*set_dsp_lut) (struct rk_lcdc_driver *dev_drv, int *lut); + int (*set_cabc_lut)(struct rk_lcdc_driver *dev_drv, int *lut); + int (*set_hwc_lut) (struct rk_lcdc_driver *dev_drv, int *hwc_lut, int mode); + int (*read_dsp_lut) (struct rk_lcdc_driver *dev_drv, int *lut); + int (*lcdc_hdmi_process) (struct rk_lcdc_driver *dev_drv, int mode); /*some lcdc need to some process in hdmi mode*/ + int (*set_irq_to_cpu)(struct rk_lcdc_driver *dev_drv,int enable); + int (*poll_vblank) (struct rk_lcdc_driver *dev_drv); + int (*lcdc_rst) (struct rk_lcdc_driver *dev_drv); + int (*dpi_open) (struct rk_lcdc_driver *dev_drv, bool open); + int (*dpi_win_sel) (struct rk_lcdc_driver *dev_drv, int layer_id); + int (*dpi_status) (struct rk_lcdc_driver *dev_drv); + int (*get_dsp_addr)(struct rk_lcdc_driver *dev_drv, unsigned int dsp_addr[][4]); + int (*set_dsp_cabc) (struct rk_lcdc_driver *dev_drv, int mode, int calc, int up, int down, int global); + int (*set_dsp_bcsh_hue) (struct rk_lcdc_driver *dev_drv,int sin_hue, int cos_hue); + int (*set_dsp_bcsh_bcs)(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode,int value); + int (*get_dsp_bcsh_hue) (struct rk_lcdc_driver *dev_drv,bcsh_hue_mode mode); + int (*get_dsp_bcsh_bcs)(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode); + int (*open_bcsh)(struct rk_lcdc_driver *dev_drv, bool open); + int (*set_screen_scaler) (struct rk_lcdc_driver *dev_drv, struct rk_screen *screen, bool enable); + int (*dump_reg) (struct rk_lcdc_driver *dev_drv); + int (*mmu_en) (struct rk_lcdc_driver *dev_drv); + int (*cfg_done) (struct rk_lcdc_driver *dev_drv); + int (*set_overscan) (struct rk_lcdc_driver *dev_drv, + struct overscan *overscan); + int (*dsp_black) (struct rk_lcdc_driver *dev_drv, int enable); + int (*backlight_close)(struct rk_lcdc_driver *dev_drv, int enable); + int (*area_support_num)(struct rk_lcdc_driver *dev_drv, unsigned int *area_support); + int (*extern_func)(struct rk_lcdc_driver *dev_drv, int cmd); + int (*wait_frame_start)(struct rk_lcdc_driver *dev_drv, int enable); + int (*set_wb)(struct rk_lcdc_driver *dev_drv); +}; + +struct rk_fb_area_par { + u8 data_format; /*layer data fmt*/ + short ion_fd; + u32 phy_addr; + short acq_fence_fd; + u16 x_offset; + u16 y_offset; + u16 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/ + u16 ypos; + u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/ + u16 ysize; + u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/ + u16 yact; + u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/ + u16 yvir; + u8 fbdc_en; + u8 fbdc_cor_en; + u8 fbdc_data_format; + u16 data_space; /* SDR or HDR */ + u32 reserved0; +}; + + +struct rk_fb_win_par { + u8 win_id; + u8 z_order; /*win sel layer*/ + u8 alpha_mode; + u16 g_alpha_val; + u8 mirror_en; + struct rk_fb_area_par area_par[RK_WIN_MAX_AREA]; + u32 reserved0; +}; + +struct rk_fb_win_cfg_data { + u8 wait_fs; + short ret_fence_fd; + short rel_fence_fd[RK_MAX_BUF_NUM]; + struct rk_fb_win_par win_par[RK30_MAX_LAYER_SUPPORT]; + struct rk_fb_wb_cfg wb_cfg; +}; + +struct rk_fb_reg_wb_data { + bool state; + u8 data_format; + struct ion_handle *ion_handle; + unsigned long smem_start; + unsigned long cbr_start; /*Cbr memory start address*/ + u16 xsize; + u16 ysize; +}; + +struct rk_fb_reg_area_data { + struct sync_fence *acq_fence; + u8 data_format; /*layer data fmt*/ + u8 data_space; /* indicate SDR or HDR */ + u8 index_buf; /*judge if the buffer is index*/ + u32 y_offset; /*yuv/rgb offset -->LCDC_WINx_YRGB_MSTx*/ + u32 c_offset; /*cb cr offset--->LCDC_WINx_CBR_MSTx*/ + u32 y_vir_stride; + u32 uv_vir_stride; + u32 buff_len; + u16 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/ + u16 ypos; + u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/ + u16 ysize; + u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/ + u16 yact; + u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/ + u16 yvir; + u16 xoff; /*mem offset*/ + u16 yoff; + unsigned long smem_start; + unsigned long cbr_start; /*Cbr memory start address*/ + u32 line_length; + struct ion_handle *ion_handle; +#ifdef USE_ION_MMU + struct dma_buf *dma_buf; + struct dma_buf_attachment *attachment; + struct sg_table *sg_table; + dma_addr_t dma_addr; +#endif + u8 fbdc_en; + u8 fbdc_cor_en; + u8 fbdc_data_format; +}; + +struct rk_fb_reg_win_data { + int win_id; + int z_order; /*win sel layer*/ + u32 area_num; /*maybe two region have the same dma buff,*/ + u32 area_buf_num; /*so area_num maybe not equal to area_buf_num*/ + u8 alpha_en; + u8 alpha_mode; + u16 g_alpha_val; + u8 mirror_en; + u8 colorspace; + + struct rk_fb_reg_area_data reg_area_data[RK_WIN_MAX_AREA]; +}; + +struct rk_fb_reg_data { + struct list_head list; + int win_num; + int buf_num; + int acq_num; + struct rk_fb_reg_win_data reg_win_data[RK30_MAX_LAYER_SUPPORT]; + struct rk_fb_reg_wb_data reg_wb_data; +}; + +struct rk_lcdc_driver { + char name[6]; + int te_irq; + int id; + int prop; + struct device *dev; + u32 version; + struct rk_vop_property property; + + struct rk_lcdc_win *win[RK_MAX_FB_SUPPORT]; + struct rk_fb_reg_wb_data wb_data; + int lcdc_win_num; + int num_buf; //the num_of buffer + int atv_layer_cnt; + int fb_index_base; //the first fb index of the lcdc device + struct rk_screen *screen0; //some platform have only one lcdc,but extend + struct rk_screen *screen1; //two display devices for dual display,such as rk2918,rk2928 + struct rk_screen *cur_screen; //screen0 is primary screen ,like lcd panel,screen1 is extend screen,like hdmi + u32 pixclock; + u16 rotate_mode; + u16 cabc_mode; + u16 overlay_mode; + u16 pre_overlay; + u16 output_color; + + u16 fb_win_map; + char fb0_win_id; + char fb1_win_id; + char fb2_win_id; + char fb3_win_id; + char fb4_win_id; + + char mmu_dts_name[40]; + struct device *mmu_dev; + int iommu_enabled; + int dsp_mode; + bool hot_plug_state; + + struct rk_fb_reg_area_data reg_area_data; + /* + * front_regs means this config is scaning on the devices. + */ + struct rk_fb_reg_data *front_regs; + struct mutex front_lock; + + struct mutex fb_win_id_mutex; + struct mutex win_config; + + struct mutex switch_screen; /*for switch screen*/ + struct completion frame_done; /*sync for pan_display,whe we set a new + frame address to lcdc register,we must + make sure the frame begain to display*/ + spinlock_t cpl_lock; /*lock for completion frame done */ + int first_frame; + struct rk_fb_vsync vsync_info; + struct rk_fb_frame_time frame_time; + int wait_fs; /*wait for new frame start in kernel */ + struct sw_sync_timeline *timeline; + int timeline_max; + int suspend_flag; + int shutdown_flag; + int standby; + struct list_head update_regs_list; + struct list_head saved_list; + struct mutex update_regs_list_lock; + struct kthread_worker update_regs_worker; + struct task_struct *update_regs_thread; + struct kthread_work update_regs_work; + wait_queue_head_t update_regs_wait; + + struct mutex output_lock; + struct rk29fb_info *screen_ctr_info; + struct list_head pwrlist_head; + struct rk_lcdc_drv_ops *ops; + struct rk_fb_trsm_ops *trsm_ops; +#ifdef CONFIG_DRM_ROCKCHIP + void (*irq_call_back)(struct rk_lcdc_driver *driver); +#endif + struct overscan overscan; + struct rk_lcdc_bcsh bcsh; + int *hwc_lut; + int uboot_logo; + int bcsh_init_status; + bool cabc_pwm_pol; + u8 reserved_fb; + /*1:hdmi switch uncomplete,0:complete*/ + bool hdmi_switch; + void *trace_buf; + struct rk_fb_win_cfg_data tmp_win_cfg[DUMP_FRAME_NUM]; + struct rk_fb_reg_data tmp_regs[DUMP_FRAME_NUM]; + unsigned int area_support[RK30_MAX_LAYER_SUPPORT]; +}; + +struct rk_fb_par { + int id; + u32 state; + + unsigned long fb_phy_base; /* Start of fb address (physical address) */ + char __iomem *fb_virt_base; /* Start of fb address (virt address) */ + u32 fb_size; + struct rk_lcdc_driver *lcdc_drv; + +#if defined(CONFIG_ION_ROCKCHIP) + struct ion_handle *ion_hdl; +#endif + u32 reserved[2]; +}; + +/*disp_mode: dual display mode +* NO_DUAL,no dual display, + ONE_DUAL,use one lcdc + rk61x for dual display + DUAL,use 2 lcdcs for dual display + num_fb: the total number of fb + num_lcdc: the total number of lcdc +*/ + +struct rk_fb { + int disp_mode; + int disp_policy; + struct rk29fb_info *mach_info; + struct fb_info *fb[RK_MAX_FB_SUPPORT*2]; + int num_fb; + struct rk_lcdc_driver *lcdc_dev_drv[RK30_MAX_LCDC_SUPPORT]; + int num_lcdc; + +#if defined(CONFIG_ION_ROCKCHIP) + struct ion_client *ion_client; +#endif +}; + +extern int rk_fb_trsm_ops_register(struct rk_fb_trsm_ops *ops, int type); +extern struct rk_fb_trsm_ops *rk_fb_trsm_ops_get(int type); +extern int rk_fb_register(struct rk_lcdc_driver *dev_drv, + struct rk_lcdc_win *win, int id); +extern int rk_fb_unregister(struct rk_lcdc_driver *dev_drv); +extern struct rk_lcdc_driver *rk_get_lcdc_drv(char *name); +extern int rk_fb_get_extern_screen(struct rk_screen *screen); +extern int rk_fb_set_vop_pwm(void); +extern int rk_fb_get_prmry_screen( struct rk_screen *screen); +extern int rk_fb_set_prmry_screen(struct rk_screen *screen); +extern u32 rk_fb_get_prmry_screen_pixclock(void); +extern int rk_disp_pwr_ctr_parse_dt(struct rk_lcdc_driver *dev_drv); +extern int rk_disp_pwr_enable(struct rk_lcdc_driver *dev_drv); +extern int rk_disp_pwr_disable(struct rk_lcdc_driver *dev_drv); +extern bool is_prmry_rk_lcdc_registered(void); +extern int rk_fb_prase_timing_dt(struct device_node *np, + struct rk_screen *screen); +extern int rk_disp_prase_timing_dt(struct rk_lcdc_driver *dev_drv); + +extern int rk_fb_dpi_open(bool open); +extern int rk_fb_dpi_layer_sel(int layer_id); +extern int rk_fb_dpi_status(void); + +extern int rk_fb_switch_screen(struct rk_screen *screen, int enable, int lcdc_id); +extern int rk_fb_disp_scale(u8 scale_x, u8 scale_y, u8 lcdc_id); +extern int rkfb_create_sysfs(struct fb_info *fbi); +extern char *get_format_string(enum data_format, char *fmt); +extern int support_uboot_display(void); +extern int rk_fb_calc_fps(struct rk_screen *screen, u32 pixclock); +extern int rk_get_real_fps(int time); +extern struct device *rk_fb_get_sysmmu_device_by_compatible(const char *compt); +extern void rk_fb_platform_set_sysmmu(struct device *sysmmu, + struct device *dev); +int rk_fb_get_display_policy(void); +int rk_fb_pixel_width(int data_format); +void trace_buffer_dump(struct device *dev, + struct rk_lcdc_driver *dev_drv); +int rk_fb_set_car_reverse_status(struct rk_lcdc_driver *dev_drv, int status); +extern int rockchip_get_screen_type(void); +#endif diff --git a/include/linux/rk_keys.h b/include/linux/rk_keys.h new file mode 100644 index 000000000000..aee656daf2c8 --- /dev/null +++ b/include/linux/rk_keys.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2016, Fuzhou Rockchip Electronics Co., Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _RK_KEYS_H +#define _RK_KEYS_H + +#ifdef CONFIG_KEYBOARD_ROCKCHIP +void rk_send_power_key(int state); +void rk_send_wakeup_key(void); +#else +static inline void rk_send_power_key(int state) { } +static inline void rk_send_wakeup_key(void) { } +#endif + +#endif diff --git a/include/linux/rk_screen.h b/include/linux/rk_screen.h new file mode 100644 index 000000000000..9800bb378a1e --- /dev/null +++ b/include/linux/rk_screen.h @@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _SCREEN_H +#define _SCREEN_H + +typedef enum _REFRESH_STAGE { + REFRESH_PRE = 0, + REFRESH_END, + +} REFRESH_STAGE; + + +typedef enum _MCU_IOCTL { + MCU_WRCMD = 0, + MCU_WRDATA, + MCU_SETBYPASS, + +} MCU_IOCTL; + + +typedef enum _MCU_STATUS { + MS_IDLE = 0, + MS_MCU, + MS_EBOOK, + MS_EWAITSTART, + MS_EWAITEND, + MS_EEND, + +} MCU_STATUS; + +struct rk29_fb_setting_info { + u8 data_num; + u8 vsync_en; + u8 den_en; + u8 mcu_fmk_en; + u8 disp_on_en; + u8 standby_en; +}; + +struct rk29lcd_info { + u32 lcd_id; + u32 txd_pin; + u32 clk_pin; + u32 cs_pin; + u32 reset_pin; + int (*io_init)(void); + int (*io_deinit)(void); + int (*io_enable)(void); + int (*io_disable)(void); +}; + +struct overscan { + unsigned char left; + unsigned char top; + unsigned char right; + unsigned char bottom; +}; + +/* Screen description +*type:LVDS,RGB,MIPI,MCU +*lvds_fromat:lvds data format,set it if the screen is lvds +*face:thi display output face,18bit,24bit,etc +*ft: the time need to display one frame time +*/ +struct rk_screen { + u16 type; + u16 refresh_mode; + u16 lvds_format; + u16 face; + u16 color_mode; + u8 data_space; + u8 lcdc_id; + u8 screen_id; + struct fb_videomode mode; + u32 post_dsp_stx; + u32 post_dsp_sty; + u32 post_xsize; + u32 post_ysize; + u16 x_mirror; + u16 y_mirror; + int interlace; + int pixelrepeat; //For 480i/576i format, pixel is repeated twice. + u16 width; + u16 height; + u8 ft; + int *dsp_lut; + int *cabc_lut; + int *cabc_gamma_base; + +#if defined(CONFIG_MFD_RK616) || defined(CONFIG_LCDC_RK312X) + u32 pll_cfg_val; //bellow are for jettaB + u32 frac; + u16 scl_vst; + u16 scl_hst; + u16 vif_vst; + u16 vif_hst; +#endif + u8 hdmi_resolution; + u8 mcu_wrperiod; + u8 mcu_usefmk; + u8 mcu_frmrate; + + u8 pin_hsync; + u8 pin_vsync; + u8 pin_den; + u8 pin_dclk; + + /* Swap rule */ + u8 swap_gb; + u8 swap_rg; + u8 swap_rb; + u8 swap_delta; + u8 swap_dumy; + +#if defined(CONFIG_MIPI_DSI) + /* MIPI DSI */ + u8 dsi_lane; + u8 dsi_video_mode; + u32 hs_tx_clk; +#endif + + int xpos; //horizontal display start position on the sceen ,then can be changed by application + int ypos; + int xsize; //horizontal and vertical display size on he screen,they can be changed by application + int ysize; + struct overscan overscan; + struct rk_screen *ext_screen; + /* Operation function*/ + int (*init)(void); + int (*standby)(u8 enable); + int (*refresh)(u8 arg); + int (*scandir)(u16 dir); + int (*disparea)(u8 area); + int (*sscreen_get)(struct rk_screen *screen, u8 resolution); + int (*sscreen_set)(struct rk_screen *screen, bool type);// 1: use scaler 0:bypass +}; + +struct rk29fb_info { + u32 fb_id; + int prop; //display device property,like PRMRY,EXTEND + u32 mcu_fmk_pin; + struct rk29lcd_info *lcd_info; + int (*io_init)(struct rk29_fb_setting_info *fb_setting); + int (*io_deinit)(void); + int (*io_enable)(void); + int (*io_disable)(void); + void (*set_screen_info)(struct rk_screen *screen, struct rk29lcd_info *lcd_info ); +}; + +extern void set_lcd_info(struct rk_screen *screen, struct rk29lcd_info *lcd_info); +extern size_t get_fb_size(u8 reserved_fb); + +extern void set_tv_info(struct rk_screen *screen); +extern void set_hdmi_info(struct rk_screen *screen); + +#endif diff --git a/include/linux/rockchip-iovmm.h b/include/linux/rockchip-iovmm.h new file mode 100644 index 000000000000..73e2ff159e86 --- /dev/null +++ b/include/linux/rockchip-iovmm.h @@ -0,0 +1,156 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_PLAT_IOVMM_H +#define __ASM_PLAT_IOVMM_H + +#include <linux/list.h> +#include <linux/atomic.h> +#include <linux/spinlock.h> + +#define IEP_IOMMU_COMPATIBLE_NAME "rockchip,iep_mmu" +#define VIP_IOMMU_COMPATIBLE_NAME "rockchip,vip_mmu" +#define ISP_IOMMU_COMPATIBLE_NAME "rockchip,isp_mmu" +#define ISP0_IOMMU_COMPATIBLE_NAME "rockchip,isp0_mmu" +#define ISP1_IOMMU_COMPATIBLE_NAME "rockchip,isp1_mmu" +#define VOPB_IOMMU_COMPATIBLE_NAME "rockchip,vopb_mmu" +#define VOPL_IOMMU_COMPATIBLE_NAME "rockchip,vopl_mmu" +#define VOP_IOMMU_COMPATIBLE_NAME "rockchip,vop_mmu" +#define HEVC_IOMMU_COMPATIBLE_NAME "rockchip,hevc_mmu" +#define VPU_IOMMU_COMPATIBLE_NAME "rockchip,vpu_mmu" +#define VDEC_IOMMU_COMPATIBLE_NAME "rockchip,vdec_mmu" + +enum rk_iommu_inttype { + IOMMU_PAGEFAULT, + IOMMU_BUSERROR, + IOMMU_FAULT_UNKNOWN, + IOMMU_FAULTS_NUM +}; + +struct iommu_drvdata; + +/* + * @itype: type of fault. + * @pgtable_base: the physical address of page table base. This is 0 if @itype + * is IOMMU_BUSERROR. + * @fault_addr: the device (virtual) address that the System MMU tried to + * translated. This is 0 if @itype is IOMMU_BUSERROR. + */ +typedef int (*rockchip_iommu_fault_handler_t)(struct device *dev, + enum rk_iommu_inttype itype, + unsigned long pgtable_base, + unsigned long fault_addr, + unsigned int statu + ); + + +struct scatterlist; +struct device; + +#ifdef CONFIG_RK_IOVMM + +int rockchip_iovmm_activate(struct device *dev); +void rockchip_iovmm_deactivate(struct device *dev); + +/* rockchip_iovmm_map() - Maps a list of physical memory chunks + * @dev: the owner of the IO address space where the mapping is created + * @sg: list of physical memory chunks to map + * @offset: length in bytes where the mapping starts + * @size: how much memory to map in bytes. @offset + @size must not exceed + * total size of @sg + * + * This function returns mapped IO address in the address space of @dev. + * Returns minus error number if mapping fails. + * Caller must check its return code with IS_ERROR_VALUE() if the function + * succeeded. + * + * The caller of this function must ensure that iovmm_cleanup() is not called + * while this function is called. + * + */ +dma_addr_t rockchip_iovmm_map(struct device *dev, struct scatterlist *sg, + off_t offset, size_t size); + +/* rockchip_iovmm_unmap() - unmaps the given IO address + * @dev: the owner of the IO address space where @iova belongs + * @iova: IO address that needs to be unmapped and freed. + * + * The caller of this function must ensure that iovmm_cleanup() is not called + * while this function is called. + */ +void rockchip_iovmm_unmap(struct device *dev, dma_addr_t iova); + +/* rockchip_iovmm_map_oto - create one to one mapping for the given physical address + * @dev: the owner of the IO address space to map + * @phys: physical address to map + * @size: size of the mapping to create + * + * This function return 0 if mapping is successful. Otherwise, minus error + * value. + */ +int rockchip_iovmm_map_oto(struct device *dev, phys_addr_t phys, size_t size); + +/* rockchip_iovmm_unmap_oto - remove one to one mapping + * @dev: the owner ofthe IO address space + * @phys: physical address to remove mapping + */ +void rockchip_iovmm_unmap_oto(struct device *dev, phys_addr_t phys); + +void rockchip_iovmm_set_fault_handler(struct device *dev, + rockchip_iommu_fault_handler_t handler); +/** rockchip_iovmm_set_fault_handler() - Fault handler for IOMMUs + * Called when interrupt occurred by the IOMMUs + * The device drivers of peripheral devices that has a IOMMU can implement + * a fault handler to resolve address translation fault by IOMMU. + * The meanings of return value and parameters are described below. + * + * return value: non-zero if the fault is correctly resolved. + * zero if the fault is not handled. + */ + +int rockchip_iovmm_invalidate_tlb(struct device *dev); +#else +static inline int rockchip_iovmm_activate(struct device *dev) +{ + return -ENOSYS; +} + +static inline void rockchip_iovmm_deactivate(struct device *dev) +{ +} + +static inline dma_addr_t rockchip_iovmm_map(struct device *dev, + struct scatterlist *sg, off_t offset, size_t size) +{ + return -ENOSYS; +} + +static inline void rockchip_iovmm_unmap(struct device *dev, dma_addr_t iova) +{ +} + +static inline int rockchip_iovmm_map_oto(struct device *dev, phys_addr_t phys, + size_t size) +{ + return -ENOSYS; +} + +static inline void rockchip_iovmm_unmap_oto(struct device *dev, phys_addr_t phys) +{ +} + +static inline void rockchip_iovmm_set_fault_handler(struct device *dev, + rockchip_iommu_fault_handler_t handler) +{ +} +static inline int rockchip_iovmm_invalidate_tlb(struct device *dev) +{ + return -ENOSYS; +} + +#endif /* CONFIG_RK_IOVMM */ + +#endif /*__ASM_PLAT_IOVMM_H*/ diff --git a/include/linux/rockchip/cpu.h b/include/linux/rockchip/cpu.h new file mode 100644 index 000000000000..554299351875 --- /dev/null +++ b/include/linux/rockchip/cpu.h @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2017 Rockchip Electronics Co. Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __LINUX_ROCKCHIP_CPU_H +#define __LINUX_ROCKCHIP_CPU_H + +#include <linux/of.h> + +#ifdef CONFIG_ROCKCHIP_CPUINFO + +extern unsigned long rockchip_soc_id; + +#define ROCKCHIP_CPU_VERION_MASK 0x0000f000 +#define ROCKCHIP_CPU_VERION_SHIFT 12 + +static inline unsigned long rockchip_get_cpu_version(void) +{ + return (rockchip_soc_id & ROCKCHIP_CPU_VERION_MASK) + >> ROCKCHIP_CPU_VERION_SHIFT; +} + +static inline void rockchip_set_cpu_version(unsigned long ver) +{ + rockchip_soc_id &= ~ROCKCHIP_CPU_VERION_MASK; + rockchip_soc_id |= + (ver << ROCKCHIP_CPU_VERION_SHIFT) & ROCKCHIP_CPU_VERION_MASK; +} + +#else + +#define rockchip_soc_id 0 + +static inline unsigned long rockchip_get_cpu_version(void) +{ + return 0; +} + +static inline void rockchip_set_cpu_version(unsigned long ver) +{ +} + +#endif + +#define ROCKCHIP_CPU_MASK 0xffff0000 +#define ROCKCHIP_CPU_RK312X 0x31260000 +#define ROCKCHIP_CPU_RK3288 0x32880000 +#define ROCKCHIP_CPU_RK3308 0x33080000 + +#ifdef CONFIG_CPU_RK312X +static inline bool cpu_is_rk312x(void) +{ + if (rockchip_soc_id) + return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK312X; + return of_machine_is_compatible("rockchip,rk3126") || + of_machine_is_compatible("rockchip,rk3126b") || + of_machine_is_compatible("rockchip,rk3126c") || + of_machine_is_compatible("rockchip,rk3128"); +} +#else +static inline bool cpu_is_rk312x(void) { return false; } +#endif + +#ifdef CONFIG_CPU_RK3288 +static inline bool cpu_is_rk3288(void) +{ + if (rockchip_soc_id) + return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3288; + return of_machine_is_compatible("rockchip,rk3288") || + of_machine_is_compatible("rockchip,rk3288w"); +} +#else +static inline bool cpu_is_rk3288(void) { return false; } +#endif + +#ifdef CONFIG_CPU_RK3308 +static inline bool cpu_is_rk3308(void) +{ + if (rockchip_soc_id) + return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3308; + + return of_machine_is_compatible("rockchip,rk3308"); +} +#else +static inline bool cpu_is_rk3308(void) { return false; } +#endif + +#define ROCKCHIP_SOC_MASK (ROCKCHIP_CPU_MASK | 0xff) +#define ROCKCHIP_SOC_RK3126 (ROCKCHIP_CPU_RK312X | 0x00) +#define ROCKCHIP_SOC_RK3126B (ROCKCHIP_CPU_RK312X | 0x10) +#define ROCKCHIP_SOC_RK3126C (ROCKCHIP_CPU_RK312X | 0x20) +#define ROCKCHIP_SOC_RK3128 (ROCKCHIP_CPU_RK312X | 0x01) +#define ROCKCHIP_SOC_RK3288 (ROCKCHIP_CPU_RK3288 | 0x00) +#define ROCKCHIP_SOC_RK3288W (ROCKCHIP_CPU_RK3288 | 0x01) +#define ROCKCHIP_SOC_RK3308 (ROCKCHIP_CPU_RK3308 | 0x00) +#define ROCKCHIP_SOC_RK3308B (ROCKCHIP_CPU_RK3308 | 0x01) + +#define ROCKCHIP_SOC(id, ID) \ +static inline bool soc_is_##id(void) \ +{ \ + if (rockchip_soc_id) \ + return ((rockchip_soc_id & ROCKCHIP_SOC_MASK) == ROCKCHIP_SOC_ ##ID); \ + return of_machine_is_compatible("rockchip,"#id); \ +} + +ROCKCHIP_SOC(rk3126, RK3126) +ROCKCHIP_SOC(rk3126b, RK3126B) +ROCKCHIP_SOC(rk3126c, RK3126C) +ROCKCHIP_SOC(rk3128, RK3128) +ROCKCHIP_SOC(rk3288, RK3288) +ROCKCHIP_SOC(rk3288w, RK3288W) +ROCKCHIP_SOC(rk3308, RK3308) +ROCKCHIP_SOC(rk3308b, RK3308B) + +#endif diff --git a/include/linux/rockchip/grf.h b/include/linux/rockchip/grf.h new file mode 100644 index 000000000000..fae51232297c --- /dev/null +++ b/include/linux/rockchip/grf.h @@ -0,0 +1,700 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __MACH_ROCKCHIP_GRF_H +#define __MACH_ROCKCHIP_GRF_H + +#define RK3188_GRF_GPIO0L_DIR 0x0000 +#define RK3188_GRF_GPIO0H_DIR 0x0004 +#define RK3188_GRF_GPIO1L_DIR 0x0008 +#define RK3188_GRF_GPIO1H_DIR 0x000c +#define RK3188_GRF_GPIO2L_DIR 0x0010 +#define RK3188_GRF_GPIO2H_DIR 0x0014 +#define RK3188_GRF_GPIO3L_DIR 0x0018 +#define RK3188_GRF_GPIO3H_DIR 0x001c +#define RK3188_GRF_GPIO0L_DO 0x0020 +#define RK3188_GRF_GPIO0H_DO 0x0024 +#define RK3188_GRF_GPIO1L_DO 0x0028 +#define RK3188_GRF_GPIO1H_DO 0x002c +#define RK3188_GRF_GPIO2L_DO 0x0030 +#define RK3188_GRF_GPIO2H_DO 0x0034 +#define RK3188_GRF_GPIO3L_DO 0x0038 +#define RK3188_GRF_GPIO3H_DO 0x003c +#define RK3188_GRF_GPIO0L_EN 0x0040 +#define RK3188_GRF_GPIO0H_EN 0x0044 +#define RK3188_GRF_GPIO1L_EN 0x0048 +#define RK3188_GRF_GPIO1H_EN 0x004c +#define RK3188_GRF_GPIO2L_EN 0x0050 +#define RK3188_GRF_GPIO2H_EN 0x0054 +#define RK3188_GRF_GPIO3L_EN 0x0058 +#define RK3188_GRF_GPIO3H_EN 0x005c + +#define RK3188_GRF_GPIO0C_IOMUX 0x0068 +#define RK3188_GRF_GPIO0D_IOMUX 0x006c +#define RK3188_GRF_GPIO1A_IOMUX 0x0070 +#define RK3188_GRF_GPIO1B_IOMUX 0x0074 +#define RK3188_GRF_GPIO1C_IOMUX 0x0078 +#define RK3188_GRF_GPIO1D_IOMUX 0x007c +#define RK3188_GRF_GPIO2A_IOMUX 0x0080 +#define RK3188_GRF_GPIO2B_IOMUX 0x0084 +#define RK3188_GRF_GPIO2C_IOMUX 0x0088 +#define RK3188_GRF_GPIO2D_IOMUX 0x008c +#define RK3188_GRF_GPIO3A_IOMUX 0x0090 +#define RK3188_GRF_GPIO3B_IOMUX 0x0094 +#define RK3188_GRF_GPIO3C_IOMUX 0x0098 +#define RK3188_GRF_GPIO3D_IOMUX 0x009c +#define RK3188_GRF_SOC_CON0 0x00a0 +#define RK3188_GRF_SOC_CON1 0x00a4 +#define RK3188_GRF_SOC_CON2 0x00a8 +#define RK3188_GRF_SOC_STATUS0 0x00ac +#define RK3188_GRF_DMAC1_CON0 0x00b0 +#define RK3188_GRF_DMAC1_CON1 0x00b4 +#define RK3188_GRF_DMAC1_CON2 0x00b8 +#define RK3188_GRF_DMAC2_CON0 0x00bc +#define RK3188_GRF_DMAC2_CON1 0x00c0 +#define RK3188_GRF_DMAC2_CON2 0x00c4 +#define RK3188_GRF_DMAC2_CON3 0x00c8 +#define RK3188_GRF_CPU_CON0 0x00cc +#define RK3188_GRF_CPU_CON1 0x00d0 +#define RK3188_GRF_CPU_CON2 0x00d4 +#define RK3188_GRF_CPU_CON3 0x00d8 +#define RK3188_GRF_CPU_CON4 0x00dc +#define RK3188_GRF_CPU_CON5 0x00e0 + +#define RK3188_GRF_DDRC_CON0 0x00ec +#define RK3188_GRF_DDRC_STAT 0x00f0 +#define RK3188_GRF_IO_CON0 0x00f4 +#define RK3188_GRF_IO_CON1 0x00f8 +#define RK3188_GRF_IO_CON2 0x00fc +#define RK3188_GRF_IO_CON3 0x0100 +#define RK3188_GRF_IO_CON4 0x0104 +#define RK3188_GRF_SOC_STATUS1 0x0108 +#define RK3188_GRF_UOC0_CON0 0x010c +#define RK3188_GRF_UOC0_CON1 0x0110 +#define RK3188_GRF_UOC0_CON2 0x0114 +#define RK3188_GRF_UOC0_CON3 0x0118 +#define RK3188_GRF_UOC1_CON0 0x011c +#define RK3188_GRF_UOC1_CON1 0x0120 +#define RK3188_GRF_UOC1_CON2 0x0124 +#define RK3188_GRF_UOC1_CON3 0x0128 +#define RK3188_GRF_UOC2_CON0 0x012c +#define RK3188_GRF_UOC2_CON1 0x0130 + +#define RK3188_GRF_UOC3_CON0 0x0138 +#define RK3188_GRF_UOC3_CON1 0x013c +#define RK3188_GRF_EHCI_STAT 0x0140 +#define RK3188_GRF_OS_REG0 0x0144 +#define RK3188_GRF_OS_REG1 0x0148 +#define RK3188_GRF_OS_REG2 0x014c +#define RK3188_GRF_OS_REG3 0x0150 +#define RK3188_GRF_OS_REG4 0x0154 +#define RK3188_GRF_OS_REG5 0x0158 +#define RK3188_GRF_OS_REG6 0x015c +#define RK3188_GRF_OS_REG7 0x0160 +#define RK3188_GRF_GPIO0B_PULL 0x0164 +#define RK3188_GRF_GPIO0C_PULL 0x0168 +#define RK3188_GRF_GPIO0D_PULL 0x016c +#define RK3188_GRF_GPIO1A_PULL 0x0170 +#define RK3188_GRF_GPIO1B_PULL 0x0174 +#define RK3188_GRF_GPIO1C_PULL 0x0178 +#define RK3188_GRF_GPIO1D_PULL 0x017c +#define RK3188_GRF_GPIO2A_PULL 0x0180 +#define RK3188_GRF_GPIO2B_PULL 0x0184 +#define RK3188_GRF_GPIO2C_PULL 0x0188 +#define RK3188_GRF_GPIO2D_PULL 0x018c +#define RK3188_GRF_GPIO3A_PULL 0x0190 +#define RK3188_GRF_GPIO3B_PULL 0x0194 +#define RK3188_GRF_GPIO3C_PULL 0x0198 +#define RK3188_GRF_GPIO3D_PULL 0x019c +#define RK3188_GRF_FLASH_DATA_PULL 0x01a0 +#define RK3188_GRF_FLASH_CMD_PULL 0x01a4 + + +#define RK3288_GRF_GPIO0_A_IOMUX 0x0084 +#define RK3288_GRF_GPIO0_B_IOMUX 0x0088 +#define RK3288_GRF_GPIO0_C_IOMUX 0x008c + +#define RK3288_GRF_GPIO1D_IOMUX 0x000c +#define RK3288_GRF_GPIO2A_IOMUX 0x0010 +#define RK3288_GRF_GPIO2B_IOMUX 0x0014 +#define RK3288_GRF_GPIO2C_IOMUX 0x0018 + +#define RK3288_GRF_GPIO3A_IOMUX 0x0020 +#define RK3288_GRF_GPIO3B_IOMUX 0x0024 +#define RK3288_GRF_GPIO3C_IOMUX 0x0028 +#define RK3288_GRF_GPIO3DL_IOMUX 0x002c +#define RK3288_GRF_GPIO3DH_IOMUX 0x0030 +#define RK3288_GRF_GPIO4AL_IOMUX 0x0034 +#define RK3288_GRF_GPIO4AH_IOMUX 0x0038 +#define RK3288_GRF_GPIO4BL_IOMUX 0x003c + +#define RK3288_GRF_GPIO4C_IOMUX 0x0044 +#define RK3288_GRF_GPIO4D_IOMUX 0x0048 + +#define RK3288_GRF_GPIO5B_IOMUX 0x0050 +#define RK3288_GRF_GPIO5C_IOMUX 0x0054 + +#define RK3288_GRF_GPIO6A_IOMUX 0x005c +#define RK3288_GRF_GPIO6B_IOMUX 0x0060 +#define RK3288_GRF_GPIO6C_IOMUX 0x0064 + +#define RK3288_GRF_GPIO7A_IOMUX 0x006c +#define RK3288_GRF_GPIO7B_IOMUX 0x0070 +#define RK3288_GRF_GPIO7CL_IOMUX 0x0074 +#define RK3288_GRF_GPIO7CH_IOMUX 0x0078 + +#define RK3288_GRF_GPIO8A_IOMUX 0x0080 +#define RK3288_GRF_GPIO8B_IOMUX 0x0084 + +#define RK3288_GRF_GPIO1H_SR 0x0104 +#define RK3288_GRF_GPIO2L_SR 0x0108 +#define RK3288_GRF_GPIO2H_SR 0x010c +#define RK3288_GRF_GPIO3L_SR 0x0110 +#define RK3288_GRF_GPIO3H_SR 0x0114 +#define RK3288_GRF_GPIO4L_SR 0x0118 +#define RK3288_GRF_GPIO4H_SR 0x011c +#define RK3288_GRF_GPIO5L_SR 0x0120 +#define RK3288_GRF_GPIO5H_SR 0x0124 +#define RK3288_GRF_GPIO6L_SR 0x0128 +#define RK3288_GRF_GPIO6H_SR 0x012c +#define RK3288_GRF_GPIO7L_SR 0x0130 +#define RK3288_GRF_GPIO7H_SR 0x0134 +#define RK3288_GRF_GPIO8L_SR 0x0138 + +#define RK3288_GRF_GPIO1D_P 0x014c +#define RK3288_GRF_GPIO2A_P 0x0150 +#define RK3288_GRF_GPIO2B_P 0x0154 +#define RK3288_GRF_GPIO2C_P 0x0158 + +#define RK3288_GRF_GPIO3A_P 0x0160 +#define RK3288_GRF_GPIO3B_P 0x0164 +#define RK3288_GRF_GPIO3C_P 0x0168 +#define RK3288_GRF_GPIO3D_P 0x016c +#define RK3288_GRF_GPIO4A_P 0x0170 +#define RK3288_GRF_GPIO4B_P 0x0174 +#define RK3288_GRF_GPIO4C_P 0x0178 +#define RK3288_GRF_GPIO4D_P 0x017c + +#define RK3288_GRF_GPIO5B_P 0x0184 +#define RK3288_GRF_GPIO5C_P 0x0188 + +#define RK3288_GRF_GPIO6A_P 0x0190 +#define RK3288_GRF_GPIO6B_P 0x0194 +#define RK3288_GRF_GPIO6C_P 0x0198 + +#define RK3288_GRF_GPIO7A_P 0x01a0 +#define RK3288_GRF_GPIO7B_P 0x01a4 +#define RK3288_GRF_GPIO7C_P 0x01a8 + +#define RK3288_GRF_GPIO8A_P 0x01b0 +#define RK3288_GRF_GPIO8B_P 0x01b4 + +#define RK3288_GRF_GPIO1D_E 0x01cc +#define RK3288_GRF_GPIO2A_E 0x01d0 +#define RK3288_GRF_GPIO2B_E 0x01d4 +#define RK3288_GRF_GPIO2C_E 0x01d8 + +#define RK3288_GRF_GPIO3A_E 0x01e0 +#define RK3288_GRF_GPIO3B_E 0x01e4 +#define RK3288_GRF_GPIO3C_E 0x01e8 +#define RK3288_GRF_GPIO3D_E 0x01ec +#define RK3288_GRF_GPIO4A_E 0x01f0 +#define RK3288_GRF_GPIO4B_E 0x01f4 +#define RK3288_GRF_GPIO4C_E 0x01f8 +#define RK3288_GRF_GPIO4D_E 0x01fc + +#define RK3288_GRF_GPIO5B_E 0x0204 +#define RK3288_GRF_GPIO5C_E 0x0208 + +#define RK3288_GRF_GPIO6A_E 0x0210 +#define RK3288_GRF_GPIO6B_E 0x0214 +#define RK3288_GRF_GPIO6C_E 0x0218 + +#define RK3288_GRF_GPIO7A_E 0x0220 +#define RK3288_GRF_GPIO7B_E 0x0224 +#define RK3288_GRF_GPIO7C_E 0x0228 + +#define RK3288_GRF_GPIO8A_E 0x0230 +#define RK3288_GRF_GPIO8B_E 0x0234 + +#define RK3288_GRF_GPIO_SMT 0x0240 +#define RK3288_GRF_SOC_CON0 0x0244 +#define RK3288_GRF_SOC_CON1 0x0248 +#define RK3288_GRF_SOC_CON2 0x024c +#define RK3288_GRF_SOC_CON3 0x0250 +#define RK3288_GRF_SOC_CON4 0x0254 +#define RK3288_GRF_SOC_CON5 0x0258 +#define RK3288_GRF_SOC_CON6 0x025c +#define RK3288_GRF_SOC_CON7 0x0260 +#define RK3288_GRF_SOC_CON8 0x0264 +#define RK3288_GRF_SOC_CON9 0x0268 +#define RK3288_GRF_SOC_CON10 0x026c +#define RK3288_GRF_SOC_CON11 0x0270 +#define RK3288_GRF_SOC_CON12 0x0274 +#define RK3288_GRF_SOC_CON13 0x0278 +#define RK3288_GRF_SOC_CON14 0x027c +#define RK3288_GRF_SOC_STATUS0 0x0280 +#define RK3288_GRF_SOC_STATUS1 0x0284 +#define RK3288_GRF_SOC_STATUS2 0x0288 +#define RK3288_GRF_SOC_STATUS3 0x028c +#define RK3288_GRF_SOC_STATUS4 0x0290 +#define RK3288_GRF_SOC_STATUS5 0x0294 +#define RK3288_GRF_SOC_STATUS6 0x0298 +#define RK3288_GRF_SOC_STATUS7 0x029c +#define RK3288_GRF_SOC_STATUS8 0x02a0 +#define RK3288_GRF_SOC_STATUS9 0x02a4 +#define RK3288_GRF_SOC_STATUS10 0x02a8 +#define RK3288_GRF_SOC_STATUS11 0x02ac +#define RK3288_GRF_SOC_STATUS12 0x02b0 +#define RK3288_GRF_SOC_STATUS13 0x02b4 +#define RK3288_GRF_SOC_STATUS14 0x02b8 +#define RK3288_GRF_SOC_STATUS15 0x02bc +#define RK3288_GRF_SOC_STATUS16 0x02c0 +#define RK3288_GRF_SOC_STATUS17 0x02c4 +#define RK3288_GRF_SOC_STATUS18 0x02c8 +#define RK3288_GRF_SOC_STATUS19 0x02cc +#define RK3288_GRF_SOC_STATUS20 0x02d0 +#define RK3288_GRF_SOC_STATUS21 0x02d4 + +#define RK3288_GRF_PERIDMAC_CON0 0x02e0 +#define RK3288_GRF_PERIDMAC_CON1 0x02e4 +#define RK3288_GRF_PERIDMAC_CON2 0x02e8 +#define RK3288_GRF_PERIDMAC_CON3 0x02ec +#define RK3288_GRF_DDRC0_CON0 0x02f0 +#define RK3288_GRF_DDRC1_CON0 0x02f4 +#define RK3288_GRF_CPU_CON0 0x02f8 +#define RK3288_GRF_CPU_CON1 0x02fc +#define RK3288_GRF_CPU_CON2 0x0300 +#define RK3288_GRF_CPU_CON3 0x0304 +#define RK3288_GRF_CPU_CON4 0x0308 + +#define RK3288_GRF_CPU_STATUS0 0x0318 + +#define RK3288_GRF_UOC0_CON0 0x0320 +#define RK3288_GRF_UOC0_CON1 0x0324 +#define RK3288_GRF_UOC0_CON2 0x0328 +#define RK3288_GRF_UOC0_CON3 0x032c +#define RK3288_GRF_UOC0_CON4 0x0330 +#define RK3288_GRF_UOC1_CON0 0x0334 +#define RK3288_GRF_UOC1_CON1 0x0338 +#define RK3288_GRF_UOC1_CON2 0x033c +#define RK3288_GRF_UOC1_CON3 0x0340 +#define RK3288_GRF_UOC1_CON4 0x0344 +#define RK3288_GRF_UOC2_CON0 0x0348 +#define RK3288_GRF_UOC2_CON1 0x034c +#define RK3288_GRF_UOC2_CON2 0x0350 +#define RK3288_GRF_UOC2_CON3 0x0354 +#define RK3288_GRF_UOC3_CON0 0x0358 +#define RK3288_GRF_UOC3_CON1 0x035c +#define RK3288_GRF_UOC4_CON0 0x0360 +#define RK3288_GRF_UOC4_CON1 0x0364 +#define RK3288_GRF_PVTM_CON0 0x0368 +#define RK3288_GRF_PVTM_CON1 0x036c +#define RK3288_GRF_PVTM_CON2 0x0370 +#define RK3288_GRF_PVTM_STATUS0 0x0374 +#define RK3288_GRF_PVTM_STATUS1 0x0378 +#define RK3288_GRF_PVTM_STATUS2 0x037c +#define RK3288_GRF_IO_VSEL 0x0380 +#define RK3288_GRF_SARADC_TESTBIT 0x0384 +#define RK3288_GRF_TSADC_TESTBIT_L 0x0388 +#define RK3288_GRF_TSADC_TESTBIT_H 0x038c +#define RK3288_GRF_OS_REG0 0x0390 +#define RK3288_GRF_OS_REG1 0x0394 +#define RK3288_GRF_OS_REG2 0x0398 +#define RK3288_GRF_OS_REG3 0x039c + +#define RK3288_GRF_SOC_CON15 0x03a4 +#define RK3288_GRF_SOC_CON16 0x03a8 + +#define RK3288_SGRF_SOC_CON0 0x0000 +#define RK3288_SGRF_SOC_CON1 0x0004 +#define RK3288_SGRF_SOC_CON2 0x0008 +#define RK3288_SGRF_SOC_CON3 0x000c +#define RK3288_SGRF_SOC_CON4 0x0010 +#define RK3288_SGRF_SOC_CON5 0x0014 + +#define RK3288_SGRF_BUSDMAC_CON0 0x0020 +#define RK3288_SGRF_BUSDMAC_CON1 0x0024 + +#define RK3288_SGRF_CPU_CON0 0x0040 +#define RK3288_SGRF_CPU_CON1 0x0044 +#define RK3288_SGRF_CPU_CON2 0x0048 + +#define RK3288_SGRF_SOC_CON6 0x0050 +#define RK3288_SGRF_SOC_CON7 0x0054 +#define RK3288_SGRF_SOC_CON8 0x0058 +#define RK3288_SGRF_SOC_CON9 0x005c +#define RK3288_SGRF_SOC_CON10 0x0060 +#define RK3288_SGRF_SOC_CON11 0x0064 +#define RK3288_SGRF_SOC_CON12 0x0068 +#define RK3288_SGRF_SOC_CON13 0x006c +#define RK3288_SGRF_SOC_CON14 0x0070 +#define RK3288_SGRF_SOC_CON15 0x0074 +#define RK3288_SGRF_SOC_CON16 0x0078 +#define RK3288_SGRF_SOC_CON17 0x007c +#define RK3288_SGRF_SOC_CON18 0x0080 +#define RK3288_SGRF_SOC_CON19 0x0084 +#define RK3288_SGRF_SOC_CON20 0x0088 +#define RK3288_SGRF_SOC_CON21 0x008c + +#define RK3288_SGRF_SOC_STATUS0 0x0100 +#define RK3288_SGRF_SOC_STATUS1 0x0104 + +#define RK3288_SGRF_FAST_BOOT_ADDR 0x0120 + + +#define RK3036_GRF_GPIO0A_IOMUX 0x000a8 +#define RK3036_GRF_GPIO0B_IOMUX 0x000ac +#define RK3036_GRF_GPIO0C_IOMUX 0x000b0 +#define RK3036_GRF_GPIO0D_IOMUX 0x000b4 +#define RK3036_GRF_GPIO1A_IOMUX 0x000b8 +#define RK3036_GRF_GPIO1B_IOMUX 0x000bc +#define RK3036_GRF_GPIO1C_IOMUX 0x000c0 +#define RK3036_GRF_GPIO1D_IOMUX 0x000c4 +#define RK3036_GRF_GPIO2A_IOMUX 0x000c8 +#define RK3036_GRF_GPIO2B_IOMUX 0x000cc +#define RK3036_GRF_GPIO2C_IOMUX 0x000d0 +#define RK3036_GRF_GPIO2D_IOMUX 0x000d4 +#define RK3036_GRF_GPIO_DS 0x00100 +#define RK3036_GRF_GPIO0L_PULL 0x00118 +#define RK3036_GRF_GPIO0H_PULL 0x0011c +#define RK3036_GRF_GPIO1L_PULL 0x00120 +#define RK3036_GRF_GPIO1H_PULL 0x00124 + +#define RK3036_GRF_GPIO2L_PULL 0x00128 +#define RK3036_GRF_GPIO2H_PULL 0x0012c +#define RK3036_GRF_SOC_CON0 0x00140 +#define RK3036_GRF_SOC_CON1 0x00144 +#define RK3036_GRF_SOC_CON2 0x00148 +#define RK3036_GRF_SOC_STATUS0 0x0014c +#define RK3036_GRF_SOC_CON3 0x00154 +#define RK3036_GRF_DMAC_CON0 0x0015c +#define RK3036_GRF_DMAC_CON1 0x00160 +#define RK3036_GRF_DMAC_CON2 0x00164 +#define RK3036_GRF_UOC0_CON5 0x0017c +#define RK3036_GRF_UOC1_CON4 0x00190 +#define RK3036_GRF_UOC1_CON5 0x00194 +#define RK3036_GRF_DDRC_STAT 0x0019c +#define RK3036_GRF_UOC_CON6 0x001a0 +#define RK3036_GRF_SOC_STATUS1 0x001a4 +#define RK3036_GRF_CPU_CON0 0x001a8 +#define RK3036_GRF_CPU_CON1 0x001ac +#define RK3036_GRF_CPU_CON2 0x001b0 +#define RK3036_GRF_CPU_CON3 0x001b4 +#define RK3036_GRF_CPU_STATUS0 0x001c0 +#define RK3036_GRF_CPU_STATUS1 0x001c4 +#define RK3036_GRF_OS_REG0 0x001c8 +#define RK3036_GRF_OS_REG1 0x001cc +#define RK3036_GRF_OS_REG2 0x001d0 +#define RK3036_GRF_OS_REG3 0x001d4 +#define RK3036_GRF_OS_REG4 0x001d8 +#define RK3036_GRF_OS_REG5 0x001dc +#define RK3036_GRF_OS_REG6 0x001e0 +#define RK3036_GRF_OS_REG7 0x001e4 +#define RK3036_GRF_DLL_CON0 0x00200 +#define RK3036_GRF_DLL_CON1 0x00204 +#define RK3036_GRF_DLL_CON2 0x00208 +#define RK3036_GRF_DLL_CON3 0x0020c +#define RK3036_GRF_DLL_STATUS0 0x00210 +#define RK3036_GRF_DLL_STATUS1 0x00214 + +#define RK3036_GRF_DLL_STATUS2 0x00218 +#define RK3036_GRF_DLL_STATUS3 0x0021c +#define RK3036_GRF_DFI_WRNUM 0x00220 +#define RK3036_GRF_DFI_RDNUM 0x00224 +#define RK3036_GRF_DFI_ACTNUM 0x00228 +#define RK3036_GRF_DFI_TIMERVAL 0x0022c +#define RK3036_GRF_NIF_FIFO0 0x00230 +#define RK3036_GRF_NIF_FIFO1 0x00234 +#define RK3036_GRF_NIF_FIFO2 0x00238 +#define RK3036_GRF_NIF_FIFO3 0x0023c +#define RK3036_GRF_USBPHY0_CON0 0x00280 +#define RK3036_GRF_USBPHY0_CON1 0x00284 +#define RK3036_GRF_USBPHY0_CON2 0x00288 +#define RK3036_GRF_USBPHY0_CON3 0x0028c +#define RK3036_GRF_USBPHY0_CON4 0x00290 +#define RK3036_GRF_USBPHY0_CON5 0x00294 +#define RK3036_GRF_USBPHY0_CON6 0x00298 +#define RK3036_GRF_USBPHY0_CON7 0x0029c +#define RK3036_GRF_USBPHY1_CON0 0x002a0 +#define RK3036_GRF_USBPHY1_CON1 0x002a4 +#define RK3036_GRF_USBPHY1_CON2 0x002a8 +#define RK3036_GRF_USBPHY1_CON3 0x002ac +#define RK3036_GRF_USBPHY1_CON4 0x002b0 +#define RK3036_GRF_USBPHY1_CON5 0x002b4 +#define RK3036_GRF_USBPHY1_CON6 0x002b8 + +#define RK3036_GRF_USBPHY1_CON7 0x002bc +#define RK3036_GRF_CHIP_TAG 0x00300 +#define RK3036_GRF_SDMMC_DET_CNT 0x00304 + +#define RK312X_GRF_GPIO0A_IOMUX 0x000a8 +#define RK312X_GRF_GPIO0B_IOMUX 0x000ac +#define RK312X_GRF_GPIO0C_IOMUX 0x000b0 +#define RK312X_GRF_GPIO0D_IOMUX 0x000b4 +#define RK312X_GRF_GPIO1A_IOMUX 0x000b8 +#define RK312X_GRF_GPIO1B_IOMUX 0x000bc +#define RK312X_GRF_GPIO1C_IOMUX 0x000c0 +#define RK312X_GRF_GPIO1D_IOMUX 0x000c4 +#define RK312X_GRF_GPIO2A_IOMUX 0x000c8 +#define RK312X_GRF_GPIO2B_IOMUX 0x000cc +#define RK312X_GRF_GPIO2C_IOMUX 0x000d0 +#define RK312X_GRF_GPIO2D_IOMUX 0x000d4 +#define RK312X_GRF_GPIO3A_IOMUX 0x000d8 +#define RK312X_GRF_GPIO3B_IOMUX 0x000dc +#define RK312X_GRF_GPIO3C_IOMUX 0x000e0 +#define RK312X_GRF_GPIO3D_IOMUX 0x000e4 +#define RK312X_GRF_CIF_IOMUX 0x000ec +#define RK312X_GRF_CIF_IOMUX1 0x000f0 +#define RK312X_GRF_GPIO_DS 0x00100 +#define RK312X_GRF_GPIO0L_PULL 0x00118 +#define RK312X_GRF_GPIO0H_PULL 0x0011c +#define RK312X_GRF_GPIO1L_PULL 0x00120 +#define RK312X_GRF_GPIO1H_PULL 0x00124 +#define RK312X_GRF_GPIO2L_PULL 0x00128 +#define RK312X_GRF_GPIO2H_PULL 0x0012c +#define RK312X_GRF_GPIO3L_PULL 0x00130 +#define RK312X_GRF_GPIO3H_PULL 0x00134 +#define RK312X_GRF_ACODEC_CON 0x0013c + +#define RK312X_GRF_SOC_CON0 0x00140 +#define RK312X_GRF_SOC_CON1 0x00144 +#define RK312X_GRF_SOC_CON2 0x00148 +#define RK312X_GRF_SOC_STATUS0 0x0014c +#define RK312X_GRF_LVDS_CON0 0x00150 +#define RK312X_GRF_SOC_CON3 0x00154 +#define RK312X_GRF_DMAC_CON0 0x0015c +#define RK312X_GRF_DMAC_CON1 0x00160 +#define RK312X_GRF_DMAC_CON2 0x00164 +#define RK312X_GRF_MAC_CON0 0x00168 +#define RK312X_GRF_MAC_CON1 0x0016c +#define RK312X_GRF_TVE_CON 0x00170 +#define RK312X_GRF_UOC0_CON0 0x0017c +#define RK312X_GRF_UOC1_CON1 0x00184 +#define RK312X_GRF_UOC1_CON2 0x00188 +#define RK312X_GRF_UOC1_CON3 0x0018c +#define RK312X_GRF_UOC1_CON4 0x00190 +#define RK312X_GRF_UOC1_CON5 0x00194 +#define RK312X_GRF_DDRC_STAT 0x0019c +#define RK312X_GRF_SOC_STATUS1 0x001a4 +#define RK312X_GRF_CPU_CON0 0x001a8 +#define RK312X_GRF_CPU_CON1 0x001ac +#define RK312X_GRF_CPU_CON2 0x001b0 +#define RK312X_GRF_CPU_CON3 0x001b4 +#define RK312X_GRF_CPU_STATUS0 0x001c0 +#define RK312X_GRF_CPU_STATUS1 0x001c4 +#define RK312X_GRF_OS_REG0 0x001c8 +#define RK312X_GRF_OS_REG1 0x001cc +#define RK312X_GRF_OS_REG2 0x001d0 +#define RK312X_GRF_OS_REG3 0x001d4 +#define RK312X_GRF_OS_REG4 0x001d8 +#define RK312X_GRF_OS_REG5 0x001dc +#define RK312X_GRF_OS_REG6 0x001e0 +#define RK312X_GRF_OS_REG7 0x001e4 +#define RK312X_GRF_PVTM_CON0 0x00200 +#define RK312X_GRF_PVTM_CON1 0x00204 +#define RK312X_GRF_PVTM_CON2 0x00208 +#define RK312X_GRF_PVTM_CON3 0x0020c +#define RK312X_GRF_PVTM_STATUS0 0x00210 +#define RK312X_GRF_PVTM_STATUS1 0x00214 +#define RK312X_GRF_PVTM_STATUS2 0x00218 +#define RK312X_GRF_PVTM_STATUS3 0x0021c +#define RK312X_GRF_DFI_WRNUM 0x00220 +#define RK312X_GRF_DFI_RDNUM 0x00224 +#define RK312X_GRF_DFI_ACTNUM 0x00228 +#define RK312X_GRF_DFI_TIMERVAL 0x0022c +#define RK312X_GRF_NIF_FIFO0 0x00230 +#define RK312X_GRF_NIF_FIFO1 0x00234 +#define RK312X_GRF_NIF_FIFO2 0x00238 +#define RK312X_GRF_NIF_FIFO3 0x0023c +#define RK312X_GRF_USBPHY0_CON0 0x00280 +#define RK312X_GRF_USBPHY0_CON1 0x00284 +#define RK312X_GRF_USBPHY0_CON2 0x00288 +#define RK312X_GRF_USBPHY0_CON3 0x0028c +#define RK312X_GRF_USBPHY0_CON4 0x00290 +#define RK312X_GRF_USBPHY0_CON5 0x00294 +#define RK312X_GRF_USBPHY0_CON6 0x00298 +#define RK312X_GRF_USBPHY0_CON7 0x0029c +#define RK312X_GRF_USBPHY1_CON0 0x002a0 +#define RK312X_GRF_USBPHY1_CON1 0x002a4 +#define RK312X_GRF_USBPHY1_CON2 0x002a8 +#define RK312X_GRF_USBPHY1_CON3 0x002ac +#define RK312X_GRF_USBPHY1_CON4 0x002b0 +#define RK312X_GRF_USBPHY1_CON5 0x002b4 +#define RK312X_GRF_USBPHY1_CON6 0x002b8 +#define RK312X_GRF_USBPHY1_CON7 0x002bc +#define RK312X_GRF_UOC_STATUS0 0x002c0 +#define RK312X_GRF_CHIP_TAG 0x00300 +#define RK312X_GRF_SDMMC_DET_CNT 0x00304 +#define RK312X_GRF_EFUSE_PRG_EN 0x0037c + +#define RK3228_GRF_GPIO0A_IOMUX 0x0000 +#define RK3228_GRF_GPIO0B_IOMUX 0x0004 +#define RK3228_GRF_GPIO0C_IOMUX 0x0008 +#define RK3228_GRF_GPIO0D_IOMUX 0x000c +#define RK3228_GRF_GPIO1A_IOMUX 0x0010 +#define RK3228_GRF_GPIO1B_IOMUX 0x0014 +#define RK3228_GRF_GPIO1C_IOMUX 0x0018 +#define RK3228_GRF_GPIO1D_IOMUX 0x001c +#define RK3228_GRF_GPIO2A_IOMUX 0x0020 +#define RK3228_GRF_GPIO2B_IOMUX 0x0024 +#define RK3228_GRF_GPIO2C_IOMUX 0x0028 +#define RK3228_GRF_GPIO2D_IOMUX 0x002c +#define RK3228_GRF_GPIO3A_IOMUX 0x0030 +#define RK3228_GRF_GPIO3B_IOMUX 0x0034 +#define RK3228_GRF_GPIO3C_IOMUX 0x0038 +#define RK3228_GRF_GPIO3D_IOMUX 0x003c +#define RK3228_GRF_COM_IOMUX 0x0050 +#define RK3228_GRF_GPIO0A_P 0x0100 +#define RK3228_GRF_GPIO0B_P 0x0104 +#define RK3228_GRF_GPIO0C_P 0x0108 +#define RK3228_GRF_GPIO0D_P 0x010c +#define RK3228_GRF_GPIO1A_P 0x0110 +#define RK3228_GRF_GPIO1B_P 0x0114 +#define RK3228_GRF_GPIO1C_P 0x0118 +#define RK3228_GRF_GPIO1D_P 0x011c +#define RK3228_GRF_GPIO2A_P 0x0120 +#define RK3228_GRF_GPIO2B_P 0x0124 +#define RK3228_GRF_GPIO2C_P 0x0128 +#define RK3228_GRF_GPIO2D_P 0x012c +#define RK3228_GRF_GPIO3A_P 0x0130 +#define RK3228_GRF_GPIO3B_P 0x0134 +#define RK3228_GRF_GPIO3C_P 0x0138 +#define RK3228_GRF_GPIO3D_P 0x013c +#define RK3228_GRF_GPIO0A_E 0x0200 +#define RK3228_GRF_GPIO0B_E 0x0204 +#define RK3228_GRF_GPIO0C_E 0x0208 +#define RK3228_GRF_GPIO0D_E 0x020c +#define RK3228_GRF_GPIO1A_E 0x0210 +#define RK3228_GRF_GPIO1B_E 0x0214 +#define RK3228_GRF_GPIO1C_E 0x0218 +#define RK3228_GRF_GPIO1D_E 0x021c +#define RK3228_GRF_GPIO2A_E 0x0220 +#define RK3228_GRF_GPIO2B_E 0x0224 +#define RK3228_GRF_GPIO2C_E 0x0228 +#define RK3228_GRF_GPIO2D_E 0x022c +#define RK3228_GRF_GPIO3A_E 0x0230 +#define RK3228_GRF_GPIO3B_E 0x0234 +#define RK3228_GRF_GPIO3C_E 0x0238 +#define RK3228_GRF_GPIO3D_E 0x023c +#define RK3228_GRF_GPIO0L_SR 0x0300 +#define RK3228_GRF_GPIO0H_SR 0x0304 +#define RK3228_GRF_GPIO1L_SR 0x0308 +#define RK3228_GRF_GPIO1H_SR 0x030c +#define RK3228_GRF_GPIO2L_SR 0x0310 +#define RK3228_GRF_GPIO2H_SR 0x0314 +#define RK3228_GRF_GPIO3L_SR 0x0318 +#define RK3228_GRF_GPIO3H_SR 0x031c +#define RK3228_GRF_GPIO0L_SMT 0x0380 +#define RK3228_GRF_GPIO0H_SMT 0x0384 +#define RK3228_GRF_GPIO1L_SMT 0x0388 +#define RK3228_GRF_GPIO1H_SMT 0x038c +#define RK3228_GRF_GPIO2L_SMT 0x0390 +#define RK3228_GRF_GPIO2H_SMT 0x0394 +#define RK3228_GRF_GPIO3L_SMT 0x0398 +#define RK3228_GRF_GPIO3H_SMT 0x039c +#define RK3228_GRF_SOC_CON0 0x0400 +#define RK3228_GRF_SOC_CON1 0x0404 +#define RK3228_GRF_SOC_CON2 0x0408 +#define RK3228_GRF_SOC_CON3 0x040c +#define RK3228_GRF_SOC_CON4 0x0410 +#define RK3228_GRF_SOC_CON5 0x0414 +#define RK3228_GRF_SOC_CON6 0x0418 +#define RK3228_GRF_SOC_STATUS0 0x0480 +#define RK3228_GRF_SOC_STATUS1 0x0484 +#define RK3228_GRF_SOC_STATUS2 0x0488 +#define RK3228_GRF_CHIP_ID 0x048c +#define RK3228_GRF_CPU_CON0 0x0500 +#define RK3228_GRF_CPU_CON1 0x0504 +#define RK3228_GRF_CPU_CON2 0x0508 +#define RK3228_GRF_CPU_CON3 0x050c +#define RK3228_GRF_CPU_STATUS0 0x0520 +#define RK3228_GRF_CPU_STATUS1 0x0524 +#define RK3228_GRF_OS_REG0 0x05c8 +#define RK3228_GRF_OS_REG1 0x05cc +#define RK3228_GRF_OS_REG2 0x05d0 +#define RK3228_GRF_OS_REG3 0x05d4 +#define RK3228_GRF_OS_REG4 0x05d8 +#define RK3228_GRF_OS_REG5 0x05dc +#define RK3228_GRF_OS_REG6 0x05e0 +#define RK3228_GRF_OS_REG7 0x05e4 +#define RK3228_GRF_DDRC_STAT 0x0604 +#define RK3228_GRF_SIG_DETECT_CON 0x0680 +#define RK3228_GRF_SIG_DETECT_CON1 0x0684 +#define RK3228_GRF_SIG_DETECT_STATUS 0x0690 +#define RK3228_GRF_SIG_DETECT_STATUS1 0x0694 +#define RK3228_GRF_SIG_DETECT_CLR 0x06a0 +#define RK3228_GRF_SIG_DETECT_CLR1 0x06a4 +#define RK3228_GRF_EMMC_DET 0x06b0 +#define RK3228_GRF_HOST0_CON0 0x0700 +#define RK3228_GRF_HOST0_CON1 0x0704 +#define RK3228_GRF_HOST0_CON2 0x0708 +#define RK3228_GRF_HOST1_CON0 0x0710 +#define RK3228_GRF_HOST1_CON1 0x0714 +#define RK3228_GRF_HOST1_CON2 0x0718 +#define RK3228_GRF_HOST2_CON0 0x0720 +#define RK3228_GRF_HOST2_CON1 0x0724 +#define RK3228_GRF_HOST2_CON2 0x0728 +#define RK3228_GRF_USBPHY0_CON0 0x0760 +#define RK3228_GRF_USBPHY0_CON1 0x0764 +#define RK3228_GRF_USBPHY0_CON2 0x0768 +#define RK3228_GRF_USBPHY0_CON3 0x076c +#define RK3228_GRF_USBPHY0_CON4 0x0770 +#define RK3228_GRF_USBPHY0_CON5 0x0774 +#define RK3228_GRF_USBPHY0_CON6 0x0778 +#define RK3228_GRF_USBPHY0_CON7 0x077c +#define RK3228_GRF_USBPHY0_CON8 0x0780 +#define RK3228_GRF_USBPHY0_CON9 0x0784 +#define RK3228_GRF_USBPHY0_CON10 0x0788 +#define RK3228_GRF_USBPHY0_CON11 0x078c +#define RK3228_GRF_USBPHY0_CON12 0x0790 +#define RK3228_GRF_USBPHY0_CON13 0x0794 +#define RK3228_GRF_USBPHY0_CON14 0x0798 +#define RK3228_GRF_USBPHY0_CON15 0x079c +#define RK3228_GRF_USBPHY0_CON16 0x07a0 +#define RK3228_GRF_USBPHY0_CON17 0x07a4 +#define RK3228_GRF_USBPHY0_CON18 0x07a8 +#define RK3228_GRF_USBPHY0_CON19 0x07ac +#define RK3228_GRF_USBPHY0_CON20 0x07b0 +#define RK3228_GRF_USBPHY0_CON21 0x07b4 +#define RK3228_GRF_USBPHY0_CON22 0x07b8 +#define RK3228_GRF_USBPHY0_CON23 0x07bc +#define RK3228_GRF_USBPHY0_CON24 0x07c0 +#define RK3228_GRF_USBPHY0_CON25 0x07c4 +#define RK3228_GRF_USBPHY0_CON26 0x07c8 +#define RK3228_GRF_USBPHY1_CON0 0x0800 +#define RK3228_GRF_USBPHY1_CON1 0x0804 +#define RK3228_GRF_USBPHY1_CON2 0x0808 +#define RK3228_GRF_USBPHY1_CON3 0x080c +#define RK3228_GRF_USBPHY1_CON4 0x0810 +#define RK3228_GRF_USBPHY1_CON5 0x0814 +#define RK3228_GRF_USBPHY1_CON6 0x0818 +#define RK3228_GRF_USBPHY1_CON7 0x081c +#define RK3228_GRF_USBPHY1_CON8 0x0820 +#define RK3228_GRF_USBPHY1_CON9 0x0824 +#define RK3228_GRF_USBPHY1_CON10 0x0828 +#define RK3228_GRF_USBPHY1_CON11 0x082c +#define RK3228_GRF_USBPHY1_CON12 0x0830 +#define RK3228_GRF_USBPHY1_CON13 0x0834 +#define RK3228_GRF_USBPHY1_CON14 0x0838 +#define RK3228_GRF_USBPHY1_CON15 0x083c +#define RK3228_GRF_USBPHY1_CON16 0x0840 +#define RK3228_GRF_USBPHY1_CON17 0x0844 +#define RK3228_GRF_USBPHY1_CON18 0x0848 +#define RK3228_GRF_USBPHY1_CON19 0x084c +#define RK3228_GRF_USBPHY1_CON20 0x0850 +#define RK3228_GRF_USBPHY1_CON21 0x0854 +#define RK3228_GRF_USBPHY1_CON22 0x0858 +#define RK3228_GRF_USBPHY1_CON23 0x085c +#define RK3228_GRF_USBPHY1_CON24 0x0860 +#define RK3228_GRF_USBPHY1_CON25 0x0864 +#define RK3228_GRF_USBPHY1_CON26 0x0868 +#define RK3228_GRF_OTG_CON0 0x0880 +#define RK3228_GRF_UOC_CON0 0x0884 +#define RK3228_GRF_MAC_CON0 0x0900 +#define RK3228_GRF_MAC_CON1 0x0904 +#define RK3228_GRF_MACPHY_CON0 0x0b00 +#define RK3228_GRF_MACPHY_CON1 0x0b04 +#define RK3228_GRF_MACPHY_CON2 0x0b08 +#define RK3228_GRF_MACPHY_CON3 0x0b0c +#define RK3228_GRF_MACPHY_STATUS 0x0b10 + +#endif diff --git a/include/linux/rockchip/psci.h b/include/linux/rockchip/psci.h new file mode 100644 index 000000000000..870da27edf65 --- /dev/null +++ b/include/linux/rockchip/psci.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ROCKCHIP_PSCI_H +#define __ROCKCHIP_PSCI_H + +#define SEC_REG_RD (0x0) +#define SEC_REG_WR (0x1) + +/* + * trust firmware verison + */ +#define RKTF_VER_MAJOR(ver) (((ver) >> 16) & 0xffff) +#define RKTF_VER_MINOR(ver) ((ver) & 0xffff) + +/* + * pcsi smc funciton id + */ +#define PSCI_SIP_RKTF_VER (0x82000001) +#define PSCI_SIP_ACCESS_REG (0x82000002) +#define PSCI_SIP_ACCESS_REG64 (0xc2000002) +#define PSCI_SIP_SUSPEND_WR_CTRBITS (0x82000003) +#define PSCI_SIP_PENDING_CPUS (0x82000004) +#define PSCI_SIP_UARTDBG_CFG (0x82000005) +#define PSCI_SIP_UARTDBG_CFG64 (0xc2000005) +#define PSCI_SIP_EL3FIQ_CFG (0x82000006) +#define PSCI_SIP_SMEM_CONFIG (0x82000007) + +/* + * pcsi smc funciton err code + */ +#define PSCI_SMC_FUNC_UNK 0xffffffff + +/* + * define PSCI_SIP_UARTDBG_CFG call type + */ +#define UARTDBG_CFG_INIT 0xf0 +#define UARTDBG_CFG_OSHDL_TO_OS 0xf1 +#define UARTDBG_CFG_OSHDL_CPUSW 0xf3 +#define UARTDBG_CFG_OSHDL_DEBUG_ENABLE 0xf4 +#define UARTDBG_CFG_OSHDL_DEBUG_DISABLE 0xf5 + +/* + * rockchip psci function call interface + */ + +u32 rockchip_psci_smc_read(u32 function_id, u32 arg0, u32 arg1, u32 arg2, + u32 *val); +u32 rockchip_psci_smc_write(u32 function_id, u32 arg0, u32 arg1, u32 arg2); + +u32 rockchip_psci_smc_get_tf_ver(void); +u32 rockchip_secure_reg_read(u32 addr_phy); +u32 rockchip_secure_reg_write(u32 addr_phy, u32 val); + +#ifdef CONFIG_ARM64 +u32 rockchip_psci_smc_write64(u64 function_id, u64 arg0, u64 arg1, u64 arg2); +u32 rockchip_psci_smc_read64(u64 function_id, u64 arg0, u64 arg1, u64 arg2, + u64 *val); +u64 rockchip_secure_reg_read64(u64 addr_phy); +u32 rockchip_secure_reg_write64(u64 addr_phy, u64 val); + +void psci_fiq_debugger_uart_irq_tf_cb(u64 sp_el1, u64 offset); +#endif + +u32 psci_fiq_debugger_switch_cpu(u32 cpu); +void psci_fiq_debugger_uart_irq_tf_init(u32 irq_id, void *callback); +void psci_fiq_debugger_enable_debug(bool val); + +#if defined(CONFIG_ARM_PSCI) || defined(CONFIG_ARM64) +u32 psci_set_memory_secure(bool val); +#else +static inline u32 psci_set_memory_secure(bool val) +{ + return 0; +} +#endif + +#endif /* __ROCKCHIP_PSCI_H */ diff --git a/include/linux/rockchip/rockchip_sip.h b/include/linux/rockchip/rockchip_sip.h new file mode 100644 index 000000000000..3258eeda6e50 --- /dev/null +++ b/include/linux/rockchip/rockchip_sip.h @@ -0,0 +1,307 @@ +/* Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __ROCKCHIP_SIP_H +#define __ROCKCHIP_SIP_H + +#include <linux/arm-smccc.h> +#include <linux/io.h> + +/* SMC function IDs for SiP Service queries, compatible with kernel-3.10 */ +#define SIP_ATF_VERSION 0x82000001 +#define SIP_ACCESS_REG 0x82000002 +#define SIP_SUSPEND_MODE 0x82000003 +#define SIP_PENDING_CPUS 0x82000004 +#define SIP_UARTDBG_CFG 0x82000005 +#define SIP_UARTDBG_CFG64 0xc2000005 +#define SIP_MCU_EL3FIQ_CFG 0x82000006 +#define SIP_ACCESS_CHIP_STATE64 0xc2000006 +#define SIP_SECURE_MEM_CONFIG 0x82000007 +#define SIP_ACCESS_CHIP_EXTRA_STATE64 0xc2000007 +#define SIP_DRAM_CONFIG 0x82000008 +#define SIP_SHARE_MEM 0x82000009 +#define SIP_SIP_VERSION 0x8200000a +#define SIP_REMOTECTL_CFG 0x8200000b +#define PSCI_SIP_VPU_RESET 0x8200000c +#define RK_SIP_SOC_BUS_DIV 0x8200000d +#define SIP_LAST_LOG 0x8200000e + +/* Rockchip Sip version */ +#define SIP_IMPLEMENT_V1 (1) +#define SIP_IMPLEMENT_V2 (2) + +/* Trust firmware version */ +#define ATF_VER_MAJOR(ver) (((ver) >> 16) & 0xffff) +#define ATF_VER_MINOR(ver) (((ver) >> 0) & 0xffff) + +/* SIP_ACCESS_REG: read or write */ +#define SECURE_REG_RD 0x0 +#define SECURE_REG_WR 0x1 + +/* Fiq debugger share memory: 8KB enough */ +#define FIQ_UARTDBG_PAGE_NUMS 2 +#define FIQ_UARTDBG_SHARE_MEM_SIZE ((FIQ_UARTDBG_PAGE_NUMS) * 4096) + +/* Error return code */ +#define IS_SIP_ERROR(x) (!!(x)) + +#define SIP_RET_SUCCESS 0 +#define SIP_RET_SMC_UNKNOWN -1 +#define SIP_RET_NOT_SUPPORTED -2 +#define SIP_RET_INVALID_PARAMS -3 +#define SIP_RET_INVALID_ADDRESS -4 +#define SIP_RET_DENIED -5 +#define SIP_RET_SET_RATE_TIMEOUT -6 + +/* SIP_UARTDBG_CFG64 call types */ +#define UARTDBG_CFG_INIT 0xf0 +#define UARTDBG_CFG_OSHDL_TO_OS 0xf1 +#define UARTDBG_CFG_OSHDL_CPUSW 0xf3 +#define UARTDBG_CFG_OSHDL_DEBUG_ENABLE 0xf4 +#define UARTDBG_CFG_OSHDL_DEBUG_DISABLE 0xf5 +#define UARTDBG_CFG_PRINT_PORT 0xf7 +#define UARTDBG_CFG_FIQ_ENABEL 0xf8 +#define UARTDBG_CFG_FIQ_DISABEL 0xf9 + +/* SIP_SUSPEND_MODE32 call types */ +#define SUSPEND_MODE_CONFIG 0x01 +#define WKUP_SOURCE_CONFIG 0x02 +#define PWM_REGULATOR_CONFIG 0x03 +#define GPIO_POWER_CONFIG 0x04 +#define SUSPEND_DEBUG_ENABLE 0x05 +#define APIOS_SUSPEND_CONFIG 0x06 +#define VIRTUAL_POWEROFF 0x07 +#define SUSPEND_WFI_TIME_MS 0x08 + +/* SIP_REMOTECTL_CFG call types */ +#define REMOTECTL_SET_IRQ 0xf0 +#define REMOTECTL_SET_PWM_CH 0xf1 +#define REMOTECTL_SET_PWRKEY 0xf2 +#define REMOTECTL_GET_WAKEUP_STATE 0xf3 +#define REMOTECTL_ENABLE 0xf4 +/* wakeup state */ +#define REMOTECTL_PWRKEY_WAKEUP 0xdeadbeaf + +enum { + FIRMWARE_NONE, + FIRMWARE_TEE_32BIT, + FIRMWARE_ATF_32BIT, + FIRMWARE_ATF_64BIT, + FIRMWARE_END, +}; + +/* Share mem page types */ +typedef enum { + SHARE_PAGE_TYPE_INVALID = 0, + SHARE_PAGE_TYPE_UARTDBG, + SHARE_PAGE_TYPE_DDR, + SHARE_PAGE_TYPE_MAX, +} share_page_type_t; + +/* + * Rules: struct arm_smccc_res contains result and data, details: + * + * a0: error code(0: success, !0: error); + * a1~a3: data + */ +#ifdef CONFIG_ROCKCHIP_SIP +struct arm_smccc_res sip_smc_get_atf_version(void); +struct arm_smccc_res sip_smc_get_sip_version(void); +struct arm_smccc_res sip_smc_dram(u32 arg0, u32 arg1, u32 arg2); +struct arm_smccc_res sip_smc_request_share_mem(u32 page_num, + share_page_type_t page_type); +struct arm_smccc_res sip_smc_mcu_el3fiq(u32 arg0, u32 arg1, u32 arg2); +struct arm_smccc_res sip_smc_vpu_reset(u32 arg0, u32 arg1, u32 arg2); +struct arm_smccc_res sip_smc_get_suspend_info(u32 info); +struct arm_smccc_res sip_smc_lastlog_request(void); + +int sip_smc_set_suspend_mode(u32 ctrl, u32 config1, u32 config2); +int sip_smc_virtual_poweroff(void); +int sip_smc_remotectl_config(u32 func, u32 data); + +int sip_smc_secure_reg_write(u32 addr_phy, u32 val); +u32 sip_smc_secure_reg_read(u32 addr_phy); +struct arm_smccc_res sip_smc_soc_bus_div(u32 arg0, u32 arg1, u32 arg2); + +/***************************fiq debugger **************************************/ +void sip_fiq_debugger_enable_fiq(bool enable, uint32_t tgt_cpu); +void sip_fiq_debugger_enable_debug(bool enable); +int sip_fiq_debugger_uart_irq_tf_init(u32 irq_id, void *callback_fn); +int sip_fiq_debugger_set_print_port(u32 port_phyaddr, u32 baudrate); +int sip_fiq_debugger_request_share_memory(void); +int sip_fiq_debugger_get_target_cpu(void); +int sip_fiq_debugger_switch_cpu(u32 cpu); +int sip_fiq_debugger_is_enabled(void); +#else +static inline struct arm_smccc_res sip_smc_get_atf_version(void) +{ + struct arm_smccc_res tmp = {0}; + return tmp; +} + +static inline struct arm_smccc_res sip_smc_get_sip_version(void) +{ + struct arm_smccc_res tmp = {0}; + return tmp; +} + +static inline struct arm_smccc_res sip_smc_dram(u32 arg0, u32 arg1, u32 arg2) +{ + struct arm_smccc_res tmp = {0}; + return tmp; +} + +static inline struct arm_smccc_res sip_smc_request_share_mem + (u32 page_num, share_page_type_t page_type) +{ + struct arm_smccc_res tmp = {0}; + return tmp; +} + +static inline struct arm_smccc_res sip_smc_mcu_el3fiq + (u32 arg0, u32 arg1, u32 arg2) +{ + struct arm_smccc_res tmp = {0}; + return tmp; +} + +static inline struct arm_smccc_res +sip_smc_vpu_reset(u32 arg0, u32 arg1, u32 arg2) +{ + struct arm_smccc_res tmp = {0}; + return tmp; +} + +struct arm_smccc_res sip_smc_lastlog_request(void) +{ + struct arm_smccc_res tmp = {0}; + return tmp; +} + +static inline int sip_smc_set_suspend_mode(u32 ctrl, u32 config1, u32 config2) +{ + return 0; +} + +static inline int sip_smc_get_suspend_info(u32 info) +{ + return 0; +} + +static inline int sip_smc_virtual_poweroff(void) { return 0; } +static inline int sip_smc_remotectl_config(u32 func, u32 data) { return 0; } +static inline u32 sip_smc_secure_reg_read(u32 addr_phy) { return 0; } +static inline int sip_smc_secure_reg_write(u32 addr_phy, u32 val) { return 0; } +static inline int sip_smc_soc_bus_div(u32 arg0, u32 arg1, u32 arg2) +{ + return 0; +} + +/***************************fiq debugger **************************************/ +static inline void sip_fiq_debugger_enable_fiq + (bool enable, uint32_t tgt_cpu) { return; } + +static inline void sip_fiq_debugger_enable_debug(bool enable) { return; } +static inline int sip_fiq_debugger_uart_irq_tf_init(u32 irq_id, + void *callback_fn) +{ + return 0; +} + +static inline int sip_fiq_debugger_set_print_port(u32 port_phyaddr, + u32 baudrate) +{ + return 0; +} + +static inline int sip_fiq_debugger_request_share_memory(void) { return 0; } +static inline int sip_fiq_debugger_get_target_cpu(void) { return 0; } +static inline int sip_fiq_debugger_switch_cpu(u32 cpu) { return 0; } +static inline int sip_fiq_debugger_is_enabled(void) { return 0; } +#endif + +/* 32-bit OP-TEE context, never change order of members! */ +struct sm_nsec_ctx { + u32 usr_sp; + u32 usr_lr; + u32 irq_spsr; + u32 irq_sp; + u32 irq_lr; + u32 fiq_spsr; + u32 fiq_sp; + u32 fiq_lr; + u32 svc_spsr; + u32 svc_sp; + u32 svc_lr; + u32 abt_spsr; + u32 abt_sp; + u32 abt_lr; + u32 und_spsr; + u32 und_sp; + u32 und_lr; + u32 mon_lr; + u32 mon_spsr; + u32 r4; + u32 r5; + u32 r6; + u32 r7; + u32 r8; + u32 r9; + u32 r10; + u32 r11; + u32 r12; + u32 r0; + u32 r1; + u32 r2; + u32 r3; +}; + +/* 64-bit ATF context, never change order of members! */ +struct gp_regs_ctx { + u64 x0; + u64 x1; + u64 x2; + u64 x3; + u64 x4; + u64 x5; + u64 x6; + u64 x7; + u64 x8; + u64 x9; + u64 x10; + u64 x11; + u64 x12; + u64 x13; + u64 x14; + u64 x15; + u64 x16; + u64 x17; + u64 x18; + u64 x19; + u64 x20; + u64 x21; + u64 x22; + u64 x23; + u64 x24; + u64 x25; + u64 x26; + u64 x27; + u64 x28; + u64 x29; + u64 lr; + u64 sp_el0; + u64 scr_el3; + u64 runtime_sp; + u64 spsr_el3; + u64 elr_el3; +}; + +#endif diff --git a/include/linux/rockchip_ion.h b/include/linux/rockchip_ion.h new file mode 100644 index 000000000000..39c497774fb0 --- /dev/null +++ b/include/linux/rockchip_ion.h @@ -0,0 +1,41 @@ +/* + * + * Copyright (C) 2014 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _LINUX_ROCKCHIP_ION_H +#define _LINUX_ROCKCHIP_ION_H + +#ifdef __KERNEL__ +#include "../../drivers/staging/android/ion/ion.h" +#else +#include <linux/ion.h> +#endif + +struct ion_phys_data { + ion_user_handle_t handle; + unsigned long phys; + unsigned long size; +}; + +#define ION_IOC_ROCKCHIP_MAGIC 'R' + +/* Get phys addr of the handle specified. */ +#define ION_IOC_GET_PHYS _IOWR(ION_IOC_ROCKCHIP_MAGIC, 0, \ + struct ion_phys_data) + +extern struct ion_device *rockchip_ion_dev; + +struct ion_client *rockchip_ion_client_create(const char *name); + +#endif diff --git a/include/linux/sensor-dev.h b/include/linux/sensor-dev.h new file mode 100644 index 000000000000..19a8f03f3e0c --- /dev/null +++ b/include/linux/sensor-dev.h @@ -0,0 +1,335 @@ +/* include/linux/sensor-dev.h - sensor header file + * + * Copyright (C) 2012-2015 ROCKCHIP. + * Author: luowei <lw@rock-chips.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/miscdevice.h> +#ifdef CONFIG_HAS_EARLYSUSPEND +#include <linux/earlysuspend.h> +#endif + +#include <dt-bindings/sensor-dev.h> + +#define SENSOR_ON 1 +#define SENSOR_OFF 0 +#define SENSOR_UNKNOW_DATA -1 + +#define GPIO_HIGH 1 +#define GPIO_LOW 0 + +enum sensor_id { + ID_INVALID = 0, + + ANGLE_ID_ALL, + ANGLE_ID_KXTIK, + ANGLE_ID_LIS3DH, + + ACCEL_ID_ALL, + ACCEL_ID_LIS331, + ACCEL_ID_LSM303DLX, + ACCEL_ID_LIS3DH, + ACCEL_ID_KXSD9, + ACCEL_ID_KXTF9, + ACCEL_ID_KXTIK, + ACCEL_ID_KXTJ9, + ACCEL_ID_BMA150, + ACCEL_ID_BMA222, + ACCEL_ID_BMA250, + ACCEL_ID_ADXL34X, + ACCEL_ID_MMA8450, + ACCEL_ID_MMA845X, + ACCEL_ID_MMA7660, + ACCEL_ID_MPU6050, + ACCEL_ID_MXC6225, + ACCEL_ID_DMARD10, + ACCEL_ID_LSM303D, + ACCEL_ID_MC3230, + ACCEL_ID_MPU6880, + ACCEL_ID_MPU6500, + ACCEL_ID_LSM330, + ACCEL_ID_BMA2XX, + ACCEL_ID_STK8BAXX, + COMPASS_ID_ALL, + COMPASS_ID_AK8975, + COMPASS_ID_AK8963, + COMPASS_ID_AK09911, + COMPASS_ID_AK8972, + COMPASS_ID_AMI30X, + COMPASS_ID_AMI306, + COMPASS_ID_YAS529, + COMPASS_ID_YAS530, + COMPASS_ID_HMC5883, + COMPASS_ID_LSM303DLH, + COMPASS_ID_LSM303DLM, + COMPASS_ID_MMC314X, + COMPASS_ID_HSCDTD002B, + COMPASS_ID_HSCDTD004A, + + GYRO_ID_ALL, + GYRO_ID_L3G4200D, + GYRO_ID_L3G20D, + GYRO_ID_EWTSA, + GYRO_ID_K3G, + GYRO_ID_MPU6500, + GYRO_ID_MPU6880, + GYRO_ID_LSM330, + LIGHT_ID_ALL, + LIGHT_ID_CM3217, + LIGHT_ID_CM3218, + LIGHT_ID_CM3232, + LIGHT_ID_AL3006, + LIGHT_ID_STK3171, + LIGHT_ID_ISL29023, + LIGHT_ID_AP321XX, + LIGHT_ID_PHOTORESISTOR, + LIGHT_ID_US5152, + LIGHT_ID_STK3410, + + PROXIMITY_ID_ALL, + PROXIMITY_ID_AL3006, + PROXIMITY_ID_STK3171, + PROXIMITY_ID_AP321XX, + PROXIMITY_ID_STK3410, + + TEMPERATURE_ID_ALL, + TEMPERATURE_ID_MS5607, + + PRESSURE_ID_ALL, + PRESSURE_ID_BMA085, + PRESSURE_ID_MS5607, + + HALL_ID_ALL, + HALL_ID_OCH165T, + + SENSOR_NUM_ID, +}; + +struct sensor_axis { + int x; + int y; + int z; +}; + +struct sensor_flag { + atomic_t a_flag; + atomic_t m_flag; + atomic_t mv_flag; + atomic_t open_flag; + atomic_t debug_flag; + long long delay; + wait_queue_head_t open_wq; +}; + + +struct sensor_operate { + char *name; + int type; + int id_i2c; + int range[2]; + int brightness[2]; + int read_reg; + int read_len; + int id_reg; + int id_data; + int precision; + int ctrl_reg; + int ctrl_data; + int int_ctrl_reg; + int int_status_reg; + int trig; + int (*active)(struct i2c_client *client, int enable, int rate); + int (*init)(struct i2c_client *client); + int (*report)(struct i2c_client *client); + int (*suspend)(struct i2c_client *client); + int (*resume)(struct i2c_client *client); + struct miscdevice *misc_dev; +}; + +/* Platform data for the sensor */ +struct sensor_private_data { + int type; + struct i2c_client *client; + struct input_dev *input_dev; + int stop_work; + struct delayed_work delaywork; + struct sensor_axis axis; + char sensor_data[40]; + atomic_t is_factory; + wait_queue_head_t is_factory_ok; + struct mutex data_mutex; + struct mutex operation_mutex; + struct mutex sensor_mutex; + struct mutex i2c_mutex; + int status_cur; + int start_count; + int devid; + struct sensor_flag flags; + struct i2c_device_id *i2c_id; + struct sensor_platform_data *pdata; + struct sensor_operate *ops; + struct file_operations fops; + struct miscdevice miscdev; +#ifdef CONFIG_HAS_EARLYSUSPEND + struct early_suspend early_suspend; +#endif +}; + +struct sensor_platform_data { + int type; + int irq; + int irq_pin; + int power_pin; + int reset_pin; + int standby_pin; + int irq_enable; + int poll_delay_ms; + int x_min; + int y_min; + int z_min; + int factory; + int layout; + unsigned char address; + unsigned long irq_flags; + signed char orientation[9]; + short m_layout[4][3][3]; + int *project_name; + int power_off_in_suspend; +}; + +struct gsensor_platform_data { + u16 model; + u16 swap_xy; + u16 swap_xyz; + signed char orientation[9]; + int (*get_pendown_state)(void); + int (*init_platform_hw)(void); + int (*gsensor_platform_sleep)(void); + int (*gsensor_platform_wakeup)(void); + void (*exit_platform_hw)(void); +}; + +struct akm8975_platform_data { + short m_layout[4][3][3]; + char project_name[64]; + int gpio_DRDY; +}; + +struct akm_platform_data { + short m_layout[4][3][3]; + char project_name[64]; + char layout; + char outbit; + int gpio_DRDY; + int gpio_RST; +}; + +extern int sensor_register_slave(int type, struct i2c_client *client, + struct sensor_platform_data *slave_pdata, + struct sensor_operate *(*get_sensor_ops)(void)); + + +extern int sensor_unregister_slave(int type, struct i2c_client *client, + struct sensor_platform_data *slave_pdata, + struct sensor_operate *(*get_sensor_ops)(void)); + +#define DBG(x...) + +#define GSENSOR_IOCTL_MAGIC 'a' +#define GBUFF_SIZE 12 /* Rx buffer size */ + +/* IOCTLs for MMA8452 library */ +#define GSENSOR_IOCTL_INIT _IO(GSENSOR_IOCTL_MAGIC, 0x01) +#define GSENSOR_IOCTL_RESET _IO(GSENSOR_IOCTL_MAGIC, 0x04) +#define GSENSOR_IOCTL_CLOSE _IO(GSENSOR_IOCTL_MAGIC, 0x02) +#define GSENSOR_IOCTL_START _IO(GSENSOR_IOCTL_MAGIC, 0x03) +#define GSENSOR_IOCTL_GETDATA _IOR(GSENSOR_IOCTL_MAGIC, 0x08, char[GBUFF_SIZE+1]) +#define GSENSOR_IOCTL_APP_SET_RATE _IOW(GSENSOR_IOCTL_MAGIC, 0x10, short) +#define GSENSOR_IOCTL_GET_CALIBRATION _IOR(GSENSOR_IOCTL_MAGIC, 0x11, int[3]) + + +#define COMPASS_IOCTL_MAGIC 'c' +/* IOCTLs for APPs */ +#define ECS_IOCTL_APP_SET_MODE _IOW(COMPASS_IOCTL_MAGIC, 0x10, short) +#define ECS_IOCTL_APP_SET_MFLAG _IOW(COMPASS_IOCTL_MAGIC, 0x11, short) +#define ECS_IOCTL_APP_GET_MFLAG _IOW(COMPASS_IOCTL_MAGIC, 0x12, short) +#define ECS_IOCTL_APP_SET_AFLAG _IOW(COMPASS_IOCTL_MAGIC, 0x13, short) +#define ECS_IOCTL_APP_GET_AFLAG _IOR(COMPASS_IOCTL_MAGIC, 0x14, short) +#define ECS_IOCTL_APP_SET_TFLAG _IOR(COMPASS_IOCTL_MAGIC, 0x15, short)/* NOT use */ +#define ECS_IOCTL_APP_GET_TFLAG _IOR(COMPASS_IOCTL_MAGIC, 0x16, short)/* NOT use */ +#define ECS_IOCTL_APP_RESET_PEDOMETER _IOW(COMPASS_IOCTL_MAGIC, 0x17) /* NOT use */ +#define ECS_IOCTL_APP_SET_DELAY _IOW(COMPASS_IOCTL_MAGIC, 0x18, short) +#define ECS_IOCTL_APP_SET_MVFLAG _IOW(COMPASS_IOCTL_MAGIC, 0x19, short) +#define ECS_IOCTL_APP_GET_MVFLAG _IOR(COMPASS_IOCTL_MAGIC, 0x1A, short) +#define ECS_IOCTL_APP_GET_DELAY _IOR(COMPASS_IOCTL_MAGIC, 0x1B, short) + +#ifdef CONFIG_COMPAT +#define COMPAT_ECS_IOCTL_APP_SET_MODE _IOW(COMPASS_IOCTL_MAGIC, 0x10, compat_short_t) +#define COMPAT_ECS_IOCTL_APP_SET_MFLAG _IOW(COMPASS_IOCTL_MAGIC, 0x11, compat_short_t) +#define COMPAT_ECS_IOCTL_APP_GET_MFLAG _IOW(COMPASS_IOCTL_MAGIC, 0x12, compat_short_t) +#define COMPAT_ECS_IOCTL_APP_SET_AFLAG _IOW(COMPASS_IOCTL_MAGIC, 0x13, compat_short_t) +#define COMPAT_ECS_IOCTL_APP_GET_AFLAG _IOR(COMPASS_IOCTL_MAGIC, 0x14, compat_short_t) +#define COMPAT_ECS_IOCTL_APP_SET_TFLAG _IOR(COMPASS_IOCTL_MAGIC, 0x15, compat_short_t)/* NOT use */ +#define COMPAT_ECS_IOCTL_APP_GET_TFLAG _IOR(COMPASS_IOCTL_MAGIC, 0x16, compat_short_t)/* NOT use */ +#define COMPAT_ECS_IOCTL_APP_RESET_PEDOMETER _IOW(COMPASS_IOCTL_MAGIC, 0x17) /* NOT use */ +#define COMPAT_ECS_IOCTL_APP_SET_DELAY _IOW(COMPASS_IOCTL_MAGIC, 0x18, compat_short_t) +#define COMPAT_ECS_IOCTL_APP_SET_MVFLAG _IOW(COMPASS_IOCTL_MAGIC, 0x19, compat_short_t) +#define COMPAT_ECS_IOCTL_APP_GET_MVFLAG _IOR(COMPASS_IOCTL_MAGIC, 0x1A, compat_short_t) +#define COMPAT_ECS_IOCTL_APP_GET_DELAY _IOR(COMPASS_IOCTL_MAGIC, 0x1B, compat_short_t) +#endif + +#define LIGHTSENSOR_IOCTL_MAGIC 'l' +#define LIGHTSENSOR_IOCTL_GET_ENABLED _IOR(LIGHTSENSOR_IOCTL_MAGIC, 1, int *) +#define LIGHTSENSOR_IOCTL_ENABLE _IOW(LIGHTSENSOR_IOCTL_MAGIC, 2, int *) +#define LIGHTSENSOR_IOCTL_SET_RATE _IOW(LIGHTSENSOR_IOCTL_MAGIC, 3, short) + +#ifdef CONFIG_COMPAT +#define COMPAT_LIGHTSENSOR_IOCTL_GET_ENABLED _IOR(LIGHTSENSOR_IOCTL_MAGIC, 1, compat_uptr_t) +#define COMPAT_LIGHTSENSOR_IOCTL_ENABLE _IOW(LIGHTSENSOR_IOCTL_MAGIC, 2, compat_uptr_t) +#define COMPAT_LIGHTSENSOR_IOCTL_SET_RATE _IOW(LIGHTSENSOR_IOCTL_MAGIC, 3, compat_short_t) +#endif + +#define PSENSOR_IOCTL_MAGIC 'p' +#define PSENSOR_IOCTL_GET_ENABLED _IOR(PSENSOR_IOCTL_MAGIC, 1, int *) +#define PSENSOR_IOCTL_ENABLE _IOW(PSENSOR_IOCTL_MAGIC, 2, int *) +#define PSENSOR_IOCTL_DISABLE _IOW(PSENSOR_IOCTL_MAGIC, 3, int *) + +#ifdef CONFIG_COMPAT +#define COMPAT_PSENSOR_IOCTL_GET_ENABLED _IOR(PSENSOR_IOCTL_MAGIC, 1, compat_uptr_t) +#define COMPAT_PSENSOR_IOCTL_ENABLE _IOW(PSENSOR_IOCTL_MAGIC, 2, compat_uptr_t) +#define COMPAT_PSENSOR_IOCTL_DISABLE _IOW(PSENSOR_IOCTL_MAGIC, 3, compat_uptr_t) +#endif + +#define PRESSURE_IOCTL_MAGIC 'r' +#define PRESSURE_IOCTL_GET_ENABLED _IOR(PRESSURE_IOCTL_MAGIC, 1, int *) +#define PRESSURE_IOCTL_ENABLE _IOW(PRESSURE_IOCTL_MAGIC, 2, int *) +#define PRESSURE_IOCTL_DISABLE _IOW(PRESSURE_IOCTL_MAGIC, 3, int *) +#define PRESSURE_IOCTL_SET_DELAY _IOW(PRESSURE_IOCTL_MAGIC, 4, int *) + + +#define TEMPERATURE_IOCTL_MAGIC 't' +#define TEMPERATURE_IOCTL_GET_ENABLED _IOR(TEMPERATURE_IOCTL_MAGIC, 1, int *) +#define TEMPERATURE_IOCTL_ENABLE _IOW(TEMPERATURE_IOCTL_MAGIC, 2, int *) +#define TEMPERATURE_IOCTL_DISABLE _IOW(TEMPERATURE_IOCTL_MAGIC, 3, int *) +#define TEMPERATURE_IOCTL_SET_DELAY _IOW(TEMPERATURE_IOCTL_MAGIC, 4, int *) + + +extern int sensor_rx_data(struct i2c_client *client, char *rxData, int length); +extern int sensor_tx_data(struct i2c_client *client, char *txData, int length); +extern int sensor_write_reg(struct i2c_client *client, int addr, int value); +extern int sensor_read_reg(struct i2c_client *client, int addr); +extern int sensor_tx_data_normal(struct i2c_client *client, char *buf, int num); +extern int sensor_rx_data_normal(struct i2c_client *client, char *buf, int num); +extern int sensor_write_reg_normal(struct i2c_client *client, char value); +extern int sensor_read_reg_normal(struct i2c_client *client); + diff --git a/include/linux/soc/rockchip/pvtm.h b/include/linux/soc/rockchip/pvtm.h new file mode 100644 index 000000000000..32c7341c3ece --- /dev/null +++ b/include/linux/soc/rockchip/pvtm.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __SOC_ROCKCHIP_PVTM_H +#define __SOC_ROCKCHIP_PVTM_H + +#ifdef CONFIG_ROCKCHIP_PVTM +u32 rockchip_get_pvtm_value(unsigned int ch, unsigned int sub_ch, + unsigned int time_us); +#else +static inline u32 rockchip_get_pvtm_value(unsigned int ch, unsigned int sub_ch, + unsigned int time_us) +{ + return 0; +} +#endif + +#endif /* __SOC_ROCKCHIP_PVTM_H */ diff --git a/include/linux/soc/rockchip/rk_fiq_debugger.h b/include/linux/soc/rockchip/rk_fiq_debugger.h new file mode 100644 index 000000000000..0398974d2e13 --- /dev/null +++ b/include/linux/soc/rockchip/rk_fiq_debugger.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __PLAT_RK_FIQ_DEBUGGER_H +#define __PLAT_RK_FIQ_DEBUGGER_H + +#ifdef CONFIG_FIQ_DEBUGGER +void rk_serial_debug_init(void __iomem *base, phys_addr_t phy_base, + int irq, int signal_irq, + int wakeup_irq, unsigned int baudrate); +#else +static inline void +void rk_serial_debug_init(void __iomem *base, phys_addr_t phy_base, + int irq, int signal_irq, + int wakeup_irq, unsigned int baudrate) +{ +} +#endif + +#ifdef CONFIG_FIQ_DEBUGGER_TRUST_ZONE +void fiq_debugger_fiq(void *regs, u32 cpu); +#endif + +#endif diff --git a/include/linux/soc/rockchip/rk_vendor_storage.h b/include/linux/soc/rockchip/rk_vendor_storage.h new file mode 100644 index 000000000000..afe7a5473275 --- /dev/null +++ b/include/linux/soc/rockchip/rk_vendor_storage.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +#ifndef __PLAT_RK_VENDOR_STORAGE_H +#define __PLAT_RK_VENDOR_STORAGE_H + +#define RSV_ID 0 +#define SN_ID 1 +#define WIFI_MAC_ID 2 +#define LAN_MAC_ID 3 +#define BT_MAC_ID 4 +#define SENSOR_CALIBRATION_ID 7 + +int rk_vendor_read(u32 id, void *pbuf, u32 size); +int rk_vendor_write(u32 id, void *pbuf, u32 size); +int rk_vendor_register(void *read, void *write); +bool is_rk_vendor_ready(void); + +#endif diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index eead8ab93c0a..cddcbcc7a66f 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -121,6 +121,7 @@ struct plat_stmmacenet_data { void (*bus_setup)(void __iomem *ioaddr); int (*init)(struct platform_device *pdev, void *priv); void (*exit)(struct platform_device *pdev, void *priv); + void (*get_eth_addr)(void *priv, unsigned char *addr); void *bsp_priv; }; #endif diff --git a/include/linux/string.h b/include/linux/string.h index 98bb781a2eff..c0c8878e321e 100644 --- a/include/linux/string.h +++ b/include/linux/string.h @@ -134,6 +134,8 @@ static inline int strtobool(const char *s, bool *res) return kstrtobool(s, res); } +int match_string(const char * const *array, size_t n, const char *string); + #ifdef CONFIG_BINARY_PRINTF int vbin_printf(u32 *bin_buf, size_t size, const char *fmt, va_list args); int bstr_printf(char *buf, size_t size, const char *fmt, const u32 *bin_buf); diff --git a/include/linux/switch.h b/include/linux/switch.h new file mode 100644 index 000000000000..3e4c748e343a --- /dev/null +++ b/include/linux/switch.h @@ -0,0 +1,53 @@ +/* + * Switch class driver + * + * Copyright (C) 2008 Google, Inc. + * Author: Mike Lockwood <lockwood@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * +*/ + +#ifndef __LINUX_SWITCH_H__ +#define __LINUX_SWITCH_H__ + +struct switch_dev { + const char *name; + struct device *dev; + int index; + int state; + + ssize_t (*print_name)(struct switch_dev *sdev, char *buf); + ssize_t (*print_state)(struct switch_dev *sdev, char *buf); +}; + +struct gpio_switch_platform_data { + const char *name; + unsigned gpio; + + /* if NULL, switch_dev.name will be printed */ + const char *name_on; + const char *name_off; + /* if NULL, "0" or "1" will be printed */ + const char *state_on; + const char *state_off; +}; + +extern int switch_dev_register(struct switch_dev *sdev); +extern void switch_dev_unregister(struct switch_dev *sdev); + +static inline int switch_get_state(struct switch_dev *sdev) +{ + return sdev->state; +} + +extern void switch_set_state(struct switch_dev *sdev, int state); + +#endif /* __LINUX_SWITCH_H__ */ diff --git a/include/linux/thermal.h b/include/linux/thermal.h index 4a849f19e6c9..5b0718c850ce 100644 --- a/include/linux/thermal.h +++ b/include/linux/thermal.h @@ -98,6 +98,7 @@ struct thermal_zone_device_ops { int (*unbind) (struct thermal_zone_device *, struct thermal_cooling_device *); int (*get_temp) (struct thermal_zone_device *, int *); + int (*set_trips) (struct thermal_zone_device *, int, int); int (*get_mode) (struct thermal_zone_device *, enum thermal_device_mode *); int (*set_mode) (struct thermal_zone_device *, @@ -182,6 +183,7 @@ struct thermal_attr { * @lock: lock to protect thermal_instances list * @node: node in thermal_tz_list (in thermal_core.c) * @poll_queue: delayed work for polling + * @thermal_notifier_list: list head of thermal notifier */ struct thermal_zone_device { int id; @@ -199,6 +201,8 @@ struct thermal_zone_device { int last_temperature; int emul_temperature; int passive; + int prev_low_trip; + int prev_high_trip; unsigned int forced_passive; atomic_t need_update; struct thermal_zone_device_ops *ops; @@ -210,6 +214,9 @@ struct thermal_zone_device { struct mutex lock; struct list_head node; struct delayed_work poll_queue; +#ifdef CONFIG_ARCH_ROCKCHIP + struct srcu_notifier_head thermal_notifier_list; +#endif }; /** @@ -333,13 +340,18 @@ struct thermal_genl_event { * * Optional: * @get_trend: a pointer to a function that reads the sensor temperature trend. + * @@set_trips: a pointer to a function that sets a temperature window. When this + * window is left the driver must inform the thermal core via + * thermal_zone_device_update. * @set_emul_temp: a pointer to a function that sets sensor emulated * temperature. */ struct thermal_zone_of_device_ops { int (*get_temp)(void *, int *); - int (*get_trend)(void *, long *); + int (*get_trend)(void *, int, enum thermal_trend *); + int (*set_trips)(void *, int, int); int (*set_emul_temp)(void *, int); + int (*set_trip_temp)(void *, int, int); }; /** @@ -352,8 +364,8 @@ struct thermal_zone_of_device_ops { struct thermal_trip { struct device_node *np; - unsigned long int temperature; - unsigned long int hysteresis; + int temperature; + int hysteresis; enum thermal_trip_type type; }; @@ -364,6 +376,11 @@ thermal_zone_of_sensor_register(struct device *dev, int id, void *data, const struct thermal_zone_of_device_ops *ops); void thermal_zone_of_sensor_unregister(struct device *dev, struct thermal_zone_device *tz); +struct thermal_zone_device *devm_thermal_zone_of_sensor_register( + struct device *dev, int id, void *data, + const struct thermal_zone_of_device_ops *ops); +void devm_thermal_zone_of_sensor_unregister(struct device *dev, + struct thermal_zone_device *tz); #else static inline struct thermal_zone_device * thermal_zone_of_sensor_register(struct device *dev, int id, void *data, @@ -378,6 +395,19 @@ void thermal_zone_of_sensor_unregister(struct device *dev, { } +static inline struct thermal_zone_device *devm_thermal_zone_of_sensor_register( + struct device *dev, int id, void *data, + const struct thermal_zone_of_device_ops *ops) +{ + return ERR_PTR(-ENODEV); +} + +static inline +void devm_thermal_zone_of_sensor_unregister(struct device *dev, + struct thermal_zone_device *tz) +{ +} + #endif #if IS_ENABLED(CONFIG_THERMAL) diff --git a/include/linux/timer.h b/include/linux/timer.h index 61aa61dc410c..7bb8e0787d48 100644 --- a/include/linux/timer.h +++ b/include/linux/timer.h @@ -150,6 +150,20 @@ static inline void init_timer_on_stack_key(struct timer_list *timer, #define setup_deferrable_timer_on_stack(timer, fn, data) \ __setup_timer_on_stack((timer), (fn), (data), TIMER_DEFERRABLE) +#define TIMER_DATA_TYPE unsigned long +#define TIMER_FUNC_TYPE void (*)(TIMER_DATA_TYPE) + +static inline void timer_setup(struct timer_list *timer, + void (*callback)(struct timer_list *), + unsigned int flags) +{ + __setup_timer(timer, (TIMER_FUNC_TYPE)callback, + (TIMER_DATA_TYPE)timer, flags); +} + +#define from_timer(var, callback_timer, timer_fieldname) \ + container_of(callback_timer, typeof(*var), timer_fieldname) + /** * timer_pending - is a timer pending? * @timer: the timer in question diff --git a/include/linux/tty.h b/include/linux/tty.h index 812cdd8cff22..bac8e6dc8689 100644 --- a/include/linux/tty.h +++ b/include/linux/tty.h @@ -374,6 +374,8 @@ extern struct tty_struct *get_current_tty(void); /* tty_io.c */ extern int __init tty_init(void); extern const char *tty_name(const struct tty_struct *tty); +extern int tty_ldisc_lock(struct tty_struct *tty, unsigned long timeout); +extern void tty_ldisc_unlock(struct tty_struct *tty); #else static inline void console_init(void) { } diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h index 7e84aac39ade..b690286cb10b 100644 --- a/include/linux/usb/gadget.h +++ b/include/linux/usb/gadget.h @@ -25,6 +25,8 @@ #include <linux/workqueue.h> #include <linux/usb/ch9.h> +#define UDC_TRACE_STR_MAX 512 + struct usb_ep; /** @@ -228,304 +230,50 @@ struct usb_ep { /*-------------------------------------------------------------------------*/ -/** - * usb_ep_set_maxpacket_limit - set maximum packet size limit for endpoint - * @ep:the endpoint being configured - * @maxpacket_limit:value of maximum packet size limit - * - * This function should be used only in UDC drivers to initialize endpoint - * (usually in probe function). - */ +#if IS_ENABLED(CONFIG_USB_GADGET) +void usb_ep_set_maxpacket_limit(struct usb_ep *ep, unsigned maxpacket_limit); +int usb_ep_enable(struct usb_ep *ep); +int usb_ep_disable(struct usb_ep *ep); +struct usb_request *usb_ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags); +void usb_ep_free_request(struct usb_ep *ep, struct usb_request *req); +int usb_ep_queue(struct usb_ep *ep, struct usb_request *req, gfp_t gfp_flags); +int usb_ep_dequeue(struct usb_ep *ep, struct usb_request *req); +int usb_ep_set_halt(struct usb_ep *ep); +int usb_ep_clear_halt(struct usb_ep *ep); +int usb_ep_set_wedge(struct usb_ep *ep); +int usb_ep_fifo_status(struct usb_ep *ep); +void usb_ep_fifo_flush(struct usb_ep *ep); +#else static inline void usb_ep_set_maxpacket_limit(struct usb_ep *ep, unsigned maxpacket_limit) -{ - ep->maxpacket_limit = maxpacket_limit; - ep->maxpacket = maxpacket_limit; -} - -/** - * usb_ep_enable - configure endpoint, making it usable - * @ep:the endpoint being configured. may not be the endpoint named "ep0". - * drivers discover endpoints through the ep_list of a usb_gadget. - * - * When configurations are set, or when interface settings change, the driver - * will enable or disable the relevant endpoints. while it is enabled, an - * endpoint may be used for i/o until the driver receives a disconnect() from - * the host or until the endpoint is disabled. - * - * the ep0 implementation (which calls this routine) must ensure that the - * hardware capabilities of each endpoint match the descriptor provided - * for it. for example, an endpoint named "ep2in-bulk" would be usable - * for interrupt transfers as well as bulk, but it likely couldn't be used - * for iso transfers or for endpoint 14. some endpoints are fully - * configurable, with more generic names like "ep-a". (remember that for - * USB, "in" means "towards the USB master".) - * - * returns zero, or a negative error code. - */ +{ } static inline int usb_ep_enable(struct usb_ep *ep) -{ - int ret; - - if (ep->enabled) - return 0; - - ret = ep->ops->enable(ep, ep->desc); - if (ret) - return ret; - - ep->enabled = true; - - return 0; -} - -/** - * usb_ep_disable - endpoint is no longer usable - * @ep:the endpoint being unconfigured. may not be the endpoint named "ep0". - * - * no other task may be using this endpoint when this is called. - * any pending and uncompleted requests will complete with status - * indicating disconnect (-ESHUTDOWN) before this call returns. - * gadget drivers must call usb_ep_enable() again before queueing - * requests to the endpoint. - * - * returns zero, or a negative error code. - */ +{ return 0; } static inline int usb_ep_disable(struct usb_ep *ep) -{ - int ret; - - if (!ep->enabled) - return 0; - - ret = ep->ops->disable(ep); - if (ret) - return ret; - - ep->enabled = false; - - return 0; -} - -/** - * usb_ep_alloc_request - allocate a request object to use with this endpoint - * @ep:the endpoint to be used with with the request - * @gfp_flags:GFP_* flags to use - * - * Request objects must be allocated with this call, since they normally - * need controller-specific setup and may even need endpoint-specific - * resources such as allocation of DMA descriptors. - * Requests may be submitted with usb_ep_queue(), and receive a single - * completion callback. Free requests with usb_ep_free_request(), when - * they are no longer needed. - * - * Returns the request, or null if one could not be allocated. - */ +{ return 0; } static inline struct usb_request *usb_ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) -{ - return ep->ops->alloc_request(ep, gfp_flags); -} - -/** - * usb_ep_free_request - frees a request object - * @ep:the endpoint associated with the request - * @req:the request being freed - * - * Reverses the effect of usb_ep_alloc_request(). - * Caller guarantees the request is not queued, and that it will - * no longer be requeued (or otherwise used). - */ +{ return NULL; } static inline void usb_ep_free_request(struct usb_ep *ep, struct usb_request *req) -{ - ep->ops->free_request(ep, req); -} +{ } -/** - * usb_ep_queue - queues (submits) an I/O request to an endpoint. - * @ep:the endpoint associated with the request - * @req:the request being submitted - * @gfp_flags: GFP_* flags to use in case the lower level driver couldn't - * pre-allocate all necessary memory with the request. - * - * This tells the device controller to perform the specified request through - * that endpoint (reading or writing a buffer). When the request completes, - * including being canceled by usb_ep_dequeue(), the request's completion - * routine is called to return the request to the driver. Any endpoint - * (except control endpoints like ep0) may have more than one transfer - * request queued; they complete in FIFO order. Once a gadget driver - * submits a request, that request may not be examined or modified until it - * is given back to that driver through the completion callback. - * - * Each request is turned into one or more packets. The controller driver - * never merges adjacent requests into the same packet. OUT transfers - * will sometimes use data that's already buffered in the hardware. - * Drivers can rely on the fact that the first byte of the request's buffer - * always corresponds to the first byte of some USB packet, for both - * IN and OUT transfers. - * - * Bulk endpoints can queue any amount of data; the transfer is packetized - * automatically. The last packet will be short if the request doesn't fill it - * out completely. Zero length packets (ZLPs) should be avoided in portable - * protocols since not all usb hardware can successfully handle zero length - * packets. (ZLPs may be explicitly written, and may be implicitly written if - * the request 'zero' flag is set.) Bulk endpoints may also be used - * for interrupt transfers; but the reverse is not true, and some endpoints - * won't support every interrupt transfer. (Such as 768 byte packets.) - * - * Interrupt-only endpoints are less functional than bulk endpoints, for - * example by not supporting queueing or not handling buffers that are - * larger than the endpoint's maxpacket size. They may also treat data - * toggle differently. - * - * Control endpoints ... after getting a setup() callback, the driver queues - * one response (even if it would be zero length). That enables the - * status ack, after transferring data as specified in the response. Setup - * functions may return negative error codes to generate protocol stalls. - * (Note that some USB device controllers disallow protocol stall responses - * in some cases.) When control responses are deferred (the response is - * written after the setup callback returns), then usb_ep_set_halt() may be - * used on ep0 to trigger protocol stalls. Depending on the controller, - * it may not be possible to trigger a status-stage protocol stall when the - * data stage is over, that is, from within the response's completion - * routine. - * - * For periodic endpoints, like interrupt or isochronous ones, the usb host - * arranges to poll once per interval, and the gadget driver usually will - * have queued some data to transfer at that time. - * - * Returns zero, or a negative error code. Endpoints that are not enabled - * report errors; errors will also be - * reported when the usb peripheral is disconnected. - */ static inline int usb_ep_queue(struct usb_ep *ep, struct usb_request *req, gfp_t gfp_flags) -{ - return ep->ops->queue(ep, req, gfp_flags); -} - -/** - * usb_ep_dequeue - dequeues (cancels, unlinks) an I/O request from an endpoint - * @ep:the endpoint associated with the request - * @req:the request being canceled - * - * If the request is still active on the endpoint, it is dequeued and its - * completion routine is called (with status -ECONNRESET); else a negative - * error code is returned. This is guaranteed to happen before the call to - * usb_ep_dequeue() returns. - * - * Note that some hardware can't clear out write fifos (to unlink the request - * at the head of the queue) except as part of disconnecting from usb. Such - * restrictions prevent drivers from supporting configuration changes, - * even to configuration zero (a "chapter 9" requirement). - */ +{ return 0; } static inline int usb_ep_dequeue(struct usb_ep *ep, struct usb_request *req) -{ - return ep->ops->dequeue(ep, req); -} - -/** - * usb_ep_set_halt - sets the endpoint halt feature. - * @ep: the non-isochronous endpoint being stalled - * - * Use this to stall an endpoint, perhaps as an error report. - * Except for control endpoints, - * the endpoint stays halted (will not stream any data) until the host - * clears this feature; drivers may need to empty the endpoint's request - * queue first, to make sure no inappropriate transfers happen. - * - * Note that while an endpoint CLEAR_FEATURE will be invisible to the - * gadget driver, a SET_INTERFACE will not be. To reset endpoints for the - * current altsetting, see usb_ep_clear_halt(). When switching altsettings, - * it's simplest to use usb_ep_enable() or usb_ep_disable() for the endpoints. - * - * Returns zero, or a negative error code. On success, this call sets - * underlying hardware state that blocks data transfers. - * Attempts to halt IN endpoints will fail (returning -EAGAIN) if any - * transfer requests are still queued, or if the controller hardware - * (usually a FIFO) still holds bytes that the host hasn't collected. - */ +{ return 0; } static inline int usb_ep_set_halt(struct usb_ep *ep) -{ - return ep->ops->set_halt(ep, 1); -} - -/** - * usb_ep_clear_halt - clears endpoint halt, and resets toggle - * @ep:the bulk or interrupt endpoint being reset - * - * Use this when responding to the standard usb "set interface" request, - * for endpoints that aren't reconfigured, after clearing any other state - * in the endpoint's i/o queue. - * - * Returns zero, or a negative error code. On success, this call clears - * the underlying hardware state reflecting endpoint halt and data toggle. - * Note that some hardware can't support this request (like pxa2xx_udc), - * and accordingly can't correctly implement interface altsettings. - */ +{ return 0; } static inline int usb_ep_clear_halt(struct usb_ep *ep) -{ - return ep->ops->set_halt(ep, 0); -} - -/** - * usb_ep_set_wedge - sets the halt feature and ignores clear requests - * @ep: the endpoint being wedged - * - * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT) - * requests. If the gadget driver clears the halt status, it will - * automatically unwedge the endpoint. - * - * Returns zero on success, else negative errno. - */ -static inline int -usb_ep_set_wedge(struct usb_ep *ep) -{ - if (ep->ops->set_wedge) - return ep->ops->set_wedge(ep); - else - return ep->ops->set_halt(ep, 1); -} - -/** - * usb_ep_fifo_status - returns number of bytes in fifo, or error - * @ep: the endpoint whose fifo status is being checked. - * - * FIFO endpoints may have "unclaimed data" in them in certain cases, - * such as after aborted transfers. Hosts may not have collected all - * the IN data written by the gadget driver (and reported by a request - * completion). The gadget driver may not have collected all the data - * written OUT to it by the host. Drivers that need precise handling for - * fault reporting or recovery may need to use this call. - * - * This returns the number of such bytes in the fifo, or a negative - * errno if the endpoint doesn't use a FIFO or doesn't support such - * precise handling. - */ +{ return 0; } +static inline int usb_ep_set_wedge(struct usb_ep *ep) +{ return 0; } static inline int usb_ep_fifo_status(struct usb_ep *ep) -{ - if (ep->ops->fifo_status) - return ep->ops->fifo_status(ep); - else - return -EOPNOTSUPP; -} - -/** - * usb_ep_fifo_flush - flushes contents of a fifo - * @ep: the endpoint whose fifo is being flushed. - * - * This call may be used to flush the "unclaimed data" that may exist in - * an endpoint fifo after abnormal transaction terminations. The call - * must never be used except when endpoint is not being used for any - * protocol translation. - */ +{ return 0; } static inline void usb_ep_fifo_flush(struct usb_ep *ep) -{ - if (ep->ops->fifo_flush) - ep->ops->fifo_flush(ep); -} - +{ } +#endif /* USB_GADGET */ /*-------------------------------------------------------------------------*/ @@ -579,6 +327,7 @@ struct usb_gadget_ops { * @dev: Driver model state for this abstract device. * @out_epnum: last used out ep number * @in_epnum: last used in ep number + * @mA: last set mA value * @otg_caps: OTG capabilities of this gadget. * @sg_supported: true if we can handle scatter-gather * @is_otg: True if the USB device port uses a Mini-AB jack, so that the @@ -598,6 +347,7 @@ struct usb_gadget_ops { * @deactivated: True if gadget is deactivated - in deactivated state it cannot * be connected. * @connected: True if gadget is connected. + * @uvc_enabled: True if uvc function is enabled. * * Gadgets have a mostly-portable "gadget driver" implementing device * functions, handling all usb configurations and interfaces. Gadget @@ -631,6 +381,7 @@ struct usb_gadget { struct device dev; unsigned out_epnum; unsigned in_epnum; + unsigned mA; struct usb_otg_caps *otg_caps; unsigned sg_supported:1; @@ -646,6 +397,7 @@ struct usb_gadget { unsigned is_selfpowered:1; unsigned deactivated:1; unsigned connected:1; + unsigned uvc_enabled:1; }; #define work_to_gadget(w) (container_of((w), struct usb_gadget, work)) @@ -752,251 +504,44 @@ static inline int gadget_is_otg(struct usb_gadget *g) #endif } -/** - * usb_gadget_frame_number - returns the current frame number - * @gadget: controller that reports the frame number - * - * Returns the usb frame number, normally eleven bits from a SOF packet, - * or negative errno if this device doesn't support this capability. - */ -static inline int usb_gadget_frame_number(struct usb_gadget *gadget) -{ - return gadget->ops->get_frame(gadget); -} +/*-------------------------------------------------------------------------*/ -/** - * usb_gadget_wakeup - tries to wake up the host connected to this gadget - * @gadget: controller used to wake up the host - * - * Returns zero on success, else negative error code if the hardware - * doesn't support such attempts, or its support has not been enabled - * by the usb host. Drivers must return device descriptors that report - * their ability to support this, or hosts won't enable it. - * - * This may also try to use SRP to wake the host and start enumeration, - * even if OTG isn't otherwise in use. OTG devices may also start - * remote wakeup even when hosts don't explicitly enable it. - */ +#if IS_ENABLED(CONFIG_USB_GADGET) +int usb_gadget_frame_number(struct usb_gadget *gadget); +int usb_gadget_wakeup(struct usb_gadget *gadget); +int usb_gadget_set_selfpowered(struct usb_gadget *gadget); +int usb_gadget_clear_selfpowered(struct usb_gadget *gadget); +int usb_gadget_vbus_connect(struct usb_gadget *gadget); +int usb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA); +int usb_gadget_vbus_disconnect(struct usb_gadget *gadget); +int usb_gadget_connect(struct usb_gadget *gadget); +int usb_gadget_disconnect(struct usb_gadget *gadget); +int usb_gadget_deactivate(struct usb_gadget *gadget); +int usb_gadget_activate(struct usb_gadget *gadget); +#else +static inline int usb_gadget_frame_number(struct usb_gadget *gadget) +{ return 0; } static inline int usb_gadget_wakeup(struct usb_gadget *gadget) -{ - if (!gadget->ops->wakeup) - return -EOPNOTSUPP; - return gadget->ops->wakeup(gadget); -} - -/** - * usb_gadget_set_selfpowered - sets the device selfpowered feature. - * @gadget:the device being declared as self-powered - * - * this affects the device status reported by the hardware driver - * to reflect that it now has a local power supply. - * - * returns zero on success, else negative errno. - */ +{ return 0; } static inline int usb_gadget_set_selfpowered(struct usb_gadget *gadget) -{ - if (!gadget->ops->set_selfpowered) - return -EOPNOTSUPP; - return gadget->ops->set_selfpowered(gadget, 1); -} - -/** - * usb_gadget_clear_selfpowered - clear the device selfpowered feature. - * @gadget:the device being declared as bus-powered - * - * this affects the device status reported by the hardware driver. - * some hardware may not support bus-powered operation, in which - * case this feature's value can never change. - * - * returns zero on success, else negative errno. - */ +{ return 0; } static inline int usb_gadget_clear_selfpowered(struct usb_gadget *gadget) -{ - if (!gadget->ops->set_selfpowered) - return -EOPNOTSUPP; - return gadget->ops->set_selfpowered(gadget, 0); -} - -/** - * usb_gadget_vbus_connect - Notify controller that VBUS is powered - * @gadget:The device which now has VBUS power. - * Context: can sleep - * - * This call is used by a driver for an external transceiver (or GPIO) - * that detects a VBUS power session starting. Common responses include - * resuming the controller, activating the D+ (or D-) pullup to let the - * host detect that a USB device is attached, and starting to draw power - * (8mA or possibly more, especially after SET_CONFIGURATION). - * - * Returns zero on success, else negative errno. - */ +{ return 0; } static inline int usb_gadget_vbus_connect(struct usb_gadget *gadget) -{ - if (!gadget->ops->vbus_session) - return -EOPNOTSUPP; - return gadget->ops->vbus_session(gadget, 1); -} - -/** - * usb_gadget_vbus_draw - constrain controller's VBUS power usage - * @gadget:The device whose VBUS usage is being described - * @mA:How much current to draw, in milliAmperes. This should be twice - * the value listed in the configuration descriptor bMaxPower field. - * - * This call is used by gadget drivers during SET_CONFIGURATION calls, - * reporting how much power the device may consume. For example, this - * could affect how quickly batteries are recharged. - * - * Returns zero on success, else negative errno. - */ +{ return 0; } static inline int usb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA) -{ - if (!gadget->ops->vbus_draw) - return -EOPNOTSUPP; - return gadget->ops->vbus_draw(gadget, mA); -} - -/** - * usb_gadget_vbus_disconnect - notify controller about VBUS session end - * @gadget:the device whose VBUS supply is being described - * Context: can sleep - * - * This call is used by a driver for an external transceiver (or GPIO) - * that detects a VBUS power session ending. Common responses include - * reversing everything done in usb_gadget_vbus_connect(). - * - * Returns zero on success, else negative errno. - */ +{ return 0; } static inline int usb_gadget_vbus_disconnect(struct usb_gadget *gadget) -{ - if (!gadget->ops->vbus_session) - return -EOPNOTSUPP; - return gadget->ops->vbus_session(gadget, 0); -} - -/** - * usb_gadget_connect - software-controlled connect to USB host - * @gadget:the peripheral being connected - * - * Enables the D+ (or potentially D-) pullup. The host will start - * enumerating this gadget when the pullup is active and a VBUS session - * is active (the link is powered). This pullup is always enabled unless - * usb_gadget_disconnect() has been used to disable it. - * - * Returns zero on success, else negative errno. - */ +{ return 0; } static inline int usb_gadget_connect(struct usb_gadget *gadget) -{ - int ret; - - if (!gadget->ops->pullup) - return -EOPNOTSUPP; - - if (gadget->deactivated) { - /* - * If gadget is deactivated we only save new state. - * Gadget will be connected automatically after activation. - */ - gadget->connected = true; - return 0; - } - - ret = gadget->ops->pullup(gadget, 1); - if (!ret) - gadget->connected = 1; - return ret; -} - -/** - * usb_gadget_disconnect - software-controlled disconnect from USB host - * @gadget:the peripheral being disconnected - * - * Disables the D+ (or potentially D-) pullup, which the host may see - * as a disconnect (when a VBUS session is active). Not all systems - * support software pullup controls. - * - * Returns zero on success, else negative errno. - */ +{ return 0; } static inline int usb_gadget_disconnect(struct usb_gadget *gadget) -{ - int ret; - - if (!gadget->ops->pullup) - return -EOPNOTSUPP; - - if (gadget->deactivated) { - /* - * If gadget is deactivated we only save new state. - * Gadget will stay disconnected after activation. - */ - gadget->connected = false; - return 0; - } - - ret = gadget->ops->pullup(gadget, 0); - if (!ret) - gadget->connected = 0; - return ret; -} - -/** - * usb_gadget_deactivate - deactivate function which is not ready to work - * @gadget: the peripheral being deactivated - * - * This routine may be used during the gadget driver bind() call to prevent - * the peripheral from ever being visible to the USB host, unless later - * usb_gadget_activate() is called. For example, user mode components may - * need to be activated before the system can talk to hosts. - * - * Returns zero on success, else negative errno. - */ +{ return 0; } static inline int usb_gadget_deactivate(struct usb_gadget *gadget) -{ - int ret; - - if (gadget->deactivated) - return 0; - - if (gadget->connected) { - ret = usb_gadget_disconnect(gadget); - if (ret) - return ret; - /* - * If gadget was being connected before deactivation, we want - * to reconnect it in usb_gadget_activate(). - */ - gadget->connected = true; - } - gadget->deactivated = true; - - return 0; -} - -/** - * usb_gadget_activate - activate function which is not ready to work - * @gadget: the peripheral being activated - * - * This routine activates gadget which was previously deactivated with - * usb_gadget_deactivate() call. It calls usb_gadget_connect() if needed. - * - * Returns zero on success, else negative errno. - */ +{ return 0; } static inline int usb_gadget_activate(struct usb_gadget *gadget) -{ - if (!gadget->deactivated) - return 0; - - gadget->deactivated = false; - - /* - * If gadget has been connected before deactivation, or became connected - * while it was being deactivated, we call usb_gadget_connect(). - */ - if (gadget->connected) - return usb_gadget_connect(gadget); - - return 0; -} +{ return 0; } +#endif /* CONFIG_USB_GADGET */ /*-------------------------------------------------------------------------*/ diff --git a/include/linux/usb/hcd.h b/include/linux/usb/hcd.h index 757c554408ce..acce195be773 100644 --- a/include/linux/usb/hcd.h +++ b/include/linux/usb/hcd.h @@ -159,6 +159,7 @@ struct usb_hcd { unsigned tpl_support:1; /* OTG & EH TPL support */ unsigned cant_recv_wakeups:1; /* wakeup requests from downstream aren't received */ + unsigned rk3288_relinquish_port_quirk:1; unsigned int irq; /* irq allocated */ void __iomem *regs; /* device memory/io */ diff --git a/include/linux/usb/of.h b/include/linux/usb/of.h index c3fe9e48ce27..cd5be413b265 100644 --- a/include/linux/usb/of.h +++ b/include/linux/usb/of.h @@ -12,10 +12,16 @@ #include <linux/usb/phy.h> #if IS_ENABLED(CONFIG_OF) +enum usb_dr_mode of_usb_get_dr_mode_by_phy(struct device_node *np, int arg0); bool of_usb_host_tpl_support(struct device_node *np); int of_usb_update_otg_caps(struct device_node *np, struct usb_otg_caps *otg_caps); #else +static inline enum usb_dr_mode +of_usb_get_dr_mode_by_phy(struct device_node *np, int arg0) +{ + return USB_DR_MODE_UNKNOWN; +} static inline bool of_usb_host_tpl_support(struct device_node *np) { return false; diff --git a/include/linux/usb/quirks.h b/include/linux/usb/quirks.h index ea4f81c2a6d5..d36da901224e 100644 --- a/include/linux/usb/quirks.h +++ b/include/linux/usb/quirks.h @@ -56,6 +56,9 @@ */ #define USB_QUIRK_LINEAR_FRAME_INTR_BINTERVAL BIT(11) +/* device can't support auto suspend function */ +#define USB_QUIRK_AUTO_SUSPEND BIT(12) + /* Device needs a pause after every control message. */ #define USB_QUIRK_DELAY_CTRL_MSG BIT(13) diff --git a/include/linux/usb/xhci_pdriver.h b/include/linux/usb/xhci_pdriver.h index 376654b5b0f7..5df42af8a404 100644 --- a/include/linux/usb/xhci_pdriver.h +++ b/include/linux/usb/xhci_pdriver.h @@ -18,10 +18,19 @@ * * @usb3_lpm_capable: determines if this xhci platform supports USB3 * LPM capability + * @xhci_slow_suspend: set if this xhci platform need an extraordinary + * delay to wait for xHC enter the Halted state + * after the Run/Stop (R/S) bit is cleared to '0'. + * @usb3_disable_autosuspend: determines if this xhci platform supports + * USB3 autosuspend capability + * @usb3_warm_reset_on_resume: determines if it need warm reset on resume. * */ struct usb_xhci_pdata { unsigned usb3_lpm_capable:1; + unsigned xhci_slow_suspend:1; + unsigned usb3_disable_autosuspend:1; + unsigned usb3_warm_reset_on_resume:1; }; #endif /* __USB_CORE_XHCI_PDRIVER_H */ diff --git a/include/media/camsys_head.h b/include/media/camsys_head.h new file mode 100644 index 000000000000..4b9bcc5dd831 --- /dev/null +++ b/include/media/camsys_head.h @@ -0,0 +1,294 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __RKCAMSYS_HEAR_H__ +#define __RKCAMSYS_HEAR_H__ + +#include <linux/ioctl.h> + +/* +* C A M S Y S H E A D F I L E V E R S I O N +* +*v0.0.1: +* 1) test version; +*v0.0.2: +* 1) modify camsys_irqcnnt_t; +*v0.0.3: +* 1) add support cif phy for marvin; +*v0.0.4: +* 1) add clock information in struct camsys_devio_name_s; +*v0.0.5: +* 1) add pwren control +*v0.6.0: +* 1) add support mipi phy configuration; +* 2) add support io domain and mclk driver strength configuration; +*v0.7.0: + 1) add flash_trigger_out control +*v0.8.0: + 1) support isp iommu +*v0.9.0: + 1) add dev_name in struct camsys_devio_name_s; +*v0.a.0: + 1) support external flash IC +*v0.b.0: + 1) add CamSys_SensorBit0_CifBit4 in enum camsys_cifio_e. +*v0.c.0: + 1) support sensor powerup sequence configurable. +*v0.d.0: + 1) powerup sequence type moved to common_head.h. +*v0.e.0: + 1) add fs_id, fe_id and some reserved bytes in struct camsys_irqsta_s. +*v0.f.0: + 1) add pid in struct camsys_irqsta_s. +*v1.0.0: + 1) add enum camsys_mipiphy_dir_e. +*/ + +#define CAMSYS_HEAD_VERSION KERNEL_VERSION(1, 0x0, 0) + +#define CAMSYS_MARVIN_DEVNAME "camsys_marvin" +#define CAMSYS_CIF0_DEVNAME "camsys_cif0" +#define CAMSYS_CIF1_DEVNAME "camsys_cif1" + +#define CAMSYS_NAME_LEN 32 + +#define CAMSYS_DEVID_MARVIN 0x00000001 +#define CAMSYS_DEVID_CIF_0 0x00000002 +#define CAMSYS_DEVID_CIF_1 0x00000004 +#define CAMSYS_DEVID_INTERNAL 0x000000FF + +#define CAMSYS_DEVID_SENSOR_1A 0x01000000 +#define CAMSYS_DEVID_SENSOR_1B 0x02000000 +#define CAMSYS_DEVID_SENSOR_2 0x04000000 +#define CAMSYS_DEVID_EXTERNAL 0xFF000000 +#define CAMSYS_DEVID_EXTERNAL_NUM 8 + +#define CAMSYS_DEVCFG_FLASHLIGHT 0x00000001 +#define CAMSYS_DEVCFG_PREFLASHLIGHT 0x00000002 +#define CAMSYS_DEVCFG_SHUTTER 0x00000004 + +typedef struct camsys_irqsta_s { + unsigned int ris; //Raw interrupt status + unsigned int mis; //Masked interrupt status + unsigned int fs_id; // frame number from Frame Start (FS) short packet + unsigned int fe_id; // frame number from Frame End (FE) short packet + int pid; + unsigned int reserved[3]; +} camsys_irqsta_t; + +typedef struct camsys_irqcnnt_s { + int pid; + unsigned int timeout; //us + + unsigned int mis; + unsigned int icr; +} camsys_irqcnnt_t; + +typedef enum camsys_mmap_type_e { //this type can be filled in mmap offset argument + CamSys_Mmap_RegisterMem, + CamSys_Mmap_I2cMem, + + CamSys_Mmap_End +} camsys_mmap_type_t; + +typedef struct camsys_querymem_s { + camsys_mmap_type_t mem_type; + unsigned long mem_offset; + + unsigned int mem_size; +} camsys_querymem_t; + +typedef struct camsys_i2c_info_s { + unsigned char bus_num; + unsigned short slave_addr; + unsigned int reg_addr; //i2c device register address + unsigned int reg_size; //register address size + unsigned int val; + unsigned int val_size; //register value size + unsigned int i2cbuf_directly; + unsigned int i2cbuf_bytes; + unsigned int speed; //100000 == 100KHz +} camsys_i2c_info_t; + +typedef struct camsys_reginfo_s { + unsigned int dev_mask; + unsigned int reg_offset; + unsigned int val; +} camsys_reginfo_t; + +typedef enum camsys_sysctrl_ops_e { + + CamSys_Vdd_Start_Tag, + CamSys_Avdd, + CamSys_Dovdd, + CamSys_Dvdd, + CamSys_Afvdd, + CamSys_Vdd_End_Tag, + + CamSys_Gpio_Start_Tag, + CamSys_PwrDn, + CamSys_Rst, + CamSys_AfPwr, + CamSys_AfPwrDn, + CamSys_PwrEn, + CamSys_Gpio_End_Tag, + + CamSys_Clk_Start_Tag, + CamSys_ClkIn, + CamSys_Clk_End_Tag, + + CamSys_Phy_Start_Tag, + CamSys_Phy, + CamSys_Phy_End_Tag, + CamSys_Flash_Trigger_Start_Tag, + CamSys_Flash_Trigger, + CamSys_Flash_Trigger_End_Tag, + CamSys_IOMMU + +} camsys_sysctrl_ops_t; + +typedef struct camsys_regulator_info_s { + unsigned char name[CAMSYS_NAME_LEN]; + int min_uv; + int max_uv; +} camsys_regulator_info_t; + +typedef struct camsys_gpio_info_s { + unsigned char name[CAMSYS_NAME_LEN]; + unsigned int active; +} camsys_gpio_info_t; + +typedef struct camsys_iommu_s{ + int client_fd; + int map_fd; + unsigned long linear_addr; + unsigned long len; +}camsys_iommu_t; + +typedef struct camsys_sysctrl_s { + unsigned int dev_mask; + camsys_sysctrl_ops_t ops; + unsigned int on; + + unsigned int rev[20]; +} camsys_sysctrl_t; + +typedef struct camsys_flash_info_s { + unsigned char fl_drv_name[CAMSYS_NAME_LEN]; + camsys_gpio_info_t fl; //fl_trig + camsys_gpio_info_t fl_en; +} camsys_flash_info_t; + +enum camsys_mipiphy_dir_e { + CamSys_Mipiphy_Rx = 0, + CamSys_Mipiphy_Tx = 1, +}; + +typedef struct camsys_mipiphy_s { + unsigned int data_en_bit; // data lane enable bit; + unsigned int bit_rate; // Mbps/lane + unsigned int phy_index; // phy0,phy1 + enum camsys_mipiphy_dir_e dir; // direction +} camsys_mipiphy_t; + +typedef enum camsys_fmt_e { + CamSys_Fmt_Yuv420_8b = 0x18, + CamSys_Fmt_Yuv420_10b = 0x19, + CamSys_Fmt_LegacyYuv420_8b = 0x19, + + CamSys_Fmt_Yuv422_8b = 0x1e, + CamSys_Fmt_Yuv422_10b = 0x1f, + + CamSys_Fmt_Raw_6b = 0x28, + CamSys_Fmt_Raw_7b = 0x29, + CamSys_Fmt_Raw_8b = 0x2a, + CamSys_Fmt_Raw_10b = 0x2b, + CamSys_Fmt_Raw_12b = 0x2c, + CamSys_Fmt_Raw_14b = 0x2d, +} camsys_fmt_t; + +typedef enum camsys_cifio_e { + CamSys_SensorBit0_CifBit0 = 0x00, + CamSys_SensorBit0_CifBit2 = 0x01, + CamSys_SensorBit0_CifBit4 = 0x02, +} camsys_cifio_t; + +typedef struct camsys_cifphy_s { + unsigned int cif_num; + camsys_fmt_t fmt; + camsys_cifio_t cifio; + +} camsys_cifphy_t; + +typedef enum camsys_phy_type_e { + CamSys_Phy_Mipi, + CamSys_Phy_Cif, + + CamSys_Phy_end +} camsys_phy_type_t; + +typedef struct camsys_extdev_phy_s { + camsys_phy_type_t type; + union { + camsys_mipiphy_t mipi; + camsys_cifphy_t cif; + } info; + +} camsys_extdev_phy_t; + +typedef struct camsys_extdev_clk_s { + unsigned int in_rate; + unsigned int driver_strength; //0 - 3 +} camsys_extdev_clk_t; + +typedef struct camsys_devio_name_s { + unsigned char dev_name[CAMSYS_NAME_LEN]; + unsigned int dev_id; + + camsys_regulator_info_t avdd; // sensor avdd power regulator name + camsys_regulator_info_t dovdd; // sensor dovdd power regulator name + camsys_regulator_info_t dvdd; // sensor dvdd power regulator name "NC" describe no regulator + camsys_regulator_info_t afvdd; + + camsys_gpio_info_t pwrdn; // standby gpio name + camsys_gpio_info_t rst; // hard reset gpio name + camsys_gpio_info_t afpwr; // auto focus vcm driver ic power gpio name + camsys_gpio_info_t afpwrdn; // auto focus vcm driver ic standby gpio + camsys_gpio_info_t pwren; // power enable gpio name + + + camsys_flash_info_t fl; + + camsys_extdev_phy_t phy; + camsys_extdev_clk_t clk; + + unsigned int dev_cfg; // function bit mask configuration +} camsys_devio_name_t; + +typedef struct camsys_version_s { + unsigned int drv_ver; + unsigned int head_ver; +} camsys_version_t; + +/* + * I O C T L C O D E S F O R R O C K C H I P S C A M S Y S D E V I C E S + * + */ +#define CAMSYS_IOC_MAGIC 'M' +#define CAMSYS_IOC_MAXNR 14 + +#define CAMSYS_VERCHK _IOR(CAMSYS_IOC_MAGIC, 0, camsys_version_t) + +#define CAMSYS_I2CRD _IOWR(CAMSYS_IOC_MAGIC, 1, camsys_i2c_info_t) +#define CAMSYS_I2CWR _IOW(CAMSYS_IOC_MAGIC, 2, camsys_i2c_info_t) + +#define CAMSYS_SYSCTRL _IOW(CAMSYS_IOC_MAGIC, 3, camsys_sysctrl_t) +#define CAMSYS_REGRD _IOWR(CAMSYS_IOC_MAGIC, 4, camsys_reginfo_t) +#define CAMSYS_REGWR _IOW(CAMSYS_IOC_MAGIC, 5, camsys_reginfo_t) +#define CAMSYS_REGISTER_DEVIO _IOW(CAMSYS_IOC_MAGIC, 6, camsys_devio_name_t) +#define CAMSYS_DEREGISTER_DEVIO _IOW(CAMSYS_IOC_MAGIC, 7, unsigned int) +#define CAMSYS_IRQCONNECT _IOW(CAMSYS_IOC_MAGIC, 8, camsys_irqcnnt_t) +#define CAMSYS_IRQWAIT _IOR(CAMSYS_IOC_MAGIC, 9, camsys_irqsta_t) +#define CAMSYS_IRQDISCONNECT _IOW(CAMSYS_IOC_MAGIC, 10, camsys_irqcnnt_t) + +#define CAMSYS_QUREYMEM _IOR(CAMSYS_IOC_MAGIC, 11, camsys_querymem_t) +#define CAMSYS_QUREYIOMMU _IOW(CAMSYS_IOC_MAGIC, 12, int) +#endif diff --git a/include/media/cec-notifier.h b/include/media/cec-notifier.h new file mode 100644 index 000000000000..ca19a9305782 --- /dev/null +++ b/include/media/cec-notifier.h @@ -0,0 +1,129 @@ +/* + * cec-notifier.h - notify CEC drivers of physical address changes + * + * Copyright 2016 Russell King <rmk+kernel@arm.linux.org.uk> + * Copyright 2016-2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved. + * + * This program is free software; you may redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef LINUX_CEC_NOTIFIER_H +#define LINUX_CEC_NOTIFIER_H + +#include <linux/types.h> +#include <media/cec.h> + +struct device; +struct edid; +struct cec_adapter; +struct cec_notifier; + +#if IS_REACHABLE(CONFIG_CEC_CORE) && IS_ENABLED(CONFIG_CEC_NOTIFIER) + +/** + * cec_notifier_get - find or create a new cec_notifier for the given device. + * @dev: device that sends the events. + * + * If a notifier for device @dev already exists, then increase the refcount + * and return that notifier. + * + * If it doesn't exist, then allocate a new notifier struct and return a + * pointer to that new struct. + * + * Return NULL if the memory could not be allocated. + */ +struct cec_notifier *cec_notifier_get(struct device *dev); + +/** + * cec_notifier_put - decrease refcount and delete when the refcount reaches 0. + * @n: notifier + */ +void cec_notifier_put(struct cec_notifier *n); + +/** + * cec_notifier_set_phys_addr - set a new physical address. + * @n: the CEC notifier + * @pa: the CEC physical address + * + * Set a new CEC physical address. + * Does nothing if @n == NULL. + */ +void cec_notifier_set_phys_addr(struct cec_notifier *n, u16 pa); + +void cec_notifier_repo_cec_hpd(struct cec_notifier *n, + bool hpd_state, ktime_t ts); + +/** + * cec_notifier_set_phys_addr_from_edid - set parse the PA from the EDID. + * @n: the CEC notifier + * @edid: the struct edid pointer + * + * Parses the EDID to obtain the new CEC physical address and set it. + * Does nothing if @n == NULL. + */ +void cec_notifier_set_phys_addr_from_edid(struct cec_notifier *n, + const struct edid *edid); + +/** + * cec_notifier_register - register a callback with the notifier + * @n: the CEC notifier + * @adap: the CEC adapter, passed as argument to the callback function + * @callback: the callback function + */ +void cec_notifier_register(struct cec_notifier *n, + struct cec_adapter *adap, + void (*callback)(struct cec_adapter *adap, u16 pa)); + +/** + * cec_notifier_unregister - unregister the callback from the notifier. + * @n: the CEC notifier + */ +void cec_notifier_unregister(struct cec_notifier *n); + +#else +static inline struct cec_notifier *cec_notifier_get(struct device *dev) +{ + /* A non-NULL pointer is expected on success */ + return (struct cec_notifier *)0xdeadfeed; +} + +static inline void cec_notifier_put(struct cec_notifier *n) +{ +} + +static inline void cec_notifier_set_phys_addr(struct cec_notifier *n, u16 pa) +{ +} + +static inline void cec_notifier_set_phys_addr_from_edid(struct cec_notifier *n, + const struct edid *edid) +{ +} + +#endif + +/** + * cec_notifier_phys_addr_invalidate() - set the physical address to INVALID + * + * @n: the CEC notifier + * + * This is a simple helper function to invalidate the physical + * address. Does nothing if @n == NULL. + */ +static inline void cec_notifier_phys_addr_invalidate(struct cec_notifier *n) +{ + cec_notifier_set_phys_addr(n, CEC_PHYS_ADDR_INVALID); +} + +#endif diff --git a/include/media/cec-pin.h b/include/media/cec-pin.h new file mode 100644 index 000000000000..83b3e17e0a07 --- /dev/null +++ b/include/media/cec-pin.h @@ -0,0 +1,83 @@ +/* + * cec-pin.h - low-level CEC pin control + * + * Copyright 2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved. + * + * This program is free software; you may redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef LINUX_CEC_PIN_H +#define LINUX_CEC_PIN_H + +#include <linux/types.h> +#include <media/cec.h> + +/** + * struct cec_pin_ops - low-level CEC pin operations + * @read: read the CEC pin. Return true if high, false if low. + * @low: drive the CEC pin low. + * @high: stop driving the CEC pin. The pull-up will drive the pin + * high, unless someone else is driving the pin low. + * @enable_irq: optional, enable the interrupt to detect pin voltage changes. + * @disable_irq: optional, disable the interrupt. + * @free: optional. Free any allocated resources. Called when the + * adapter is deleted. + * @status: optional, log status information. + * @read_hpd: read the HPD pin. Return true if high, false if low or + * an error if negative. If NULL or -ENOTTY is returned, + * then this is not supported. + * + * These operations are used by the cec pin framework to manipulate + * the CEC pin. + */ +struct cec_pin_ops { + bool (*read)(struct cec_adapter *adap); + void (*low)(struct cec_adapter *adap); + void (*high)(struct cec_adapter *adap); + bool (*enable_irq)(struct cec_adapter *adap); + void (*disable_irq)(struct cec_adapter *adap); + void (*free)(struct cec_adapter *adap); + void (*status)(struct cec_adapter *adap, struct seq_file *file); + int (*read_hpd)(struct cec_adapter *adap); +}; + +/** + * cec_pin_changed() - update pin state from interrupt + * + * @adap: pointer to the cec adapter + * @value: when true the pin is high, otherwise it is low + * + * If changes of the CEC voltage are detected via an interrupt, then + * cec_pin_changed is called from the interrupt with the new value. + */ +void cec_pin_changed(struct cec_adapter *adap, bool value); + +/** + * cec_pin_allocate_adapter() - allocate a pin-based cec adapter + * + * @pin_ops: low-level pin operations + * @priv: will be stored in adap->priv and can be used by the adapter ops. + * Use cec_get_drvdata(adap) to get the priv pointer. + * @name: the name of the CEC adapter. Note: this name will be copied. + * @caps: capabilities of the CEC adapter. This will be ORed with + * CEC_CAP_MONITOR_ALL and CEC_CAP_MONITOR_PIN. + * + * Allocate a cec adapter using the cec pin framework. + * + * Return: a pointer to the cec adapter or an error pointer + */ +struct cec_adapter *cec_pin_allocate_adapter(const struct cec_pin_ops *pin_ops, + void *priv, const char *name, u32 caps); + +#endif diff --git a/include/media/cec.h b/include/media/cec.h new file mode 100644 index 000000000000..1048888a96c2 --- /dev/null +++ b/include/media/cec.h @@ -0,0 +1,432 @@ +/* + * cec - HDMI Consumer Electronics Control support header + * + * Copyright 2016 Cisco Systems, Inc. and/or its affiliates. All rights reserved. + * + * This program is free software; you may redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef _MEDIA_CEC_H +#define _MEDIA_CEC_H + +#include <linux/poll.h> +#include <linux/fs.h> +#include <linux/debugfs.h> +#include <linux/device.h> +#include <linux/cdev.h> +#include <linux/kthread.h> +#include <linux/timer.h> +#include <linux/cec-funcs.h> +#include <media/rc-core.h> +#include <media/cec-notifier.h> + +/** + * struct cec_devnode - cec device node + * @dev: cec device + * @cdev: cec character device + * @minor: device node minor number + * @registered: the device was correctly registered + * @unregistered: the device was unregistered + * @fhs_lock: lock to control access to the filehandle list + * @fhs: the list of open filehandles (cec_fh) + * + * This structure represents a cec-related device node. + * + * The @parent is a physical device. It must be set by core or device drivers + * before registering the node. + */ +struct cec_devnode { + /* sysfs */ + struct device dev; + struct cdev cdev; + + /* device info */ + int minor; + bool registered; + bool unregistered; + struct list_head fhs; + struct mutex lock; +}; + +struct cec_adapter; +struct cec_data; +struct cec_pin; + +struct cec_data { + struct list_head list; + struct list_head xfer_list; + struct cec_adapter *adap; + struct cec_msg msg; + struct cec_fh *fh; + struct delayed_work work; + struct completion c; + u8 attempts; + bool new_initiator; + bool blocking; + bool completed; +}; + +struct cec_msg_entry { + struct list_head list; + struct cec_msg msg; +}; + +struct cec_event_entry { + struct list_head list; + struct cec_event ev; +}; + +#define CEC_NUM_CORE_EVENTS 2 +#define CEC_NUM_EVENTS CEC_EVENT_PIN_HPD_HIGH + +struct cec_fh { + struct list_head list; + struct list_head xfer_list; + struct cec_adapter *adap; + u8 mode_initiator; + u8 mode_follower; + + /* Events */ + wait_queue_head_t wait; + struct mutex lock; + struct list_head events[CEC_NUM_EVENTS]; /* queued events */ + u8 queued_events[CEC_NUM_EVENTS]; + unsigned int total_queued_events; + struct cec_event_entry core_events[CEC_NUM_CORE_EVENTS]; + struct list_head msgs; /* queued messages */ + unsigned int queued_msgs; +}; + +#define CEC_SIGNAL_FREE_TIME_RETRY 3 +#define CEC_SIGNAL_FREE_TIME_NEW_INITIATOR 5 +#define CEC_SIGNAL_FREE_TIME_NEXT_XFER 7 + +/* The nominal data bit period is 2.4 ms */ +#define CEC_FREE_TIME_TO_USEC(ft) ((ft) * 2400) + +struct cec_adap_ops { + /* Low-level callbacks */ + int (*adap_enable)(struct cec_adapter *adap, bool enable); + int (*adap_monitor_all_enable)(struct cec_adapter *adap, bool enable); + int (*adap_log_addr)(struct cec_adapter *adap, u8 logical_addr); + int (*adap_transmit)(struct cec_adapter *adap, u8 attempts, + u32 signal_free_time, struct cec_msg *msg); + void (*adap_status)(struct cec_adapter *adap, struct seq_file *file); + void (*adap_free)(struct cec_adapter *adap); + + /* High-level CEC message callback */ + int (*received)(struct cec_adapter *adap, struct cec_msg *msg); +}; + +/* + * The minimum message length you can receive (excepting poll messages) is 2. + * With a transfer rate of at most 36 bytes per second this makes 18 messages + * per second worst case. + * + * We queue at most 3 seconds worth of received messages. The CEC specification + * requires that messages are replied to within a second, so 3 seconds should + * give more than enough margin. Since most messages are actually more than 2 + * bytes, this is in practice a lot more than 3 seconds. + */ +#define CEC_MAX_MSG_RX_QUEUE_SZ (18 * 3) + +/* + * The transmit queue is limited to 1 second worth of messages (worst case). + * Messages can be transmitted by userspace and kernel space. But for both it + * makes no sense to have a lot of messages queued up. One second seems + * reasonable. + */ +#define CEC_MAX_MSG_TX_QUEUE_SZ (18 * 1) + +struct cec_adapter { + struct module *owner; + char name[32]; + struct cec_devnode devnode; + struct mutex lock; + struct rc_dev *rc; + + struct list_head transmit_queue; + unsigned int transmit_queue_sz; + struct list_head wait_queue; + struct cec_data *transmitting; + + struct task_struct *kthread_config; + struct completion config_completion; + + struct task_struct *kthread; + wait_queue_head_t kthread_waitq; + wait_queue_head_t waitq; + + const struct cec_adap_ops *ops; + void *priv; + u32 capabilities; + u8 available_log_addrs; + + u16 phys_addr; + bool needs_hpd; + bool is_configuring; + bool is_configured; + bool cec_pin_is_high; + u32 monitor_all_cnt; + u32 monitor_pin_cnt; + u32 follower_cnt; + struct cec_fh *cec_follower; + struct cec_fh *cec_initiator; + bool passthrough; + struct cec_log_addrs log_addrs; + + u32 tx_timeouts; + +#ifdef CONFIG_CEC_NOTIFIER + struct cec_notifier *notifier; +#endif +#ifdef CONFIG_CEC_PIN + struct cec_pin *pin; +#endif + + struct dentry *cec_dir; + struct dentry *status_file; + + u16 phys_addrs[15]; + u32 sequence; + + char device_name[32]; + char input_phys[32]; + char input_drv[32]; +}; + +static inline void *cec_get_drvdata(const struct cec_adapter *adap) +{ + return adap->priv; +} + +static inline bool cec_has_log_addr(const struct cec_adapter *adap, u8 log_addr) +{ + return adap->log_addrs.log_addr_mask & (1 << log_addr); +} + +static inline bool cec_is_sink(const struct cec_adapter *adap) +{ + return adap->phys_addr == 0; +} + +#define cec_phys_addr_exp(pa) \ + ((pa) >> 12), ((pa) >> 8) & 0xf, ((pa) >> 4) & 0xf, (pa) & 0xf + +struct edid; + +#if IS_ENABLED(CONFIG_CEC_CORE) +struct cec_adapter *cec_allocate_adapter(const struct cec_adap_ops *ops, + void *priv, const char *name, u32 caps, u8 available_las); +int cec_register_adapter(struct cec_adapter *adap, struct device *parent); +void cec_unregister_adapter(struct cec_adapter *adap); +void cec_delete_adapter(struct cec_adapter *adap); + +int cec_s_log_addrs(struct cec_adapter *adap, struct cec_log_addrs *log_addrs, + bool block); +void cec_s_phys_addr(struct cec_adapter *adap, u16 phys_addr, + bool block); +void cec_s_phys_addr_from_edid(struct cec_adapter *adap, + const struct edid *edid); +int cec_transmit_msg(struct cec_adapter *adap, struct cec_msg *msg, + bool block); + +/* Called by the adapter */ +void cec_transmit_done_ts(struct cec_adapter *adap, u8 status, + u8 arb_lost_cnt, u8 nack_cnt, u8 low_drive_cnt, + u8 error_cnt, ktime_t ts); + +static inline void cec_transmit_done(struct cec_adapter *adap, u8 status, + u8 arb_lost_cnt, u8 nack_cnt, + u8 low_drive_cnt, u8 error_cnt) +{ + cec_transmit_done_ts(adap, status, arb_lost_cnt, nack_cnt, + low_drive_cnt, error_cnt, ktime_get()); +} +/* + * Simplified version of cec_transmit_done for hardware that doesn't retry + * failed transmits. So this is always just one attempt in which case + * the status is sufficient. + */ +void cec_transmit_attempt_done_ts(struct cec_adapter *adap, + u8 status, ktime_t ts); + +static inline void cec_transmit_attempt_done(struct cec_adapter *adap, + u8 status) +{ + cec_transmit_attempt_done_ts(adap, status, ktime_get()); +} + +void cec_received_msg_ts(struct cec_adapter *adap, + struct cec_msg *msg, ktime_t ts); + +static inline void cec_received_msg(struct cec_adapter *adap, + struct cec_msg *msg) +{ + cec_received_msg_ts(adap, msg, ktime_get()); +} + +/** + * cec_queue_pin_cec_event() - queue a CEC pin event with a given timestamp. + * + * @adap: pointer to the cec adapter + * @is_high: when true the CEC pin is high, otherwise it is low + * @ts: the timestamp for this event + * + */ +void cec_queue_pin_cec_event(struct cec_adapter *adap, + bool is_high, ktime_t ts); + +/** + * cec_queue_pin_hpd_event() - queue a pin event with a given timestamp. + * + * @adap: pointer to the cec adapter + * @is_high: when true the HPD pin is high, otherwise it is low + * @ts: the timestamp for this event + * + */ +void cec_queue_pin_hpd_event(struct cec_adapter *adap, bool is_high, ktime_t ts); + +/** + * cec_get_edid_phys_addr() - find and return the physical address + * + * @edid: pointer to the EDID data + * @size: size in bytes of the EDID data + * @offset: If not %NULL then the location of the physical address + * bytes in the EDID will be returned here. This is set to 0 + * if there is no physical address found. + * + * Return: the physical address or CEC_PHYS_ADDR_INVALID if there is none. + */ +u16 cec_get_edid_phys_addr(const u8 *edid, unsigned int size, + unsigned int *offset); + +/** + * cec_set_edid_phys_addr() - find and set the physical address + * + * @edid: pointer to the EDID data + * @size: size in bytes of the EDID data + * @phys_addr: the new physical address + * + * This function finds the location of the physical address in the EDID + * and fills in the given physical address and updates the checksum + * at the end of the EDID block. It does nothing if the EDID doesn't + * contain a physical address. + */ +void cec_set_edid_phys_addr(u8 *edid, unsigned int size, u16 phys_addr); + +/** + * cec_phys_addr_for_input() - calculate the PA for an input + * + * @phys_addr: the physical address of the parent + * @input: the number of the input port, must be between 1 and 15 + * + * This function calculates a new physical address based on the input + * port number. For example: + * + * PA = 0.0.0.0 and input = 2 becomes 2.0.0.0 + * + * PA = 3.0.0.0 and input = 1 becomes 3.1.0.0 + * + * PA = 3.2.1.0 and input = 5 becomes 3.2.1.5 + * + * PA = 3.2.1.3 and input = 5 becomes f.f.f.f since it maxed out the depth. + * + * Return: the new physical address or CEC_PHYS_ADDR_INVALID. + */ +u16 cec_phys_addr_for_input(u16 phys_addr, u8 input); + +/** + * cec_phys_addr_validate() - validate a physical address from an EDID + * + * @phys_addr: the physical address to validate + * @parent: if not %NULL, then this is filled with the parents PA. + * @port: if not %NULL, then this is filled with the input port. + * + * This validates a physical address as read from an EDID. If the + * PA is invalid (such as 1.0.1.0 since '0' is only allowed at the end), + * then it will return -EINVAL. + * + * The parent PA is passed into %parent and the input port is passed into + * %port. For example: + * + * PA = 0.0.0.0: has parent 0.0.0.0 and input port 0. + * + * PA = 1.0.0.0: has parent 0.0.0.0 and input port 1. + * + * PA = 3.2.0.0: has parent 3.0.0.0 and input port 2. + * + * PA = f.f.f.f: has parent f.f.f.f and input port 0. + * + * Return: 0 if the PA is valid, -EINVAL if not. + */ +int cec_phys_addr_validate(u16 phys_addr, u16 *parent, u16 *port); + +#ifdef CONFIG_CEC_NOTIFIER +void cec_register_cec_notifier(struct cec_adapter *adap, + struct cec_notifier *notifier); +#endif + +#else + +static inline int cec_register_adapter(struct cec_adapter *adap, + struct device *parent) +{ + return 0; +} + +static inline void cec_unregister_adapter(struct cec_adapter *adap) +{ +} + +static inline void cec_delete_adapter(struct cec_adapter *adap) +{ +} + +static inline void cec_s_phys_addr(struct cec_adapter *adap, u16 phys_addr, + bool block) +{ +} + +static inline void cec_s_phys_addr_from_edid(struct cec_adapter *adap, + const struct edid *edid) +{ +} + +static inline u16 cec_get_edid_phys_addr(const u8 *edid, unsigned int size, + unsigned int *offset) +{ + if (offset) + *offset = 0; + return CEC_PHYS_ADDR_INVALID; +} + +static inline void cec_set_edid_phys_addr(u8 *edid, unsigned int size, + u16 phys_addr) +{ +} + +static inline u16 cec_phys_addr_for_input(u16 phys_addr, u8 input) +{ + return CEC_PHYS_ADDR_INVALID; +} + +static inline int cec_phys_addr_validate(u16 phys_addr, u16 *parent, u16 *port) +{ + return 0; +} + +#endif + +#endif /* _MEDIA_CEC_H */ diff --git a/include/media/ir-kbd-i2c.h b/include/media/ir-kbd-i2c.h index d8564354debb..ac8c55617a79 100644 --- a/include/media/ir-kbd-i2c.h +++ b/include/media/ir-kbd-i2c.h @@ -20,7 +20,8 @@ struct IR_i2c { struct delayed_work work; char name[32]; char phys[32]; - int (*get_key)(struct IR_i2c *ir, enum rc_type *protocol, + int (*get_key)(struct IR_i2c *ir, + enum rc_proto *protocol, u32 *scancode, u8 *toggle); }; @@ -38,14 +39,15 @@ enum ir_kbd_get_key_fn { struct IR_i2c_init_data { char *ir_codes; const char *name; - u64 type; /* RC_BIT_RC5, etc */ + u64 type; /* RC_PROTO_BIT_RC5, etc */ u32 polling_interval; /* 0 means DEFAULT_POLLING_INTERVAL */ /* * Specify either a function pointer or a value indicating one of * ir_kbd_i2c's internal get_key functions */ - int (*get_key)(struct IR_i2c *ir, enum rc_type *protocol, + int (*get_key)(struct IR_i2c *ir, + enum rc_proto *protocol, u32 *scancode, u8 *toggle); enum ir_kbd_get_key_fn internal_get_key_func; diff --git a/include/media/lirc.h b/include/media/lirc.h index 4b3ab2966b5a..554988c860c1 100644 --- a/include/media/lirc.h +++ b/include/media/lirc.h @@ -1,168 +1 @@ -/* - * lirc.h - linux infrared remote control header file - * last modified 2010/07/13 by Jarod Wilson - */ - -#ifndef _LINUX_LIRC_H -#define _LINUX_LIRC_H - -#include <linux/types.h> -#include <linux/ioctl.h> - -#define PULSE_BIT 0x01000000 -#define PULSE_MASK 0x00FFFFFF - -#define LIRC_MODE2_SPACE 0x00000000 -#define LIRC_MODE2_PULSE 0x01000000 -#define LIRC_MODE2_FREQUENCY 0x02000000 -#define LIRC_MODE2_TIMEOUT 0x03000000 - -#define LIRC_VALUE_MASK 0x00FFFFFF -#define LIRC_MODE2_MASK 0xFF000000 - -#define LIRC_SPACE(val) (((val)&LIRC_VALUE_MASK) | LIRC_MODE2_SPACE) -#define LIRC_PULSE(val) (((val)&LIRC_VALUE_MASK) | LIRC_MODE2_PULSE) -#define LIRC_FREQUENCY(val) (((val)&LIRC_VALUE_MASK) | LIRC_MODE2_FREQUENCY) -#define LIRC_TIMEOUT(val) (((val)&LIRC_VALUE_MASK) | LIRC_MODE2_TIMEOUT) - -#define LIRC_VALUE(val) ((val)&LIRC_VALUE_MASK) -#define LIRC_MODE2(val) ((val)&LIRC_MODE2_MASK) - -#define LIRC_IS_SPACE(val) (LIRC_MODE2(val) == LIRC_MODE2_SPACE) -#define LIRC_IS_PULSE(val) (LIRC_MODE2(val) == LIRC_MODE2_PULSE) -#define LIRC_IS_FREQUENCY(val) (LIRC_MODE2(val) == LIRC_MODE2_FREQUENCY) -#define LIRC_IS_TIMEOUT(val) (LIRC_MODE2(val) == LIRC_MODE2_TIMEOUT) - -/* used heavily by lirc userspace */ -#define lirc_t int - -/*** lirc compatible hardware features ***/ - -#define LIRC_MODE2SEND(x) (x) -#define LIRC_SEND2MODE(x) (x) -#define LIRC_MODE2REC(x) ((x) << 16) -#define LIRC_REC2MODE(x) ((x) >> 16) - -#define LIRC_MODE_RAW 0x00000001 -#define LIRC_MODE_PULSE 0x00000002 -#define LIRC_MODE_MODE2 0x00000004 -#define LIRC_MODE_LIRCCODE 0x00000010 - - -#define LIRC_CAN_SEND_RAW LIRC_MODE2SEND(LIRC_MODE_RAW) -#define LIRC_CAN_SEND_PULSE LIRC_MODE2SEND(LIRC_MODE_PULSE) -#define LIRC_CAN_SEND_MODE2 LIRC_MODE2SEND(LIRC_MODE_MODE2) -#define LIRC_CAN_SEND_LIRCCODE LIRC_MODE2SEND(LIRC_MODE_LIRCCODE) - -#define LIRC_CAN_SEND_MASK 0x0000003f - -#define LIRC_CAN_SET_SEND_CARRIER 0x00000100 -#define LIRC_CAN_SET_SEND_DUTY_CYCLE 0x00000200 -#define LIRC_CAN_SET_TRANSMITTER_MASK 0x00000400 - -#define LIRC_CAN_REC_RAW LIRC_MODE2REC(LIRC_MODE_RAW) -#define LIRC_CAN_REC_PULSE LIRC_MODE2REC(LIRC_MODE_PULSE) -#define LIRC_CAN_REC_MODE2 LIRC_MODE2REC(LIRC_MODE_MODE2) -#define LIRC_CAN_REC_LIRCCODE LIRC_MODE2REC(LIRC_MODE_LIRCCODE) - -#define LIRC_CAN_REC_MASK LIRC_MODE2REC(LIRC_CAN_SEND_MASK) - -#define LIRC_CAN_SET_REC_CARRIER (LIRC_CAN_SET_SEND_CARRIER << 16) -#define LIRC_CAN_SET_REC_DUTY_CYCLE (LIRC_CAN_SET_SEND_DUTY_CYCLE << 16) - -#define LIRC_CAN_SET_REC_DUTY_CYCLE_RANGE 0x40000000 -#define LIRC_CAN_SET_REC_CARRIER_RANGE 0x80000000 -#define LIRC_CAN_GET_REC_RESOLUTION 0x20000000 -#define LIRC_CAN_SET_REC_TIMEOUT 0x10000000 -#define LIRC_CAN_SET_REC_FILTER 0x08000000 - -#define LIRC_CAN_MEASURE_CARRIER 0x02000000 -#define LIRC_CAN_USE_WIDEBAND_RECEIVER 0x04000000 - -#define LIRC_CAN_SEND(x) ((x)&LIRC_CAN_SEND_MASK) -#define LIRC_CAN_REC(x) ((x)&LIRC_CAN_REC_MASK) - -#define LIRC_CAN_NOTIFY_DECODE 0x01000000 - -/*** IOCTL commands for lirc driver ***/ - -#define LIRC_GET_FEATURES _IOR('i', 0x00000000, __u32) - -#define LIRC_GET_SEND_MODE _IOR('i', 0x00000001, __u32) -#define LIRC_GET_REC_MODE _IOR('i', 0x00000002, __u32) -#define LIRC_GET_SEND_CARRIER _IOR('i', 0x00000003, __u32) -#define LIRC_GET_REC_CARRIER _IOR('i', 0x00000004, __u32) -#define LIRC_GET_SEND_DUTY_CYCLE _IOR('i', 0x00000005, __u32) -#define LIRC_GET_REC_DUTY_CYCLE _IOR('i', 0x00000006, __u32) -#define LIRC_GET_REC_RESOLUTION _IOR('i', 0x00000007, __u32) - -#define LIRC_GET_MIN_TIMEOUT _IOR('i', 0x00000008, __u32) -#define LIRC_GET_MAX_TIMEOUT _IOR('i', 0x00000009, __u32) - -#define LIRC_GET_MIN_FILTER_PULSE _IOR('i', 0x0000000a, __u32) -#define LIRC_GET_MAX_FILTER_PULSE _IOR('i', 0x0000000b, __u32) -#define LIRC_GET_MIN_FILTER_SPACE _IOR('i', 0x0000000c, __u32) -#define LIRC_GET_MAX_FILTER_SPACE _IOR('i', 0x0000000d, __u32) - -/* code length in bits, currently only for LIRC_MODE_LIRCCODE */ -#define LIRC_GET_LENGTH _IOR('i', 0x0000000f, __u32) - -#define LIRC_SET_SEND_MODE _IOW('i', 0x00000011, __u32) -#define LIRC_SET_REC_MODE _IOW('i', 0x00000012, __u32) -/* Note: these can reset the according pulse_width */ -#define LIRC_SET_SEND_CARRIER _IOW('i', 0x00000013, __u32) -#define LIRC_SET_REC_CARRIER _IOW('i', 0x00000014, __u32) -#define LIRC_SET_SEND_DUTY_CYCLE _IOW('i', 0x00000015, __u32) -#define LIRC_SET_REC_DUTY_CYCLE _IOW('i', 0x00000016, __u32) -#define LIRC_SET_TRANSMITTER_MASK _IOW('i', 0x00000017, __u32) - -/* - * when a timeout != 0 is set the driver will send a - * LIRC_MODE2_TIMEOUT data packet, otherwise LIRC_MODE2_TIMEOUT is - * never sent, timeout is disabled by default - */ -#define LIRC_SET_REC_TIMEOUT _IOW('i', 0x00000018, __u32) - -/* 1 enables, 0 disables timeout reports in MODE2 */ -#define LIRC_SET_REC_TIMEOUT_REPORTS _IOW('i', 0x00000019, __u32) - -/* - * pulses shorter than this are filtered out by hardware (software - * emulation in lirc_dev?) - */ -#define LIRC_SET_REC_FILTER_PULSE _IOW('i', 0x0000001a, __u32) -/* - * spaces shorter than this are filtered out by hardware (software - * emulation in lirc_dev?) - */ -#define LIRC_SET_REC_FILTER_SPACE _IOW('i', 0x0000001b, __u32) -/* - * if filter cannot be set independently for pulse/space, this should - * be used - */ -#define LIRC_SET_REC_FILTER _IOW('i', 0x0000001c, __u32) - -/* - * if enabled from the next key press on the driver will send - * LIRC_MODE2_FREQUENCY packets - */ -#define LIRC_SET_MEASURE_CARRIER_MODE _IOW('i', 0x0000001d, __u32) - -/* - * to set a range use - * LIRC_SET_REC_DUTY_CYCLE_RANGE/LIRC_SET_REC_CARRIER_RANGE with the - * lower bound first and later - * LIRC_SET_REC_DUTY_CYCLE/LIRC_SET_REC_CARRIER with the upper bound - */ - -#define LIRC_SET_REC_DUTY_CYCLE_RANGE _IOW('i', 0x0000001e, __u32) -#define LIRC_SET_REC_CARRIER_RANGE _IOW('i', 0x0000001f, __u32) - -#define LIRC_NOTIFY_DECODE _IO('i', 0x00000020) - -#define LIRC_SETUP_START _IO('i', 0x00000021) -#define LIRC_SETUP_END _IO('i', 0x00000022) - -#define LIRC_SET_WIDEBAND_RECEIVER _IOW('i', 0x00000023, __u32) - -#endif +#include <uapi/linux/lirc.h> diff --git a/include/media/lirc_dev.h b/include/media/lirc_dev.h deleted file mode 100644 index 0ab59a571fee..000000000000 --- a/include/media/lirc_dev.h +++ /dev/null @@ -1,238 +0,0 @@ -/* - * LIRC base driver - * - * by Artur Lipowski <alipowski@interia.pl> - * This code is licensed under GNU GPL - * - */ - -#ifndef _LINUX_LIRC_DEV_H -#define _LINUX_LIRC_DEV_H - -#define MAX_IRCTL_DEVICES 8 -#define BUFLEN 16 - -#define mod(n, div) ((n) % (div)) - -#include <linux/slab.h> -#include <linux/fs.h> -#include <linux/ioctl.h> -#include <linux/poll.h> -#include <linux/kfifo.h> -#include <media/lirc.h> - -struct lirc_buffer { - wait_queue_head_t wait_poll; - spinlock_t fifo_lock; - unsigned int chunk_size; - unsigned int size; /* in chunks */ - /* Using chunks instead of bytes pretends to simplify boundary checking - * And should allow for some performance fine tunning later */ - struct kfifo fifo; -}; - -static inline void lirc_buffer_clear(struct lirc_buffer *buf) -{ - unsigned long flags; - - if (kfifo_initialized(&buf->fifo)) { - spin_lock_irqsave(&buf->fifo_lock, flags); - kfifo_reset(&buf->fifo); - spin_unlock_irqrestore(&buf->fifo_lock, flags); - } else - WARN(1, "calling %s on an uninitialized lirc_buffer\n", - __func__); -} - -static inline int lirc_buffer_init(struct lirc_buffer *buf, - unsigned int chunk_size, - unsigned int size) -{ - int ret; - - init_waitqueue_head(&buf->wait_poll); - spin_lock_init(&buf->fifo_lock); - buf->chunk_size = chunk_size; - buf->size = size; - ret = kfifo_alloc(&buf->fifo, size * chunk_size, GFP_KERNEL); - - return ret; -} - -static inline void lirc_buffer_free(struct lirc_buffer *buf) -{ - if (kfifo_initialized(&buf->fifo)) { - kfifo_free(&buf->fifo); - } else - WARN(1, "calling %s on an uninitialized lirc_buffer\n", - __func__); -} - -static inline int lirc_buffer_len(struct lirc_buffer *buf) -{ - int len; - unsigned long flags; - - spin_lock_irqsave(&buf->fifo_lock, flags); - len = kfifo_len(&buf->fifo); - spin_unlock_irqrestore(&buf->fifo_lock, flags); - - return len; -} - -static inline int lirc_buffer_full(struct lirc_buffer *buf) -{ - return lirc_buffer_len(buf) == buf->size * buf->chunk_size; -} - -static inline int lirc_buffer_empty(struct lirc_buffer *buf) -{ - return !lirc_buffer_len(buf); -} - -static inline int lirc_buffer_available(struct lirc_buffer *buf) -{ - return buf->size - (lirc_buffer_len(buf) / buf->chunk_size); -} - -static inline unsigned int lirc_buffer_read(struct lirc_buffer *buf, - unsigned char *dest) -{ - unsigned int ret = 0; - - if (lirc_buffer_len(buf) >= buf->chunk_size) - ret = kfifo_out_locked(&buf->fifo, dest, buf->chunk_size, - &buf->fifo_lock); - return ret; - -} - -static inline unsigned int lirc_buffer_write(struct lirc_buffer *buf, - unsigned char *orig) -{ - unsigned int ret; - - ret = kfifo_in_locked(&buf->fifo, orig, buf->chunk_size, - &buf->fifo_lock); - - return ret; -} - -/** - * struct lirc_driver - Defines the parameters on a LIRC driver - * - * @name: this string will be used for logs - * - * @minor: indicates minor device (/dev/lirc) number for - * registered driver if caller fills it with negative - * value, then the first free minor number will be used - * (if available). - * - * @code_length: length of the remote control key code expressed in bits. - * - * @buffer_size: Number of FIFO buffers with @chunk_size size. If zero, - * creates a buffer with BUFLEN size (16 bytes). - * - * @sample_rate: if zero, the device will wait for an event with a new - * code to be parsed. Otherwise, specifies the sample - * rate for polling. Value should be between 0 - * and HZ. If equal to HZ, it would mean one polling per - * second. - * - * @features: lirc compatible hardware features, like LIRC_MODE_RAW, - * LIRC_CAN_*, as defined at include/media/lirc.h. - * - * @chunk_size: Size of each FIFO buffer. - * - * @data: it may point to any driver data and this pointer will - * be passed to all callback functions. - * - * @min_timeout: Minimum timeout for record. Valid only if - * LIRC_CAN_SET_REC_TIMEOUT is defined. - * - * @max_timeout: Maximum timeout for record. Valid only if - * LIRC_CAN_SET_REC_TIMEOUT is defined. - * - * @add_to_buf: add_to_buf will be called after specified period of the - * time or triggered by the external event, this behavior - * depends on value of the sample_rate this function will - * be called in user context. This routine should return - * 0 if data was added to the buffer and -ENODATA if none - * was available. This should add some number of bits - * evenly divisible by code_length to the buffer. - * - * @rbuf: if not NULL, it will be used as a read buffer, you will - * have to write to the buffer by other means, like irq's - * (see also lirc_serial.c). - * - * @set_use_inc: set_use_inc will be called after device is opened - * - * @set_use_dec: set_use_dec will be called after device is closed - * - * @rdev: Pointed to struct rc_dev associated with the LIRC - * device. - * - * @fops: file_operations for drivers which don't fit the current - * driver model. - * Some ioctl's can be directly handled by lirc_dev if the - * driver's ioctl function is NULL or if it returns - * -ENOIOCTLCMD (see also lirc_serial.c). - * - * @dev: pointer to the struct device associated with the LIRC - * device. - * - * @owner: the module owning this struct - */ -struct lirc_driver { - char name[40]; - int minor; - __u32 code_length; - unsigned int buffer_size; /* in chunks holding one code each */ - int sample_rate; - __u32 features; - - unsigned int chunk_size; - - void *data; - int min_timeout; - int max_timeout; - int (*add_to_buf)(void *data, struct lirc_buffer *buf); - struct lirc_buffer *rbuf; - int (*set_use_inc)(void *data); - void (*set_use_dec)(void *data); - struct rc_dev *rdev; - const struct file_operations *fops; - struct device *dev; - struct module *owner; -}; - -/* following functions can be called ONLY from user context - * - * returns negative value on error or minor number - * of the registered device if success - * contents of the structure pointed by p is copied - */ -extern int lirc_register_driver(struct lirc_driver *d); - -/* returns negative value on error or 0 if success -*/ -extern int lirc_unregister_driver(int minor); - -/* Returns the private data stored in the lirc_driver - * associated with the given device file pointer. - */ -void *lirc_get_pdata(struct file *file); - -/* default file operations - * used by drivers if they override only some operations - */ -int lirc_dev_fop_open(struct inode *inode, struct file *file); -int lirc_dev_fop_close(struct inode *inode, struct file *file); -unsigned int lirc_dev_fop_poll(struct file *file, poll_table *wait); -long lirc_dev_fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg); -ssize_t lirc_dev_fop_read(struct file *file, char __user *buffer, size_t length, - loff_t *ppos); -ssize_t lirc_dev_fop_write(struct file *file, const char __user *buffer, - size_t length, loff_t *ppos); - -#endif diff --git a/include/media/rc-core.h b/include/media/rc-core.h index ec921f6538c7..221ce3452cd0 100644 --- a/include/media/rc-core.h +++ b/include/media/rc-core.h @@ -17,21 +17,25 @@ #define _RC_CORE #include <linux/spinlock.h> +#include <linux/cdev.h> #include <linux/kfifo.h> #include <linux/time.h> #include <linux/timer.h> #include <media/rc-map.h> -extern int rc_core_debug; -#define IR_dprintk(level, fmt, ...) \ -do { \ - if (rc_core_debug >= level) \ - printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__); \ -} while (0) - +/** + * enum rc_driver_type - type of the RC driver. + * + * @RC_DRIVER_SCANCODE: Driver or hardware generates a scancode. + * @RC_DRIVER_IR_RAW: Driver or hardware generates pulse/space sequences. + * It needs a Infra-Red pulse/space decoder + * @RC_DRIVER_IR_RAW_TX: Device transmitter only, + * driver requires pulse/space data sequence. + */ enum rc_driver_type { - RC_DRIVER_SCANCODE = 0, /* Driver or hardware generates a scancode */ - RC_DRIVER_IR_RAW, /* Needs a Infra-Red pulse/space decoder */ + RC_DRIVER_SCANCODE = 0, + RC_DRIVER_IR_RAW, + RC_DRIVER_IR_RAW_TX, }; /** @@ -58,10 +62,38 @@ enum rc_filter_type { }; /** + * struct lirc_fh - represents an open lirc file + * @list: list of open file handles + * @rc: rcdev for this lirc chardev + * @carrier_low: when setting the carrier range, first the low end must be + * set with an ioctl and then the high end with another ioctl + * @send_timeout_reports: report timeouts in lirc raw IR. + * @rawir: queue for incoming raw IR + * @scancodes: queue for incoming decoded scancodes + * @wait_poll: poll struct for lirc device + * @send_mode: lirc mode for sending, either LIRC_MODE_SCANCODE or + * LIRC_MODE_PULSE + * @rec_mode: lirc mode for receiving, either LIRC_MODE_SCANCODE or + * LIRC_MODE_MODE2 + */ +struct lirc_fh { + struct list_head list; + struct rc_dev *rc; + int carrier_low; + bool send_timeout_reports; + DECLARE_KFIFO_PTR(rawir, unsigned int); + DECLARE_KFIFO_PTR(scancodes, struct lirc_scancode); + wait_queue_head_t wait_poll; + u8 send_mode; + u8 rec_mode; +}; + +/** * struct rc_dev - represents a remote control device * @dev: driver model's view of this device + * @managed_alloc: devm_rc_allocate_device was used to create rc_dev * @sysfs_groups: sysfs attribute groups - * @input_name: name of the input child device + * @device_name: name of the rc child device * @input_phys: physical path to the input child device * @input_id: id of the input child device (struct input_id) * @driver_name: name of the hardware driver which registered this device @@ -74,10 +106,14 @@ enum rc_filter_type { * @input_dev: the input child device used to communicate events to userspace * @driver_type: specifies if protocol decoding is done in hardware or software * @idle: used to keep track of RX state - * @allowed_protocols: bitmask with the supported RC_BIT_* protocols - * @enabled_protocols: bitmask with the enabled RC_BIT_* protocols - * @allowed_wakeup_protocols: bitmask with the supported RC_BIT_* wakeup protocols - * @enabled_wakeup_protocols: bitmask with the enabled RC_BIT_* wakeup protocols + * @encode_wakeup: wakeup filtering uses IR encode API, therefore the allowed + * wakeup protocols is the set of all raw encoders + * @allowed_protocols: bitmask with the supported RC_PROTO_BIT_* protocols + * @enabled_protocols: bitmask with the enabled RC_PROTO_BIT_* protocols + * @allowed_wakeup_protocols: bitmask with the supported RC_PROTO_BIT_* wakeup + * protocols + * @wakeup_protocol: the enabled RC_PROTO_* wakeup protocol or + * RC_PROTO_UNKNOWN if disabled. * @scancode_filter: scancode filter * @scancode_wakeup_filter: scancode wakeup filters * @scancode_mask: some hardware decoders are not capable of providing the full @@ -91,6 +127,8 @@ enum rc_filter_type { * @keypressed: whether a key is currently pressed * @keyup_jiffies: time (in jiffies) when the current keypress should be released * @timer_keyup: timer for releasing a keypress + * @timer_repeat: timer for autorepeat events. This is needed for CEC, which + * has non-standard repeats. * @last_keycode: keycode of last keypress * @last_protocol: protocol of last keypress * @last_scancode: scancode of last keypress @@ -100,9 +138,16 @@ enum rc_filter_type { * @max_timeout: maximum timeout supported by device * @rx_resolution : resolution (in ns) of input sampler * @tx_resolution: resolution (in ns) of output sampler + * @lirc_dev: lirc device + * @lirc_cdev: lirc char cdev + * @gap_start: time when gap starts + * @gap_duration: duration of initial gap + * @gap: true if we're in a gap + * @lirc_fh_lock: protects lirc_fh list + * @lirc_fh: list of open files + * @registered: set to true by rc_register_device(), false by + * rc_unregister_device * @change_protocol: allow changing the protocol used on hardware decoders - * @change_wakeup_protocol: allow changing the protocol used for wakeup - * filtering * @open: callback to allow drivers to enable polling/irq when IR input device * is opened. * @close: callback to allow drivers to disable polling/irq when IR input device @@ -117,15 +162,19 @@ enum rc_filter_type { * @s_learning_mode: enable wide band receiver used for learning * @s_carrier_report: enable carrier reports * @s_filter: set the scancode filter - * @s_wakeup_filter: set the wakeup scancode filter + * @s_wakeup_filter: set the wakeup scancode filter. If the mask is zero + * then wakeup should be disabled. wakeup_protocol will be set to + * a valid protocol if mask is nonzero. + * @s_timeout: set hardware timeout in ns */ struct rc_dev { struct device dev; + bool managed_alloc; const struct attribute_group *sysfs_groups[5]; - const char *input_name; + const char *device_name; const char *input_phys; struct input_id input_id; - char *driver_name; + const char *driver_name; const char *map_name; struct rc_map rc_map; struct mutex lock; @@ -134,10 +183,11 @@ struct rc_dev { struct input_dev *input_dev; enum rc_driver_type driver_type; bool idle; + bool encode_wakeup; u64 allowed_protocols; u64 enabled_protocols; u64 allowed_wakeup_protocols; - u64 enabled_wakeup_protocols; + enum rc_proto wakeup_protocol; struct rc_scancode_filter scancode_filter; struct rc_scancode_filter scancode_wakeup_filter; u32 scancode_mask; @@ -147,8 +197,9 @@ struct rc_dev { bool keypressed; unsigned long keyup_jiffies; struct timer_list timer_keyup; + struct timer_list timer_repeat; u32 last_keycode; - enum rc_type last_protocol; + enum rc_proto last_protocol; u32 last_scancode; u8 last_toggle; u32 timeout; @@ -156,8 +207,17 @@ struct rc_dev { u32 max_timeout; u32 rx_resolution; u32 tx_resolution; - int (*change_protocol)(struct rc_dev *dev, u64 *rc_type); - int (*change_wakeup_protocol)(struct rc_dev *dev, u64 *rc_type); +#ifdef CONFIG_LIRC + struct device lirc_dev; + struct cdev lirc_cdev; + ktime_t gap_start; + u64 gap_duration; + bool gap; + spinlock_t lirc_fh_lock; + struct list_head lirc_fh; +#endif + bool registered; + int (*change_protocol)(struct rc_dev *dev, u64 *rc_proto); int (*open)(struct rc_dev *dev); void (*close)(struct rc_dev *dev); int (*s_tx_mask)(struct rc_dev *dev, u32 mask); @@ -172,6 +232,8 @@ struct rc_dev { struct rc_scancode_filter *filter); int (*s_wakeup_filter)(struct rc_dev *dev, struct rc_scancode_filter *filter); + int (*s_timeout)(struct rc_dev *dev, + unsigned int timeout); }; #define to_rc_dev(d) container_of(d, struct rc_dev, dev) @@ -183,17 +245,71 @@ struct rc_dev { * Remote Controller, at sys/class/rc. */ -struct rc_dev *rc_allocate_device(void); +/** + * rc_allocate_device - Allocates a RC device + * + * @rc_driver_type: specifies the type of the RC output to be allocated + * returns a pointer to struct rc_dev. + */ +struct rc_dev *rc_allocate_device(enum rc_driver_type); + +/** + * devm_rc_allocate_device - Managed RC device allocation + * + * @dev: pointer to struct device + * @rc_driver_type: specifies the type of the RC output to be allocated + * returns a pointer to struct rc_dev. + */ +struct rc_dev *devm_rc_allocate_device(struct device *dev, enum rc_driver_type); + +/** + * rc_free_device - Frees a RC device + * + * @dev: pointer to struct rc_dev. + */ void rc_free_device(struct rc_dev *dev); + +/** + * rc_register_device - Registers a RC device + * + * @dev: pointer to struct rc_dev. + */ int rc_register_device(struct rc_dev *dev); + +/** + * devm_rc_register_device - Manageded registering of a RC device + * + * @parent: pointer to struct device. + * @dev: pointer to struct rc_dev. + */ +int devm_rc_register_device(struct device *parent, struct rc_dev *dev); + +/** + * rc_unregister_device - Unregisters a RC device + * + * @dev: pointer to struct rc_dev. + */ void rc_unregister_device(struct rc_dev *dev); +/** + * rc_open - Opens a RC device + * + * @rdev: pointer to struct rc_dev. + */ int rc_open(struct rc_dev *rdev); + +/** + * rc_open - Closes a RC device + * + * @rdev: pointer to struct rc_dev. + */ void rc_close(struct rc_dev *rdev); void rc_repeat(struct rc_dev *dev); -void rc_keydown(struct rc_dev *dev, enum rc_type protocol, u32 scancode, u8 toggle); -void rc_keydown_notimeout(struct rc_dev *dev, enum rc_type protocol, u32 scancode, u8 toggle); +void rc_keydown(struct rc_dev *dev, enum rc_proto protocol, u32 scancode, + u8 toggle); +void rc_keydown_notimeout(struct rc_dev *dev, enum rc_proto protocol, + u32 scancode, u8 toggle); void rc_keyup(struct rc_dev *dev); u32 rc_g_keycode_from_table(struct rc_dev *dev, u32 scancode); @@ -202,23 +318,12 @@ u32 rc_g_keycode_from_table(struct rc_dev *dev, u32 scancode); * The Raw interface is specific to InfraRed. It may be a good idea to * split it later into a separate header. */ - -enum raw_event_type { - IR_SPACE = (1 << 0), - IR_PULSE = (1 << 1), - IR_START_EVENT = (1 << 2), - IR_STOP_EVENT = (1 << 3), -}; - struct ir_raw_event { union { u32 duration; - - struct { - u32 carrier; - u8 duty_cycle; - }; + u32 carrier; }; + u8 duty_cycle; unsigned pulse:1; unsigned reset:1; @@ -226,19 +331,7 @@ struct ir_raw_event { unsigned carrier_report:1; }; -#define DEFINE_IR_RAW_EVENT(event) \ - struct ir_raw_event event = { \ - { .duration = 0 } , \ - .pulse = 0, \ - .reset = 0, \ - .timeout = 0, \ - .carrier_report = 0 } - -static inline void init_ir_raw_event(struct ir_raw_event *ev) -{ - memset(ev, 0, sizeof(*ev)); -} - +#define IR_DEFAULT_TIMEOUT MS_TO_NS(125) #define IR_MAX_DURATION 500000000 /* 500 ms */ #define US_TO_NS(usec) ((usec) * 1000) #define MS_TO_US(msec) ((msec) * 1000) @@ -246,17 +339,20 @@ static inline void init_ir_raw_event(struct ir_raw_event *ev) void ir_raw_event_handle(struct rc_dev *dev); int ir_raw_event_store(struct rc_dev *dev, struct ir_raw_event *ev); -int ir_raw_event_store_edge(struct rc_dev *dev, enum raw_event_type type); +int ir_raw_event_store_edge(struct rc_dev *dev, bool pulse); int ir_raw_event_store_with_filter(struct rc_dev *dev, - struct ir_raw_event *ev); + struct ir_raw_event *ev); +int ir_raw_event_store_with_timeout(struct rc_dev *dev, + struct ir_raw_event *ev); void ir_raw_event_set_idle(struct rc_dev *dev, bool idle); +int ir_raw_encode_scancode(enum rc_proto protocol, u32 scancode, + struct ir_raw_event *events, unsigned int max); +int ir_raw_encode_carrier(enum rc_proto protocol); static inline void ir_raw_event_reset(struct rc_dev *dev) { - DEFINE_IR_RAW_EVENT(ev); - ev.reset = true; - - ir_raw_event_store(dev, &ev); + ir_raw_event_store(dev, &((struct ir_raw_event) { .reset = true })); + dev->idle = true; ir_raw_event_handle(dev); } @@ -277,4 +373,35 @@ static inline u32 ir_extract_bits(u32 data, u32 mask) return value; } +/* Get NEC scancode and protocol type from address and command bytes */ +static inline u32 ir_nec_bytes_to_scancode(u8 address, u8 not_address, + u8 command, u8 not_command, + enum rc_proto *protocol) +{ + u32 scancode; + + if ((command ^ not_command) != 0xff) { + /* NEC transport, but modified protocol, used by at + * least Apple and TiVo remotes + */ + scancode = not_address << 24 | + address << 16 | + not_command << 8 | + command; + *protocol = RC_PROTO_NEC32; + } else if ((address ^ not_address) != 0xff) { + /* Extended NEC */ + scancode = address << 16 | + not_address << 8 | + command; + *protocol = RC_PROTO_NECX; + } else { + /* Normal NEC */ + scancode = address << 8 | command; + *protocol = RC_PROTO_NEC; + } + + return scancode; +} + #endif /* _RC_CORE */ diff --git a/include/media/rc-map.h b/include/media/rc-map.h index 7c4bbc4dfab4..6c951a1e8af0 100644 --- a/include/media/rc-map.h +++ b/include/media/rc-map.h @@ -10,59 +10,74 @@ */ #include <linux/input.h> +#include <uapi/linux/lirc.h> -enum rc_type { - RC_TYPE_UNKNOWN = 0, /* Protocol not known */ - RC_TYPE_OTHER = 1, /* Protocol known but proprietary */ - RC_TYPE_RC5 = 2, /* Philips RC5 protocol */ - RC_TYPE_RC5X = 3, /* Philips RC5x protocol */ - RC_TYPE_RC5_SZ = 4, /* StreamZap variant of RC5 */ - RC_TYPE_JVC = 5, /* JVC protocol */ - RC_TYPE_SONY12 = 6, /* Sony 12 bit protocol */ - RC_TYPE_SONY15 = 7, /* Sony 15 bit protocol */ - RC_TYPE_SONY20 = 8, /* Sony 20 bit protocol */ - RC_TYPE_NEC = 9, /* NEC protocol */ - RC_TYPE_SANYO = 10, /* Sanyo protocol */ - RC_TYPE_MCE_KBD = 11, /* RC6-ish MCE keyboard/mouse */ - RC_TYPE_RC6_0 = 12, /* Philips RC6-0-16 protocol */ - RC_TYPE_RC6_6A_20 = 13, /* Philips RC6-6A-20 protocol */ - RC_TYPE_RC6_6A_24 = 14, /* Philips RC6-6A-24 protocol */ - RC_TYPE_RC6_6A_32 = 15, /* Philips RC6-6A-32 protocol */ - RC_TYPE_RC6_MCE = 16, /* MCE (Philips RC6-6A-32 subtype) protocol */ - RC_TYPE_SHARP = 17, /* Sharp protocol */ - RC_TYPE_XMP = 18, /* XMP protocol */ -}; - -#define RC_BIT_NONE 0 -#define RC_BIT_UNKNOWN (1 << RC_TYPE_UNKNOWN) -#define RC_BIT_OTHER (1 << RC_TYPE_OTHER) -#define RC_BIT_RC5 (1 << RC_TYPE_RC5) -#define RC_BIT_RC5X (1 << RC_TYPE_RC5X) -#define RC_BIT_RC5_SZ (1 << RC_TYPE_RC5_SZ) -#define RC_BIT_JVC (1 << RC_TYPE_JVC) -#define RC_BIT_SONY12 (1 << RC_TYPE_SONY12) -#define RC_BIT_SONY15 (1 << RC_TYPE_SONY15) -#define RC_BIT_SONY20 (1 << RC_TYPE_SONY20) -#define RC_BIT_NEC (1 << RC_TYPE_NEC) -#define RC_BIT_SANYO (1 << RC_TYPE_SANYO) -#define RC_BIT_MCE_KBD (1 << RC_TYPE_MCE_KBD) -#define RC_BIT_RC6_0 (1 << RC_TYPE_RC6_0) -#define RC_BIT_RC6_6A_20 (1 << RC_TYPE_RC6_6A_20) -#define RC_BIT_RC6_6A_24 (1 << RC_TYPE_RC6_6A_24) -#define RC_BIT_RC6_6A_32 (1 << RC_TYPE_RC6_6A_32) -#define RC_BIT_RC6_MCE (1 << RC_TYPE_RC6_MCE) -#define RC_BIT_SHARP (1 << RC_TYPE_SHARP) -#define RC_BIT_XMP (1 << RC_TYPE_XMP) +#define RC_PROTO_BIT_NONE 0ULL +#define RC_PROTO_BIT_UNKNOWN BIT_ULL(RC_PROTO_UNKNOWN) +#define RC_PROTO_BIT_OTHER BIT_ULL(RC_PROTO_OTHER) +#define RC_PROTO_BIT_RC5 BIT_ULL(RC_PROTO_RC5) +#define RC_PROTO_BIT_RC5X_20 BIT_ULL(RC_PROTO_RC5X_20) +#define RC_PROTO_BIT_RC5_SZ BIT_ULL(RC_PROTO_RC5_SZ) +#define RC_PROTO_BIT_JVC BIT_ULL(RC_PROTO_JVC) +#define RC_PROTO_BIT_SONY12 BIT_ULL(RC_PROTO_SONY12) +#define RC_PROTO_BIT_SONY15 BIT_ULL(RC_PROTO_SONY15) +#define RC_PROTO_BIT_SONY20 BIT_ULL(RC_PROTO_SONY20) +#define RC_PROTO_BIT_NEC BIT_ULL(RC_PROTO_NEC) +#define RC_PROTO_BIT_NECX BIT_ULL(RC_PROTO_NECX) +#define RC_PROTO_BIT_NEC32 BIT_ULL(RC_PROTO_NEC32) +#define RC_PROTO_BIT_SANYO BIT_ULL(RC_PROTO_SANYO) +#define RC_PROTO_BIT_MCIR2_KBD BIT_ULL(RC_PROTO_MCIR2_KBD) +#define RC_PROTO_BIT_MCIR2_MSE BIT_ULL(RC_PROTO_MCIR2_MSE) +#define RC_PROTO_BIT_RC6_0 BIT_ULL(RC_PROTO_RC6_0) +#define RC_PROTO_BIT_RC6_6A_20 BIT_ULL(RC_PROTO_RC6_6A_20) +#define RC_PROTO_BIT_RC6_6A_24 BIT_ULL(RC_PROTO_RC6_6A_24) +#define RC_PROTO_BIT_RC6_6A_32 BIT_ULL(RC_PROTO_RC6_6A_32) +#define RC_PROTO_BIT_RC6_MCE BIT_ULL(RC_PROTO_RC6_MCE) +#define RC_PROTO_BIT_SHARP BIT_ULL(RC_PROTO_SHARP) +#define RC_PROTO_BIT_XMP BIT_ULL(RC_PROTO_XMP) +#define RC_PROTO_BIT_CEC BIT_ULL(RC_PROTO_CEC) +#define RC_PROTO_BIT_IMON BIT_ULL(RC_PROTO_IMON) -#define RC_BIT_ALL (RC_BIT_UNKNOWN | RC_BIT_OTHER | \ - RC_BIT_RC5 | RC_BIT_RC5X | RC_BIT_RC5_SZ | \ - RC_BIT_JVC | \ - RC_BIT_SONY12 | RC_BIT_SONY15 | RC_BIT_SONY20 | \ - RC_BIT_NEC | RC_BIT_SANYO | RC_BIT_MCE_KBD | \ - RC_BIT_RC6_0 | RC_BIT_RC6_6A_20 | RC_BIT_RC6_6A_24 | \ - RC_BIT_RC6_6A_32 | RC_BIT_RC6_MCE | RC_BIT_SHARP | \ - RC_BIT_XMP) +#define RC_PROTO_BIT_ALL \ + (RC_PROTO_BIT_UNKNOWN | RC_PROTO_BIT_OTHER | \ + RC_PROTO_BIT_RC5 | RC_PROTO_BIT_RC5X_20 | \ + RC_PROTO_BIT_RC5_SZ | RC_PROTO_BIT_JVC | \ + RC_PROTO_BIT_SONY12 | RC_PROTO_BIT_SONY15 | \ + RC_PROTO_BIT_SONY20 | RC_PROTO_BIT_NEC | \ + RC_PROTO_BIT_NECX | RC_PROTO_BIT_NEC32 | \ + RC_PROTO_BIT_SANYO | \ + RC_PROTO_BIT_MCIR2_KBD | RC_PROTO_BIT_MCIR2_MSE | \ + RC_PROTO_BIT_RC6_0 | RC_PROTO_BIT_RC6_6A_20 | \ + RC_PROTO_BIT_RC6_6A_24 | RC_PROTO_BIT_RC6_6A_32 | \ + RC_PROTO_BIT_RC6_MCE | RC_PROTO_BIT_SHARP | \ + RC_PROTO_BIT_XMP | RC_PROTO_BIT_CEC | \ + RC_PROTO_BIT_IMON) +/* All rc protocols for which we have decoders */ +#define RC_PROTO_BIT_ALL_IR_DECODER \ + (RC_PROTO_BIT_RC5 | RC_PROTO_BIT_RC5X_20 | \ + RC_PROTO_BIT_RC5_SZ | RC_PROTO_BIT_JVC | \ + RC_PROTO_BIT_SONY12 | RC_PROTO_BIT_SONY15 | \ + RC_PROTO_BIT_SONY20 | RC_PROTO_BIT_NEC | \ + RC_PROTO_BIT_NECX | RC_PROTO_BIT_NEC32 | \ + RC_PROTO_BIT_SANYO | RC_PROTO_BIT_MCIR2_KBD | \ + RC_PROTO_BIT_MCIR2_MSE | \ + RC_PROTO_BIT_RC6_0 | RC_PROTO_BIT_RC6_6A_20 | \ + RC_PROTO_BIT_RC6_6A_24 | RC_PROTO_BIT_RC6_6A_32 | \ + RC_PROTO_BIT_RC6_MCE | RC_PROTO_BIT_SHARP | \ + RC_PROTO_BIT_XMP | RC_PROTO_BIT_IMON) +#define RC_PROTO_BIT_ALL_IR_ENCODER \ + (RC_PROTO_BIT_RC5 | RC_PROTO_BIT_RC5X_20 | \ + RC_PROTO_BIT_RC5_SZ | RC_PROTO_BIT_JVC | \ + RC_PROTO_BIT_SONY12 | RC_PROTO_BIT_SONY15 | \ + RC_PROTO_BIT_SONY20 | RC_PROTO_BIT_NEC | \ + RC_PROTO_BIT_NECX | RC_PROTO_BIT_NEC32 | \ + RC_PROTO_BIT_SANYO | RC_PROTO_BIT_MCIR2_KBD | \ + RC_PROTO_BIT_MCIR2_MSE | \ + RC_PROTO_BIT_RC6_0 | RC_PROTO_BIT_RC6_6A_20 | \ + RC_PROTO_BIT_RC6_6A_24 | \ + RC_PROTO_BIT_RC6_6A_32 | RC_PROTO_BIT_RC6_MCE | \ + RC_PROTO_BIT_SHARP | RC_PROTO_BIT_IMON) #define RC_SCANCODE_UNKNOWN(x) (x) #define RC_SCANCODE_OTHER(x) (x) @@ -74,21 +89,45 @@ enum rc_type { #define RC_SCANCODE_RC6_0(sys, cmd) (((sys) << 8) | (cmd)) #define RC_SCANCODE_RC6_6A(vendor, sys, cmd) (((vendor) << 16) | ((sys) << 8) | (cmd)) +/** + * struct rc_map_table - represents a scancode/keycode pair + * + * @scancode: scan code (u32) + * @keycode: Linux input keycode + */ struct rc_map_table { u32 scancode; u32 keycode; }; +/** + * struct rc_map - represents a keycode map table + * + * @scan: pointer to struct &rc_map_table + * @size: Max number of entries + * @len: Number of entries that are in use + * @alloc: size of \*scan, in bytes + * @rc_proto: type of the remote controller protocol, as defined at + * enum &rc_proto + * @name: name of the key map table + * @lock: lock to protect access to this structure + */ struct rc_map { struct rc_map_table *scan; - unsigned int size; /* Max number of entries */ - unsigned int len; /* Used number of entries */ - unsigned int alloc; /* Size of *scan in bytes */ - enum rc_type rc_type; + unsigned int size; + unsigned int len; + unsigned int alloc; + enum rc_proto rc_proto; const char *name; spinlock_t lock; }; +/** + * struct rc_map_list - list of the registered &rc_map maps + * + * @list: pointer to struct &list_head + * @map: pointer to struct &rc_map + */ struct rc_map_list { struct list_head list; struct rc_map map; @@ -96,10 +135,25 @@ struct rc_map_list { /* Routines from rc-map.c */ +/** + * rc_map_register() - Registers a Remote Controler scancode map + * + * @map: pointer to struct rc_map_list + */ int rc_map_register(struct rc_map_list *map); + +/** + * rc_map_unregister() - Unregisters a Remote Controler scancode map + * + * @map: pointer to struct rc_map_list + */ void rc_map_unregister(struct rc_map_list *map); + +/** + * rc_map_get - gets an RC map from its name + * @name: name of the RC scancode map + */ struct rc_map *rc_map_get(const char *name); -void rc_map_init(void); /* Names of the several keytables defined in-kernel */ @@ -123,6 +177,7 @@ void rc_map_init(void); #define RC_MAP_BEHOLD_COLUMBUS "rc-behold-columbus" #define RC_MAP_BEHOLD "rc-behold" #define RC_MAP_BUDGET_CI_OLD "rc-budget-ci-old" +#define RC_MAP_CEC "rc-cec" #define RC_MAP_CINERGY_1400 "rc-cinergy-1400" #define RC_MAP_CINERGY "rc-cinergy" #define RC_MAP_DELOCK_61959 "rc-delock-61959" @@ -145,11 +200,13 @@ void rc_map_init(void); #define RC_MAP_FLYVIDEO "rc-flyvideo" #define RC_MAP_FUSIONHDTV_MCE "rc-fusionhdtv-mce" #define RC_MAP_GADMEI_RM008Z "rc-gadmei-rm008z" +#define RC_MAP_GEEKBOX "rc-geekbox" #define RC_MAP_GENIUS_TVGO_A11MCE "rc-genius-tvgo-a11mce" #define RC_MAP_GOTVIEW7135 "rc-gotview7135" #define RC_MAP_HAUPPAUGE_NEW "rc-hauppauge" #define RC_MAP_IMON_MCE "rc-imon-mce" #define RC_MAP_IMON_PAD "rc-imon-pad" +#define RC_MAP_IMON_RSC "rc-imon-rsc" #define RC_MAP_IODATA_BCTV7E "rc-iodata-bctv7e" #define RC_MAP_IT913X_V1 "rc-it913x-v1" #define RC_MAP_IT913X_V2 "rc-it913x-v2" @@ -158,7 +215,6 @@ void rc_map_init(void); #define RC_MAP_KWORLD_PC150U "rc-kworld-pc150u" #define RC_MAP_KWORLD_PLUS_TV_ANALOG "rc-kworld-plus-tv-analog" #define RC_MAP_LEADTEK_Y04G0051 "rc-leadtek-y04g0051" -#define RC_MAP_LIRC "rc-lirc" #define RC_MAP_LME2510 "rc-lme2510" #define RC_MAP_MANLI "rc-manli" #define RC_MAP_MEDION_X10 "rc-medion-x10" diff --git a/include/media/rk-isp10-config.h b/include/media/rk-isp10-config.h new file mode 100644 index 000000000000..63e02e7e93f4 --- /dev/null +++ b/include/media/rk-isp10-config.h @@ -0,0 +1,592 @@ +/* + ************************************************************************* + * Rockchip driver for CIF ISP 1.0 + * (Based on Intel driver for sofiaxxx) + * + * Copyright (C) 2015 Intel Mobile Communications GmbH + * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + ************************************************************************* + */ +#ifndef _RK_ISP11_CONFIG_H +#define _RK_ISP11_CONFIG_H + +#include <media/v4l2-config_rockchip.h> + +#define CIFISP_MODULE_MAX 18 +/* ISP Other module ID */ +#define CIFISP_DPCC_ID 0 +#define CIFISP_BLS_ID 1 +#define CIFISP_SDG_ID 2 +#define CIFISP_LSC_ID 3 +#define CIFISP_AWB_GAIN_ID 4 +#define CIFISP_FLT_ID 5 +#define CIFISP_BDM_ID 6 +#define CIFISP_CTK_ID 7 +#define CIFISP_GOC_ID 8 +#define CIFISP_CPROC_ID 9 +#define CIFISP_IE_ID 10 +#define CIFISP_WDR_ID 11 +#define CIFISP_DPF_ID 12 +#define CIFISP_DPF_STRENGTH_ID 13 +/* ISP Meas module ID, It must be after other id */ +#define CIFISP_MEAS_ID 14 +#define CIFISP_AEC_ID (CIFISP_MEAS_ID + 0) +#define CIFISP_AFC_ID (CIFISP_MEAS_ID + 1) +#define CIFISP_AWB_ID (CIFISP_MEAS_ID + 2) +#define CIFISP_HST_ID (CIFISP_MEAS_ID + 3) + +#define CIFISP_MODULE_DPCC (1 << CIFISP_DPCC_ID) +#define CIFISP_MODULE_BLS (1 << CIFISP_BLS_ID) +#define CIFISP_MODULE_SDG (1 << CIFISP_SDG_ID) +#define CIFISP_MODULE_HST (1 << CIFISP_HST_ID) +#define CIFISP_MODULE_LSC (1 << CIFISP_LSC_ID) +#define CIFISP_MODULE_AWB_GAIN (1 << CIFISP_AWB_GAIN_ID) +#define CIFISP_MODULE_FLT (1 << CIFISP_FLT_ID) +#define CIFISP_MODULE_BDM (1 << CIFISP_BDM_ID) +#define CIFISP_MODULE_CTK (1 << CIFISP_CTK_ID) +#define CIFISP_MODULE_GOC (1 << CIFISP_GOC_ID) +#define CIFISP_MODULE_CPROC (1 << CIFISP_CPROC_ID) +#define CIFISP_MODULE_AFC (1 << CIFISP_AFC_ID) +#define CIFISP_MODULE_AWB (1 << CIFISP_AWB_ID) +#define CIFISP_MODULE_IE (1 << CIFISP_IE_ID) +#define CIFISP_MODULE_AEC (1 << CIFISP_AEC_ID) +#define CIFISP_MODULE_WDR (1 << CIFISP_WDR_ID) +#define CIFISP_MODULE_DPF (1 << CIFISP_DPF_ID) +#define CIFISP_MODULE_DPF_STRENGTH (1 << CIFISP_DPF_STRENGTH_ID) + +#define CIFISP_CTK_COEFF_MAX 0x100 +#define CIFISP_CTK_OFFSET_MAX 0x800 + +#define CIFISP_AE_MEAN_MAX 25 +#define CIFISP_HIST_BIN_N_MAX 16 +#define CIFISP_AFM_MAX_WINDOWS 3 +#define CIFISP_DEGAMMA_CURVE_SIZE 17 + +#define CIFISP_BDM_MAX_TH 0xFF + +/* maximum value for horizontal start address */ +#define CIFISP_BLS_START_H_MAX (0x00000FFF) +/* maximum value for horizontal stop address */ +#define CIFISP_BLS_STOP_H_MAX (0x00000FFF) +/* maximum value for vertical start address */ +#define CIFISP_BLS_START_V_MAX (0x00000FFF) +/* maximum value for vertical stop address */ +#define CIFISP_BLS_STOP_V_MAX (0x00000FFF) +/* maximum is 2^18 = 262144*/ +#define CIFISP_BLS_SAMPLES_MAX (0x00000012) +/* maximum value for fixed black level */ +#define CIFISP_BLS_FIX_SUB_MAX (0x00000FFF) +/* minimum value for fixed black level */ +#define CIFISP_BLS_FIX_SUB_MIN (0xFFFFF000) +/* 13 bit range (signed)*/ +#define CIFISP_BLS_FIX_MASK (0x00001FFF) +/* AWB */ +#define CIFISP_AWB_MAX_GRID 1 +#define CIFISP_AWB_MAX_FRAMES 7 + +/* Gamma out*/ +/* Maximum number of color samples supported */ +#define CIFISP_GAMMA_OUT_MAX_SAMPLES 17 + +/* LSC */ +#define CIFISP_LSC_GRAD_TBL_SIZE 8 +#define CIFISP_LSC_SIZE_TBL_SIZE 8 +/* + * The following matches the tuning process, + * not the max capabilities of the chip. + */ +#define CIFISP_LSC_DATA_TBL_SIZE 289 +/* HIST */ +#define CIFISP_HISTOGRAM_WEIGHT_GRIDS_SIZE 25 + +/* DPCC */ +#define CIFISP_DPCC_METHODS_MAX (3) + +/* DPF */ +#define CIFISP_DPF_MAX_NLF_COEFFS 17 +#define CIFISP_DPF_MAX_SPATIAL_COEFFS 6 + +#define CIFISP_STAT_AWB BIT(0) +#define CIFISP_STAT_AUTOEXP BIT(1) +#define CIFISP_STAT_AFM_FIN BIT(2) +#define CIFISP_STAT_HIST BIT(3) + +enum cifisp_histogram_mode { + CIFISP_HISTOGRAM_MODE_DISABLE = 0, + CIFISP_HISTOGRAM_MODE_RGB_COMBINED = 1, + CIFISP_HISTOGRAM_MODE_R_HISTOGRAM = 2, + CIFISP_HISTOGRAM_MODE_G_HISTOGRAM = 3, + CIFISP_HISTOGRAM_MODE_B_HISTOGRAM = 4, + CIFISP_HISTOGRAM_MODE_Y_HISTOGRAM = 5 +}; + +enum cifisp_exp_ctrl_autostop { + CIFISP_EXP_CTRL_AUTOSTOP_0 = 0, + CIFISP_EXP_CTRL_AUTOSTOP_1 = 1 +}; + +enum cifisp_exp_meas_mode { +/* < Y = 16 + 0.25R + 0.5G + 0.1094B */ + CIFISP_EXP_MEASURING_MODE_0 = 0, +/* < Y = (R + G + B) x (85/256) */ + CIFISP_EXP_MEASURING_MODE_1 = 1, +}; + +struct cifisp_window { + unsigned short h_offs; + unsigned short v_offs; + unsigned short h_size; + unsigned short v_size; +}; + +enum cifisp_awb_mode_type { + CIFISP_AWB_MODE_MANUAL = 0, + CIFISP_AWB_MODE_RGB = 1, + CIFISP_AWB_MODE_YCBCR = 2 +}; + +enum cifisp_bls_win_enable { + ISP_BLS_CTRL_WINDOW_ENABLE_0 = 0, + ISP_BLS_CTRL_WINDOW_ENABLE_1 = 1, + ISP_BLS_CTRL_WINDOW_ENABLE_2 = 2, + ISP_BLS_CTRL_WINDOW_ENABLE_3 = 3 +}; + +enum cifisp_flt_mode { + CIFISP_FLT_STATIC_MODE, + CIFISP_FLT_DYNAMIC_MODE +}; + +struct cifisp_awb_meas { + unsigned int cnt; + unsigned char mean_y; + unsigned char mean_cb; + unsigned char mean_cr; + unsigned short mean_r; + unsigned short mean_b; + unsigned short mean_g; +}; + +struct cifisp_awb_stat { + struct cifisp_awb_meas awb_mean[CIFISP_AWB_MAX_GRID]; +}; + +struct cifisp_hist_stat { + unsigned int hist_bins[CIFISP_HIST_BIN_N_MAX]; +}; + +/*! BLS mean measured values */ +struct cifisp_bls_meas_val { + /*! Mean measured value for Bayer pattern R.*/ + unsigned short meas_r; + /*! Mean measured value for Bayer pattern Gr.*/ + unsigned short meas_gr; + /*! Mean measured value for Bayer pattern Gb.*/ + unsigned short meas_gb; + /*! Mean measured value for Bayer pattern B.*/ + unsigned short meas_b; +}; + +/* + * BLS fixed subtraction values. The values will be subtracted from the sensor + * values. Therefore a negative value means addition instead of subtraction! + */ +struct cifisp_bls_fixed_val { + /*! Fixed (signed!) subtraction value for Bayer pattern R. */ + signed short r; + /*! Fixed (signed!) subtraction value for Bayer pattern Gr. */ + signed short gr; + /*! Fixed (signed!) subtraction value for Bayer pattern Gb. */ + signed short gb; + /*! Fixed (signed!) subtraction value for Bayer pattern B. */ + signed short b; +}; + +/* Configuration used by black level subtraction */ +struct cifisp_bls_config { + /* + * Automatic mode activated means that the measured values + * are subtracted.Otherwise the fixed subtraction + * values will be subtracted. + */ + bool enable_auto; + unsigned char en_windows; + struct cifisp_window bls_window1; /* < Measurement window 1. */ + struct cifisp_window bls_window2; /* !< Measurement window 2 */ + /* + * Set amount of measured pixels for each Bayer position + * (A, B,C and D) to 2^bls_samples. + */ + unsigned char bls_samples; + /* !< Fixed subtraction values. */ + struct cifisp_bls_fixed_val fixed_val; +}; + +struct cifisp_ae_stat { + unsigned char exp_mean[CIFISP_AE_MEAN_MAX]; + struct cifisp_bls_meas_val bls_val; /* available wit exposure results */ +}; + +struct cifisp_af_meas_val { + unsigned int sum; + unsigned int lum; +}; + +struct cifisp_af_stat { + struct cifisp_af_meas_val window[CIFISP_AFM_MAX_WINDOWS]; +}; + +enum cifisp_vcm_val { + CIFISP_VCM_INVAL = -1, + CIFISP_VCM_MOVE_START = 0, + CIFISP_VCM_MOVE_RUNNING = 1, + CIFISP_VCM_MOVE_END = 2 +}; + +struct cifisp_vcm_tim { + struct timeval vcm_start_t; + struct timeval vcm_end_t; +}; + +struct cifisp_subdev_stat { + struct cifisp_vcm_tim vcm; +}; + +struct cifisp_stat { + struct cifisp_awb_stat awb; + struct cifisp_ae_stat ae; + struct cifisp_af_stat af; + struct cifisp_hist_stat hist; +}; + +struct cifisp_stat_buffer { + unsigned int meas_type; + struct cifisp_stat params; + struct isp_supplemental_sensor_mode_data sensor_mode; + struct cifisp_subdev_stat subdev_stat; + struct timeval vs_t; + struct timeval fi_t; +}; + +struct cifisp_dpcc_methods_config { + unsigned int method; + unsigned int line_thresh; + unsigned int line_mad_fac; + unsigned int pg_fac; + unsigned int rnd_thresh; + unsigned int rg_fac; +}; + +struct cifisp_dpcc_config { + unsigned int mode; + unsigned int output_mode; + unsigned int set_use; + struct cifisp_dpcc_methods_config methods[CIFISP_DPCC_METHODS_MAX]; + unsigned int ro_limits; + unsigned int rnd_offs; +}; + +struct cifisp_gamma_corr_curve { + unsigned short gamma_y[CIFISP_DEGAMMA_CURVE_SIZE]; +}; + +struct cifisp_gamma_curve_x_axis_pnts { + unsigned int gamma_dx0; + unsigned int gamma_dx1; +}; + +/* Configuration used by sensor degamma */ +struct cifisp_sdg_config { + struct cifisp_gamma_corr_curve curve_r; + struct cifisp_gamma_corr_curve curve_g; + struct cifisp_gamma_corr_curve curve_b; + struct cifisp_gamma_curve_x_axis_pnts xa_pnts; +}; + +/* Configuration used by Lens shading correction */ +struct cifisp_lsc_config { + unsigned int r_data_tbl[CIFISP_LSC_DATA_TBL_SIZE]; + unsigned int gr_data_tbl[CIFISP_LSC_DATA_TBL_SIZE]; + unsigned int gb_data_tbl[CIFISP_LSC_DATA_TBL_SIZE]; + unsigned int b_data_tbl[CIFISP_LSC_DATA_TBL_SIZE]; + + unsigned int x_grad_tbl[CIFISP_LSC_GRAD_TBL_SIZE]; + unsigned int y_grad_tbl[CIFISP_LSC_GRAD_TBL_SIZE]; + + unsigned int x_size_tbl[CIFISP_LSC_SIZE_TBL_SIZE]; + unsigned int y_size_tbl[CIFISP_LSC_SIZE_TBL_SIZE]; + unsigned short config_width; + unsigned short config_height; +}; + +struct cifisp_ie_config { + enum v4l2_colorfx effect; + unsigned short color_sel; + /* 3x3 Matrix Coefficients for Emboss Effect 1 */ + unsigned short eff_mat_1; + /* 3x3 Matrix Coefficients for Emboss Effect 2 */ + unsigned short eff_mat_2; + /* 3x3 Matrix Coefficients for Emboss 3/Sketch 1 */ + unsigned short eff_mat_3; + /* 3x3 Matrix Coefficients for Sketch Effect 2 */ + unsigned short eff_mat_4; + /* 3x3 Matrix Coefficients for Sketch Effect 3 */ + unsigned short eff_mat_5; + /* Chrominance increment values of tint (used for sepia effect) */ + unsigned short eff_tint; +}; + +/* Configuration used by auto white balance */ +struct cifisp_awb_meas_config { + /* + * white balance measurement window (in pixels) + * Note: currently the h and v offsets are mapped to grid offsets + */ + struct cifisp_window awb_wnd; + enum cifisp_awb_mode_type awb_mode; + /* + * only pixels values < max_y contribute to awb measurement + * (set to 0 to disable this feature) + */ + unsigned char max_y; + /* only pixels values > min_y contribute to awb measurement */ + unsigned char min_y; + /* + * Chrominance sum maximum value, only consider pixels with Cb+Cr + * smaller than threshold for awb measurements + */ + unsigned char max_csum; + /* + * Chrominance minimum value, only consider pixels with Cb/Cr + * each greater than threshold value for awb measurements + */ + unsigned char min_c; + /* + * number of frames - 1 used for mean value calculation + * (ucFrames=0 means 1 Frame) + */ + unsigned char frames; + /* reference Cr value for AWB regulation, target for AWB */ + unsigned char awb_ref_cr; + /* reference Cb value for AWB regulation, target for AWB */ + unsigned char awb_ref_cb; + bool enable_ymax_cmp; +}; + +struct cifisp_awb_gain_config { + unsigned short gain_red; + unsigned short gain_green_r; + unsigned short gain_blue; + unsigned short gain_green_b; +}; + +/* Configuration used by ISP filtering */ +struct cifisp_flt_config { + enum cifisp_flt_mode mode; /* ISP_FILT_MODE register fields */ + unsigned char grn_stage1; /* ISP_FILT_MODE register fields */ + unsigned char chr_h_mode; /* ISP_FILT_MODE register fields */ + unsigned char chr_v_mode; /* ISP_FILT_MODE register fields */ + unsigned int thresh_bl0; + unsigned int thresh_bl1; + unsigned int thresh_sh0; + unsigned int thresh_sh1; + unsigned int lum_weight; + unsigned int fac_sh1; + unsigned int fac_sh0; + unsigned int fac_mid; + unsigned int fac_bl0; + unsigned int fac_bl1; +}; + +/* Configuration used by Bayer DeMosaic */ +struct cifisp_bdm_config { + unsigned char demosaic_th; +}; + +/* Configuration used by Cross Talk correction */ +struct cifisp_ctk_config { + unsigned short coeff0; + unsigned short coeff1; + unsigned short coeff2; + unsigned short coeff3; + unsigned short coeff4; + unsigned short coeff5; + unsigned short coeff6; + unsigned short coeff7; + unsigned short coeff8; + /* offset for the crosstalk correction matrix */ + unsigned short ct_offset_r; + unsigned short ct_offset_g; + unsigned short ct_offset_b; +}; + +enum cifisp_goc_mode { + CIFISP_GOC_MODE_LOGARITHMIC, + CIFISP_GOC_MODE_EQUIDISTANT +}; + +/* Configuration used by Gamma Out correction */ +struct cifisp_goc_config { + enum cifisp_goc_mode mode; + unsigned short gamma_y[CIFISP_GAMMA_OUT_MAX_SAMPLES]; +}; + +/* CCM (Color Correction) */ +struct cifisp_cproc_config { + unsigned char c_out_range; + unsigned char y_in_range; + unsigned char y_out_range; + unsigned char contrast; + unsigned char brightness; + unsigned char sat; + unsigned char hue; +}; + +/* Configuration used by Histogram */ +struct cifisp_hst_config { + enum cifisp_histogram_mode mode; + unsigned char histogram_predivider; + struct cifisp_window meas_window; + unsigned char hist_weight[CIFISP_HISTOGRAM_WEIGHT_GRIDS_SIZE]; +}; + +/* Configuration used by Auto Exposure Control */ +struct cifisp_aec_config { + enum cifisp_exp_meas_mode mode; + enum cifisp_exp_ctrl_autostop autostop; + struct cifisp_window meas_window; +}; + +struct cifisp_afc_config { + unsigned char num_afm_win; /* max CIFISP_AFM_MAX_WINDOWS */ + struct cifisp_window afm_win[CIFISP_AFM_MAX_WINDOWS]; + unsigned int thres; + unsigned int var_shift; +}; + +enum cifisp_dpf_gain_usage { +/* don't use any gains in preprocessing stage */ + CIFISP_DPF_GAIN_USAGE_DISABLED = 1, +/* use only the noise function gains from registers DPF_NF_GAIN_R, ... */ + CIFISP_DPF_GAIN_USAGE_NF_GAINS = 2, +/* use only the gains from LSC module */ + CIFISP_DPF_GAIN_USAGE_LSC_GAINS = 3, +/* use the moise function gains and the gains from LSC module */ + CIFISP_DPF_GAIN_USAGE_NF_LSC_GAINS = 4, +/* use only the gains from AWB module */ + CIFISP_DPF_GAIN_USAGE_AWB_GAINS = 5, +/* use the gains from AWB and LSC module */ + CIFISP_DPF_GAIN_USAGE_AWB_LSC_GAINS = 6, +/* upper border (only for an internal evaluation) */ + CIFISP_DPF_GAIN_USAGE_MAX +}; + +enum cifisp_dpf_rb_filtersize { +/* red and blue filter kernel size 13x9 (means 7x5 active pixel) */ + CIFISP_DPF_RB_FILTERSIZE_13x9 = 0, +/* red and blue filter kernel size 9x9 (means 5x5 active pixel) */ + CIFISP_DPF_RB_FILTERSIZE_9x9 = 1, +}; + +enum cifisp_dpf_nll_scale_mode { +/* use a linear scaling */ + CIFISP_NLL_SCALE_LINEAR = 0, +/* use a logarithmic scaling */ + CIFISP_NLL_SCALE_LOGARITHMIC = 1, +}; + +struct cifisp_dpf_nll { + unsigned short coeff[CIFISP_DPF_MAX_NLF_COEFFS]; + enum cifisp_dpf_nll_scale_mode scale_mode; +}; + +struct cifisp_dpf_rb_flt { + enum cifisp_dpf_rb_filtersize fltsize; + unsigned char spatial_coeff[CIFISP_DPF_MAX_SPATIAL_COEFFS]; + bool r_enable; + bool b_enable; +}; + +struct cifisp_dpf_g_flt { + unsigned char spatial_coeff[CIFISP_DPF_MAX_SPATIAL_COEFFS]; + bool gr_enable; + bool gb_enable; +}; + +struct cifisp_dpf_gain { + enum cifisp_dpf_gain_usage mode; + unsigned short nf_r_gain; + unsigned short nf_b_gain; + unsigned short nf_gr_gain; + unsigned short nf_gb_gain; +}; + +struct cifisp_dpf_config { + struct cifisp_dpf_gain gain; + struct cifisp_dpf_g_flt g_flt; + struct cifisp_dpf_rb_flt rb_flt; + struct cifisp_dpf_nll nll; +}; + +struct cifisp_dpf_strength_config { + unsigned char r; + unsigned char g; + unsigned char b; +}; + +struct cifisp_last_capture_config { + struct cifisp_cproc_config cproc; + struct cifisp_goc_config goc; + struct cifisp_ctk_config ctk; + struct cifisp_bdm_config bdm; + struct cifisp_flt_config flt; + struct cifisp_awb_gain_config awb_gain; + struct cifisp_awb_meas_config awb_meas; + struct cifisp_lsc_config lsc; + struct cifisp_sdg_config sdg; + struct cifisp_bls_config bls; +}; + +struct cifisp_isp_other_cfg { + unsigned int s_frame_id;/* Set isp hardware frame id */ + + unsigned int module_ens; + + struct cifisp_dpcc_config dpcc_config; + struct cifisp_bls_config bls_config; + struct cifisp_sdg_config sdg_config; + struct cifisp_lsc_config lsc_config; + struct cifisp_awb_gain_config awb_gain_config; + struct cifisp_flt_config flt_config; + struct cifisp_bdm_config bdm_config; + struct cifisp_ctk_config ctk_config; + struct cifisp_goc_config goc_config; + struct cifisp_cproc_config cproc_config; + struct cifisp_ie_config ie_config; + struct cifisp_dpf_config dpf_config; + struct cifisp_dpf_strength_config dpf_strength_config; +}; + +struct cifisp_isp_meas_cfg { + unsigned int s_frame_id; /* Set isp hardware frame id */ + + unsigned int module_ens; + + struct cifisp_awb_meas_config awb_meas_config; + struct cifisp_hst_config hst_config; + struct cifisp_aec_config aec_config; + struct cifisp_afc_config afc_config; +}; + +struct cifisp_isp_metadata { + struct cifisp_isp_other_cfg other_cfg; + struct cifisp_isp_meas_cfg meas_cfg; + struct cifisp_stat_buffer meas_stat; +}; +#endif diff --git a/include/media/rk-isp10-ioctl.h b/include/media/rk-isp10-ioctl.h new file mode 100644 index 000000000000..367e28003d9e --- /dev/null +++ b/include/media/rk-isp10-ioctl.h @@ -0,0 +1,140 @@ +/* + ************************************************************************* + * Rockchip driver for CIF ISP 1.0 + * (Based on Intel driver for sofiaxxx) + * + * Copyright (C) 2015 Intel Mobile Communications GmbH + * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + ************************************************************************* + */ +#include <linux/v4l2-controls.h> +#include <media/rk-isp10-config.h> +#include <media/v4l2-controls_rockchip.h> + +#ifndef _RK_ISP10_IOCTL_H +#define _RK_ISP10_IOCTL_H + +/* Private IOCTLs */ +/* DPCC */ +#define CIFISP_IOC_G_DPCC \ + _IOR('v', BASE_VIDIOC_PRIVATE + 0, struct cifisp_dpcc_config) +#define CIFISP_IOC_S_DPCC \ + _IOW('v', BASE_VIDIOC_PRIVATE + 1, struct cifisp_dpcc_config) +/* Black Level Subtraction */ +#define CIFISP_IOC_G_BLS \ + _IOR('v', BASE_VIDIOC_PRIVATE + 2, struct cifisp_bls_config) +#define CIFISP_IOC_S_BLS \ + _IOW('v', BASE_VIDIOC_PRIVATE + 3, struct cifisp_bls_config) +/* Sensor DeGamma */ +#define CIFISP_IOC_G_SDG \ + _IOR('v', BASE_VIDIOC_PRIVATE + 4, struct cifisp_sdg_config) +#define CIFISP_IOC_S_SDG \ + _IOW('v', BASE_VIDIOC_PRIVATE + 5, struct cifisp_sdg_config) +/* Lens Shading Correction */ +#define CIFISP_IOC_G_LSC \ + _IOR('v', BASE_VIDIOC_PRIVATE + 6, struct cifisp_lsc_config) +#define CIFISP_IOC_S_LSC \ + _IOW('v', BASE_VIDIOC_PRIVATE + 7, struct cifisp_lsc_config) +/* Auto White Balance */ +#define CIFISP_IOC_G_AWB_MEAS \ + _IOR('v', BASE_VIDIOC_PRIVATE + 8, struct cifisp_awb_meas_config) +#define CIFISP_IOC_S_AWB_MEAS \ + _IOW('v', BASE_VIDIOC_PRIVATE + 9, struct cifisp_awb_meas_config) +/* ISP Filtering( Sharpening & Noise reduction */ +#define CIFISP_IOC_G_FLT \ + _IOR('v', BASE_VIDIOC_PRIVATE + 10, struct cifisp_flt_config) +#define CIFISP_IOC_S_FLT \ + _IOW('v', BASE_VIDIOC_PRIVATE + 11, struct cifisp_flt_config) +/* Bayer Demosaic */ +#define CIFISP_IOC_G_BDM \ + _IOR('v', BASE_VIDIOC_PRIVATE + 12, struct cifisp_bdm_config) +#define CIFISP_IOC_S_BDM \ + _IOW('v', BASE_VIDIOC_PRIVATE + 13, struct cifisp_bdm_config) +/* Cross Talk correction */ +#define CIFISP_IOC_G_CTK \ + _IOR('v', BASE_VIDIOC_PRIVATE + 14, struct cifisp_ctk_config) +#define CIFISP_IOC_S_CTK \ + _IOW('v', BASE_VIDIOC_PRIVATE + 15, struct cifisp_ctk_config) +/* Gamma Out Correction */ +#define CIFISP_IOC_G_GOC \ + _IOR('v', BASE_VIDIOC_PRIVATE + 16, struct cifisp_goc_config) +#define CIFISP_IOC_S_GOC \ + _IOW('v', BASE_VIDIOC_PRIVATE + 17, struct cifisp_goc_config) +/* Histogram Measurement */ +#define CIFISP_IOC_G_HST \ + _IOR('v', BASE_VIDIOC_PRIVATE + 18, struct cifisp_hst_config) +#define CIFISP_IOC_S_HST \ + _IOW('v', BASE_VIDIOC_PRIVATE + 19, struct cifisp_hst_config) +/* Auto Exposure Measurements */ +#define CIFISP_IOC_G_AEC \ + _IOR('v', BASE_VIDIOC_PRIVATE + 20, struct cifisp_aec_config) +#define CIFISP_IOC_S_AEC \ + _IOW('v', BASE_VIDIOC_PRIVATE + 21, struct cifisp_aec_config) +#define CIFISP_IOC_G_BPL \ + _IOR('v', BASE_VIDIOC_PRIVATE + 22, struct cifisp_aec_config) +#define CIFISP_IOC_G_AWB_GAIN \ + _IOR('v', BASE_VIDIOC_PRIVATE + 23, struct cifisp_awb_gain_config) +#define CIFISP_IOC_S_AWB_GAIN \ + _IOW('v', BASE_VIDIOC_PRIVATE + 24, struct cifisp_awb_gain_config) +#define CIFISP_IOC_G_CPROC \ + _IOR('v', BASE_VIDIOC_PRIVATE + 25, struct cifisp_cproc_config) +#define CIFISP_IOC_S_CPROC \ + _IOW('v', BASE_VIDIOC_PRIVATE + 26, struct cifisp_cproc_config) +#define CIFISP_IOC_G_AFC \ + _IOR('v', BASE_VIDIOC_PRIVATE + 27, struct cifisp_afc_config) +#define CIFISP_IOC_S_AFC \ + _IOW('v', BASE_VIDIOC_PRIVATE + 28, struct cifisp_afc_config) +#define CIFISP_IOC_G_IE \ + _IOR('v', BASE_VIDIOC_PRIVATE + 29, struct cifisp_ie_config) +#define CIFISP_IOC_S_IE \ + _IOW('v', BASE_VIDIOC_PRIVATE + 30, struct cifisp_ie_config) +#define CIFISP_IOC_G_DPF \ + _IOR('v', BASE_VIDIOC_PRIVATE + 31, struct cifisp_dpf_config) +#define CIFISP_IOC_S_DPF \ + _IOW('v', BASE_VIDIOC_PRIVATE + 32, struct cifisp_dpf_config) +#define CIFISP_IOC_G_DPF_STRENGTH \ + _IOR('v', BASE_VIDIOC_PRIVATE + 33, struct cifisp_dpf_strength_config) +#define CIFISP_IOC_S_DPF_STRENGTH \ + _IOW('v', BASE_VIDIOC_PRIVATE + 34, struct cifisp_dpf_strength_config) +#define CIFISP_IOC_G_LAST_CONFIG \ + _IOR('v', BASE_VIDIOC_PRIVATE + 35, struct cifisp_last_capture_config) + +/* CIF-ISP Private control IDs */ +#define V4L2_CID_CIFISP_DPCC (V4L2_CID_PRIVATE_BASE + CIFISP_DPCC_ID) +#define V4L2_CID_CIFISP_BLS (V4L2_CID_PRIVATE_BASE + CIFISP_BLS_ID) +#define V4L2_CID_CIFISP_SDG (V4L2_CID_PRIVATE_BASE + CIFISP_SDG_ID) +#define V4L2_CID_CIFISP_HST (V4L2_CID_PRIVATE_BASE + CIFISP_HST_ID) +#define V4L2_CID_CIFISP_LSC (V4L2_CID_PRIVATE_BASE + CIFISP_LSC_ID) +#define V4L2_CID_CIFISP_AWB_GAIN (V4L2_CID_PRIVATE_BASE + CIFISP_AWB_GAIN_ID) +#define V4L2_CID_CIFISP_FLT (V4L2_CID_PRIVATE_BASE + CIFISP_FLT_ID) +#define V4L2_CID_CIFISP_BDM (V4L2_CID_PRIVATE_BASE + CIFISP_BDM_ID) +#define V4L2_CID_CIFISP_CTK (V4L2_CID_PRIVATE_BASE + CIFISP_CTK_ID) +#define V4L2_CID_CIFISP_GOC (V4L2_CID_PRIVATE_BASE + CIFISP_GOC_ID) +#define V4L2_CID_CIFISP_CPROC (V4L2_CID_PRIVATE_BASE + CIFISP_CPROC_ID) +#define V4L2_CID_CIFISP_AFC (V4L2_CID_PRIVATE_BASE + CIFISP_AFC_ID) +#define V4L2_CID_CIFISP_AWB_MEAS (V4L2_CID_PRIVATE_BASE + CIFISP_AWB_ID) +#define V4L2_CID_CIFISP_IE (V4L2_CID_PRIVATE_BASE + CIFISP_IE_ID) +#define V4L2_CID_CIFISP_AEC (V4L2_CID_PRIVATE_BASE + CIFISP_AEC_ID) +#define V4L2_CID_CIFISP_DPF (V4L2_CID_PRIVATE_BASE + CIFISP_DPF_ID) + +/* Camera Sensors' running modes */ +#define CI_MODE_PREVIEW 0x8000 +#define CI_MODE_VIDEO 0x4000 +#define CI_MODE_STILL_CAPTURE 0x2000 +#define CI_MODE_CONTINUOUS 0x1000 +#define CI_MODE_NONE 0x0000 + +/* Kernel API */ +void cif_isp11_v4l2_s_frame_interval( + unsigned int numerator, + unsigned int denominator); +int cif_isp11_v4l2_g_frame_interval( + unsigned int *numerator, + unsigned int *denominator); +#endif diff --git a/include/media/soc_camera.h b/include/media/soc_camera.h index 97aa13314bfd..1594f24cedfa 100644 --- a/include/media/soc_camera.h +++ b/include/media/soc_camera.h @@ -41,6 +41,10 @@ struct soc_camera_device { unsigned char iface; /* Host number */ unsigned char devnum; /* Device number per host */ struct soc_camera_sense *sense; /* See comment in struct definition */ + + struct soc_camera_ops *ops;/*yzm*/ + struct mutex video_lock;/*yzm*/ + struct video_device *vdev; struct v4l2_ctrl_handler ctrl_handler; const struct soc_camera_format_xlate *current_fmt; @@ -94,6 +98,20 @@ struct soc_camera_host_ops { struct module *owner; int (*add)(struct soc_camera_device *); void (*remove)(struct soc_camera_device *); + + int (*suspend)(struct soc_camera_device *, pm_message_t); + int (*resume)(struct soc_camera_device *); + /* ddl@rock-chips.com : + * Add ioctrl - VIDIOC_ENUM_FRAMEINTERVALS for soc-camera + */ + int (*enum_frameinervals)(struct soc_camera_device *, + struct v4l2_frmivalenum *); + int (*get_ctrl)(struct soc_camera_device *, struct v4l2_control *); + int (*set_ctrl)(struct soc_camera_device *, struct v4l2_control *); + int (*s_stream)(struct soc_camera_device *, int enable); + const struct v4l2_queryctrl *controls; + int num_controls; + int (*clock_start)(struct soc_camera_host *); void (*clock_stop)(struct soc_camera_host *); /* @@ -115,6 +133,7 @@ struct soc_camera_host_ops { * to change the output sizes */ int (*set_livecrop)(struct soc_camera_device *, const struct v4l2_crop *); + int (*get_fmt)(struct soc_camera_device *, struct v4l2_format *); int (*set_fmt)(struct soc_camera_device *, struct v4l2_format *); int (*try_fmt)(struct soc_camera_device *, struct v4l2_format *); void (*init_videobuf)(struct videobuf_queue *, @@ -145,6 +164,7 @@ struct soc_camera_subdev_desc { /* sensor driver private platform data */ void *drv_priv; + struct soc_camera_device *socdev;/*yzm*/ /* * Set unbalanced_power to true to deal with legacy drivers, failing to @@ -159,6 +179,8 @@ struct soc_camera_subdev_desc { int (*power)(struct device *, int); int (*reset)(struct device *); + int (*powerdown)(struct device *, int);/*yzm*/ + /* * some platforms may support different data widths than the sensors * native ones due to different data line routing. Let the board code @@ -209,7 +231,7 @@ struct soc_camera_link { unsigned long flags; void *priv; - + void *priv_usr; /* Set by platforms to handle misbehaving drivers */ bool unbalanced_power; /* Used by soc-camera helper functions */ @@ -218,6 +240,7 @@ struct soc_camera_link { /* Optional callbacks to power on or off and reset the sensor */ int (*power)(struct device *, int); int (*reset)(struct device *); + int (*powerdown)(struct device *, int); /*yzm*/ /* * some platforms may support different data widths than the sensors * native ones due to different data line routing. Let the board code @@ -300,6 +323,18 @@ struct soc_camera_format_xlate { const struct soc_mbus_pixelfmt *host_fmt; }; +struct soc_camera_ops { + int (*suspend)(struct soc_camera_device *, pm_message_t state); + int (*resume)(struct soc_camera_device *); + unsigned long (*query_bus_param)(struct soc_camera_device *); + int (*set_bus_param)(struct soc_camera_device *, unsigned long); + int (*enum_input)(struct soc_camera_device *, struct v4l2_input *); + const struct v4l2_queryctrl *controls; + struct v4l2_querymenu *menus; + int num_controls; + int num_menus; +}; + #define SOCAM_SENSE_PCLK_CHANGED (1 << 0) /** @@ -326,6 +361,18 @@ struct soc_camera_sense { unsigned long pixel_clock; }; +static inline struct v4l2_queryctrl const *soc_camera_find_qctrl( + struct soc_camera_ops *ops, int id) +{ + int i; + + for (i = 0; i < ops->num_controls; i++) + if (ops->controls[i].id == id) + return &ops->controls[i]; + + return NULL; +} + #define SOCAM_DATAWIDTH(x) BIT((x) - 1) #define SOCAM_DATAWIDTH_4 SOCAM_DATAWIDTH(4) #define SOCAM_DATAWIDTH_8 SOCAM_DATAWIDTH(8) @@ -336,7 +383,8 @@ struct soc_camera_sense { #define SOCAM_DATAWIDTH_16 SOCAM_DATAWIDTH(16) #define SOCAM_DATAWIDTH_18 SOCAM_DATAWIDTH(18) #define SOCAM_DATAWIDTH_24 SOCAM_DATAWIDTH(24) - +#define SOCAM_MCLK_24MHZ BIT(29) +#define SOCAM_MCLK_48MHZ BIT(31) #define SOCAM_DATAWIDTH_MASK (SOCAM_DATAWIDTH_4 | SOCAM_DATAWIDTH_8 | \ SOCAM_DATAWIDTH_9 | SOCAM_DATAWIDTH_10 | \ SOCAM_DATAWIDTH_12 | SOCAM_DATAWIDTH_15 | \ diff --git a/include/media/tc358743.h b/include/media/tc35874x.h index 4513f2f9cfbc..b86143a0e9ba 100644 --- a/include/media/tc358743.h +++ b/include/media/tc35874x.h @@ -1,5 +1,5 @@ /* - * tc358743 - Toshiba HDMI to CSI-2 bridge + * tc35874x - Toshiba HDMI to CSI-2 bridge * * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights * reserved. @@ -23,26 +23,27 @@ * References (c = chapter, p = page): * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60 * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls + * REF_03 - Toshiba, TC358749XBG (H2C+), Functional Specification, Rev 0.74 */ -#ifndef _TC358743_ -#define _TC358743_ +#ifndef _TC35874X_ +#define _TC35874X_ -enum tc358743_ddc5v_delays { +enum tc35874x_ddc5v_delays { DDC5V_DELAY_0_MS, DDC5V_DELAY_50_MS, DDC5V_DELAY_100_MS, DDC5V_DELAY_200_MS, }; -enum tc358743_hdmi_detection_delay { +enum tc35874x_hdmi_detection_delay { HDMI_MODE_DELAY_0_MS, HDMI_MODE_DELAY_25_MS, HDMI_MODE_DELAY_50_MS, HDMI_MODE_DELAY_100_MS, }; -struct tc358743_platform_data { +struct tc35874x_platform_data { /* System clock connected to REFCLK (pin H5) */ u32 refclk_hz; /* 26 MHz, 27 MHz or 42 MHz */ @@ -51,7 +52,7 @@ struct tc358743_platform_data { * Sets DDC5V_MODE in register DDC_CTL. * Default: DDC5V_DELAY_0_MS */ - enum tc358743_ddc5v_delays ddc5v_delay; + enum tc35874x_ddc5v_delays ddc5v_delay; bool enable_hdcp; @@ -89,7 +90,7 @@ struct tc358743_platform_data { * Sets HDMI_DET_V in register HDMI_DET. * Default: HDMI_MODE_DELAY_0_MS */ - enum tc358743_hdmi_detection_delay hdmi_detection_delay; + enum tc35874x_hdmi_detection_delay hdmi_detection_delay; /* Reset PHY automatically when TMDS clock goes from DC to AC. * Sets PHY_AUTO_RST2 in register PHY_CTL2. @@ -124,8 +125,8 @@ struct tc358743_platform_data { /* custom controls */ /* Audio sample rate in Hz */ -#define TC358743_CID_AUDIO_SAMPLING_RATE (V4L2_CID_USER_TC358743_BASE + 0) +#define TC35874X_CID_AUDIO_SAMPLING_RATE (V4L2_CID_USER_TC35874X_BASE + 0) /* Audio present status */ -#define TC358743_CID_AUDIO_PRESENT (V4L2_CID_USER_TC358743_BASE + 1) +#define TC35874X_CID_AUDIO_PRESENT (V4L2_CID_USER_TC35874X_BASE + 1) -#endif +#endif
\ No newline at end of file diff --git a/include/media/v4l2-async.h b/include/media/v4l2-async.h index 1d6d7da4c45d..74f2ea27d117 100644 --- a/include/media/v4l2-async.h +++ b/include/media/v4l2-async.h @@ -23,11 +23,24 @@ struct v4l2_async_notifier; /* A random max subdevice number, used to allocate an array on stack */ #define V4L2_MAX_SUBDEVS 128U +/** + * enum v4l2_async_match_type - type of asynchronous subdevice logic to be used + * in order to identify a match + * + * @V4L2_ASYNC_MATCH_CUSTOM: Match will use the logic provided by &struct + * v4l2_async_subdev.match ops + * @V4L2_ASYNC_MATCH_DEVNAME: Match will use the device name + * @V4L2_ASYNC_MATCH_I2C: Match will check for I2C adapter ID and address + * @V4L2_ASYNC_MATCH_FWNODE: Match will use firmware node + * + * This enum is used by the asyncrhronous sub-device logic to define the + * algorithm that will be used to match an asynchronous device. + */ enum v4l2_async_match_type { V4L2_ASYNC_MATCH_CUSTOM, V4L2_ASYNC_MATCH_DEVNAME, V4L2_ASYNC_MATCH_I2C, - V4L2_ASYNC_MATCH_OF, + V4L2_ASYNC_MATCH_FWNODE, }; /** @@ -37,13 +50,17 @@ enum v4l2_async_match_type { * @match: union of per-bus type matching data sets * @list: used to link struct v4l2_async_subdev objects, waiting to be * probed, to a notifier->waiting list + * + * When this struct is used as a member in a driver specific struct, + * the driver specific struct shall contain the &struct + * v4l2_async_subdev as its first member. */ struct v4l2_async_subdev { enum v4l2_async_match_type match_type; union { struct { - const struct device_node *node; - } of; + struct fwnode_handle *fwnode; + } fwnode; struct { const char *name; } device_name; @@ -63,37 +80,126 @@ struct v4l2_async_subdev { }; /** + * struct v4l2_async_notifier_operations - Asynchronous V4L2 notifier operations + * @bound: a subdevice driver has successfully probed one of the subdevices + * @complete: all subdevices have been probed successfully + * @unbind: a subdevice is leaving + */ +struct v4l2_async_notifier_operations { + int (*bound)(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *subdev, + struct v4l2_async_subdev *asd); + int (*complete)(struct v4l2_async_notifier *notifier); + void (*unbind)(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *subdev, + struct v4l2_async_subdev *asd); +}; + +/** * struct v4l2_async_notifier - v4l2_device notifier data * - * @num_subdevs: number of subdevices + * @ops: notifier operations + * @num_subdevs: number of subdevices used in the subdevs array + * @max_subdevs: number of subdevices allocated in the subdevs array * @subdevs: array of pointers to subdevice descriptors - * @v4l2_dev: pointer to struct v4l2_device + * @v4l2_dev: v4l2_device of the root notifier, NULL otherwise + * @sd: sub-device that registered the notifier, NULL otherwise + * @parent: parent notifier * @waiting: list of struct v4l2_async_subdev, waiting for their drivers * @done: list of struct v4l2_subdev, already probed * @list: member in a global list of notifiers - * @bound: a subdevice driver has successfully probed one of subdevices - * @complete: all subdevices have been probed successfully - * @unbind: a subdevice is leaving */ struct v4l2_async_notifier { + const struct v4l2_async_notifier_operations *ops; unsigned int num_subdevs; + unsigned int max_subdevs; struct v4l2_async_subdev **subdevs; struct v4l2_device *v4l2_dev; + struct v4l2_subdev *sd; + struct v4l2_async_notifier *parent; struct list_head waiting; struct list_head done; struct list_head list; - int (*bound)(struct v4l2_async_notifier *notifier, - struct v4l2_subdev *subdev, - struct v4l2_async_subdev *asd); - int (*complete)(struct v4l2_async_notifier *notifier); - void (*unbind)(struct v4l2_async_notifier *notifier, - struct v4l2_subdev *subdev, - struct v4l2_async_subdev *asd); }; +/** + * v4l2_async_notifier_register - registers a subdevice asynchronous notifier + * + * @v4l2_dev: pointer to &struct v4l2_device + * @notifier: pointer to &struct v4l2_async_notifier + */ int v4l2_async_notifier_register(struct v4l2_device *v4l2_dev, struct v4l2_async_notifier *notifier); + +/** + * v4l2_async_subdev_notifier_register - registers a subdevice asynchronous + * notifier for a sub-device + * + * @sd: pointer to &struct v4l2_subdev + * @notifier: pointer to &struct v4l2_async_notifier + */ +int v4l2_async_subdev_notifier_register(struct v4l2_subdev *sd, + struct v4l2_async_notifier *notifier); + +/** + * v4l2_async_notifier_unregister - unregisters a subdevice asynchronous notifier + * + * @notifier: pointer to &struct v4l2_async_notifier + */ void v4l2_async_notifier_unregister(struct v4l2_async_notifier *notifier); + +/** + * v4l2_async_notifier_cleanup - clean up notifier resources + * @notifier: the notifier the resources of which are to be cleaned up + * + * Release memory resources related to a notifier, including the async + * sub-devices allocated for the purposes of the notifier but not the notifier + * itself. The user is responsible for calling this function to clean up the + * notifier after calling @v4l2_async_notifier_parse_fwnode_endpoints or + * @v4l2_fwnode_reference_parse_sensor_common. + * + * There is no harm from calling v4l2_async_notifier_cleanup in other + * cases as long as its memory has been zeroed after it has been + * allocated. + */ +void v4l2_async_notifier_cleanup(struct v4l2_async_notifier *notifier); + +/** + * v4l2_async_register_subdev - registers a sub-device to the asynchronous + * subdevice framework + * + * @sd: pointer to &struct v4l2_subdev + */ int v4l2_async_register_subdev(struct v4l2_subdev *sd); + +/** + * v4l2_async_register_subdev_sensor_common - registers a sensor sub-device to + * the asynchronous sub-device + * framework and parse set up common + * sensor related devices + * + * @sd: pointer to struct &v4l2_subdev + * + * This function is just like v4l2_async_register_subdev() with the exception + * that calling it will also parse firmware interfaces for remote references + * using v4l2_async_notifier_parse_fwnode_sensor_common() and registers the + * async sub-devices. The sub-device is similarly unregistered by calling + * v4l2_async_unregister_subdev(). + * + * While registered, the subdev module is marked as in-use. + * + * An error is returned if the module is no longer loaded on any attempts + * to register it. + */ +int __must_check v4l2_async_register_subdev_sensor_common( + struct v4l2_subdev *sd); + +/** + * v4l2_async_unregister_subdev - unregisters a sub-device to the asynchronous + * subdevice framework + * + * @sd: pointer to &struct v4l2_subdev + */ void v4l2_async_unregister_subdev(struct v4l2_subdev *sd); + #endif diff --git a/include/media/v4l2-chip-ident.h b/include/media/v4l2-chip-ident.h new file mode 100644 index 000000000000..359ccc948dfd --- /dev/null +++ b/include/media/v4l2-chip-ident.h @@ -0,0 +1,414 @@ +/* + v4l2 chip identifiers header + + This header provides a list of chip identifiers that can be returned + through the VIDIOC_DBG_G_CHIP_IDENT ioctl. + + Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef V4L2_CHIP_IDENT_H_ +#define V4L2_CHIP_IDENT_H_ + +/* VIDIOC_DBG_G_CHIP_IDENT: identifies the actual chip installed on the board */ + +/* KEEP THIS LIST ORDERED BY ID! + Otherwise it will be hard to see which ranges are already in use when + adding support to a new chip family. */ +enum { + /* general idents: reserved range 0-49 */ + V4L2_IDENT_NONE = 0, /* No chip matched */ + V4L2_IDENT_AMBIGUOUS = 1, /* Match too general, multiple chips matched */ + V4L2_IDENT_UNKNOWN = 2, /* Chip found, but cannot identify */ + + /* module tvaudio: reserved range 50-99 */ + V4L2_IDENT_TVAUDIO = 50, /* A tvaudio chip, unknown which it is exactly */ + + /* Sony IMX074 */ + V4L2_IDENT_IMX074 = 74, + + /* module saa7110: just ident 100 */ + V4L2_IDENT_SAA7110 = 100, + + /* module saa7115: reserved range 101-149 */ + V4L2_IDENT_SAA7111 = 101, + V4L2_IDENT_SAA7111A = 102, + V4L2_IDENT_SAA7113 = 103, + V4L2_IDENT_SAA7114 = 104, + V4L2_IDENT_SAA7115 = 105, + V4L2_IDENT_SAA7118 = 108, + + /* module saa7127: reserved range 150-199 */ + V4L2_IDENT_SAA7127 = 157, + V4L2_IDENT_SAA7129 = 159, + + /* module cx25840: reserved range 200-249 */ + V4L2_IDENT_CX25836 = 236, + V4L2_IDENT_CX25837 = 237, + V4L2_IDENT_CX25840 = 240, + V4L2_IDENT_CX25841 = 241, + V4L2_IDENT_CX25842 = 242, + V4L2_IDENT_CX25843 = 243, + + /* OmniVision sensors: reserved range 250-299 */ + V4L2_IDENT_OV7670 = 250, + V4L2_IDENT_OV7720 = 251, + V4L2_IDENT_OV7725 = 252, + V4L2_IDENT_OV7660 = 253, + V4L2_IDENT_OV9650 = 254, + V4L2_IDENT_OV9655 = 255, + V4L2_IDENT_SOI968 = 256, + V4L2_IDENT_OV9640 = 257, + V4L2_IDENT_OV6650 = 258, + V4L2_IDENT_OV2640 = 259, + V4L2_IDENT_OV9740 = 260, + V4L2_IDENT_OV5642 = 261, +/***********yzm**********/ + V4L2_IDENT_OV2655 = 262, /* ddl@rock-chips.com : ov2655 support */ + V4L2_IDENT_OV2659 = 263, + V4L2_IDENT_OV3640 = 264, + V4L2_IDENT_OV5640 = 265, + V4L2_IDENT_OV7675 = 266, + V4L2_IDENT_OV7690 = 267, + V4L2_IDENT_OV3660 = 268, + V4L2_IDENT_TP2825 = 269, + V4L2_IDENT_GC2155 = 270, + V4L2_IDENT_ADV7181 = 271, + V4L2_IDENT_GC2145 = 272, +/***********yzm********end*/ + /* module saa7146: reserved range 300-309 */ + V4L2_IDENT_SAA7146 = 300, +/***********yzm*************/ + /* Samsung sensors: reserved range 310-319 */ + V4L2_IDENT_S5K66A = 310, /* ddl@rock-chips.com : s5k66a support */ + V4L2_IDENT_S5K5CA = 311, /* ddl@rock-chips.com : s5k5ca support */ + + V4L2_IDENT_MTK9335ISP = 320, /* ddl@rock-chips.com : MTK9335ISP support */ + V4L2_IDENT_ICATCH7002_MI1040 = 321, + V4L2_IDENT_ICATCH7002_OV5693 =322, + V4L2_IDENT_ICATCH7002_OV8825 = 323, //zyt + V4L2_IDENT_ICATCH7002_OV2720 = 324, //zyt +/************yzm************end*/ + /* Conexant MPEG encoder/decoders: reserved range 400-420 */ + V4L2_IDENT_CX23418_843 = 403, /* Integrated A/V Decoder on the '418 */ + V4L2_IDENT_CX23415 = 415, + V4L2_IDENT_CX23416 = 416, + V4L2_IDENT_CX23417 = 417, + V4L2_IDENT_CX23418 = 418, + + /* module bt819: reserved range 810-819 */ + V4L2_IDENT_BT815A = 815, + V4L2_IDENT_BT817A = 817, + V4L2_IDENT_BT819A = 819, + + /* module au0828 */ + V4L2_IDENT_AU0828 = 828, + + /* module bttv: ident 848 + 849 */ + V4L2_IDENT_BT848 = 848, + V4L2_IDENT_BT849 = 849, + + /* module bt856: just ident 856 */ + V4L2_IDENT_BT856 = 856, + + /* module bt866: just ident 866 */ + V4L2_IDENT_BT866 = 866, + + /* module bttv: ident 878 + 879 */ + V4L2_IDENT_BT878 = 878, + V4L2_IDENT_BT879 = 879, + + /* module ks0127: reserved range 1120-1129 */ + V4L2_IDENT_KS0122S = 1122, + V4L2_IDENT_KS0127 = 1127, + V4L2_IDENT_KS0127B = 1128, + + /* module indycam: just ident 2000 */ + V4L2_IDENT_INDYCAM = 2000, + + /* module vp27smpx: just ident 2700 */ + V4L2_IDENT_VP27SMPX = 2700, + + /* module vpx3220: reserved range: 3210-3229 */ + V4L2_IDENT_VPX3214C = 3214, + V4L2_IDENT_VPX3216B = 3216, + V4L2_IDENT_VPX3220A = 3220, + + /* VX855 just ident 3409 */ + /* Other via devs could use 3314, 3324, 3327, 3336, 3364, 3353 */ + V4L2_IDENT_VIA_VX855 = 3409, + + /* module tvp5150 */ + V4L2_IDENT_TVP5150 = 5150, + + /* module saa5246a: just ident 5246 */ + V4L2_IDENT_SAA5246A = 5246, + + /* module saa5249: just ident 5249 */ + V4L2_IDENT_SAA5249 = 5249, + + /* module cs5345: just ident 5345 */ + V4L2_IDENT_CS5345 = 5345, + + /* module tea6415c: just ident 6415 */ + V4L2_IDENT_TEA6415C = 6415, + + /* module tea6420: just ident 6420 */ + V4L2_IDENT_TEA6420 = 6420, + + /* module saa6588: just ident 6588 */ + V4L2_IDENT_SAA6588 = 6588, + + /* module vs6624: just ident 6624 */ + V4L2_IDENT_VS6624 = 6624, + + /* module saa6752hs: reserved range 6750-6759 */ + V4L2_IDENT_SAA6752HS = 6752, + V4L2_IDENT_SAA6752HS_AC3 = 6753, + + /* modules tef6862: just ident 6862 */ + V4L2_IDENT_TEF6862 = 6862, + + /* module tvp7002: just ident 7002 */ + V4L2_IDENT_TVP7002 = 7002, + + /* module adv7170: just ident 7170 */ + V4L2_IDENT_ADV7170 = 7170, + + /* module adv7175: just ident 7175 */ + V4L2_IDENT_ADV7175 = 7175, + + /* module adv7180: just ident 7180 */ + V4L2_IDENT_ADV7180 = 7180, + + /* module adv7183: just ident 7183 */ + V4L2_IDENT_ADV7183 = 7183, + + /* module saa7185: just ident 7185 */ + V4L2_IDENT_SAA7185 = 7185, + + /* module saa7191: just ident 7191 */ + V4L2_IDENT_SAA7191 = 7191, + + /* module ths7303: just ident 7303 */ + V4L2_IDENT_THS7303 = 7303, + + /* module adv7343: just ident 7343 */ + V4L2_IDENT_ADV7343 = 7343, + + /* module ths7353: just ident 7353 */ + V4L2_IDENT_THS7353 = 7353, + + /* module adv7393: just ident 7393 */ + V4L2_IDENT_ADV7393 = 7393, + + /* module adv7604: just ident 7604 */ + V4L2_IDENT_ADV7604 = 7604, + + /* module saa7706h: just ident 7706 */ + V4L2_IDENT_SAA7706H = 7706, + + /* module mt9v011, just ident 8243 */ + V4L2_IDENT_MT9V011 = 8243, + + /* module wm8739: just ident 8739 */ + V4L2_IDENT_WM8739 = 8739, + + /* module wm8775: just ident 8775 */ + V4L2_IDENT_WM8775 = 8775, + + /* Marvell controllers starting at 8801 */ + V4L2_IDENT_CAFE = 8801, + V4L2_IDENT_ARMADA610 = 8802, + + /* AKM AK8813/AK8814 */ + V4L2_IDENT_AK8813 = 8813, + V4L2_IDENT_AK8814 = 8814, + + /* module cx23885 and cx25840 */ + V4L2_IDENT_CX23885 = 8850, + V4L2_IDENT_CX23885_AV = 8851, /* Integrated A/V decoder */ + V4L2_IDENT_CX23887 = 8870, + V4L2_IDENT_CX23887_AV = 8871, /* Integrated A/V decoder */ + V4L2_IDENT_CX23888 = 8880, + V4L2_IDENT_CX23888_AV = 8881, /* Integrated A/V decoder */ + V4L2_IDENT_CX23888_IR = 8882, /* Integrated infrared controller */ + + /* module ad9389b: just ident 9389 */ + V4L2_IDENT_AD9389B = 9389, + + /* module tda9840: just ident 9840 */ + V4L2_IDENT_TDA9840 = 9840, + + /* module tw9910: just ident 9910 */ + V4L2_IDENT_TW9910 = 9910, + + /* module sn9c20x: just ident 10000 */ + V4L2_IDENT_SN9C20X = 10000, + + /* Siliconfile sensors: reserved range 10100 - 10199 */ + V4L2_IDENT_NOON010PC30 = 10100,/*yzm*/ + /* module cx231xx and cx25840 */ + V4L2_IDENT_CX2310X_AV = 23099, /* Integrated A/V decoder; not in '100 */ + V4L2_IDENT_CX23100 = 23100, + V4L2_IDENT_CX23101 = 23101, + V4L2_IDENT_CX23102 = 23102, + + /* module msp3400: reserved range 34000-34999 for msp34xx */ + V4L2_IDENT_MSPX4XX = 34000, /* generic MSPX4XX identifier, only + use internally (tveeprom.c). */ + + V4L2_IDENT_MSP3400B = 34002, + V4L2_IDENT_MSP3400C = 34003, + V4L2_IDENT_MSP3400D = 34004, + V4L2_IDENT_MSP3400G = 34007, + V4L2_IDENT_MSP3401G = 34017, + V4L2_IDENT_MSP3402G = 34027, + V4L2_IDENT_MSP3405D = 34054, + V4L2_IDENT_MSP3405G = 34057, + V4L2_IDENT_MSP3407D = 34074, + V4L2_IDENT_MSP3407G = 34077, + + V4L2_IDENT_MSP3410B = 34102, + V4L2_IDENT_MSP3410C = 34103, + V4L2_IDENT_MSP3410D = 34104, + V4L2_IDENT_MSP3410G = 34107, + V4L2_IDENT_MSP3411G = 34117, + V4L2_IDENT_MSP3412G = 34127, + V4L2_IDENT_MSP3415D = 34154, + V4L2_IDENT_MSP3415G = 34157, + V4L2_IDENT_MSP3417D = 34174, + V4L2_IDENT_MSP3417G = 34177, + + V4L2_IDENT_MSP3420G = 34207, + V4L2_IDENT_MSP3421G = 34217, + V4L2_IDENT_MSP3422G = 34227, + V4L2_IDENT_MSP3425G = 34257, + V4L2_IDENT_MSP3427G = 34277, + + V4L2_IDENT_MSP3430G = 34307, + V4L2_IDENT_MSP3431G = 34317, + V4L2_IDENT_MSP3435G = 34357, + V4L2_IDENT_MSP3437G = 34377, + + V4L2_IDENT_MSP3440G = 34407, + V4L2_IDENT_MSP3441G = 34417, + V4L2_IDENT_MSP3442G = 34427, + V4L2_IDENT_MSP3445G = 34457, + V4L2_IDENT_MSP3447G = 34477, + + V4L2_IDENT_MSP3450G = 34507, + V4L2_IDENT_MSP3451G = 34517, + V4L2_IDENT_MSP3452G = 34527, + V4L2_IDENT_MSP3455G = 34557, + V4L2_IDENT_MSP3457G = 34577, + + V4L2_IDENT_MSP3460G = 34607, + V4L2_IDENT_MSP3461G = 34617, + V4L2_IDENT_MSP3465G = 34657, + V4L2_IDENT_MSP3467G = 34677, + + /* module msp3400: reserved range 44000-44999 for msp44xx */ + V4L2_IDENT_MSP4400G = 44007, + V4L2_IDENT_MSP4408G = 44087, + V4L2_IDENT_MSP4410G = 44107, + V4L2_IDENT_MSP4418G = 44187, + V4L2_IDENT_MSP4420G = 44207, + V4L2_IDENT_MSP4428G = 44287, + V4L2_IDENT_MSP4440G = 44407, + V4L2_IDENT_MSP4448G = 44487, + V4L2_IDENT_MSP4450G = 44507, + V4L2_IDENT_MSP4458G = 44587, + + /* Micron CMOS sensor chips: 45000-45099 */ + V4L2_IDENT_MT9M001C12ST = 45000, + V4L2_IDENT_MT9M001C12STM = 45005, + V4L2_IDENT_MT9M111 = 45007, + V4L2_IDENT_MT9M112 = 45008, + V4L2_IDENT_MT9D112 = 45009, /* ddl@rock-chips.com : MT9D112 support */ + V4L2_IDENT_MT9V022IX7ATC = 45010, /* No way to detect "normal" I77ATx */ + V4L2_IDENT_MT9V022IX7ATM = 45015, /* and "lead free" IA7ATx chips */ + V4L2_IDENT_MT9T031 = 45020, + V4L2_IDENT_MT9T111 = 45021, + V4L2_IDENT_MT9T112 = 45022, + V4L2_IDENT_MT9V111 = 45031, + V4L2_IDENT_MT9V112 = 45032, + + V4L2_IDENT_MT9P111 = 45033, /* ddl@rock-chips.com : MT9P111 support */ + V4L2_IDENT_MT9D113 = 45034, /* ddl@rock-chips.com : MT9D113 support */ + + /* HV7131R CMOS sensor: just ident 46000 */ + V4L2_IDENT_HV7131R = 46000, + + /* Sharp RJ54N1CB0C, 0xCB0C = 51980 */ + V4L2_IDENT_RJ54N1CB0C = 51980, + + /* module m52790: just ident 52790 */ + V4L2_IDENT_M52790 = 52790, + + /* module cs53132a: just ident 53132 */ + V4L2_IDENT_CS53l32A = 53132, + + /* modules upd61151 MPEG2 encoder: just ident 54000 */ + V4L2_IDENT_UPD61161 = 54000, + /* modules upd61152 MPEG2 encoder with AC3: just ident 54001 */ + V4L2_IDENT_UPD61162 = 54001, + + /* module upd64031a: just ident 64031 */ + V4L2_IDENT_UPD64031A = 64031, + + /* module upd64083: just ident 64083 */ + V4L2_IDENT_UPD64083 = 64083, + +/*************yzm************/ + V4L2_IDENT_NT99250 = 64100, /* ddl@rock-chips.com : nt99250 support */ + V4L2_IDENT_SID130B = 64101, /* ddl@rock-chips.com : sid130B support */ + + V4L2_IDENT_GT2005 = 64110, /* ddl@rock-chips.com : GT2005 support */ + V4L2_IDENT_GC0307 = 64111, /* ddl@rock-chips.com : GC0308 support */ + V4L2_IDENT_GC0308 = 64112, /* ddl@rock-chips.com : GC0308 support */ + V4L2_IDENT_GC0309 = 64113, /* ddl@rock-chips.com : GC0309 support */ + V4L2_IDENT_GC2015 = 64114, /* ddl@rock-chips.com : gc2015 support */ + V4L2_IDENT_GC0329 = 64115, /* ddl@rock-chips.com : GC0329 support */ + V4L2_IDENT_GC2035= 64116, /* ddl@rock-chips.com : GC0329 support */ + V4L2_IDENT_GC0328 = 64117, + + V4L2_IDENT_SP0838 = 64120, /* ddl@rock-chips.com : SP0838 support */ + V4L2_IDENT_SP2518 = 64121, /* ddl@rock-chips.com : SP2518 support */ + V4L2_IDENT_SP0718 = 64122, /* ddl@rock-chips.com : SP0718 support */ + V4L2_IDENT_GC0312 = 64124, + + V4L2_IDENT_HI253 = 64130, /* ddl@rock-chips.com : hi253 support */ + V4L2_IDENT_HI704 = 64131, /* ddl@rock-chips.com : hi704 support */ + + V4L2_IDENT_SIV120B = 64140, /* ddl@rock-chips.com : siv120b support */ + V4L2_IDENT_SIV121D= 64141, /* ddl@rock-chips.com : sid130B support */ + + + V4L2_IDENT_HM2057 = 64150, + V4L2_IDENT_HM5065 = 64151, + + V4L2_IDENT_NT99160 = 64161, /* oyyf@rock-chips.com : nt99160 support */ + V4L2_IDENT_NT99340 = 64162, /* oyyf@rock-chips.com : nt99340 support */ + V4L2_IDENT_NT99252 = 64163, /* oyyf@rock-chips.com : nt99252 support */ + V4L2_IDENT_NT99240 = 64164, /* oyyf@rock-chips.com : nt99252 support */ +/***********yzm***********end*/ + + /* Don't just add new IDs at the end: KEEP THIS LIST ORDERED BY ID! */ +}; + +#endif diff --git a/include/media/v4l2-config_rockchip.h b/include/media/v4l2-config_rockchip.h new file mode 100644 index 000000000000..e5550903dcdb --- /dev/null +++ b/include/media/v4l2-config_rockchip.h @@ -0,0 +1,127 @@ +/* + ************************************************************************* + * Rockchip driver for CIF ISP 1.0 + * (Based on Intel driver for sofiaxxx) + * + * Copyright (C) 2015 Intel Mobile Communications GmbH + * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + ************************************************************************* + */ + +#ifndef _V4L2_CONFIG_ROCKCHIP_H +#define _V4L2_CONFIG_ROCKCHIP_H + +#define CAMERA_STRLEN 32 +#define CAMERA_METADATA_LEN (2 * PAGE_SIZE) +#define VALID_FR_EXP_T_INDEX 0 +#define VALID_FR_EXP_G_INDEX 1 +#define SENSOR_CONFIG_NUM 4 +#define SENSOR_READ_MODE 0 +#define SENSOR_WRITE_MODE 1 + +/* Sensor resolution specific data for AE calculation.*/ +struct isp_supplemental_sensor_mode_data { + unsigned int coarse_integration_time_min; + unsigned int coarse_integration_time_max_margin; + unsigned int fine_integration_time_min; + unsigned int fine_integration_time_max_margin; + unsigned int frame_length_lines; + unsigned int line_length_pck; + unsigned int vt_pix_clk_freq_hz; + unsigned int crop_horizontal_start; /* Sensor crop start cord. (x0,y0)*/ + unsigned int crop_vertical_start; + unsigned int crop_horizontal_end; /* Sensor crop end cord. (x1,y1)*/ + unsigned int crop_vertical_end; + unsigned int sensor_output_width; /* input size to ISP */ + unsigned int sensor_output_height; + unsigned int isp_input_horizontal_start; /* cif isp input */ + unsigned int isp_input_vertical_start; + unsigned int isp_input_width; + unsigned int isp_input_height; + unsigned int isp_output_width; /* cif isp output */ + unsigned int isp_output_height; + unsigned char binning_factor_x; /* horizontal binning factor used */ + unsigned char binning_factor_y; /* vertical binning factor used */ + /* + *0: Exposure time valid fileds; + *1: Exposure gain valid fileds; + *(2 fileds == 1 frames) + */ + unsigned char exposure_valid_frame[2]; + int exp_time; + unsigned short gain; + unsigned char max_exp_gain_h; + unsigned char max_exp_gain_l; +}; + +struct camera_module_info_s { + char sensor_name[CAMERA_STRLEN]; + char module_name[CAMERA_STRLEN]; + char len_name[CAMERA_STRLEN]; + char fov_h[CAMERA_STRLEN]; + char fov_v[CAMERA_STRLEN]; + char focal_length[CAMERA_STRLEN]; + char focus_distance[CAMERA_STRLEN]; + int facing; + int orientation; + bool iq_mirror; + bool iq_flip; + int flash_support; + int flash_exp_percent; + int af_support; +}; + +struct sensor_resolution_s { + unsigned short width; + unsigned short height; +}; + +struct sensor_config_info_s { + unsigned char config_num; + unsigned char sensor_fmt[SENSOR_CONFIG_NUM]; + struct sensor_resolution_s reso[SENSOR_CONFIG_NUM]; +}; + +struct sensor_reg_rw_s { + unsigned char reg_access_mode; + unsigned char reg_addr_len; + unsigned char reg_data_len; + unsigned short addr; + unsigned short data; +}; + +struct flash_timeinfo_s { + struct timeval preflash_start_t; + struct timeval preflash_end_t; + struct timeval mainflash_start_t; + struct timeval mainflash_end_t; + int flash_turn_on_time; + int flash_on_timeout; +}; + +struct frame_timeinfo_s { + struct timeval vs_t; + struct timeval fi_t; +}; + +struct sensor_metadata_s { + unsigned int exp_time; + unsigned int gain; +}; + +struct v4l2_buffer_metadata_s { + unsigned int frame_id; + struct frame_timeinfo_s frame_t; + struct flash_timeinfo_s flash_t; + struct sensor_metadata_s sensor; + unsigned char isp[CAMERA_METADATA_LEN - 512]; +}; + +#endif + diff --git a/include/media/v4l2-controls_rockchip.h b/include/media/v4l2-controls_rockchip.h new file mode 100644 index 000000000000..c185a58e33da --- /dev/null +++ b/include/media/v4l2-controls_rockchip.h @@ -0,0 +1,37 @@ +/* + ************************************************************************* + * Rockchip driver for CIF ISP 1.0 + * (Based on Intel driver for sofiaxxx) + * + * Copyright (C) 2015 Intel Mobile Communications GmbH + * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + ************************************************************************* + */ + +#ifndef _V4L2_CONTROLS_ROCKCHIP_H +#define _V4L2_CONTROLS_ROCKCHIP_H + +#include <linux/videodev2.h> +#include <media/v4l2-config_rockchip.h> + +#define RK_VIDIOC_CAMERA_MODULEINFO \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 10, struct camera_module_info_s) +#define RK_VIDIOC_SENSOR_MODE_DATA \ + _IOR('v', BASE_VIDIOC_PRIVATE, struct isp_supplemental_sensor_mode_data) +#define RK_VIDIOC_SENSOR_CONFIGINFO \ + _IOR('v', BASE_VIDIOC_PRIVATE + 1, struct sensor_config_info_s) +#define RK_VIDIOC_SENSOR_REG_ACCESS \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 2, struct sensor_reg_rw_s) + +#define V4L2_CID_USER_RK_BASE (V4L2_CID_USER_BASE + 0x1080) +#define RK_V4L2_CID_VBLANKING (V4L2_CID_USER_RK_BASE + 1) +#define RK_V4L2_CID_GAIN_PERCENT (V4L2_CID_USER_RK_BASE + 2) +#define RK_V4L2_CID_AUTO_FPS (V4L2_CID_USER_RK_BASE + 3) +#define RK_V4L2_CID_VTS (V4L2_CID_USER_RK_BASE + 4) +#endif diff --git a/include/media/v4l2-ctrls.h b/include/media/v4l2-ctrls.h index da6fe9802fee..0a9434afd862 100644 --- a/include/media/v4l2-ctrls.h +++ b/include/media/v4l2-ctrls.h @@ -44,6 +44,12 @@ struct poll_table_struct; * @p_u16: Pointer to a 16-bit unsigned value. * @p_u32: Pointer to a 32-bit unsigned value. * @p_char: Pointer to a string. + * @p_h264_sps: Pointer to a struct v4l2_ctrl_h264_sps. + * @p_h264_pps: Pointer to a struct v4l2_ctrl_h264_pps. + * @p_h264_scal_mtrx: Pointer to a struct v4l2_ctrl_h264_scaling_matrix. + * @p_h264_slice_param: Pointer to a struct v4l2_ctrl_h264_slice_param. + * @p_h264_decode_param: Pointer to a struct v4l2_ctrl_h264_decode_param. + * @p_vp8_frame_hdr: Pointer to a struct v4l2_ctrl_vp8_frame_hdr. * @p: Pointer to a compound value. */ union v4l2_ctrl_ptr { @@ -53,6 +59,12 @@ union v4l2_ctrl_ptr { u16 *p_u16; u32 *p_u32; char *p_char; + struct v4l2_ctrl_h264_sps *p_h264_sps; + struct v4l2_ctrl_h264_pps *p_h264_pps; + struct v4l2_ctrl_h264_scaling_matrix *p_h264_scal_mtrx; + struct v4l2_ctrl_h264_slice_param *p_h264_slice_param; + struct v4l2_ctrl_h264_decode_param *p_h264_decode_param; + struct v4l2_ctrl_vp8_frame_hdr *p_vp8_frame_hdr; void *p; }; @@ -146,6 +158,9 @@ typedef void (*v4l2_ctrl_notify_fnc)(struct v4l2_ctrl *ctrl, void *priv); * @elem_size: The size in bytes of the control. * @dims: The size of each dimension. * @nr_of_dims:The number of dimensions in @dims. + * @max_stores:The maximum number of configuration stores of this control. + * @nr_of_stores: The number of allocated configuration stores of this control. + * @store: The configuration store that the control op operates on. * @menu_skip_mask: The control's skip mask for menu controls. This makes it * easy to skip menu items that are not valid. If bit X is set, * then menu item X is skipped. Of course, this only works for @@ -202,6 +217,9 @@ struct v4l2_ctrl { u32 elem_size; u32 dims[V4L2_CTRL_MAX_DIMS]; u32 nr_of_dims; + u16 max_stores; + u16 nr_of_stores; + u16 store; union { u64 step; u64 menu_skip_mask; @@ -219,6 +237,7 @@ struct v4l2_ctrl { union v4l2_ctrl_ptr p_new; union v4l2_ctrl_ptr p_cur; + union v4l2_ctrl_ptr *p_stores; }; /** @@ -285,6 +304,7 @@ struct v4l2_ctrl_handler { * @def: The control's default value. * @dims: The size of each dimension. * @elem_size: The size in bytes of the control. + * @max_stores: The maximum number of stores allowed. * @flags: The control's flags. * @menu_skip_mask: The control's skip mask for menu controls. This makes it * easy to skip menu items that are not valid. If bit X is set, @@ -313,6 +333,7 @@ struct v4l2_ctrl_config { s64 def; u32 dims[V4L2_CTRL_MAX_DIMS]; u32 elem_size; + u16 max_stores; u32 flags; u64 menu_skip_mask; const char * const *qmenu; @@ -886,6 +907,13 @@ static inline int v4l2_ctrl_s_ctrl_string(struct v4l2_ctrl *ctrl, const char *s) return rval; } +static inline void v4l2_ctrl_set_max_stores(struct v4l2_ctrl *ctrl, u16 max_stores) +{ + ctrl->max_stores = max_stores; +} + +int v4l2_ctrl_apply_store(struct v4l2_ctrl_handler *hdl, unsigned store); + /* Internal helper functions that deal with control events. */ extern const struct v4l2_subscribed_event_ops v4l2_ctrl_sub_ev_ops; void v4l2_ctrl_replace(struct v4l2_event *old, const struct v4l2_event *new); diff --git a/include/media/v4l2-dev.h b/include/media/v4l2-dev.h index acbcd2f5fe7f..5a562ad58bb9 100644 --- a/include/media/v4l2-dev.h +++ b/include/media/v4l2-dev.h @@ -90,6 +90,9 @@ struct video_device /* device ops */ const struct v4l2_file_operations *fops; + /* device capabilities as used in v4l2_capabilities */ + u32 device_caps; + /* sysfs */ struct device dev; /* v4l device */ struct cdev *cdev; /* character device */ diff --git a/include/media/v4l2-flash-led-class.h b/include/media/v4l2-flash-led-class.h index 3d184ab52274..86cf5afef297 100644 --- a/include/media/v4l2-flash-led-class.h +++ b/include/media/v4l2-flash-led-class.h @@ -101,7 +101,7 @@ static inline struct v4l2_flash *v4l2_ctrl_to_v4l2_flash(struct v4l2_ctrl *c) /** * v4l2_flash_init - initialize V4L2 flash led sub-device * @dev: flash device, e.g. an I2C device - * @of_node: of_node of the LED, may be NULL if the same as device's + * @fwn: fwnode_handle of the LED, may be NULL if the same as device's * @fled_cdev: LED flash class device to wrap * @iled_cdev: LED flash class device representing indicator LED associated * with fled_cdev, may be NULL @@ -115,7 +115,7 @@ static inline struct v4l2_flash *v4l2_ctrl_to_v4l2_flash(struct v4l2_ctrl *c) * PTR_ERR() to obtain the numeric return value. */ struct v4l2_flash *v4l2_flash_init( - struct device *dev, struct device_node *of_node, + struct device *dev, struct fwnode_handle *fwn, struct led_classdev_flash *fled_cdev, struct led_classdev_flash *iled_cdev, const struct v4l2_flash_ops *ops, @@ -131,7 +131,7 @@ void v4l2_flash_release(struct v4l2_flash *v4l2_flash); #else static inline struct v4l2_flash *v4l2_flash_init( - struct device *dev, struct device_node *of_node, + struct device *dev, struct fwnode_handle *fwn, struct led_classdev_flash *fled_cdev, struct led_classdev_flash *iled_cdev, const struct v4l2_flash_ops *ops, diff --git a/include/media/v4l2-fwnode.h b/include/media/v4l2-fwnode.h new file mode 100644 index 000000000000..392fd150315d --- /dev/null +++ b/include/media/v4l2-fwnode.h @@ -0,0 +1,322 @@ +/* + * V4L2 fwnode binding parsing library + * + * Copyright (c) 2016 Intel Corporation. + * Author: Sakari Ailus <sakari.ailus@linux.intel.com> + * + * Copyright (C) 2012 - 2013 Samsung Electronics Co., Ltd. + * Author: Sylwester Nawrocki <s.nawrocki@samsung.com> + * + * Copyright (C) 2012 Renesas Electronics Corp. + * Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + */ +#ifndef _V4L2_FWNODE_H +#define _V4L2_FWNODE_H + +#include <linux/errno.h> +#include <linux/fwnode.h> +#include <linux/list.h> +#include <linux/types.h> + +#include <media/v4l2-mediabus.h> + +struct fwnode_handle; +struct v4l2_async_notifier; +struct v4l2_async_subdev; + +/** + * struct v4l2_fwnode_bus_mipi_csi2 - MIPI CSI-2 bus data structure + * @flags: media bus (V4L2_MBUS_*) flags + * @data_lanes: an array of physical data lane indexes + * @clock_lane: physical lane index of the clock lane + * @num_data_lanes: number of data lanes + * @lane_polarities: polarity of the lanes. The order is the same of + * the physical lanes. + */ +struct v4l2_fwnode_bus_mipi_csi2 { + unsigned int flags; + unsigned char data_lanes[4]; + unsigned char clock_lane; + unsigned short num_data_lanes; + bool lane_polarities[5]; +}; + +/** + * struct v4l2_fwnode_bus_parallel - parallel data bus data structure + * @flags: media bus (V4L2_MBUS_*) flags + * @bus_width: bus width in bits + * @data_shift: data shift in bits + */ +struct v4l2_fwnode_bus_parallel { + unsigned int flags; + unsigned char bus_width; + unsigned char data_shift; +}; + +/** + * struct v4l2_fwnode_endpoint - the endpoint data structure + * @base: fwnode endpoint of the v4l2_fwnode + * @bus_type: bus type + * @bus: bus configuration data structure + * @link_frequencies: array of supported link frequencies + * @nr_of_link_frequencies: number of elements in link_frequenccies array + */ +struct v4l2_fwnode_endpoint { + struct fwnode_endpoint base; + /* + * Fields below this line will be zeroed by + * v4l2_fwnode_parse_endpoint() + */ + enum v4l2_mbus_type bus_type; + union { + struct v4l2_fwnode_bus_parallel parallel; + struct v4l2_fwnode_bus_mipi_csi2 mipi_csi2; + } bus; + u64 *link_frequencies; + unsigned int nr_of_link_frequencies; +}; + +/** + * struct v4l2_fwnode_link - a link between two endpoints + * @local_node: pointer to device_node of this endpoint + * @local_port: identifier of the port this endpoint belongs to + * @remote_node: pointer to device_node of the remote endpoint + * @remote_port: identifier of the port the remote endpoint belongs to + */ +struct v4l2_fwnode_link { + struct fwnode_handle *local_node; + unsigned int local_port; + struct fwnode_handle *remote_node; + unsigned int remote_port; +}; + +/** + * v4l2_fwnode_endpoint_parse() - parse all fwnode node properties + * @fwnode: pointer to the endpoint's fwnode handle + * @vep: pointer to the V4L2 fwnode data structure + * + * All properties are optional. If none are found, we don't set any flags. This + * means the port has a static configuration and no properties have to be + * specified explicitly. If any properties that identify the bus as parallel + * are found and slave-mode isn't set, we set V4L2_MBUS_MASTER. Similarly, if + * we recognise the bus as serial CSI-2 and clock-noncontinuous isn't set, we + * set the V4L2_MBUS_CSI2_CONTINUOUS_CLOCK flag. The caller should hold a + * reference to @fwnode. + * + * NOTE: This function does not parse properties the size of which is variable + * without a low fixed limit. Please use v4l2_fwnode_endpoint_alloc_parse() in + * new drivers instead. + * + * Return: 0 on success or a negative error code on failure. + */ +int v4l2_fwnode_endpoint_parse(struct fwnode_handle *fwnode, + struct v4l2_fwnode_endpoint *vep); + +/* + * v4l2_fwnode_endpoint_free() - free the V4L2 fwnode acquired by + * v4l2_fwnode_endpoint_alloc_parse() + * @vep - the V4L2 fwnode the resources of which are to be released + * + * It is safe to call this function with NULL argument or on a V4L2 fwnode the + * parsing of which failed. + */ +void v4l2_fwnode_endpoint_free(struct v4l2_fwnode_endpoint *vep); + +/** + * v4l2_fwnode_endpoint_alloc_parse() - parse all fwnode node properties + * @fwnode: pointer to the endpoint's fwnode handle + * + * All properties are optional. If none are found, we don't set any flags. This + * means the port has a static configuration and no properties have to be + * specified explicitly. If any properties that identify the bus as parallel + * are found and slave-mode isn't set, we set V4L2_MBUS_MASTER. Similarly, if + * we recognise the bus as serial CSI-2 and clock-noncontinuous isn't set, we + * set the V4L2_MBUS_CSI2_CONTINUOUS_CLOCK flag. The caller should hold a + * reference to @fwnode. + * + * v4l2_fwnode_endpoint_alloc_parse() has two important differences to + * v4l2_fwnode_endpoint_parse(): + * + * 1. It also parses variable size data. + * + * 2. The memory it has allocated to store the variable size data must be freed + * using v4l2_fwnode_endpoint_free() when no longer needed. + * + * Return: Pointer to v4l2_fwnode_endpoint if successful, on an error pointer + * on error. + */ +struct v4l2_fwnode_endpoint *v4l2_fwnode_endpoint_alloc_parse( + struct fwnode_handle *fwnode); + +/** + * v4l2_fwnode_parse_link() - parse a link between two endpoints + * @fwnode: pointer to the endpoint's fwnode at the local end of the link + * @link: pointer to the V4L2 fwnode link data structure + * + * Fill the link structure with the local and remote nodes and port numbers. + * The local_node and remote_node fields are set to point to the local and + * remote port's parent nodes respectively (the port parent node being the + * parent node of the port node if that node isn't a 'ports' node, or the + * grand-parent node of the port node otherwise). + * + * A reference is taken to both the local and remote nodes, the caller must use + * v4l2_fwnode_put_link() to drop the references when done with the + * link. + * + * Return: 0 on success, or -ENOLINK if the remote endpoint fwnode can't be + * found. + */ +int v4l2_fwnode_parse_link(struct fwnode_handle *fwnode, + struct v4l2_fwnode_link *link); + +/** + * v4l2_fwnode_put_link() - drop references to nodes in a link + * @link: pointer to the V4L2 fwnode link data structure + * + * Drop references to the local and remote nodes in the link. This function + * must be called on every link parsed with v4l2_fwnode_parse_link(). + */ +void v4l2_fwnode_put_link(struct v4l2_fwnode_link *link); + +/** + * v4l2_async_notifier_parse_fwnode_endpoints - Parse V4L2 fwnode endpoints in a + * device node + * @dev: the device the endpoints of which are to be parsed + * @notifier: notifier for @dev + * @asd_struct_size: size of the driver's async sub-device struct, including + * sizeof(struct v4l2_async_subdev). The &struct + * v4l2_async_subdev shall be the first member of + * the driver's async sub-device struct, i.e. both + * begin at the same memory address. + * @parse_endpoint: Driver's callback function called on each V4L2 fwnode + * endpoint. Optional. + * Return: %0 on success + * %-ENOTCONN if the endpoint is to be skipped but this + * should not be considered as an error + * %-EINVAL if the endpoint configuration is invalid + * + * Parse the fwnode endpoints of the @dev device and populate the async sub- + * devices array of the notifier. The @parse_endpoint callback function is + * called for each endpoint with the corresponding async sub-device pointer to + * let the caller initialize the driver-specific part of the async sub-device + * structure. + * + * The notifier memory shall be zeroed before this function is called on the + * notifier. + * + * This function may not be called on a registered notifier and may be called on + * a notifier only once. + * + * Do not change the notifier's subdevs array, take references to the subdevs + * array itself or change the notifier's num_subdevs field. This is because this + * function allocates and reallocates the subdevs array based on parsing + * endpoints. + * + * The &struct v4l2_fwnode_endpoint passed to the callback function + * @parse_endpoint is released once the function is finished. If there is a need + * to retain that configuration, the user needs to allocate memory for it. + * + * Any notifier populated using this function must be released with a call to + * v4l2_async_notifier_cleanup() after it has been unregistered and the async + * sub-devices are no longer in use, even if the function returned an error. + * + * Return: %0 on success, including when no async sub-devices are found + * %-ENOMEM if memory allocation failed + * %-EINVAL if graph or endpoint parsing failed + * Other error codes as returned by @parse_endpoint + */ +int v4l2_async_notifier_parse_fwnode_endpoints( + struct device *dev, struct v4l2_async_notifier *notifier, + size_t asd_struct_size, + int (*parse_endpoint)(struct device *dev, + struct v4l2_fwnode_endpoint *vep, + struct v4l2_async_subdev *asd)); + +/** + * v4l2_async_notifier_parse_fwnode_endpoints_by_port - Parse V4L2 fwnode + * endpoints of a port in a + * device node + * @dev: the device the endpoints of which are to be parsed + * @notifier: notifier for @dev + * @asd_struct_size: size of the driver's async sub-device struct, including + * sizeof(struct v4l2_async_subdev). The &struct + * v4l2_async_subdev shall be the first member of + * the driver's async sub-device struct, i.e. both + * begin at the same memory address. + * @port: port number where endpoints are to be parsed + * @parse_endpoint: Driver's callback function called on each V4L2 fwnode + * endpoint. Optional. + * Return: %0 on success + * %-ENOTCONN if the endpoint is to be skipped but this + * should not be considered as an error + * %-EINVAL if the endpoint configuration is invalid + * + * This function is just like v4l2_async_notifier_parse_fwnode_endpoints() with + * the exception that it only parses endpoints in a given port. This is useful + * on devices that have both sinks and sources: the async sub-devices connected + * to sources have already been configured by another driver (on capture + * devices). In this case the driver must know which ports to parse. + * + * Parse the fwnode endpoints of the @dev device on a given @port and populate + * the async sub-devices array of the notifier. The @parse_endpoint callback + * function is called for each endpoint with the corresponding async sub-device + * pointer to let the caller initialize the driver-specific part of the async + * sub-device structure. + * + * The notifier memory shall be zeroed before this function is called on the + * notifier the first time. + * + * This function may not be called on a registered notifier and may be called on + * a notifier only once per port. + * + * Do not change the notifier's subdevs array, take references to the subdevs + * array itself or change the notifier's num_subdevs field. This is because this + * function allocates and reallocates the subdevs array based on parsing + * endpoints. + * + * The &struct v4l2_fwnode_endpoint passed to the callback function + * @parse_endpoint is released once the function is finished. If there is a need + * to retain that configuration, the user needs to allocate memory for it. + * + * Any notifier populated using this function must be released with a call to + * v4l2_async_notifier_cleanup() after it has been unregistered and the async + * sub-devices are no longer in use, even if the function returned an error. + * + * Return: %0 on success, including when no async sub-devices are found + * %-ENOMEM if memory allocation failed + * %-EINVAL if graph or endpoint parsing failed + * Other error codes as returned by @parse_endpoint + */ +int v4l2_async_notifier_parse_fwnode_endpoints_by_port( + struct device *dev, struct v4l2_async_notifier *notifier, + size_t asd_struct_size, unsigned int port, + int (*parse_endpoint)(struct device *dev, + struct v4l2_fwnode_endpoint *vep, + struct v4l2_async_subdev *asd)); + +/** + * v4l2_fwnode_reference_parse_sensor_common - parse common references on + * sensors for async sub-devices + * @dev: the device node the properties of which are parsed for references + * @notifier: the async notifier where the async subdevs will be added + * + * Parse common sensor properties for remote devices related to the + * sensor and set up async sub-devices for them. + * + * Any notifier populated using this function must be released with a call to + * v4l2_async_notifier_release() after it has been unregistered and the async + * sub-devices are no longer in use, even in the case the function returned an + * error. + * + * Return: 0 on success + * -ENOMEM if memory allocation failed + * -EINVAL if property parsing failed + */ +int v4l2_async_notifier_parse_fwnode_sensor_common( + struct device *dev, struct v4l2_async_notifier *notifier); + +#endif /* _V4L2_FWNODE_H */ diff --git a/include/media/v4l2-ioctl.h b/include/media/v4l2-ioctl.h index 017ffb2220c7..68fbe47bf9af 100644 --- a/include/media/v4l2-ioctl.h +++ b/include/media/v4l2-ioctl.h @@ -38,6 +38,10 @@ struct v4l2_ioctl_ops { struct v4l2_fmtdesc *f); int (*vidioc_enum_fmt_sdr_out) (struct file *file, void *fh, struct v4l2_fmtdesc *f); + int (*vidioc_enum_fmt_meta_cap)(struct file *file, void *fh, + struct v4l2_fmtdesc *f); + int (*vidioc_enum_fmt_meta_out)(struct file *file, void *fh, + struct v4l2_fmtdesc *f); /* VIDIOC_G_FMT handlers */ int (*vidioc_g_fmt_vid_cap) (struct file *file, void *fh, @@ -64,6 +68,10 @@ struct v4l2_ioctl_ops { struct v4l2_format *f); int (*vidioc_g_fmt_sdr_out) (struct file *file, void *fh, struct v4l2_format *f); + int (*vidioc_g_fmt_meta_cap)(struct file *file, void *fh, + struct v4l2_format *f); + int (*vidioc_g_fmt_meta_out)(struct file *file, void *fh, + struct v4l2_format *f); /* VIDIOC_S_FMT handlers */ int (*vidioc_s_fmt_vid_cap) (struct file *file, void *fh, @@ -90,6 +98,10 @@ struct v4l2_ioctl_ops { struct v4l2_format *f); int (*vidioc_s_fmt_sdr_out) (struct file *file, void *fh, struct v4l2_format *f); + int (*vidioc_s_fmt_meta_cap)(struct file *file, void *fh, + struct v4l2_format *f); + int (*vidioc_s_fmt_meta_out)(struct file *file, void *fh, + struct v4l2_format *f); /* VIDIOC_TRY_FMT handlers */ int (*vidioc_try_fmt_vid_cap) (struct file *file, void *fh, @@ -116,6 +128,10 @@ struct v4l2_ioctl_ops { struct v4l2_format *f); int (*vidioc_try_fmt_sdr_out) (struct file *file, void *fh, struct v4l2_format *f); + int (*vidioc_try_fmt_meta_cap)(struct file *file, void *fh, + struct v4l2_format *f); + int (*vidioc_try_fmt_meta_out)(struct file *file, void *fh, + struct v4l2_format *f); /* Buffer handlers */ int (*vidioc_reqbufs) (struct file *file, void *fh, struct v4l2_requestbuffers *b); diff --git a/include/media/v4l2-subdev.h b/include/media/v4l2-subdev.h index b273cf9ac047..28318dd124c7 100644 --- a/include/media/v4l2-subdev.h +++ b/include/media/v4l2-subdev.h @@ -409,12 +409,30 @@ struct v4l2_subdev_video_ops { struct v4l2_subdev_frame_interval *interval); int (*s_frame_interval)(struct v4l2_subdev *sd, struct v4l2_subdev_frame_interval *interval); + + int (*enum_framesizes)(struct v4l2_subdev *sd, + struct v4l2_frmsizeenum *fsize); + int (*enum_frameintervals)(struct v4l2_subdev *sd, + struct v4l2_frmivalenum *fival); + int (*s_dv_timings)(struct v4l2_subdev *sd, struct v4l2_dv_timings *timings); int (*g_dv_timings)(struct v4l2_subdev *sd, struct v4l2_dv_timings *timings); int (*query_dv_timings)(struct v4l2_subdev *sd, struct v4l2_dv_timings *timings); + + int (*enum_mbus_fmt)(struct v4l2_subdev *sd, unsigned int index, + u32 *code); + int (*enum_mbus_fsizes)(struct v4l2_subdev *sd, + struct v4l2_frmsizeenum *fsize); + int (*g_mbus_fmt)(struct v4l2_subdev *sd, + struct v4l2_mbus_framefmt *fmt); + int (*try_mbus_fmt)(struct v4l2_subdev *sd, + struct v4l2_mbus_framefmt *fmt); + int (*s_mbus_fmt)(struct v4l2_subdev *sd, + struct v4l2_mbus_framefmt *fmt); + int (*g_mbus_config)(struct v4l2_subdev *sd, struct v4l2_mbus_config *cfg); int (*s_mbus_config)(struct v4l2_subdev *sd, @@ -724,8 +742,7 @@ struct v4l2_subdev { struct video_device *devnode; /* pointer to the physical device, if any */ struct device *dev; - /* The device_node of the subdev, usually the same as dev->of_node. */ - struct device_node *of_node; + struct fwnode_handle *fwnode; /* Links this subdev to a global subdev_list or @notifier->done list. */ struct list_head async_list; /* Pointer to respective struct v4l2_async_subdev. */ @@ -733,6 +750,9 @@ struct v4l2_subdev { /* Pointer to the managing notifier. */ struct v4l2_async_notifier *notifier; /* common part of subdevice platform data */ + struct v4l2_async_notifier *subdev_notifier; + /* A sub-device notifier implicitly registered for the sub-device + using v4l2_device_register_sensor_subdev(). */ struct v4l2_subdev_platform_data *pdata; }; diff --git a/include/media/videobuf2-core.h b/include/media/videobuf2-core.h index d4227a8a2a23..8c4e172b80ca 100644 --- a/include/media/videobuf2-core.h +++ b/include/media/videobuf2-core.h @@ -380,6 +380,9 @@ struct vb2_buf_ops { * @fileio_read_once: report EOF after reading the first buffer * @fileio_write_immediately: queue buffer after each write() call * @allow_zero_bytesused: allow bytesused == 0 to be passed to the driver + * @use_dma_bidirectional: use DMA_BIDIRECTIONAL for CAPTURE buffers; this + * allows HW to read from the CAPTURE buffers in + * addition to writing; ignored for OUTPUT queues * @lock: pointer to a mutex that protects the vb2_queue struct. The * driver can set this to a mutex to let the v4l2 core serialize * the queuing ioctls. If the driver wants to handle locking @@ -435,6 +438,7 @@ struct vb2_buf_ops { * when a buffer with the V4L2_BUF_FLAG_LAST is dequeued. * @fileio: file io emulator internal data, used only if emulator is active * @threadio: thread io internal data, used only if thread is active + * @dma_dir: DMA direction to use for buffers on this queue */ struct vb2_queue { unsigned int type; @@ -442,6 +446,7 @@ struct vb2_queue { unsigned fileio_read_once:1; unsigned fileio_write_immediately:1; unsigned allow_zero_bytesused:1; + unsigned use_dma_bidirectional:1; struct mutex *lock; void *owner; @@ -483,6 +488,7 @@ struct vb2_queue { struct vb2_fileio_data *fileio; struct vb2_threadio_data *threadio; + enum dma_data_direction dma_dir; #ifdef CONFIG_VIDEO_ADV_DEBUG /* diff --git a/include/media/videobuf2-dma-contig.h b/include/media/videobuf2-dma-contig.h index c33dfa69d7ab..2087c9a68be3 100644 --- a/include/media/videobuf2-dma-contig.h +++ b/include/media/videobuf2-dma-contig.h @@ -16,6 +16,8 @@ #include <media/videobuf2-v4l2.h> #include <linux/dma-mapping.h> +struct dma_attrs; + static inline dma_addr_t vb2_dma_contig_plane_dma_addr(struct vb2_buffer *vb, unsigned int plane_no) { @@ -24,7 +26,14 @@ vb2_dma_contig_plane_dma_addr(struct vb2_buffer *vb, unsigned int plane_no) return *addr; } -void *vb2_dma_contig_init_ctx(struct device *dev); +void *vb2_dma_contig_init_ctx_attrs(struct device *dev, + struct dma_attrs *attrs); + +static inline void *vb2_dma_contig_init_ctx(struct device *dev) +{ + return vb2_dma_contig_init_ctx_attrs(dev, NULL); +} + void vb2_dma_contig_cleanup_ctx(void *alloc_ctx); extern const struct vb2_mem_ops vb2_dma_contig_memops; diff --git a/include/media/videobuf2-v4l2.h b/include/media/videobuf2-v4l2.h index 5abab1e7c7e8..ec1aeabec426 100644 --- a/include/media/videobuf2-v4l2.h +++ b/include/media/videobuf2-v4l2.h @@ -31,6 +31,7 @@ * @timestamp: frame timestamp * @timecode: frame timecode * @sequence: sequence count of this frame + * @config_store: this buffer should use this configuration store * Should contain enough information to be able to cover all the fields * of struct v4l2_buffer at videodev2.h */ @@ -42,6 +43,7 @@ struct vb2_v4l2_buffer { struct timeval timestamp; struct v4l2_timecode timecode; __u32 sequence; + __u32 config_store; }; /* diff --git a/include/misc/rk_scr_api.h b/include/misc/rk_scr_api.h new file mode 100644 index 000000000000..535e83a9183c --- /dev/null +++ b/include/misc/rk_scr_api.h @@ -0,0 +1,33 @@ +/* + * Driver for Rockchip Smart Card Reader Controller + * + * Copyright (C) 2012-2016 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __RK_SCR_API_H__ +#define __RK_SCR_API_H__ + +int scr_open(void); +int scr_close(void); +int scr_check_card_insert(void); +int scr_reset(void); + +int scr_get_atr_data(unsigned char *atr_buf, unsigned char *atr_len); +ssize_t scr_write(unsigned char *buf, unsigned int write_cnt, + unsigned int *to_read_cnt); +ssize_t scr_read(unsigned char *buf, unsigned int to_read_cnt, + unsigned int *have_read_cnt); + +void scr_set_etu_duration(unsigned int F, unsigned int D); +void scr_set_work_waitingtime(unsigned char wi); + +#endif /* __RK_SCR_API_H__ */ diff --git a/include/net/inet_connection_sock.h b/include/net/inet_connection_sock.h index 49dcad4fe99e..72599bbc8255 100644 --- a/include/net/inet_connection_sock.h +++ b/include/net/inet_connection_sock.h @@ -289,11 +289,6 @@ static inline int inet_csk_reqsk_queue_len(const struct sock *sk) return reqsk_queue_len(&inet_csk(sk)->icsk_accept_queue); } -static inline int inet_csk_reqsk_queue_young(const struct sock *sk) -{ - return reqsk_queue_len_young(&inet_csk(sk)->icsk_accept_queue); -} - static inline int inet_csk_reqsk_queue_is_full(const struct sock *sk) { return inet_csk_reqsk_queue_len(sk) >= sk->sk_max_ack_backlog; diff --git a/include/soc/rockchip/android-version.h b/include/soc/rockchip/android-version.h new file mode 100644 index 000000000000..e0d865bab335 --- /dev/null +++ b/include/soc/rockchip/android-version.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2017 Rockchip Electronics Co. Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef ANDROID_VERSION +#define ANDROID_VERSION(a, b, c, r) \ + (((a) << 24) + ((b) << 16) + ((c) << 8) + (r)) +#endif diff --git a/include/soc/rockchip/pm_domains.h b/include/soc/rockchip/pm_domains.h new file mode 100644 index 000000000000..b566cb8a5ef2 --- /dev/null +++ b/include/soc/rockchip/pm_domains.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __SOC_ROCKCHIP_PM_DOMAINS_H +#define __SOC_ROCKCHIP_PM_DOMAINS_H + +#include <linux/errno.h> + +struct device; + +#ifdef CONFIG_ROCKCHIP_PM_DOMAINS +int rockchip_pmu_idle_request(struct device *dev, bool idle); +int rockchip_save_qos(struct device *dev); +int rockchip_restore_qos(struct device *dev); +void rockchip_dump_pmu(void); +#else +static inline int rockchip_pmu_idle_request(struct device *dev, bool idle) +{ + return -ENOTSUPP; +} + +static inline int rockchip_save_qos(struct device *dev) +{ + return -ENOTSUPP; +} + +static inline int rockchip_restore_qos(struct device *dev) +{ + return -ENOTSUPP; +} + +static inline void rockchip_dump_pmu(void) +{ +} +#endif + +#endif diff --git a/include/soc/rockchip/rk3368-mailbox.h b/include/soc/rockchip/rk3368-mailbox.h new file mode 100644 index 000000000000..77208277f419 --- /dev/null +++ b/include/soc/rockchip/rk3368-mailbox.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __RK3368_MAILBOX_H__ +#define __RK3368_MAILBOX_H__ + +struct rk3368_mbox_msg { + u32 cmd; + int tx_size; + void *tx_buf; + int rx_size; + void *rx_buf; + void *cl_data; +}; + +#endif /* __RK3368_MAILBOX_H__ */ diff --git a/include/soc/rockchip/rkfb_dmc.h b/include/soc/rockchip/rkfb_dmc.h new file mode 100644 index 000000000000..5e82b3194dd3 --- /dev/null +++ b/include/soc/rockchip/rkfb_dmc.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Rockchip devfb driver will probe earlier than devfreq, so it needs to register + * dmc_notify after than rk3399 dmc driver. +*/ + +#if defined(CONFIG_LCDC_RK322X) +int vop_register_dmc(void); +#else +static inline int vop_register_dmc(void) { return 0;}; +#endif diff --git a/include/soc/rockchip/rockchip-system-status.h b/include/soc/rockchip/rockchip-system-status.h new file mode 100644 index 000000000000..ebcc65d040cf --- /dev/null +++ b/include/soc/rockchip/rockchip-system-status.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef __SOC_ROCKCHIP_SYSTEM_STATUS_H +#define __SOC_ROCKCHIP_SYSTEM_STATUS_H + +int rockchip_register_system_status_notifier(struct notifier_block *nb); +int rockchip_unregister_system_status_notifier(struct notifier_block *nb); +void rockchip_set_system_status(unsigned long status); +void rockchip_clear_system_status(unsigned long status); +unsigned long rockchip_get_system_status(void); + +#endif diff --git a/include/soc/rockchip/rockchip_dmc.h b/include/soc/rockchip/rockchip_dmc.h new file mode 100644 index 000000000000..aaa8cbeed94e --- /dev/null +++ b/include/soc/rockchip/rockchip_dmc.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef __SOC_ROCKCHIP_DMC_H +#define __SOC_ROCKCHIP_DMC_H + +#include <linux/devfreq.h> + +#ifdef CONFIG_ARM_ROCKCHIP_DMC_DEVFREQ +void rockchip_dmcfreq_lock(void); +void rockchip_dmcfreq_unlock(void); +int rockchip_dmcfreq_wait_complete(void); +int rockchip_dmcfreq_vop_bandwidth_request(struct devfreq *devfreq, + unsigned int bw_mbyte); +void rockchip_dmcfreq_vop_bandwidth_update(struct devfreq *devfreq, + unsigned int bw_mbyte); + +#else +static inline void rockchip_dmcfreq_lock(void) +{ +} + +static inline void rockchip_dmcfreq_unlock(void) +{ +} + +static inline int rockchip_dmcfreq_wait_complete(void) +{ + return 0; +} + +static inline int +rockchip_dmcfreq_vop_bandwidth_request(struct devfreq *devfreq, + unsigned int bw_mbyte) +{ + return 0; +} + +static inline void +rockchip_dmcfreq_vop_bandwidth_update(struct devfreq *devfreq, + unsigned int bw_mbyte) +{ +} +#endif + +#endif diff --git a/include/soc/rockchip/rockchip_ipa.h b/include/soc/rockchip/rockchip_ipa.h new file mode 100644 index 000000000000..2485abb70f05 --- /dev/null +++ b/include/soc/rockchip/rockchip_ipa.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ +#ifndef __SOC_ROCKCHIP_IPA_H +#define __SOC_ROCKCHIP_IPA_H + +struct ipa_power_model_data { + u32 static_coefficient; + u32 dynamic_coefficient; + s32 ts[4]; + struct thermal_zone_device *tz; +}; + +#ifdef CONFIG_ROCKCHIP_IPA +int rockchip_ipa_power_model_init(struct device *dev, + struct ipa_power_model_data **data); +unsigned long +rockchip_ipa_get_static_power(struct ipa_power_model_data *model_data, + unsigned long voltage); +#else +static inline int +rockchip_ipa_power_model_init(struct device *dev, + struct ipa_power_model_data **data) +{ + return -ENOTSUPP; +}; + +static inline unsigned long +rockchip_ipa_get_static_power(struct ipa_power_model_data *data, + unsigned long voltage) +{ + return 0; +} +#endif /* CONFIG_ROCKCHIP_IPA */ + +#endif diff --git a/include/soc/rockchip/rockchip_opp_select.h b/include/soc/rockchip/rockchip_opp_select.h new file mode 100644 index 000000000000..1324feebbf39 --- /dev/null +++ b/include/soc/rockchip/rockchip_opp_select.h @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __SOC_ROCKCHIP_OPP_SELECT_H +#define __SOC_ROCKCHIP_OPP_SELECT_H + +struct thermal_opp_info; + +enum thermal_opp_type { + THERMAL_OPP_TPYE_CPU = 0, + THERMAL_OPP_TPYE_DEV, +}; + +struct thermal_opp_device_data { + enum thermal_opp_type type; + void *data; + int (*low_temp_adjust)(struct thermal_opp_info *info, bool is_low); + int (*high_temp_adjust)(struct thermal_opp_info *info, bool is_low); +}; + +struct thermal_opp_table { + unsigned long rate; + unsigned long volt; + unsigned long low_temp_volt; +}; + +struct thermal_opp_info { + struct device *dev; + struct thermal_zone_device *tz; + struct notifier_block thermal_nb; + struct sel_table *low_temp_table; + struct thermal_opp_table *opp_table; + struct thermal_opp_device_data *dev_data; + unsigned int num_opps; + unsigned long low_limit; + unsigned long high_limit; + int low_temp; + int high_temp; + int temp_hysteresis; + int max_volt; + int low_temp_min_volt; + int high_temp_max_volt; + bool is_low_temp; + bool is_high_temp; +}; + +#ifdef CONFIG_ROCKCHIP_OPP +void rockchip_of_get_lkg_sel(struct device *dev, struct device_node *np, + char *lkg_name, int process, + int *volt_sel, int *scale_sel); +void rockchip_of_get_pvtm_sel(struct device *dev, struct device_node *np, + char *reg_name, int process, + int *volt_sel, int *scale_sel); +void rockchip_of_get_bin_sel(struct device *dev, struct device_node *np, + int bin, int *scale_sel); +int rockchip_get_efuse_value(struct device_node *np, char *porp_name, + int *value); +void rockchip_get_soc_info(struct device *dev, + const struct of_device_id *matches, + int *bin, int *process); +void rockchip_get_scale_volt_sel(struct device *dev, char *lkg_name, + char *reg_name, int bin, int process, + int *scale, int *volt_sel); +int rockchip_set_opp_info(struct device *dev, int process, int volt_sel); +int rockchip_adjust_power_scale(struct device *dev, int scale); +int rockchip_init_opp_table(struct device *dev, + const struct of_device_id *matches, + char *lkg_name, char *reg_name); +struct thermal_opp_info * +rockchip_register_thermal_notifier(struct device *dev, + struct thermal_opp_device_data *data); +void rockchip_unregister_thermal_notifier(struct thermal_opp_info *info); +int rockchip_cpu_low_temp_adjust(struct thermal_opp_info *info, + bool is_low); +int rockchip_cpu_high_temp_adjust(struct thermal_opp_info *info, + bool is_high); +int rockchip_dev_low_temp_adjust(struct thermal_opp_info *info, + bool is_low); +int rockchip_dev_high_temp_adjust(struct thermal_opp_info *info, + bool is_high); +#else +static inline void rockchip_of_get_lkg_sel(struct device *dev, + struct device_node *np, + char *lkg_name, int process, + int *volt_sel, int *scale_sel) +{ +} + +static inline void rockchip_of_get_pvtm_sel(struct device *dev, + struct device_node *np, + char *reg_name, int process, + int *volt_sel, int *scale_sel) +{ +} + +static inline void rockchip_of_get_bin_sel(struct device *dev, + struct device_node *np, int bin, + int *scale_sel) +{ +} + +static inline int rockchip_get_efuse_value(struct device_node *np, + char *porp_name, int *value) +{ + return -ENOTSUPP; +} + +static inline void rockchip_get_soc_info(struct device *dev, + const struct of_device_id *matches, + int *bin, int *process) +{ +} + +static inline void rockchip_get_scale_volt_sel(struct device *dev, + char *lkg_name, char *reg_name, + int bin, int process, int *scale, + int *volt_sel) +{ +} + +static inline int rockchip_set_opp_info(struct device *dev, int process, + int volt_sel) +{ + return -ENOTSUPP; +} + +static inline int rockchip_adjust_power_scale(struct device *dev, int scale) +{ + return -ENOTSUPP; +} + +static inline int rockchip_init_opp_table(struct device *dev, + const struct of_device_id *matches, + char *lkg_name, char *reg_name) +{ + return -ENOTSUPP; +} + +static inline struct thermal_opp_info * +rockchip_register_thermal_notifier(struct device *dev, + struct thermal_opp_device_data *data) +{ + return ERR_PTR(-ENOTSUPP); +} + +static inline void +rockchip_unregister_thermal_notifier(struct thermal_opp_info *info) +{ +} + +static inline int rockchip_cpu_low_temp_adjust(struct thermal_opp_info *info, + bool is_low) +{ + return -ENOTSUPP; +} + +static inline int rockchip_cpu_high_temp_adjust(struct thermal_opp_info *info, + bool is_high) +{ + return -ENOTSUPP; +} + +static inline int rockchip_dev_low_temp_adjust(struct thermal_opp_info *info, + bool is_low) +{ + return -ENOTSUPP; +} + +static inline int rockchip_dev_high_temp_adjust(struct thermal_opp_info *info, + bool is_high) +{ + return -ENOTSUPP; +} +#endif /* CONFIG_ROCKCHIP_OPP */ + +#endif diff --git a/include/soc/rockchip/rockchip_phy_typec.h b/include/soc/rockchip/rockchip_phy_typec.h new file mode 100644 index 000000000000..7f0d022d2d34 --- /dev/null +++ b/include/soc/rockchip/rockchip_phy_typec.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd + * Author: Lin Huang <hl@rock-chips.com> + */ + +#ifndef __SOC_ROCKCHIP_PHY_TYPEC_H +#define __SOC_ROCKCHIP_PHY_TYPEC_H + +struct usb3phy_reg { + u32 offset; + u32 enable_bit; + u32 write_enable; +}; + +struct rockchip_usb3phy_port_cfg { + struct usb3phy_reg typec_conn_dir; + struct usb3phy_reg usb3tousb2_en; + struct usb3phy_reg usb3host_disable; + struct usb3phy_reg usb3host_port; + struct usb3phy_reg external_psm; + struct usb3phy_reg pipe_status; + struct usb3phy_reg uphy_dp_sel; +}; + +struct phy_config { + int swing; + int pe; +}; + +struct rockchip_typec_phy { + struct device *dev; + void __iomem *base; + struct extcon_dev *extcon; + struct regmap *grf_regs; + struct clk *clk_core; + struct clk *clk_ref; + struct reset_control *uphy_rst; + struct reset_control *pipe_rst; + struct reset_control *tcphy_rst; + struct rockchip_usb3phy_port_cfg port_cfgs; + /* mutex to protect access to individual PHYs */ + struct mutex lock; + + bool flip; + u8 mode; + struct phy_config config[3][4]; + struct { + int link_rate; + u8 lane_count; + } dp; + int (*typec_phy_config)(struct phy *phy, int link_rate, + int lanes, u8 swing, u8 pre_emp); +}; + +#endif diff --git a/include/soc/rockchip/rockchip_sip.h b/include/soc/rockchip/rockchip_sip.h new file mode 100644 index 000000000000..bca3ffb31655 --- /dev/null +++ b/include/soc/rockchip/rockchip_sip.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd + * Author: Lin Huang <hl@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef __SOC_ROCKCHIP_SIP_H +#define __SOC_ROCKCHIP_SIP_H + +#define ROCKCHIP_SIP_DRAM_FREQ 0x82000008 +#define ROCKCHIP_SIP_CONFIG_DRAM_INIT 0x00 +#define ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE 0x01 +#define ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE 0x02 +#define ROCKCHIP_SIP_CONFIG_DRAM_SET_AT_SR 0x03 +#define ROCKCHIP_SIP_CONFIG_DRAM_GET_BW 0x04 +#define ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE 0x05 +#define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 0x06 +#define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07 +#define ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION 0x08 +#define ROCKCHIP_SIP_CONFIG_DRAM_POST_SET_RATE 0x09 + +#endif diff --git a/include/soc/rockchip/scpi.h b/include/soc/rockchip/scpi.h new file mode 100644 index 000000000000..ad1a4e51a4dd --- /dev/null +++ b/include/soc/rockchip/scpi.h @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SOC_ROCKCHIP_SCPI_H +#define __SOC_ROCKCHIP_SCPI_H + +#ifdef CONFIG_RK3368_SCPI_PROTOCOL +struct scpi_opp_entry { + u32 freq_hz; + u32 volt_mv; +} __packed; + +struct scpi_opp { + struct scpi_opp_entry *opp; + u32 latency; /* in usecs */ + int count; +} __packed; + +unsigned long scpi_clk_get_val(u16 clk_id); +int scpi_clk_set_val(u16 clk_id, unsigned long rate); +int scpi_dvfs_get_idx(u8 domain); +int scpi_dvfs_set_idx(u8 domain, u8 idx); +struct scpi_opp *scpi_dvfs_get_opps(u8 domain); +int scpi_get_sensor(char *name); +int scpi_get_sensor_value(u16 sensor, u32 *val); +int scpi_sys_set_jtagmux_on_off(u32 en); +int scpi_sys_set_mcu_state_suspend(void); +int scpi_sys_set_mcu_state_resume(void); + +int scpi_ddr_dclk_mode(u32 dclk_mode); +int scpi_ddr_init(u32 dram_speed_bin, u32 freq, u32 lcdc_type, + u32 addr_mcu_el3); +int scpi_ddr_set_clk_rate(u32 rate, u32 lcdc_type); +int scpi_ddr_send_timing(u32 *p, u32 size); +int scpi_ddr_round_rate(u32 m_hz); +int scpi_ddr_set_auto_self_refresh(u32 en); +int scpi_ddr_get_clk_rate(void); +int scpi_thermal_get_temperature(void); +int scpi_thermal_set_clk_cycle(u32 cycle); +#else +static inline unsigned long scpi_clk_get_val(u16 clk_id) +{ + return -EPERM; +} + +static inline int scpi_clk_set_val(u16 clk_id, unsigned long rate) +{ + return -EPERM; +} + +static inline int scpi_dvfs_get_idx(u8 domain) +{ + return -EPERM; +} + +static inline int scpi_dvfs_set_idx(u8 domain, u8 idx) +{ + return -EPERM; +} + +static inline struct scpi_opp *scpi_dvfs_get_opps(u8 domain) +{ + return ERR_PTR(-EPERM); +} + +static inline int scpi_get_sensor(char *name) +{ + return -EPERM; +} + +static inline int scpi_get_sensor_value(u16 sensor, u32 *val) +{ + return -EPERM; +} + +static inline int scpi_sys_set_jtagmux_on_off(u32 en) +{ + return -EPERM; +} + +static inline int scpi_sys_set_mcu_state_suspend(void) +{ + return -EPERM; +} + +static inline int scpi_sys_set_mcu_state_resume(void) +{ + return -EPERM; +} + +static inline int scpi_ddr_dclk_mode(u32 dclk_mode) +{ + return -EPERM; +} + +static inline int scpi_ddr_init(u32 dram_speed_bin, u32 freq, u32 lcdc_type, + u32 addr_mcu_el3) +{ + return -EPERM; +} + +static inline int scpi_ddr_set_clk_rate(u32 rate, u32 lcdc_type) +{ + return -EPERM; +} + +static inline int scpi_ddr_send_timing(u32 *p, u32 size) +{ + return -EPERM; +} + +static inline int scpi_ddr_round_rate(u32 m_hz) +{ + return -EPERM; +} + +static inline int scpi_ddr_set_auto_self_refresh(u32 en) +{ + return -EPERM; +} + +static inline int scpi_ddr_get_clk_rate(void) +{ + return -EPERM; +} + +static inline int scpi_thermal_get_temperature(void) +{ + return -EPERM; +} + +static inline int scpi_thermal_set_clk_cycle(u32 cycle) +{ + return -EPERM; +} +#endif +#endif diff --git a/include/sound/da7219.h b/include/sound/da7219.h index 3f39e135312d..02876acdc840 100644 --- a/include/sound/da7219.h +++ b/include/sound/da7219.h @@ -14,17 +14,10 @@ #ifndef __DA7219_PDATA_H #define __DA7219_PDATA_H -/* LDO */ -enum da7219_ldo_lvl_sel { - DA7219_LDO_LVL_SEL_1_05V = 0, - DA7219_LDO_LVL_SEL_1_10V, - DA7219_LDO_LVL_SEL_1_20V, - DA7219_LDO_LVL_SEL_1_40V, -}; - /* Mic Bias */ enum da7219_micbias_voltage { - DA7219_MICBIAS_1_8V = 1, + DA7219_MICBIAS_1_6V = 0, + DA7219_MICBIAS_1_8V, DA7219_MICBIAS_2_0V, DA7219_MICBIAS_2_2V, DA7219_MICBIAS_2_4V, @@ -41,9 +34,6 @@ enum da7219_mic_amp_in_sel { struct da7219_aad_pdata; struct da7219_pdata { - /* Internal LDO */ - enum da7219_ldo_lvl_sel ldo_lvl_sel; - /* Mic */ enum da7219_micbias_voltage micbias_lvl; enum da7219_mic_amp_in_sel mic_amp_in_sel; diff --git a/include/sound/hdmi-codec.h b/include/sound/hdmi-codec.h new file mode 100644 index 000000000000..fd0ff40679a3 --- /dev/null +++ b/include/sound/hdmi-codec.h @@ -0,0 +1,116 @@ +/* + * hdmi-codec.h - HDMI Codec driver API + * + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com + * + * Author: Jyri Sarha <jsarha@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#ifndef __HDMI_CODEC_H__ +#define __HDMI_CODEC_H__ + +#include <linux/hdmi.h> +#include <drm/drm_edid.h> +#include <sound/asoundef.h> +#include <uapi/sound/asound.h> + +/* + * Protocol between ASoC cpu-dai and HDMI-encoder + */ +struct hdmi_codec_daifmt { + enum { + HDMI_I2S, + HDMI_RIGHT_J, + HDMI_LEFT_J, + HDMI_DSP_A, + HDMI_DSP_B, + HDMI_AC97, + HDMI_SPDIF, + } fmt; + int bit_clk_inv:1; + int frame_clk_inv:1; + int bit_clk_master:1; + int frame_clk_master:1; +}; + +/* + * HDMI audio parameters + */ +struct hdmi_codec_params { + struct hdmi_audio_infoframe cea; + struct snd_aes_iec958 iec; + int sample_rate; + int sample_width; + int channels; + int mode; +}; + +enum { + LPCM = 0, + NLPCM, + HBR, +}; + +struct hdmi_codec_pdata; +struct hdmi_codec_ops { + /* + * Called when ASoC starts an audio stream setup. + * Optional + */ + int (*audio_startup)(struct device *dev, void *data); + + /* + * Configures HDMI-encoder for audio stream. + * Mandatory + */ + int (*hw_params)(struct device *dev, void *data, + struct hdmi_codec_daifmt *fmt, + struct hdmi_codec_params *hparms); + + /* + * Shuts down the audio stream. + * Mandatory + */ + void (*audio_shutdown)(struct device *dev, void *data); + + /* + * Mute/unmute HDMI audio stream. + * Optional + */ + int (*digital_mute)(struct device *dev, void *data, bool enable); + + /* + * Provides EDID-Like-Data from connected HDMI device. + * Optional + */ + int (*get_eld)(struct device *dev, void *data, + uint8_t *buf, size_t len); +}; + +/* HDMI codec initalization data */ +struct hdmi_codec_pdata { + const struct hdmi_codec_ops *ops; + uint i2s:1; + uint spdif:1; + int max_i2s_channels; + void *data; +}; + +struct snd_soc_codec; +struct snd_soc_jack; + +int hdmi_codec_set_jack_detect(struct snd_soc_codec *codec, + struct snd_soc_jack *jack); + +#define HDMI_CODEC_DRV_NAME "hdmi-audio-codec" + +#endif /* __HDMI_CODEC_H__ */ diff --git a/include/sound/pcm.h b/include/sound/pcm.h index b0be09279943..700811929a2b 100644 --- a/include/sound/pcm.h +++ b/include/sound/pcm.h @@ -1399,6 +1399,37 @@ static inline u64 pcm_format_to_bits(snd_pcm_format_t pcm_format) return 1ULL << (__force int) pcm_format; } +#ifdef CONFIG_SND_SOC_ROCKCHIP_VAD +snd_pcm_sframes_t snd_pcm_vad_read(struct snd_pcm_substream *substream, + void __user *buf, snd_pcm_uframes_t frames); +/** + * snd_pcm_vad_avail - Get the available (readable) space for vad + * @runtime: PCM substream instance + * + * Result is between 0 ... (boundary - 1) + */ +snd_pcm_uframes_t snd_pcm_vad_avail(struct snd_pcm_substream *substream); +/** + * snd_pcm_vad_attached - Check whether vad is attached to substream or not + * @substream: PCM substream instance + * + * Result is true for attached or false for detached + */ +bool snd_pcm_vad_attached(struct snd_pcm_substream *substream); +int snd_pcm_vad_preprocess(struct snd_pcm_substream *substream, + void *buf, snd_pcm_uframes_t size); +/** + * snd_pcm_vad_memcpy - Copy vad data to dst + * @substream: PCM substream instance + * @buf: dst buf + * @frames: size in frame + * + * Result is copied frames for success or errno for fail + */ +snd_pcm_sframes_t snd_pcm_vad_memcpy(struct snd_pcm_substream *substream, + void *buf, snd_pcm_uframes_t frames); +#endif + /* printk helpers */ #define pcm_err(pcm, fmt, args...) \ dev_err((pcm)->card->dev, fmt, ##args) diff --git a/include/sound/pcm_iec958.h b/include/sound/pcm_iec958.h index 0eed397aca8e..36f023acb201 100644 --- a/include/sound/pcm_iec958.h +++ b/include/sound/pcm_iec958.h @@ -6,4 +6,6 @@ int snd_pcm_create_iec958_consumer(struct snd_pcm_runtime *runtime, u8 *cs, size_t len); +int snd_pcm_create_iec958_consumer_hw_params(struct snd_pcm_hw_params *params, + u8 *cs, size_t len); #endif diff --git a/include/sound/simple_card.h b/include/sound/simple_card.h index 0399352f3a62..69c66991eb1e 100644 --- a/include/sound/simple_card.h +++ b/include/sound/simple_card.h @@ -35,4 +35,6 @@ struct asoc_simple_card_info { struct asoc_simple_dai codec_dai; }; +struct snd_soc_jack *asoc_simple_card_get_hp_jack(void); + #endif /* __SIMPLE_CARD_H */ diff --git a/include/sound/soc.h b/include/sound/soc.h index fb955e69a78e..2f9176a1693e 100644 --- a/include/sound/soc.h +++ b/include/sound/soc.h @@ -1638,12 +1638,17 @@ unsigned int snd_soc_of_parse_daifmt(struct device_node *np, const char *prefix, struct device_node **bitclkmaster, struct device_node **framemaster); +int snd_soc_get_dai_name(struct of_phandle_args *args, + const char **dai_name); int snd_soc_of_get_dai_name(struct device_node *of_node, const char **dai_name); int snd_soc_of_get_dai_link_codecs(struct device *dev, struct device_node *of_node, struct snd_soc_dai_link *dai_link); +struct snd_soc_dai *snd_soc_find_dai( + const struct snd_soc_dai_link_component *dlc); + #include <sound/soc-dai.h> #ifdef CONFIG_DEBUG_FS diff --git a/include/trace/events/sync.h b/include/trace/events/sync.h new file mode 100644 index 000000000000..a1c58d1c25e9 --- /dev/null +++ b/include/trace/events/sync.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#undef TRACE_SYSTEM +#define TRACE_SYSTEM sync + +#if !defined(_TRACE_SYNC_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_SYNC_H + +#include <linux/sync.h> +#include <linux/tracepoint.h> + +TRACE_EVENT(sync_timeline, + TP_PROTO(struct sync_timeline *timeline), + + TP_ARGS(timeline), + + TP_STRUCT__entry( + __string(name, timeline->name) + __array(char, value, 32) + ), + + TP_fast_assign( + __assign_str(name, timeline->name); + if (timeline->ops->timeline_value_str) { + timeline->ops->timeline_value_str(timeline, + __entry->value, + sizeof(__entry->value)); + } else { + __entry->value[0] = '\0'; + } + ), + + TP_printk("name=%s value=%s", __get_str(name), __entry->value) +); + +TRACE_EVENT(sync_wait, + TP_PROTO(struct sync_fence *fence, int begin), + + TP_ARGS(fence, begin), + + TP_STRUCT__entry( + __string(name, fence->name) + __field(s32, status) + __field(u32, begin) + ), + + TP_fast_assign( + __assign_str(name, fence->name); + __entry->status = fence->status; + __entry->begin = begin; + ), + + TP_printk("%s name=%s state=%d", __entry->begin ? "begin" : "end", + __get_str(name), __entry->status) +); + +TRACE_EVENT(sync_pt, + TP_PROTO(struct sync_pt *pt), + + TP_ARGS(pt), + + TP_STRUCT__entry( + __string(timeline, pt->parent->name) + __array(char, value, 32) + ), + + TP_fast_assign( + __assign_str(timeline, pt->parent->name); + if (pt->parent->ops->pt_value_str) { + pt->parent->ops->pt_value_str(pt, + __entry->value, + sizeof(__entry->value)); + } else { + __entry->value[0] = '\0'; + } + ), + + TP_printk("name=%s value=%s", __get_str(timeline), __entry->value) + ); + +#endif /* if !defined(_TRACE_SYNC_H) || defined(TRACE_HEADER_MULTI_READ) */ + +/* This part must be outside protection */ +#include <trace/define_trace.h> diff --git a/include/trace/events/v4l2.h b/include/trace/events/v4l2.h index 22afa26e34b2..b3e3bfc297e2 100644 --- a/include/trace/events/v4l2.h +++ b/include/trace/events/v4l2.h @@ -29,6 +29,7 @@ EM( V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, "VIDEO_OUTPUT_MPLANE" ) \ EM( V4L2_BUF_TYPE_SDR_CAPTURE, "SDR_CAPTURE" ) \ EM( V4L2_BUF_TYPE_SDR_OUTPUT, "SDR_OUTPUT" ) \ + EM( V4L2_BUF_TYPE_META_CAPTURE, "META_CAPTURE" ) \ EMe(V4L2_BUF_TYPE_PRIVATE, "PRIVATE" ) SHOW_TYPE diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h index 3801584a0c53..5149380a76e5 100644 --- a/include/uapi/drm/drm.h +++ b/include/uapi/drm/drm.h @@ -631,6 +631,7 @@ struct drm_gem_open { #define DRM_CAP_CURSOR_WIDTH 0x8 #define DRM_CAP_CURSOR_HEIGHT 0x9 #define DRM_CAP_ADDFB2_MODIFIERS 0x10 +#define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12 /** DRM_IOCTL_GET_CAP ioctl argument type */ struct drm_get_cap { @@ -662,12 +663,20 @@ struct drm_get_cap { */ #define DRM_CLIENT_CAP_ATOMIC 3 +/** + * DRM_CLIENT_CAP_SHARE_PLANES + * + * If set to 1, the DRM core will expose share planes to userspace. + */ +#define DRM_CLIENT_CAP_SHARE_PLANES 4 + /** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ struct drm_set_client_cap { __u64 capability; __u64 value; }; +#define DRM_RDWR O_RDWR #define DRM_CLOEXEC O_CLOEXEC struct drm_prime_handle { __u32 handle; @@ -826,7 +835,7 @@ struct drm_event_vblank { __u32 tv_sec; __u32 tv_usec; __u32 sequence; - __u32 reserved; + __u32 crtc_id; /* 0 on older kernels that do not support this */ }; /* typedef area */ diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index f28f79966e9e..6bd694d9a66f 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -116,6 +116,13 @@ #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ +#define DRM_FORMAT_NV12_10 fourcc_code('N', 'A', '1', '2') /* 2x2 subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV21_10 fourcc_code('N', 'A', '2', '1') /* 2x2 subsampled Cb:Cr plane */ +#define DRM_FORMAT_NV16_10 fourcc_code('N', 'A', '1', '6') /* 2x1 subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV61_10 fourcc_code('N', 'A', '6', '1') /* 2x1 subsampled Cb:Cr plane */ +#define DRM_FORMAT_NV24_10 fourcc_code('N', 'A', '2', '4') /* non-subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV42_10 fourcc_code('N', 'A', '4', '2') /* non-subsampled Cb:Cr plane */ + /* * 3 plane YCbCr * index 0: Y plane, [7:0] Y @@ -156,6 +163,7 @@ #define DRM_FORMAT_MOD_VENDOR_NV 0x03 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 +#define DRM_FORMAT_MOD_VENDOR_ARM 0x06 /* add more to the end as needed */ #define fourcc_mod_code(vendor, val) \ @@ -230,4 +238,10 @@ */ #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) +/* + * FIXME: AFBC is arm vendor format, it's a compressed format. + * + */ +#define DRM_FORMAT_MOD_ARM_AFBC fourcc_mod_code(ARM, 1) + #endif /* DRM_FOURCC_H */ diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index 6c11ca401de8..fd3126a04b57 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -73,7 +73,21 @@ #define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14) #define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14) - +/* Picture aspect ratio options */ +#define DRM_MODE_PICTURE_ASPECT_NONE 0 +#define DRM_MODE_PICTURE_ASPECT_4_3 1 +#define DRM_MODE_PICTURE_ASPECT_16_9 2 + +/* Aspect ratio flag bitmask (4 bits 22:19) */ +#define DRM_MODE_FLAG_PIC_AR_MASK (0x0F<<19) +#define DRM_MODE_FLAG_PIC_AR_NONE \ + (DRM_MODE_PICTURE_ASPECT_NONE<<19) +#define DRM_MODE_FLAG_PIC_AR_4_3 \ + (DRM_MODE_PICTURE_ASPECT_4_3<<19) +#define DRM_MODE_FLAG_PIC_AR_16_9 \ + (DRM_MODE_PICTURE_ASPECT_16_9<<19) + +#define DRM_MODE_FLAG_PPIXDATA (1<<31) /* DPMS flags */ /* bit compatible with the xorg definitions. */ #define DRM_MODE_DPMS_ON 0 @@ -81,6 +95,11 @@ #define DRM_MODE_DPMS_SUSPEND 2 #define DRM_MODE_DPMS_OFF 3 +/* Content Protection Flags */ +#define DRM_MODE_CONTENT_PROTECTION_UNDESIRED 0 +#define DRM_MODE_CONTENT_PROTECTION_DESIRED 1 +#define DRM_MODE_CONTENT_PROTECTION_ENABLED 2 + /* Scaling mode options */ #define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or software can still scale) */ @@ -88,11 +107,6 @@ #define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */ #define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */ -/* Picture aspect ratio options */ -#define DRM_MODE_PICTURE_ASPECT_NONE 0 -#define DRM_MODE_PICTURE_ASPECT_4_3 1 -#define DRM_MODE_PICTURE_ASPECT_16_9 2 - /* Dithering mode options */ #define DRM_MODE_DITHERING_OFF 0 #define DRM_MODE_DITHERING_ON 1 @@ -103,6 +117,11 @@ #define DRM_MODE_DIRTY_ON 1 #define DRM_MODE_DIRTY_ANNOTATE 2 +/* Content Protection Flags */ +#define DRM_MODE_CONTENT_PROTECTION_UNDESIRED 0 +#define DRM_MODE_CONTENT_PROTECTION_DESIRED 1 +#define DRM_MODE_CONTENT_PROTECTION_ENABLED 2 + struct drm_mode_modeinfo { __u32 clock; __u16 hdisplay; @@ -202,6 +221,7 @@ struct drm_mode_get_plane_res { #define DRM_MODE_ENCODER_VIRTUAL 5 #define DRM_MODE_ENCODER_DSI 6 #define DRM_MODE_ENCODER_DPMST 7 +#define DRM_MODE_ENCODER_DPI 8 struct drm_mode_get_encoder { __u32 encoder_id; @@ -215,14 +235,16 @@ struct drm_mode_get_encoder { /* This is for connectors with multiple signal types. */ /* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */ -#define DRM_MODE_SUBCONNECTOR_Automatic 0 -#define DRM_MODE_SUBCONNECTOR_Unknown 0 -#define DRM_MODE_SUBCONNECTOR_DVID 3 -#define DRM_MODE_SUBCONNECTOR_DVIA 4 -#define DRM_MODE_SUBCONNECTOR_Composite 5 -#define DRM_MODE_SUBCONNECTOR_SVIDEO 6 -#define DRM_MODE_SUBCONNECTOR_Component 8 -#define DRM_MODE_SUBCONNECTOR_SCART 9 +enum drm_mode_subconnector { + DRM_MODE_SUBCONNECTOR_Automatic = 0, + DRM_MODE_SUBCONNECTOR_Unknown = 0, + DRM_MODE_SUBCONNECTOR_DVID = 3, + DRM_MODE_SUBCONNECTOR_DVIA = 4, + DRM_MODE_SUBCONNECTOR_Composite = 5, + DRM_MODE_SUBCONNECTOR_SVIDEO = 6, + DRM_MODE_SUBCONNECTOR_Component = 8, + DRM_MODE_SUBCONNECTOR_SCART = 9, +}; #define DRM_MODE_CONNECTOR_Unknown 0 #define DRM_MODE_CONNECTOR_VGA 1 @@ -241,6 +263,7 @@ struct drm_mode_get_encoder { #define DRM_MODE_CONNECTOR_eDP 14 #define DRM_MODE_CONNECTOR_VIRTUAL 15 #define DRM_MODE_CONNECTOR_DSI 16 +#define DRM_MODE_CONNECTOR_DPI 17 struct drm_mode_get_connector { @@ -487,6 +510,44 @@ struct drm_mode_crtc_lut { __u64 blue; }; +struct drm_color_ctm { + /* Conversion matrix in S31.32 format. */ + __s64 matrix[9]; +}; + +struct drm_color_lut { + /* + * Data is U0.16 fixed point format. + */ + __u16 red; + __u16 green; + __u16 blue; + __u16 reserved; +}; + +enum supported_eotf_type { + TRADITIONAL_GAMMA_SDR = 0, + TRADITIONAL_GAMMA_HDR, + SMPTE_ST2084, + HLG, + FUTURE_EOTF +}; + +/* HDR Metadata */ +struct hdr_static_metadata { + uint16_t eotf; + uint16_t type; + uint16_t display_primaries_x[3]; + uint16_t display_primaries_y[3]; + uint16_t white_point_x; + uint16_t white_point_y; + uint16_t max_mastering_display_luminance; + uint16_t min_mastering_display_luminance; + uint16_t max_fall; + uint16_t max_cll; + uint16_t min_cll; +}; + #define DRM_MODE_PAGE_FLIP_EVENT 0x01 #define DRM_MODE_PAGE_FLIP_ASYNC 0x02 #define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT|DRM_MODE_PAGE_FLIP_ASYNC) diff --git a/include/uapi/drm/rockchip_drm.h b/include/uapi/drm/rockchip_drm.h new file mode 100644 index 000000000000..496fd771d17c --- /dev/null +++ b/include/uapi/drm/rockchip_drm.h @@ -0,0 +1,175 @@ +/* + * + * Copyright (c) Fuzhou Rockchip Electronics Co.Ltd + * Authors: + * Mark Yao <yzq@rock-chips.com> + * + * base on exynos_drm.h + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef _UAPI_ROCKCHIP_DRM_H +#define _UAPI_ROCKCHIP_DRM_H + +#include <drm/drm.h> + +/* memory type definitions. */ +enum drm_rockchip_gem_mem_type { + /* Physically Continuous memory. */ + ROCKCHIP_BO_CONTIG = 1 << 0, + /* cachable mapping. */ + ROCKCHIP_BO_CACHABLE = 1 << 1, + /* write-combine mapping. */ + ROCKCHIP_BO_WC = 1 << 2, + ROCKCHIP_BO_SECURE = 1 << 3, + ROCKCHIP_BO_MASK = ROCKCHIP_BO_CONTIG | ROCKCHIP_BO_CACHABLE | + ROCKCHIP_BO_WC +}; + +/** + * User-desired buffer creation information structure. + * + * @size: user-desired memory allocation size. + * @flags: user request for setting memory type or cache attributes. + * @handle: returned a handle to created gem object. + * - this handle will be set by gem module of kernel side. + */ +struct drm_rockchip_gem_create { + uint64_t size; + uint32_t flags; + uint32_t handle; +}; + +struct drm_rockchip_gem_phys { + uint32_t handle; + uint32_t phy_addr; +}; + +/** + * A structure for getting buffer offset. + * + * @handle: a pointer to gem object created. + * @pad: just padding to be 64-bit aligned. + * @offset: relatived offset value of the memory region allocated. + * - this value should be set by user. + */ +struct drm_rockchip_gem_map_off { + uint32_t handle; + uint32_t pad; + uint64_t offset; +}; + +/* acquire type definitions. */ +enum drm_rockchip_gem_cpu_acquire_type { + DRM_ROCKCHIP_GEM_CPU_ACQUIRE_SHARED = 0x0, + DRM_ROCKCHIP_GEM_CPU_ACQUIRE_EXCLUSIVE = 0x1, +}; + +/** + * A structure for acquiring buffer for CPU access. + * + * @handle: a handle to gem object created. + * @flags: acquire flag + */ +struct drm_rockchip_gem_cpu_acquire { + uint32_t handle; + uint32_t flags; +}; + +/* + * A structure for releasing buffer for GPU access. + * + * @handle: a handle to gem object created. + */ +struct drm_rockchip_gem_cpu_release { + uint32_t handle; +}; + +struct drm_rockchip_rga_get_ver { + __u32 major; + __u32 minor; +}; + +struct drm_rockchip_rga_cmd { + __u32 offset; + __u32 data; +}; + +enum drm_rockchip_rga_buf_type { + RGA_BUF_TYPE_USERPTR = 1 << 31, + RGA_BUF_TYPE_GEMFD = 1 << 30, + RGA_BUF_TYPE_FLUSH = 1 << 29, +}; + +struct drm_rockchip_rga_set_cmdlist { + __u64 cmd; + __u64 cmd_buf; + __u32 cmd_nr; + __u32 cmd_buf_nr; + __u64 user_data; +}; + +struct drm_rockchip_rga_exec { + __u64 async; +}; + +enum rockchip_plane_feture { + ROCKCHIP_DRM_PLANE_FEATURE_SCALE, + ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, + ROCKCHIP_DRM_PLANE_FEATURE_HDR2SDR, + ROCKCHIP_DRM_PLANE_FEATURE_SDR2HDR, + ROCKCHIP_DRM_PLANE_FEATURE_AFBDC, + ROCKCHIP_DRM_PLANE_FEATURE_PDAF_POS, + ROCKCHIP_DRM_PLANE_FEATURE_MAX, +}; + +enum rockchip_crtc_feture { + ROCKCHIP_DRM_CRTC_FEATURE_AFBDC, +}; + +enum rockchip_cabc_mode { + ROCKCHIP_DRM_CABC_MODE_DISABLE, + ROCKCHIP_DRM_CABC_MODE_NORMAL, + ROCKCHIP_DRM_CABC_MODE_LOWPOWER, + ROCKCHIP_DRM_CABC_MODE_USERSPACE, +}; + +#define DRM_ROCKCHIP_GEM_CREATE 0x00 +#define DRM_ROCKCHIP_GEM_MAP_OFFSET 0x01 +#define DRM_ROCKCHIP_GEM_CPU_ACQUIRE 0x02 +#define DRM_ROCKCHIP_GEM_CPU_RELEASE 0x03 +#define DRM_ROCKCHIP_GEM_GET_PHYS 0x04 + +#define DRM_ROCKCHIP_RGA_GET_VER 0x20 +#define DRM_ROCKCHIP_RGA_SET_CMDLIST 0x21 +#define DRM_ROCKCHIP_RGA_EXEC 0x22 + +#define DRM_IOCTL_ROCKCHIP_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_ROCKCHIP_GEM_CREATE, struct drm_rockchip_gem_create) + +#define DRM_IOCTL_ROCKCHIP_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_ROCKCHIP_GEM_MAP_OFFSET, struct drm_rockchip_gem_map_off) + +#define DRM_IOCTL_ROCKCHIP_GEM_CPU_ACQUIRE DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_ROCKCHIP_GEM_CPU_ACQUIRE, struct drm_rockchip_gem_cpu_acquire) + +#define DRM_IOCTL_ROCKCHIP_GEM_CPU_RELEASE DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_ROCKCHIP_GEM_CPU_RELEASE, struct drm_rockchip_gem_cpu_release) + +#define DRM_IOCTL_ROCKCHIP_GEM_GET_PHYS DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_ROCKCHIP_GEM_GET_PHYS, struct drm_rockchip_gem_phys) + +#define DRM_IOCTL_ROCKCHIP_RGA_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_ROCKCHIP_RGA_GET_VER, struct drm_rockchip_rga_get_ver) + +#define DRM_IOCTL_ROCKCHIP_RGA_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_ROCKCHIP_RGA_SET_CMDLIST, struct drm_rockchip_rga_set_cmdlist) + +#define DRM_IOCTL_ROCKCHIP_RGA_EXEC DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_ROCKCHIP_RGA_EXEC, struct drm_rockchip_rga_exec) + +#endif /* _UAPI_ROCKCHIP_DRM_H */ diff --git a/include/uapi/linux/Kbuild b/include/uapi/linux/Kbuild index ebd10e624598..823d784a6244 100644 --- a/include/uapi/linux/Kbuild +++ b/include/uapi/linux/Kbuild @@ -81,6 +81,8 @@ header-y += capi.h header-y += cciss_defs.h header-y += cciss_ioctl.h header-y += cdrom.h +header-y += cec.h +header-y += cec-funcs.h header-y += cgroupstats.h header-y += chio.h header-y += cm4000_cs.h @@ -352,6 +354,7 @@ header-y += reiserfs_fs.h header-y += reiserfs_xattr.h header-y += resource.h header-y += rfkill.h +header-y += rkisp1-config.h header-y += romfs_fs.h header-y += rose.h header-y += route.h diff --git a/include/uapi/linux/cec-funcs.h b/include/uapi/linux/cec-funcs.h new file mode 100644 index 000000000000..c451eec42a83 --- /dev/null +++ b/include/uapi/linux/cec-funcs.h @@ -0,0 +1,1969 @@ +/* + * cec - HDMI Consumer Electronics Control message functions + * + * Copyright 2016 Cisco Systems, Inc. and/or its affiliates. All rights reserved. + * + * This program is free software; you may redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * Alternatively you can redistribute this file under the terms of the + * BSD license as stated below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. The names of its contributors may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef _CEC_UAPI_FUNCS_H +#define _CEC_UAPI_FUNCS_H + +#include <linux/cec.h> + +/* One Touch Play Feature */ +static inline void cec_msg_active_source(struct cec_msg *msg, __u16 phys_addr) +{ + msg->len = 4; + msg->msg[0] |= 0xf; /* broadcast */ + msg->msg[1] = CEC_MSG_ACTIVE_SOURCE; + msg->msg[2] = phys_addr >> 8; + msg->msg[3] = phys_addr & 0xff; +} + +static inline void cec_ops_active_source(const struct cec_msg *msg, + __u16 *phys_addr) +{ + *phys_addr = (msg->msg[2] << 8) | msg->msg[3]; +} + +static inline void cec_msg_image_view_on(struct cec_msg *msg) +{ + msg->len = 2; + msg->msg[1] = CEC_MSG_IMAGE_VIEW_ON; +} + +static inline void cec_msg_text_view_on(struct cec_msg *msg) +{ + msg->len = 2; + msg->msg[1] = CEC_MSG_TEXT_VIEW_ON; +} + + +/* Routing Control Feature */ +static inline void cec_msg_inactive_source(struct cec_msg *msg, + __u16 phys_addr) +{ + msg->len = 4; + msg->msg[1] = CEC_MSG_INACTIVE_SOURCE; + msg->msg[2] = phys_addr >> 8; + msg->msg[3] = phys_addr & 0xff; +} + +static inline void cec_ops_inactive_source(const struct cec_msg *msg, + __u16 *phys_addr) +{ + *phys_addr = (msg->msg[2] << 8) | msg->msg[3]; +} + +static inline void cec_msg_request_active_source(struct cec_msg *msg, + int reply) +{ + msg->len = 2; + msg->msg[0] |= 0xf; /* broadcast */ + msg->msg[1] = CEC_MSG_REQUEST_ACTIVE_SOURCE; + msg->reply = reply ? CEC_MSG_ACTIVE_SOURCE : 0; +} + +static inline void cec_msg_routing_information(struct cec_msg *msg, + __u16 phys_addr) +{ + msg->len = 4; + msg->msg[0] |= 0xf; /* broadcast */ + msg->msg[1] = CEC_MSG_ROUTING_INFORMATION; + msg->msg[2] = phys_addr >> 8; + msg->msg[3] = phys_addr & 0xff; +} + +static inline void cec_ops_routing_information(const struct cec_msg *msg, + __u16 *phys_addr) +{ + *phys_addr = (msg->msg[2] << 8) | msg->msg[3]; +} + +static inline void cec_msg_routing_change(struct cec_msg *msg, + int reply, + __u16 orig_phys_addr, + __u16 new_phys_addr) +{ + msg->len = 6; + msg->msg[0] |= 0xf; /* broadcast */ + msg->msg[1] = CEC_MSG_ROUTING_CHANGE; + msg->msg[2] = orig_phys_addr >> 8; + msg->msg[3] = orig_phys_addr & 0xff; + msg->msg[4] = new_phys_addr >> 8; + msg->msg[5] = new_phys_addr & 0xff; + msg->reply = reply ? CEC_MSG_ROUTING_INFORMATION : 0; +} + +static inline void cec_ops_routing_change(const struct cec_msg *msg, + __u16 *orig_phys_addr, + __u16 *new_phys_addr) +{ + *orig_phys_addr = (msg->msg[2] << 8) | msg->msg[3]; + *new_phys_addr = (msg->msg[4] << 8) | msg->msg[5]; +} + +static inline void cec_msg_set_stream_path(struct cec_msg *msg, __u16 phys_addr) +{ + msg->len = 4; + msg->msg[0] |= 0xf; /* broadcast */ + msg->msg[1] = CEC_MSG_SET_STREAM_PATH; + msg->msg[2] = phys_addr >> 8; + msg->msg[3] = phys_addr & 0xff; +} + +static inline void cec_ops_set_stream_path(const struct cec_msg *msg, + __u16 *phys_addr) +{ + *phys_addr = (msg->msg[2] << 8) | msg->msg[3]; +} + + +/* Standby Feature */ +static inline void cec_msg_standby(struct cec_msg *msg) +{ + msg->len = 2; + msg->msg[1] = CEC_MSG_STANDBY; +} + + +/* One Touch Record Feature */ +static inline void cec_msg_record_off(struct cec_msg *msg, int reply) +{ + msg->len = 2; + msg->msg[1] = CEC_MSG_RECORD_OFF; + msg->reply = reply ? CEC_MSG_RECORD_STATUS : 0; +} + +struct cec_op_arib_data { + __u16 transport_id; + __u16 service_id; + __u16 orig_network_id; +}; + +struct cec_op_atsc_data { + __u16 transport_id; + __u16 program_number; +}; + +struct cec_op_dvb_data { + __u16 transport_id; + __u16 service_id; + __u16 orig_network_id; +}; + +struct cec_op_channel_data { + __u8 channel_number_fmt; + __u16 major; + __u16 minor; +}; + +struct cec_op_digital_service_id { + __u8 service_id_method; + __u8 dig_bcast_system; + union { + struct cec_op_arib_data arib; + struct cec_op_atsc_data atsc; + struct cec_op_dvb_data dvb; + struct cec_op_channel_data channel; + }; +}; + +struct cec_op_record_src { + __u8 type; + union { + struct cec_op_digital_service_id digital; + struct { + __u8 ana_bcast_type; + __u16 ana_freq; + __u8 bcast_system; + } analog; + struct { + __u8 plug; + } ext_plug; + struct { + __u16 phys_addr; + } ext_phys_addr; + }; +}; + +static inline void cec_set_digital_service_id(__u8 *msg, + const struct cec_op_digital_service_id *digital) +{ + *msg++ = (digital->service_id_method << 7) | digital->dig_bcast_system; + if (digital->service_id_method == CEC_OP_SERVICE_ID_METHOD_BY_CHANNEL) { + *msg++ = (digital->channel.channel_number_fmt << 2) | + (digital->channel.major >> 8); + *msg++ = digital->channel.major & 0xff; + *msg++ = digital->channel.minor >> 8; + *msg++ = digital->channel.minor & 0xff; + *msg++ = 0; + *msg++ = 0; + return; + } + switch (digital->dig_bcast_system) { + case CEC_OP_DIG_SERVICE_BCAST_SYSTEM_ATSC_GEN: + case CEC_OP_DIG_SERVICE_BCAST_SYSTEM_ATSC_CABLE: + case CEC_OP_DIG_SERVICE_BCAST_SYSTEM_ATSC_SAT: + case CEC_OP_DIG_SERVICE_BCAST_SYSTEM_ATSC_T: + *msg++ = digital->atsc.transport_id >> 8; + *msg++ = digital->atsc.transport_id & 0xff; + *msg++ = digital->atsc.program_number >> 8; + *msg++ = digital->atsc.program_number & 0xff; + *msg++ = 0; + *msg++ = 0; + break; + default: + *msg++ = digital->dvb.transport_id >> 8; + *msg++ = digital->dvb.transport_id & 0xff; + *msg++ = digital->dvb.service_id >> 8; + *msg++ = digital->dvb.service_id & 0xff; + *msg++ = digital->dvb.orig_network_id >> 8; + *msg++ = digital->dvb.orig_network_id & 0xff; + break; + } +} + +static inline void cec_get_digital_service_id(const __u8 *msg, + struct cec_op_digital_service_id *digital) +{ + digital->service_id_method = msg[0] >> 7; + digital->dig_bcast_system = msg[0] & 0x7f; + if (digital->service_id_method == CEC_OP_SERVICE_ID_METHOD_BY_CHANNEL) { + digital->channel.channel_number_fmt = msg[1] >> 2; + digital->channel.major = ((msg[1] & 3) << 6) | msg[2]; + digital->channel.minor = (msg[3] << 8) | msg[4]; + return; + } + digital->dvb.transport_id = (msg[1] << 8) | msg[2]; + digital->dvb.service_id = (msg[3] << 8) | msg[4]; + digital->dvb.orig_network_id = (msg[5] << 8) | msg[6]; +} + +static inline void cec_msg_record_on_own(struct cec_msg *msg) +{ + msg->len = 3; + msg->msg[1] = CEC_MSG_RECORD_ON; + msg->msg[2] = CEC_OP_RECORD_SRC_OWN; +} + +static inline void cec_msg_record_on_digital(struct cec_msg *msg, + const struct cec_op_digital_service_id *digital) +{ + msg->len = 10; + msg->msg[1] = CEC_MSG_RECORD_ON; + msg->msg[2] = CEC_OP_RECORD_SRC_DIGITAL; + cec_set_digital_service_id(msg->msg + 3, digital); +} + +static inline void cec_msg_record_on_analog(struct cec_msg *msg, + __u8 ana_bcast_type, + __u16 ana_freq, + __u8 bcast_system) +{ + msg->len = 7; + msg->msg[1] = CEC_MSG_RECORD_ON; + msg->msg[2] = CEC_OP_RECORD_SRC_ANALOG; + msg->msg[3] = ana_bcast_type; + msg->msg[4] = ana_freq >> 8; + msg->msg[5] = ana_freq & 0xff; + msg->msg[6] = bcast_system; +} + +static inline void cec_msg_record_on_plug(struct cec_msg *msg, + __u8 plug) +{ + msg->len = 4; + msg->msg[1] = CEC_MSG_RECORD_ON; + msg->msg[2] = CEC_OP_RECORD_SRC_EXT_PLUG; + msg->msg[3] = plug; +} + +static inline void cec_msg_record_on_phys_addr(struct cec_msg *msg, + __u16 phys_addr) +{ + msg->len = 5; + msg->msg[1] = CEC_MSG_RECORD_ON; + msg->msg[2] = CEC_OP_RECORD_SRC_EXT_PHYS_ADDR; + msg->msg[3] = phys_addr >> 8; + msg->msg[4] = phys_addr & 0xff; +} + +static inline void cec_msg_record_on(struct cec_msg *msg, + int reply, + const struct cec_op_record_src *rec_src) +{ + switch (rec_src->type) { + case CEC_OP_RECORD_SRC_OWN: + cec_msg_record_on_own(msg); + break; + case CEC_OP_RECORD_SRC_DIGITAL: + cec_msg_record_on_digital(msg, &rec_src->digital); + break; + case CEC_OP_RECORD_SRC_ANALOG: + cec_msg_record_on_analog(msg, + rec_src->analog.ana_bcast_type, + rec_src->analog.ana_freq, + rec_src->analog.bcast_system); + break; + case CEC_OP_RECORD_SRC_EXT_PLUG: + cec_msg_record_on_plug(msg, rec_src->ext_plug.plug); + break; + case CEC_OP_RECORD_SRC_EXT_PHYS_ADDR: + cec_msg_record_on_phys_addr(msg, + rec_src->ext_phys_addr.phys_addr); + break; + } + msg->reply = reply ? CEC_MSG_RECORD_STATUS : 0; +} + +static inline void cec_ops_record_on(const struct cec_msg *msg, + struct cec_op_record_src *rec_src) +{ + rec_src->type = msg->msg[2]; + switch (rec_src->type) { + case CEC_OP_RECORD_SRC_OWN: + break; + case CEC_OP_RECORD_SRC_DIGITAL: + cec_get_digital_service_id(msg->msg + 3, &rec_src->digital); + break; + case CEC_OP_RECORD_SRC_ANALOG: + rec_src->analog.ana_bcast_type = msg->msg[3]; + rec_src->analog.ana_freq = + (msg->msg[4] << 8) | msg->msg[5]; + rec_src->analog.bcast_system = msg->msg[6]; + break; + case CEC_OP_RECORD_SRC_EXT_PLUG: + rec_src->ext_plug.plug = msg->msg[3]; + break; + case CEC_OP_RECORD_SRC_EXT_PHYS_ADDR: + rec_src->ext_phys_addr.phys_addr = + (msg->msg[3] << 8) | msg->msg[4]; + break; + } +} + +static inline void cec_msg_record_status(struct cec_msg *msg, __u8 rec_status) +{ + msg->len = 3; + msg->msg[1] = CEC_MSG_RECORD_STATUS; + msg->msg[2] = rec_status; +} + +static inline void cec_ops_record_status(const struct cec_msg *msg, + __u8 *rec_status) +{ + *rec_status = msg->msg[2]; +} + +static inline void cec_msg_record_tv_screen(struct cec_msg *msg, + int reply) +{ + msg->len = 2; + msg->msg[1] = CEC_MSG_RECORD_TV_SCREEN; + msg->reply = reply ? CEC_MSG_RECORD_ON : 0; +} + + +/* Timer Programming Feature */ +static inline void cec_msg_timer_status(struct cec_msg *msg, + __u8 timer_overlap_warning, + __u8 media_info, + __u8 prog_info, + __u8 prog_error, + __u8 duration_hr, + __u8 duration_min) +{ + msg->len = 3; + msg->msg[1] = CEC_MSG_TIMER_STATUS; + msg->msg[2] = (timer_overlap_warning << 7) | + (media_info << 5) | + (prog_info ? 0x10 : 0) | + (prog_info ? prog_info : prog_error); + if (prog_info == CEC_OP_PROG_INFO_NOT_ENOUGH_SPACE || + prog_info == CEC_OP_PROG_INFO_MIGHT_NOT_BE_ENOUGH_SPACE || + prog_error == CEC_OP_PROG_ERROR_DUPLICATE) { + msg->len += 2; + msg->msg[3] = ((duration_hr / 10) << 4) | (duration_hr % 10); + msg->msg[4] = ((duration_min / 10) << 4) | (duration_min % 10); + } +} + +static inline void cec_ops_timer_status(const struct cec_msg *msg, + __u8 *timer_overlap_warning, + __u8 *media_info, + __u8 *prog_info, + __u8 *prog_error, + __u8 *duration_hr, + __u8 *duration_min) +{ + *timer_overlap_warning = msg->msg[2] >> 7; + *media_info = (msg->msg[2] >> 5) & 3; + if (msg->msg[2] & 0x10) { + *prog_info = msg->msg[2] & 0xf; + *prog_error = 0; + } else { + *prog_info = 0; + *prog_error = msg->msg[2] & 0xf; + } + if (*prog_info == CEC_OP_PROG_INFO_NOT_ENOUGH_SPACE || + *prog_info == CEC_OP_PROG_INFO_MIGHT_NOT_BE_ENOUGH_SPACE || + *prog_error == CEC_OP_PROG_ERROR_DUPLICATE) { + *duration_hr = (msg->msg[3] >> 4) * 10 + (msg->msg[3] & 0xf); + *duration_min = (msg->msg[4] >> 4) * 10 + (msg->msg[4] & 0xf); + } else { + *duration_hr = *duration_min = 0; + } +} + +static inline void cec_msg_timer_cleared_status(struct cec_msg *msg, + __u8 timer_cleared_status) +{ + msg->len = 3; + msg->msg[1] = CEC_MSG_TIMER_CLEARED_STATUS; + msg->msg[2] = timer_cleared_status; +} + +static inline void cec_ops_timer_cleared_status(const struct cec_msg *msg, + __u8 *timer_cleared_status) +{ + *timer_cleared_status = msg->msg[2]; +} + +static inline void cec_msg_clear_analogue_timer(struct cec_msg *msg, + int reply, + __u8 day, + __u8 month, + __u8 start_hr, + __u8 start_min, + __u8 duration_hr, + __u8 duration_min, + __u8 recording_seq, + __u8 ana_bcast_type, + __u16 ana_freq, + __u8 bcast_system) +{ + msg->len = 13; + msg->msg[1] = CEC_MSG_CLEAR_ANALOGUE_TIMER; + msg->msg[2] = day; + msg->msg[3] = month; + /* Hours and minutes are in BCD format */ + msg->msg[4] = ((start_hr / 10) << 4) | (start_hr % 10); + msg->msg[5] = ((start_min / 10) << 4) | (start_min % 10); + msg->msg[6] = ((duration_hr / 10) << 4) | (duration_hr % 10); + msg->msg[7] = ((duration_min / 10) << 4) | (duration_min % 10); + msg->msg[8] = recording_seq; + msg->msg[9] = ana_bcast_type; + msg->msg[10] = ana_freq >> 8; + msg->msg[11] = ana_freq & 0xff; + msg->msg[12] = bcast_system; + msg->reply = reply ? CEC_MSG_TIMER_CLEARED_STATUS : 0; +} + +static inline void cec_ops_clear_analogue_timer(const struct cec_msg *msg, + __u8 *day, + __u8 *month, + __u8 *start_hr, + __u8 *start_min, + __u8 *duration_hr, + __u8 *duration_min, + __u8 *recording_seq, + __u8 *ana_bcast_type, + __u16 *ana_freq, + __u8 *bcast_system) +{ + *day = msg->msg[2]; + *month = msg->msg[3]; + /* Hours and minutes are in BCD format */ + *start_hr = (msg->msg[4] >> 4) * 10 + (msg->msg[4] & 0xf); + *start_min = (msg->msg[5] >> 4) * 10 + (msg->msg[5] & 0xf); + *duration_hr = (msg->msg[6] >> 4) * 10 + (msg->msg[6] & 0xf); + *duration_min = (msg->msg[7] >> 4) * 10 + (msg->msg[7] & 0xf); + *recording_seq = msg->msg[8]; + *ana_bcast_type = msg->msg[9]; + *ana_freq = (msg->msg[10] << 8) | msg->msg[11]; + *bcast_system = msg->msg[12]; +} + +static inline void cec_msg_clear_digital_timer(struct cec_msg *msg, + int reply, + __u8 day, + __u8 month, + __u8 start_hr, + __u8 start_min, + __u8 duration_hr, + __u8 duration_min, + __u8 recording_seq, + const struct cec_op_digital_service_id *digital) +{ + msg->len = 16; + msg->reply = reply ? CEC_MSG_TIMER_CLEARED_STATUS : 0; + msg->msg[1] = CEC_MSG_CLEAR_DIGITAL_TIMER; + msg->msg[2] = day; + msg->msg[3] = month; + /* Hours and minutes are in BCD format */ + msg->msg[4] = ((start_hr / 10) << 4) | (start_hr % 10); + msg->msg[5] = ((start_min / 10) << 4) | (start_min % 10); + msg->msg[6] = ((duration_hr / 10) << 4) | (duration_hr % 10); + msg->msg[7] = ((duration_min / 10) << 4) | (duration_min % 10); + msg->msg[8] = recording_seq; + cec_set_digital_service_id(msg->msg + 9, digital); +} + +static inline void cec_ops_clear_digital_timer(const struct cec_msg *msg, + __u8 *day, + __u8 *month, + __u8 *start_hr, + __u8 *start_min, + __u8 *duration_hr, + __u8 *duration_min, + __u8 *recording_seq, + struct cec_op_digital_service_id *digital) +{ + *day = msg->msg[2]; + *month = msg->msg[3]; + /* Hours and minutes are in BCD format */ + *start_hr = (msg->msg[4] >> 4) * 10 + (msg->msg[4] & 0xf); + *start_min = (msg->msg[5] >> 4) * 10 + (msg->msg[5] & 0xf); + *duration_hr = (msg->msg[6] >> 4) * 10 + (msg->msg[6] & 0xf); + *duration_min = (msg->msg[7] >> 4) * 10 + (msg->msg[7] & 0xf); + *recording_seq = msg->msg[8]; + cec_get_digital_service_id(msg->msg + 9, digital); +} + +static inline void cec_msg_clear_ext_timer(struct cec_msg *msg, + int reply, + __u8 day, + __u8 month, + __u8 start_hr, + __u8 start_min, + __u8 duration_hr, + __u8 duration_min, + __u8 recording_seq, + __u8 ext_src_spec, + __u8 plug, + __u16 phys_addr) +{ + msg->len = 13; + msg->msg[1] = CEC_MSG_CLEAR_EXT_TIMER; + msg->msg[2] = day; + msg->msg[3] = month; + /* Hours and minutes are in BCD format */ + msg->msg[4] = ((start_hr / 10) << 4) | (start_hr % 10); + msg->msg[5] = ((start_min / 10) << 4) | (start_min % 10); + msg->msg[6] = ((duration_hr / 10) << 4) | (duration_hr % 10); + msg->msg[7] = ((duration_min / 10) << 4) | (duration_min % 10); + msg->msg[8] = recording_seq; + msg->msg[9] = ext_src_spec; + msg->msg[10] = plug; + msg->msg[11] = phys_addr >> 8; + msg->msg[12] = phys_addr & 0xff; + msg->reply = reply ? CEC_MSG_TIMER_CLEARED_STATUS : 0; +} + +static inline void cec_ops_clear_ext_timer(const struct cec_msg *msg, + __u8 *day, + __u8 *month, + __u8 *start_hr, + __u8 *start_min, + __u8 *duration_hr, + __u8 *duration_min, + __u8 *recording_seq, + __u8 *ext_src_spec, + __u8 *plug, + __u16 *phys_addr) +{ + *day = msg->msg[2]; + *month = msg->msg[3]; + /* Hours and minutes are in BCD format */ + *start_hr = (msg->msg[4] >> 4) * 10 + (msg->msg[4] & 0xf); + *start_min = (msg->msg[5] >> 4) * 10 + (msg->msg[5] & 0xf); + *duration_hr = (msg->msg[6] >> 4) * 10 + (msg->msg[6] & 0xf); + *duration_min = (msg->msg[7] >> 4) * 10 + (msg->msg[7] & 0xf); + *recording_seq = msg->msg[8]; + *ext_src_spec = msg->msg[9]; + *plug = msg->msg[10]; + *phys_addr = (msg->msg[11] << 8) | msg->msg[12]; +} + +static inline void cec_msg_set_analogue_timer(struct cec_msg *msg, + int reply, + __u8 day, + __u8 month, + __u8 start_hr, + __u8 start_min, + __u8 duration_hr, + __u8 duration_min, + __u8 recording_seq, + __u8 ana_bcast_type, + __u16 ana_freq, + __u8 bcast_system) +{ + msg->len = 13; + msg->msg[1] = CEC_MSG_SET_ANALOGUE_TIMER; + msg->msg[2] = day; + msg->msg[3] = month; + /* Hours and minutes are in BCD format */ + msg->msg[4] = ((start_hr / 10) << 4) | (start_hr % 10); + msg->msg[5] = ((start_min / 10) << 4) | (start_min % 10); + msg->msg[6] = ((duration_hr / 10) << 4) | (duration_hr % 10); + msg->msg[7] = ((duration_min / 10) << 4) | (duration_min % 10); + msg->msg[8] = recording_seq; + msg->msg[9] = ana_bcast_type; + msg->msg[10] = ana_freq >> 8; + msg->msg[11] = ana_freq & 0xff; + msg->msg[12] = bcast_system; + msg->reply = reply ? CEC_MSG_TIMER_STATUS : 0; +} + +static inline void cec_ops_set_analogue_timer(const struct cec_msg *msg, + __u8 *day, + __u8 *month, + __u8 *start_hr, + __u8 *start_min, + __u8 *duration_hr, + __u8 *duration_min, + __u8 *recording_seq, + __u8 *ana_bcast_type, + __u16 *ana_freq, + __u8 *bcast_system) +{ + *day = msg->msg[2]; + *month = msg->msg[3]; + /* Hours and minutes are in BCD format */ + *start_hr = (msg->msg[4] >> 4) * 10 + (msg->msg[4] & 0xf); + *start_min = (msg->msg[5] >> 4) * 10 + (msg->msg[5] & 0xf); + *duration_hr = (msg->msg[6] >> 4) * 10 + (msg->msg[6] & 0xf); + *duration_min = (msg->msg[7] >> 4) * 10 + (msg->msg[7] & 0xf); + *recording_seq = msg->msg[8]; + *ana_bcast_type = msg->msg[9]; + *ana_freq = (msg->msg[10] << 8) | msg->msg[11]; + *bcast_system = msg->msg[12]; +} + +static inline void cec_msg_set_digital_timer(struct cec_msg *msg, + int reply, + __u8 day, + __u8 month, + __u8 start_hr, + __u8 start_min, + __u8 duration_hr, + __u8 duration_min, + __u8 recording_seq, + const struct cec_op_digital_service_id *digital) +{ + msg->len = 16; + msg->reply = reply ? CEC_MSG_TIMER_STATUS : 0; + msg->msg[1] = CEC_MSG_SET_DIGITAL_TIMER; + msg->msg[2] = day; + msg->msg[3] = month; + /* Hours and minutes are in BCD format */ + msg->msg[4] = ((start_hr / 10) << 4) | (start_hr % 10); + msg->msg[5] = ((start_min / 10) << 4) | (start_min % 10); + msg->msg[6] = ((duration_hr / 10) << 4) | (duration_hr % 10); + msg->msg[7] = ((duration_min / 10) << 4) | (duration_min % 10); + msg->msg[8] = recording_seq; + cec_set_digital_service_id(msg->msg + 9, digital); +} + +static inline void cec_ops_set_digital_timer(const struct cec_msg *msg, + __u8 *day, + __u8 *month, + __u8 *start_hr, + __u8 *start_min, + __u8 *duration_hr, + __u8 *duration_min, + __u8 *recording_seq, + struct cec_op_digital_service_id *digital) +{ + *day = msg->msg[2]; + *month = msg->msg[3]; + /* Hours and minutes are in BCD format */ + *start_hr = (msg->msg[4] >> 4) * 10 + (msg->msg[4] & 0xf); + *start_min = (msg->msg[5] >> 4) * 10 + (msg->msg[5] & 0xf); + *duration_hr = (msg->msg[6] >> 4) * 10 + (msg->msg[6] & 0xf); + *duration_min = (msg->msg[7] >> 4) * 10 + (msg->msg[7] & 0xf); + *recording_seq = msg->msg[8]; + cec_get_digital_service_id(msg->msg + 9, digital); +} + +static inline void cec_msg_set_ext_timer(struct cec_msg *msg, + int reply, + __u8 day, + __u8 month, + __u8 start_hr, + __u8 start_min, + __u8 duration_hr, + __u8 duration_min, + __u8 recording_seq, + __u8 ext_src_spec, + __u8 plug, + __u16 phys_addr) +{ + msg->len = 13; + msg->msg[1] = CEC_MSG_SET_EXT_TIMER; + msg->msg[2] = day; + msg->msg[3] = month; + /* Hours and minutes are in BCD format */ + msg->msg[4] = ((start_hr / 10) << 4) | (start_hr % 10); + msg->msg[5] = ((start_min / 10) << 4) | (start_min % 10); + msg->msg[6] = ((duration_hr / 10) << 4) | (duration_hr % 10); + msg->msg[7] = ((duration_min / 10) << 4) | (duration_min % 10); + msg->msg[8] = recording_seq; + msg->msg[9] = ext_src_spec; + msg->msg[10] = plug; + msg->msg[11] = phys_addr >> 8; + msg->msg[12] = phys_addr & 0xff; + msg->reply = reply ? CEC_MSG_TIMER_STATUS : 0; +} + +static inline void cec_ops_set_ext_timer(const struct cec_msg *msg, + __u8 *day, + __u8 *month, + __u8 *start_hr, + __u8 *start_min, + __u8 *duration_hr, + __u8 *duration_min, + __u8 *recording_seq, + __u8 *ext_src_spec, + __u8 *plug, + __u16 *phys_addr) +{ + *day = msg->msg[2]; + *month = msg->msg[3]; + /* Hours and minutes are in BCD format */ + *start_hr = (msg->msg[4] >> 4) * 10 + (msg->msg[4] & 0xf); + *start_min = (msg->msg[5] >> 4) * 10 + (msg->msg[5] & 0xf); + *duration_hr = (msg->msg[6] >> 4) * 10 + (msg->msg[6] & 0xf); + *duration_min = (msg->msg[7] >> 4) * 10 + (msg->msg[7] & 0xf); + *recording_seq = msg->msg[8]; + *ext_src_spec = msg->msg[9]; + *plug = msg->msg[10]; + *phys_addr = (msg->msg[11] << 8) | msg->msg[12]; +} + +static inline void cec_msg_set_timer_program_title(struct cec_msg *msg, + const char *prog_title) +{ + unsigned int len = strlen(prog_title); + + if (len > 14) + len = 14; + msg->len = 2 + len; + msg->msg[1] = CEC_MSG_SET_TIMER_PROGRAM_TITLE; + memcpy(msg->msg + 2, prog_title, len); +} + +static inline void cec_ops_set_timer_program_title(const struct cec_msg *msg, + char *prog_title) +{ + unsigned int len = msg->len > 2 ? msg->len - 2 : 0; + + if (len > 14) + len = 14; + memcpy(prog_title, msg->msg + 2, len); + prog_title[len] = '\0'; +} + +/* System Information Feature */ +static inline void cec_msg_cec_version(struct cec_msg *msg, __u8 cec_version) +{ + msg->len = 3; + msg->msg[1] = CEC_MSG_CEC_VERSION; + msg->msg[2] = cec_version; +} + +static inline void cec_ops_cec_version(const struct cec_msg *msg, + __u8 *cec_version) +{ + *cec_version = msg->msg[2]; +} + +static inline void cec_msg_get_cec_version(struct cec_msg *msg, + int reply) +{ + msg->len = 2; + msg->msg[1] = CEC_MSG_GET_CEC_VERSION; + msg->reply = reply ? CEC_MSG_CEC_VERSION : 0; +} + +static inline void cec_msg_report_physical_addr(struct cec_msg *msg, + __u16 phys_addr, __u8 prim_devtype) +{ + msg->len = 5; + msg->msg[0] |= 0xf; /* broadcast */ + msg->msg[1] = CEC_MSG_REPORT_PHYSICAL_ADDR; + msg->msg[2] = phys_addr >> 8; + msg->msg[3] = phys_addr & 0xff; + msg->msg[4] = prim_devtype; +} + +static inline void cec_ops_report_physical_addr(const struct cec_msg *msg, + __u16 *phys_addr, __u8 *prim_devtype) +{ + *phys_addr = (msg->msg[2] << 8) | msg->msg[3]; + *prim_devtype = msg->msg[4]; +} + +static inline void cec_msg_give_physical_addr(struct cec_msg *msg, + int reply) +{ + msg->len = 2; + msg->msg[1] = CEC_MSG_GIVE_PHYSICAL_ADDR; + msg->reply = reply ? CEC_MSG_REPORT_PHYSICAL_ADDR : 0; +} + +static inline void cec_msg_set_menu_language(struct cec_msg *msg, + const char *language) +{ + msg->len = 5; + msg->msg[0] |= 0xf; /* broadcast */ + msg->msg[1] = CEC_MSG_SET_MENU_LANGUAGE; + memcpy(msg->msg + 2, language, 3); +} + +static inline void cec_ops_set_menu_language(const struct cec_msg *msg, + char *language) +{ + memcpy(language, msg->msg + 2, 3); + language[3] = '\0'; +} + +static inline void cec_msg_get_menu_language(struct cec_msg *msg, + int reply) +{ + msg->len = 2; + msg->msg[1] = CEC_MSG_GET_MENU_LANGUAGE; + msg->reply = reply ? CEC_MSG_SET_MENU_LANGUAGE : 0; +} + +/* + * Assumes a single RC Profile byte and a single Device Features byte, + * i.e. no extended features are supported by this helper function. + * + * As of CEC 2.0 no extended features are defined, should those be added + * in the future, then this function needs to be adapted or a new function + * should be added. + */ +static inline void cec_msg_report_features(struct cec_msg *msg, + __u8 cec_version, __u8 all_device_types, + __u8 rc_profile, __u8 dev_features) +{ + msg->len = 6; + msg->msg[0] |= 0xf; /* broadcast */ + msg->msg[1] = CEC_MSG_REPORT_FEATURES; + msg->msg[2] = cec_version; + msg->msg[3] = all_device_types; + msg->msg[4] = rc_profile; + msg->msg[5] = dev_features; +} + +static inline void cec_ops_report_features(const struct cec_msg *msg, + __u8 *cec_version, __u8 *all_device_types, + const __u8 **rc_profile, const __u8 **dev_features) +{ + const __u8 *p = &msg->msg[4]; + + *cec_version = msg->msg[2]; + *all_device_types = msg->msg[3]; + *rc_profile = p; + while (p < &msg->msg[14] && (*p & CEC_OP_FEAT_EXT)) + p++; + if (!(*p & CEC_OP_FEAT_EXT)) { + *dev_features = p + 1; + while (p < &msg->msg[15] && (*p & CEC_OP_FEAT_EXT)) + p++; + } + if (*p & CEC_OP_FEAT_EXT) + *rc_profile = *dev_features = NULL; +} + +static inline void cec_msg_give_features(struct cec_msg *msg, + int reply) +{ + msg->len = 2; + msg->msg[1] = CEC_MSG_GIVE_FEATURES; + msg->reply = reply ? CEC_MSG_REPORT_FEATURES : 0; +} + +/* Deck Control Feature */ +static inline void cec_msg_deck_control(struct cec_msg *msg, + __u8 deck_control_mode) +{ + msg->len = 3; + msg->msg[1] = CEC_MSG_DECK_CONTROL; + msg->msg[2] = deck_control_mode; +} + +static inline void cec_ops_deck_control(const struct cec_msg *msg, + __u8 *deck_control_mode) +{ + *deck_control_mode = msg->msg[2]; +} + +static inline void cec_msg_deck_status(struct cec_msg *msg, + __u8 deck_info) +{ + msg->len = 3; + msg->msg[1] = CEC_MSG_DECK_STATUS; + msg->msg[2] = deck_info; +} + +static inline void cec_ops_deck_status(const struct cec_msg *msg, + __u8 *deck_info) +{ + *deck_info = msg->msg[2]; +} + +static inline void cec_msg_give_deck_status(struct cec_msg *msg, + int reply, + __u8 status_req) +{ + msg->len = 3; + msg->msg[1] = CEC_MSG_GIVE_DECK_STATUS; + msg->msg[2] = status_req; + msg->reply = reply ? CEC_MSG_DECK_STATUS : 0; +} + +static inline void cec_ops_give_deck_status(const struct cec_msg *msg, + __u8 *status_req) +{ + *status_req = msg->msg[2]; +} + +static inline void cec_msg_play(struct cec_msg *msg, + __u8 play_mode) +{ + msg->len = 3; + msg->msg[1] = CEC_MSG_PLAY; + msg->msg[2] = play_mode; +} + +static inline void cec_ops_play(const struct cec_msg *msg, + __u8 *play_mode) +{ + *play_mode = msg->msg[2]; +} + + +/* Tuner Control Feature */ +struct cec_op_tuner_device_info { + __u8 rec_flag; + __u8 tuner_display_info; + __u8 is_analog; + union { + struct cec_op_digital_service_id digital; + struct { + __u8 ana_bcast_type; + __u16 ana_freq; + __u8 bcast_system; + } analog; + }; +}; + +static inline void cec_msg_tuner_device_status_analog(struct cec_msg *msg, + __u8 rec_flag, + __u8 tuner_display_info, + __u8 ana_bcast_type, + __u16 ana_freq, + __u8 bcast_system) +{ + msg->len = 7; + msg->msg[1] = CEC_MSG_TUNER_DEVICE_STATUS; + msg->msg[2] = (rec_flag << 7) | tuner_display_info; + msg->msg[3] = ana_bcast_type; + msg->msg[4] = ana_freq >> 8; + msg->msg[5] = ana_freq & 0xff; + msg->msg[6] = bcast_system; +} + +static inline void cec_msg_tuner_device_status_digital(struct cec_msg *msg, + __u8 rec_flag, __u8 tuner_display_info, + const struct cec_op_digital_service_id *digital) +{ + msg->len = 10; + msg->msg[1] = CEC_MSG_TUNER_DEVICE_STATUS; + msg->msg[2] = (rec_flag << 7) | tuner_display_info; + cec_set_digital_service_id(msg->msg + 3, digital); +} + +static inline void cec_msg_tuner_device_status(struct cec_msg *msg, + const struct cec_op_tuner_device_info *tuner_dev_info) +{ + if (tuner_dev_info->is_analog) + cec_msg_tuner_device_status_analog(msg, + tuner_dev_info->rec_flag, + tuner_dev_info->tuner_display_info, + tuner_dev_info->analog.ana_bcast_type, + tuner_dev_info->analog.ana_freq, + tuner_dev_info->analog.bcast_system); + else + cec_msg_tuner_device_status_digital(msg, + tuner_dev_info->rec_flag, + tuner_dev_info->tuner_display_info, + &tuner_dev_info->digital); +} + +static inline void cec_ops_tuner_device_status(const struct cec_msg *msg, + struct cec_op_tuner_device_info *tuner_dev_info) +{ + tuner_dev_info->is_analog = msg->len < 10; + tuner_dev_info->rec_flag = msg->msg[2] >> 7; + tuner_dev_info->tuner_display_info = msg->msg[2] & 0x7f; + if (tuner_dev_info->is_analog) { + tuner_dev_info->analog.ana_bcast_type = msg->msg[3]; + tuner_dev_info->analog.ana_freq = (msg->msg[4] << 8) | msg->msg[5]; + tuner_dev_info->analog.bcast_system = msg->msg[6]; + return; + } + cec_get_digital_service_id(msg->msg + 3, &tuner_dev_info->digital); +} + +static inline void cec_msg_give_tuner_device_status(struct cec_msg *msg, + int reply, + __u8 status_req) +{ + msg->len = 3; + msg->msg[1] = CEC_MSG_GIVE_TUNER_DEVICE_STATUS; + msg->msg[2] = status_req; + msg->reply = reply ? CEC_MSG_TUNER_DEVICE_STATUS : 0; +} + +static inline void cec_ops_give_tuner_device_status(const struct cec_msg *msg, + __u8 *status_req) +{ + *status_req = msg->msg[2]; +} + +static inline void cec_msg_select_analogue_service(struct cec_msg *msg, + __u8 ana_bcast_type, + __u16 ana_freq, + __u8 bcast_system) +{ + msg->len = 6; + msg->msg[1] = CEC_MSG_SELECT_ANALOGUE_SERVICE; + msg->msg[2] = ana_bcast_type; + msg->msg[3] = ana_freq >> 8; + msg->msg[4] = ana_freq & 0xff; + msg->msg[5] = bcast_system; +} + +static inline void cec_ops_select_analogue_service(const struct cec_msg *msg, + __u8 *ana_bcast_type, + __u16 *ana_freq, + __u8 *bcast_system) +{ + *ana_bcast_type = msg->msg[2]; + *ana_freq = (msg->msg[3] << 8) | msg->msg[4]; + *bcast_system = msg->msg[5]; +} + +static inline void cec_msg_select_digital_service(struct cec_msg *msg, + const struct cec_op_digital_service_id *digital) +{ + msg->len = 9; + msg->msg[1] = CEC_MSG_SELECT_DIGITAL_SERVICE; + cec_set_digital_service_id(msg->msg + 2, digital); +} + +static inline void cec_ops_select_digital_service(const struct cec_msg *msg, + struct cec_op_digital_service_id *digital) +{ + cec_get_digital_service_id(msg->msg + 2, digital); +} + +static inline void cec_msg_tuner_step_decrement(struct cec_msg *msg) +{ + msg->len = 2; + msg->msg[1] = CEC_MSG_TUNER_STEP_DECREMENT; +} + +static inline void cec_msg_tuner_step_increment(struct cec_msg *msg) +{ + msg->len = 2; + msg->msg[1] = CEC_MSG_TUNER_STEP_INCREMENT; +} + + +/* Vendor Specific Commands Feature */ +static inline void cec_msg_device_vendor_id(struct cec_msg *msg, __u32 vendor_id) +{ + msg->len = 5; + msg->msg[0] |= 0xf; /* broadcast */ + msg->msg[1] = CEC_MSG_DEVICE_VENDOR_ID; + msg->msg[2] = vendor_id >> 16; + msg->msg[3] = (vendor_id >> 8) & 0xff; + msg->msg[4] = vendor_id & 0xff; +} + +static inline void cec_ops_device_vendor_id(const struct cec_msg *msg, + __u32 *vendor_id) +{ + *vendor_id = (msg->msg[2] << 16) | (msg->msg[3] << 8) | msg->msg[4]; +} + +static inline void cec_msg_give_device_vendor_id(struct cec_msg *msg, + int reply) +{ + msg->len = 2; + msg->msg[1] = CEC_MSG_GIVE_DEVICE_VENDOR_ID; + msg->reply = reply ? CEC_MSG_DEVICE_VENDOR_ID : 0; +} + +static inline void cec_msg_vendor_command(struct cec_msg *msg, + __u8 size, const __u8 *vendor_cmd) +{ + if (size > 14) + size = 14; + msg->len = 2 + size; + msg->msg[1] = CEC_MSG_VENDOR_COMMAND; + memcpy(msg->msg + 2, vendor_cmd, size); +} + +static inline void cec_ops_vendor_command(const struct cec_msg *msg, + __u8 *size, + const __u8 **vendor_cmd) +{ + *size = msg->len - 2; + + if (*size > 14) + *size = 14; + *vendor_cmd = msg->msg + 2; +} + +static inline void cec_msg_vendor_command_with_id(struct cec_msg *msg, + __u32 vendor_id, __u8 size, + const __u8 *vendor_cmd) +{ + if (size > 11) + size = 11; + msg->len = 5 + size; + msg->msg[1] = CEC_MSG_VENDOR_COMMAND_WITH_ID; + msg->msg[2] = vendor_id >> 16; + msg->msg[3] = (vendor_id >> 8) & 0xff; + msg->msg[4] = vendor_id & 0xff; + memcpy(msg->msg + 5, vendor_cmd, size); +} + +static inline void cec_ops_vendor_command_with_id(const struct cec_msg *msg, + __u32 *vendor_id, __u8 *size, + const __u8 **vendor_cmd) +{ + *size = msg->len - 5; + + if (*size > 11) + *size = 11; + *vendor_id = (msg->msg[2] << 16) | (msg->msg[3] << 8) | msg->msg[4]; + *vendor_cmd = msg->msg + 5; +} + +static inline void cec_msg_vendor_remote_button_down(struct cec_msg *msg, + __u8 size, + const __u8 *rc_code) +{ + if (size > 14) + size = 14; + msg->len = 2 + size; + msg->msg[1] = CEC_MSG_VENDOR_REMOTE_BUTTON_DOWN; + memcpy(msg->msg + 2, rc_code, size); +} + +static inline void cec_ops_vendor_remote_button_down(const struct cec_msg *msg, + __u8 *size, + const __u8 **rc_code) +{ + *size = msg->len - 2; + + if (*size > 14) + *size = 14; + *rc_code = msg->msg + 2; +} + +static inline void cec_msg_vendor_remote_button_up(struct cec_msg *msg) +{ + msg->len = 2; + msg->msg[1] = CEC_MSG_VENDOR_REMOTE_BUTTON_UP; +} + + +/* OSD Display Feature */ +static inline void cec_msg_set_osd_string(struct cec_msg *msg, + __u8 disp_ctl, + const char *osd) +{ + unsigned int len = strlen(osd); + + if (len > 13) + len = 13; + msg->len = 3 + len; + msg->msg[1] = CEC_MSG_SET_OSD_STRING; + msg->msg[2] = disp_ctl; + memcpy(msg->msg + 3, osd, len); +} + +static inline void cec_ops_set_osd_string(const struct cec_msg *msg, + __u8 *disp_ctl, + char *osd) +{ + unsigned int len = msg->len > 3 ? msg->len - 3 : 0; + + *disp_ctl = msg->msg[2]; + if (len > 13) + len = 13; + memcpy(osd, msg->msg + 3, len); + osd[len] = '\0'; +} + + +/* Device OSD Transfer Feature */ +static inline void cec_msg_set_osd_name(struct cec_msg *msg, const char *name) +{ + unsigned int len = strlen(name); + + if (len > 14) + len = 14; + msg->len = 2 + len; + msg->msg[1] = CEC_MSG_SET_OSD_NAME; + memcpy(msg->msg + 2, name, len); +} + +static inline void cec_ops_set_osd_name(const struct cec_msg *msg, + char *name) +{ + unsigned int len = msg->len > 2 ? msg->len - 2 : 0; + + if (len > 14) + len = 14; + memcpy(name, msg->msg + 2, len); + name[len] = '\0'; +} + +static inline void cec_msg_give_osd_name(struct cec_msg *msg, + int reply) +{ + msg->len = 2; + msg->msg[1] = CEC_MSG_GIVE_OSD_NAME; + msg->reply = reply ? CEC_MSG_SET_OSD_NAME : 0; +} + + +/* Device Menu Control Feature */ +static inline void cec_msg_menu_status(struct cec_msg *msg, + __u8 menu_state) +{ + msg->len = 3; + msg->msg[1] = CEC_MSG_MENU_STATUS; + msg->msg[2] = menu_state; +} + +static inline void cec_ops_menu_status(const struct cec_msg *msg, + __u8 *menu_state) +{ + *menu_state = msg->msg[2]; +} + +static inline void cec_msg_menu_request(struct cec_msg *msg, + int reply, + __u8 menu_req) +{ + msg->len = 3; + msg->msg[1] = CEC_MSG_MENU_REQUEST; + msg->msg[2] = menu_req; + msg->reply = reply ? CEC_MSG_MENU_STATUS : 0; +} + +static inline void cec_ops_menu_request(const struct cec_msg *msg, + __u8 *menu_req) +{ + *menu_req = msg->msg[2]; +} + +struct cec_op_ui_command { + __u8 ui_cmd; + __u8 has_opt_arg; + union { + struct cec_op_channel_data channel_identifier; + __u8 ui_broadcast_type; + __u8 ui_sound_presentation_control; + __u8 play_mode; + __u8 ui_function_media; + __u8 ui_function_select_av_input; + __u8 ui_function_select_audio_input; + }; +}; + +static inline void cec_msg_user_control_pressed(struct cec_msg *msg, + const struct cec_op_ui_command *ui_cmd) +{ + msg->len = 3; + msg->msg[1] = CEC_MSG_USER_CONTROL_PRESSED; + msg->msg[2] = ui_cmd->ui_cmd; + if (!ui_cmd->has_opt_arg) + return; + switch (ui_cmd->ui_cmd) { + case 0x56: + case 0x57: + case 0x60: + case 0x68: + case 0x69: + case 0x6a: + /* The optional operand is one byte for all these ui commands */ + msg->len++; + msg->msg[3] = ui_cmd->play_mode; + break; + case 0x67: + msg->len += 4; + msg->msg[3] = (ui_cmd->channel_identifier.channel_number_fmt << 2) | + (ui_cmd->channel_identifier.major >> 8); + msg->msg[4] = ui_cmd->channel_identifier.major & 0xff; + msg->msg[5] = ui_cmd->channel_identifier.minor >> 8; + msg->msg[6] = ui_cmd->channel_identifier.minor & 0xff; + break; + } +} + +static inline void cec_ops_user_control_pressed(const struct cec_msg *msg, + struct cec_op_ui_command *ui_cmd) +{ + ui_cmd->ui_cmd = msg->msg[2]; + ui_cmd->has_opt_arg = 0; + if (msg->len == 3) + return; + switch (ui_cmd->ui_cmd) { + case 0x56: + case 0x57: + case 0x60: + case 0x68: + case 0x69: + case 0x6a: + /* The optional operand is one byte for all these ui commands */ + ui_cmd->play_mode = msg->msg[3]; + ui_cmd->has_opt_arg = 1; + break; + case 0x67: + if (msg->len < 7) + break; + ui_cmd->has_opt_arg = 1; + ui_cmd->channel_identifier.channel_number_fmt = msg->msg[3] >> 2; + ui_cmd->channel_identifier.major = ((msg->msg[3] & 3) << 6) | msg->msg[4]; + ui_cmd->channel_identifier.minor = (msg->msg[5] << 8) | msg->msg[6]; + break; + } +} + +static inline void cec_msg_user_control_released(struct cec_msg *msg) +{ + msg->len = 2; + msg->msg[1] = CEC_MSG_USER_CONTROL_RELEASED; +} + +/* Remote Control Passthrough Feature */ + +/* Power Status Feature */ +static inline void cec_msg_report_power_status(struct cec_msg *msg, + __u8 pwr_state) +{ + msg->len = 3; + msg->msg[1] = CEC_MSG_REPORT_POWER_STATUS; + msg->msg[2] = pwr_state; +} + +static inline void cec_ops_report_power_status(const struct cec_msg *msg, + __u8 *pwr_state) +{ + *pwr_state = msg->msg[2]; +} + +static inline void cec_msg_give_device_power_status(struct cec_msg *msg, + int reply) +{ + msg->len = 2; + msg->msg[1] = CEC_MSG_GIVE_DEVICE_POWER_STATUS; + msg->reply = reply ? CEC_MSG_REPORT_POWER_STATUS : 0; +} + +/* General Protocol Messages */ +static inline void cec_msg_feature_abort(struct cec_msg *msg, + __u8 abort_msg, __u8 reason) +{ + msg->len = 4; + msg->msg[1] = CEC_MSG_FEATURE_ABORT; + msg->msg[2] = abort_msg; + msg->msg[3] = reason; +} + +static inline void cec_ops_feature_abort(const struct cec_msg *msg, + __u8 *abort_msg, __u8 *reason) +{ + *abort_msg = msg->msg[2]; + *reason = msg->msg[3]; +} + +/* This changes the current message into a feature abort message */ +static inline void cec_msg_reply_feature_abort(struct cec_msg *msg, __u8 reason) +{ + cec_msg_set_reply_to(msg, msg); + msg->len = 4; + msg->msg[2] = msg->msg[1]; + msg->msg[3] = reason; + msg->msg[1] = CEC_MSG_FEATURE_ABORT; +} + +static inline void cec_msg_abort(struct cec_msg *msg) +{ + msg->len = 2; + msg->msg[1] = CEC_MSG_ABORT; +} + + +/* System Audio Control Feature */ +static inline void cec_msg_report_audio_status(struct cec_msg *msg, + __u8 aud_mute_status, + __u8 aud_vol_status) +{ + msg->len = 3; + msg->msg[1] = CEC_MSG_REPORT_AUDIO_STATUS; + msg->msg[2] = (aud_mute_status << 7) | (aud_vol_status & 0x7f); +} + +static inline void cec_ops_report_audio_status(const struct cec_msg *msg, + __u8 *aud_mute_status, + __u8 *aud_vol_status) +{ + *aud_mute_status = msg->msg[2] >> 7; + *aud_vol_status = msg->msg[2] & 0x7f; +} + +static inline void cec_msg_give_audio_status(struct cec_msg *msg, + int reply) +{ + msg->len = 2; + msg->msg[1] = CEC_MSG_GIVE_AUDIO_STATUS; + msg->reply = reply ? CEC_MSG_REPORT_AUDIO_STATUS : 0; +} + +static inline void cec_msg_set_system_audio_mode(struct cec_msg *msg, + __u8 sys_aud_status) +{ + msg->len = 3; + msg->msg[1] = CEC_MSG_SET_SYSTEM_AUDIO_MODE; + msg->msg[2] = sys_aud_status; +} + +static inline void cec_ops_set_system_audio_mode(const struct cec_msg *msg, + __u8 *sys_aud_status) +{ + *sys_aud_status = msg->msg[2]; +} + +static inline void cec_msg_system_audio_mode_request(struct cec_msg *msg, + int reply, + __u16 phys_addr) +{ + msg->len = phys_addr == 0xffff ? 2 : 4; + msg->msg[1] = CEC_MSG_SYSTEM_AUDIO_MODE_REQUEST; + msg->msg[2] = phys_addr >> 8; + msg->msg[3] = phys_addr & 0xff; + msg->reply = reply ? CEC_MSG_SET_SYSTEM_AUDIO_MODE : 0; + +} + +static inline void cec_ops_system_audio_mode_request(const struct cec_msg *msg, + __u16 *phys_addr) +{ + if (msg->len < 4) + *phys_addr = 0xffff; + else + *phys_addr = (msg->msg[2] << 8) | msg->msg[3]; +} + +static inline void cec_msg_system_audio_mode_status(struct cec_msg *msg, + __u8 sys_aud_status) +{ + msg->len = 3; + msg->msg[1] = CEC_MSG_SYSTEM_AUDIO_MODE_STATUS; + msg->msg[2] = sys_aud_status; +} + +static inline void cec_ops_system_audio_mode_status(const struct cec_msg *msg, + __u8 *sys_aud_status) +{ + *sys_aud_status = msg->msg[2]; +} + +static inline void cec_msg_give_system_audio_mode_status(struct cec_msg *msg, + int reply) +{ + msg->len = 2; + msg->msg[1] = CEC_MSG_GIVE_SYSTEM_AUDIO_MODE_STATUS; + msg->reply = reply ? CEC_MSG_SYSTEM_AUDIO_MODE_STATUS : 0; +} + +static inline void cec_msg_report_short_audio_descriptor(struct cec_msg *msg, + __u8 num_descriptors, + const __u32 *descriptors) +{ + unsigned int i; + + if (num_descriptors > 4) + num_descriptors = 4; + msg->len = 2 + num_descriptors * 3; + msg->msg[1] = CEC_MSG_REPORT_SHORT_AUDIO_DESCRIPTOR; + for (i = 0; i < num_descriptors; i++) { + msg->msg[2 + i * 3] = (descriptors[i] >> 16) & 0xff; + msg->msg[3 + i * 3] = (descriptors[i] >> 8) & 0xff; + msg->msg[4 + i * 3] = descriptors[i] & 0xff; + } +} + +static inline void cec_ops_report_short_audio_descriptor(const struct cec_msg *msg, + __u8 *num_descriptors, + __u32 *descriptors) +{ + unsigned int i; + + *num_descriptors = (msg->len - 2) / 3; + if (*num_descriptors > 4) + *num_descriptors = 4; + for (i = 0; i < *num_descriptors; i++) + descriptors[i] = (msg->msg[2 + i * 3] << 16) | + (msg->msg[3 + i * 3] << 8) | + msg->msg[4 + i * 3]; +} + +static inline void cec_msg_request_short_audio_descriptor(struct cec_msg *msg, + int reply, + __u8 num_descriptors, + const __u8 *audio_format_id, + const __u8 *audio_format_code) +{ + unsigned int i; + + if (num_descriptors > 4) + num_descriptors = 4; + msg->len = 2 + num_descriptors; + msg->msg[1] = CEC_MSG_REQUEST_SHORT_AUDIO_DESCRIPTOR; + msg->reply = reply ? CEC_MSG_REPORT_SHORT_AUDIO_DESCRIPTOR : 0; + for (i = 0; i < num_descriptors; i++) + msg->msg[2 + i] = (audio_format_id[i] << 6) | + (audio_format_code[i] & 0x3f); +} + +static inline void cec_ops_request_short_audio_descriptor(const struct cec_msg *msg, + __u8 *num_descriptors, + __u8 *audio_format_id, + __u8 *audio_format_code) +{ + unsigned int i; + + *num_descriptors = msg->len - 2; + if (*num_descriptors > 4) + *num_descriptors = 4; + for (i = 0; i < *num_descriptors; i++) { + audio_format_id[i] = msg->msg[2 + i] >> 6; + audio_format_code[i] = msg->msg[2 + i] & 0x3f; + } +} + + +/* Audio Rate Control Feature */ +static inline void cec_msg_set_audio_rate(struct cec_msg *msg, + __u8 audio_rate) +{ + msg->len = 3; + msg->msg[1] = CEC_MSG_SET_AUDIO_RATE; + msg->msg[2] = audio_rate; +} + +static inline void cec_ops_set_audio_rate(const struct cec_msg *msg, + __u8 *audio_rate) +{ + *audio_rate = msg->msg[2]; +} + + +/* Audio Return Channel Control Feature */ +static inline void cec_msg_report_arc_initiated(struct cec_msg *msg) +{ + msg->len = 2; + msg->msg[1] = CEC_MSG_REPORT_ARC_INITIATED; +} + +static inline void cec_msg_initiate_arc(struct cec_msg *msg, + int reply) +{ + msg->len = 2; + msg->msg[1] = CEC_MSG_INITIATE_ARC; + msg->reply = reply ? CEC_MSG_REPORT_ARC_INITIATED : 0; +} + +static inline void cec_msg_request_arc_initiation(struct cec_msg *msg, + int reply) +{ + msg->len = 2; + msg->msg[1] = CEC_MSG_REQUEST_ARC_INITIATION; + msg->reply = reply ? CEC_MSG_INITIATE_ARC : 0; +} + +static inline void cec_msg_report_arc_terminated(struct cec_msg *msg) +{ + msg->len = 2; + msg->msg[1] = CEC_MSG_REPORT_ARC_TERMINATED; +} + +static inline void cec_msg_terminate_arc(struct cec_msg *msg, + int reply) +{ + msg->len = 2; + msg->msg[1] = CEC_MSG_TERMINATE_ARC; + msg->reply = reply ? CEC_MSG_REPORT_ARC_TERMINATED : 0; +} + +static inline void cec_msg_request_arc_termination(struct cec_msg *msg, + int reply) +{ + msg->len = 2; + msg->msg[1] = CEC_MSG_REQUEST_ARC_TERMINATION; + msg->reply = reply ? CEC_MSG_TERMINATE_ARC : 0; +} + + +/* Dynamic Audio Lipsync Feature */ +/* Only for CEC 2.0 and up */ +static inline void cec_msg_report_current_latency(struct cec_msg *msg, + __u16 phys_addr, + __u8 video_latency, + __u8 low_latency_mode, + __u8 audio_out_compensated, + __u8 audio_out_delay) +{ + msg->len = 6; + msg->msg[0] |= 0xf; /* broadcast */ + msg->msg[1] = CEC_MSG_REPORT_CURRENT_LATENCY; + msg->msg[2] = phys_addr >> 8; + msg->msg[3] = phys_addr & 0xff; + msg->msg[4] = video_latency; + msg->msg[5] = (low_latency_mode << 2) | audio_out_compensated; + if (audio_out_compensated == 3) + msg->msg[msg->len++] = audio_out_delay; +} + +static inline void cec_ops_report_current_latency(const struct cec_msg *msg, + __u16 *phys_addr, + __u8 *video_latency, + __u8 *low_latency_mode, + __u8 *audio_out_compensated, + __u8 *audio_out_delay) +{ + *phys_addr = (msg->msg[2] << 8) | msg->msg[3]; + *video_latency = msg->msg[4]; + *low_latency_mode = (msg->msg[5] >> 2) & 1; + *audio_out_compensated = msg->msg[5] & 3; + if (*audio_out_compensated == 3 && msg->len >= 7) + *audio_out_delay = msg->msg[6]; + else + *audio_out_delay = 0; +} + +static inline void cec_msg_request_current_latency(struct cec_msg *msg, + int reply, + __u16 phys_addr) +{ + msg->len = 4; + msg->msg[0] |= 0xf; /* broadcast */ + msg->msg[1] = CEC_MSG_REQUEST_CURRENT_LATENCY; + msg->msg[2] = phys_addr >> 8; + msg->msg[3] = phys_addr & 0xff; + msg->reply = reply ? CEC_MSG_REPORT_CURRENT_LATENCY : 0; +} + +static inline void cec_ops_request_current_latency(const struct cec_msg *msg, + __u16 *phys_addr) +{ + *phys_addr = (msg->msg[2] << 8) | msg->msg[3]; +} + + +/* Capability Discovery and Control Feature */ +static inline void cec_msg_cdc_hec_inquire_state(struct cec_msg *msg, + __u16 phys_addr1, + __u16 phys_addr2) +{ + msg->len = 9; + msg->msg[0] |= 0xf; /* broadcast */ + msg->msg[1] = CEC_MSG_CDC_MESSAGE; + /* msg[2] and msg[3] (phys_addr) are filled in by the CEC framework */ + msg->msg[4] = CEC_MSG_CDC_HEC_INQUIRE_STATE; + msg->msg[5] = phys_addr1 >> 8; + msg->msg[6] = phys_addr1 & 0xff; + msg->msg[7] = phys_addr2 >> 8; + msg->msg[8] = phys_addr2 & 0xff; +} + +static inline void cec_ops_cdc_hec_inquire_state(const struct cec_msg *msg, + __u16 *phys_addr, + __u16 *phys_addr1, + __u16 *phys_addr2) +{ + *phys_addr = (msg->msg[2] << 8) | msg->msg[3]; + *phys_addr1 = (msg->msg[5] << 8) | msg->msg[6]; + *phys_addr2 = (msg->msg[7] << 8) | msg->msg[8]; +} + +static inline void cec_msg_cdc_hec_report_state(struct cec_msg *msg, + __u16 target_phys_addr, + __u8 hec_func_state, + __u8 host_func_state, + __u8 enc_func_state, + __u8 cdc_errcode, + __u8 has_field, + __u16 hec_field) +{ + msg->len = has_field ? 10 : 8; + msg->msg[0] |= 0xf; /* broadcast */ + msg->msg[1] = CEC_MSG_CDC_MESSAGE; + /* msg[2] and msg[3] (phys_addr) are filled in by the CEC framework */ + msg->msg[4] = CEC_MSG_CDC_HEC_REPORT_STATE; + msg->msg[5] = target_phys_addr >> 8; + msg->msg[6] = target_phys_addr & 0xff; + msg->msg[7] = (hec_func_state << 6) | + (host_func_state << 4) | + (enc_func_state << 2) | + cdc_errcode; + if (has_field) { + msg->msg[8] = hec_field >> 8; + msg->msg[9] = hec_field & 0xff; + } +} + +static inline void cec_ops_cdc_hec_report_state(const struct cec_msg *msg, + __u16 *phys_addr, + __u16 *target_phys_addr, + __u8 *hec_func_state, + __u8 *host_func_state, + __u8 *enc_func_state, + __u8 *cdc_errcode, + __u8 *has_field, + __u16 *hec_field) +{ + *phys_addr = (msg->msg[2] << 8) | msg->msg[3]; + *target_phys_addr = (msg->msg[5] << 8) | msg->msg[6]; + *hec_func_state = msg->msg[7] >> 6; + *host_func_state = (msg->msg[7] >> 4) & 3; + *enc_func_state = (msg->msg[7] >> 4) & 3; + *cdc_errcode = msg->msg[7] & 3; + *has_field = msg->len >= 10; + *hec_field = *has_field ? ((msg->msg[8] << 8) | msg->msg[9]) : 0; +} + +static inline void cec_msg_cdc_hec_set_state(struct cec_msg *msg, + __u16 phys_addr1, + __u16 phys_addr2, + __u8 hec_set_state, + __u16 phys_addr3, + __u16 phys_addr4, + __u16 phys_addr5) +{ + msg->len = 10; + msg->msg[0] |= 0xf; /* broadcast */ + msg->msg[1] = CEC_MSG_CDC_MESSAGE; + /* msg[2] and msg[3] (phys_addr) are filled in by the CEC framework */ + msg->msg[4] = CEC_MSG_CDC_HEC_INQUIRE_STATE; + msg->msg[5] = phys_addr1 >> 8; + msg->msg[6] = phys_addr1 & 0xff; + msg->msg[7] = phys_addr2 >> 8; + msg->msg[8] = phys_addr2 & 0xff; + msg->msg[9] = hec_set_state; + if (phys_addr3 != CEC_PHYS_ADDR_INVALID) { + msg->msg[msg->len++] = phys_addr3 >> 8; + msg->msg[msg->len++] = phys_addr3 & 0xff; + if (phys_addr4 != CEC_PHYS_ADDR_INVALID) { + msg->msg[msg->len++] = phys_addr4 >> 8; + msg->msg[msg->len++] = phys_addr4 & 0xff; + if (phys_addr5 != CEC_PHYS_ADDR_INVALID) { + msg->msg[msg->len++] = phys_addr5 >> 8; + msg->msg[msg->len++] = phys_addr5 & 0xff; + } + } + } +} + +static inline void cec_ops_cdc_hec_set_state(const struct cec_msg *msg, + __u16 *phys_addr, + __u16 *phys_addr1, + __u16 *phys_addr2, + __u8 *hec_set_state, + __u16 *phys_addr3, + __u16 *phys_addr4, + __u16 *phys_addr5) +{ + *phys_addr = (msg->msg[2] << 8) | msg->msg[3]; + *phys_addr1 = (msg->msg[5] << 8) | msg->msg[6]; + *phys_addr2 = (msg->msg[7] << 8) | msg->msg[8]; + *hec_set_state = msg->msg[9]; + *phys_addr3 = *phys_addr4 = *phys_addr5 = CEC_PHYS_ADDR_INVALID; + if (msg->len >= 12) + *phys_addr3 = (msg->msg[10] << 8) | msg->msg[11]; + if (msg->len >= 14) + *phys_addr4 = (msg->msg[12] << 8) | msg->msg[13]; + if (msg->len >= 16) + *phys_addr5 = (msg->msg[14] << 8) | msg->msg[15]; +} + +static inline void cec_msg_cdc_hec_set_state_adjacent(struct cec_msg *msg, + __u16 phys_addr1, + __u8 hec_set_state) +{ + msg->len = 8; + msg->msg[0] |= 0xf; /* broadcast */ + msg->msg[1] = CEC_MSG_CDC_MESSAGE; + /* msg[2] and msg[3] (phys_addr) are filled in by the CEC framework */ + msg->msg[4] = CEC_MSG_CDC_HEC_SET_STATE_ADJACENT; + msg->msg[5] = phys_addr1 >> 8; + msg->msg[6] = phys_addr1 & 0xff; + msg->msg[7] = hec_set_state; +} + +static inline void cec_ops_cdc_hec_set_state_adjacent(const struct cec_msg *msg, + __u16 *phys_addr, + __u16 *phys_addr1, + __u8 *hec_set_state) +{ + *phys_addr = (msg->msg[2] << 8) | msg->msg[3]; + *phys_addr1 = (msg->msg[5] << 8) | msg->msg[6]; + *hec_set_state = msg->msg[7]; +} + +static inline void cec_msg_cdc_hec_request_deactivation(struct cec_msg *msg, + __u16 phys_addr1, + __u16 phys_addr2, + __u16 phys_addr3) +{ + msg->len = 11; + msg->msg[0] |= 0xf; /* broadcast */ + msg->msg[1] = CEC_MSG_CDC_MESSAGE; + /* msg[2] and msg[3] (phys_addr) are filled in by the CEC framework */ + msg->msg[4] = CEC_MSG_CDC_HEC_REQUEST_DEACTIVATION; + msg->msg[5] = phys_addr1 >> 8; + msg->msg[6] = phys_addr1 & 0xff; + msg->msg[7] = phys_addr2 >> 8; + msg->msg[8] = phys_addr2 & 0xff; + msg->msg[9] = phys_addr3 >> 8; + msg->msg[10] = phys_addr3 & 0xff; +} + +static inline void cec_ops_cdc_hec_request_deactivation(const struct cec_msg *msg, + __u16 *phys_addr, + __u16 *phys_addr1, + __u16 *phys_addr2, + __u16 *phys_addr3) +{ + *phys_addr = (msg->msg[2] << 8) | msg->msg[3]; + *phys_addr1 = (msg->msg[5] << 8) | msg->msg[6]; + *phys_addr2 = (msg->msg[7] << 8) | msg->msg[8]; + *phys_addr3 = (msg->msg[9] << 8) | msg->msg[10]; +} + +static inline void cec_msg_cdc_hec_notify_alive(struct cec_msg *msg) +{ + msg->len = 5; + msg->msg[0] |= 0xf; /* broadcast */ + msg->msg[1] = CEC_MSG_CDC_MESSAGE; + /* msg[2] and msg[3] (phys_addr) are filled in by the CEC framework */ + msg->msg[4] = CEC_MSG_CDC_HEC_NOTIFY_ALIVE; +} + +static inline void cec_ops_cdc_hec_notify_alive(const struct cec_msg *msg, + __u16 *phys_addr) +{ + *phys_addr = (msg->msg[2] << 8) | msg->msg[3]; +} + +static inline void cec_msg_cdc_hec_discover(struct cec_msg *msg) +{ + msg->len = 5; + msg->msg[0] |= 0xf; /* broadcast */ + msg->msg[1] = CEC_MSG_CDC_MESSAGE; + /* msg[2] and msg[3] (phys_addr) are filled in by the CEC framework */ + msg->msg[4] = CEC_MSG_CDC_HEC_DISCOVER; +} + +static inline void cec_ops_cdc_hec_discover(const struct cec_msg *msg, + __u16 *phys_addr) +{ + *phys_addr = (msg->msg[2] << 8) | msg->msg[3]; +} + +static inline void cec_msg_cdc_hpd_set_state(struct cec_msg *msg, + __u8 input_port, + __u8 hpd_state) +{ + msg->len = 6; + msg->msg[0] |= 0xf; /* broadcast */ + msg->msg[1] = CEC_MSG_CDC_MESSAGE; + /* msg[2] and msg[3] (phys_addr) are filled in by the CEC framework */ + msg->msg[4] = CEC_MSG_CDC_HPD_SET_STATE; + msg->msg[5] = (input_port << 4) | hpd_state; +} + +static inline void cec_ops_cdc_hpd_set_state(const struct cec_msg *msg, + __u16 *phys_addr, + __u8 *input_port, + __u8 *hpd_state) +{ + *phys_addr = (msg->msg[2] << 8) | msg->msg[3]; + *input_port = msg->msg[5] >> 4; + *hpd_state = msg->msg[5] & 0xf; +} + +static inline void cec_msg_cdc_hpd_report_state(struct cec_msg *msg, + __u8 hpd_state, + __u8 hpd_error) +{ + msg->len = 6; + msg->msg[0] |= 0xf; /* broadcast */ + msg->msg[1] = CEC_MSG_CDC_MESSAGE; + /* msg[2] and msg[3] (phys_addr) are filled in by the CEC framework */ + msg->msg[4] = CEC_MSG_CDC_HPD_REPORT_STATE; + msg->msg[5] = (hpd_state << 4) | hpd_error; +} + +static inline void cec_ops_cdc_hpd_report_state(const struct cec_msg *msg, + __u16 *phys_addr, + __u8 *hpd_state, + __u8 *hpd_error) +{ + *phys_addr = (msg->msg[2] << 8) | msg->msg[3]; + *hpd_state = msg->msg[5] >> 4; + *hpd_error = msg->msg[5] & 0xf; +} + +#endif diff --git a/include/uapi/linux/cec.h b/include/uapi/linux/cec.h new file mode 100644 index 000000000000..af6682f5ea85 --- /dev/null +++ b/include/uapi/linux/cec.h @@ -0,0 +1,1076 @@ +/* + * cec - HDMI Consumer Electronics Control public header + * + * Copyright 2016 Cisco Systems, Inc. and/or its affiliates. All rights reserved. + * + * This program is free software; you may redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * Alternatively you can redistribute this file under the terms of the + * BSD license as stated below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. The names of its contributors may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef _CEC_UAPI_H +#define _CEC_UAPI_H + +#include <linux/types.h> +#include <linux/string.h> + +#define CEC_MAX_MSG_SIZE 16 + +/** + * struct cec_msg - CEC message structure. + * @tx_ts: Timestamp in nanoseconds using CLOCK_MONOTONIC. Set by the + * driver when the message transmission has finished. + * @rx_ts: Timestamp in nanoseconds using CLOCK_MONOTONIC. Set by the + * driver when the message was received. + * @len: Length in bytes of the message. + * @timeout: The timeout (in ms) that is used to timeout CEC_RECEIVE. + * Set to 0 if you want to wait forever. This timeout can also be + * used with CEC_TRANSMIT as the timeout for waiting for a reply. + * If 0, then it will use a 1 second timeout instead of waiting + * forever as is done with CEC_RECEIVE. + * @sequence: The framework assigns a sequence number to messages that are + * sent. This can be used to track replies to previously sent + * messages. + * @flags: Set to 0. + * @msg: The message payload. + * @reply: This field is ignored with CEC_RECEIVE and is only used by + * CEC_TRANSMIT. If non-zero, then wait for a reply with this + * opcode. Set to CEC_MSG_FEATURE_ABORT if you want to wait for + * a possible ABORT reply. If there was an error when sending the + * msg or FeatureAbort was returned, then reply is set to 0. + * If reply is non-zero upon return, then len/msg are set to + * the received message. + * If reply is zero upon return and status has the + * CEC_TX_STATUS_FEATURE_ABORT bit set, then len/msg are set to + * the received feature abort message. + * If reply is zero upon return and status has the + * CEC_TX_STATUS_MAX_RETRIES bit set, then no reply was seen at + * all. If reply is non-zero for CEC_TRANSMIT and the message is a + * broadcast, then -EINVAL is returned. + * if reply is non-zero, then timeout is set to 1000 (the required + * maximum response time). + * @rx_status: The message receive status bits. Set by the driver. + * @tx_status: The message transmit status bits. Set by the driver. + * @tx_arb_lost_cnt: The number of 'Arbitration Lost' events. Set by the driver. + * @tx_nack_cnt: The number of 'Not Acknowledged' events. Set by the driver. + * @tx_low_drive_cnt: The number of 'Low Drive Detected' events. Set by the + * driver. + * @tx_error_cnt: The number of 'Error' events. Set by the driver. + */ +struct cec_msg { + __u64 tx_ts; + __u64 rx_ts; + __u32 len; + __u32 timeout; + __u32 sequence; + __u32 flags; + __u8 msg[CEC_MAX_MSG_SIZE]; + __u8 reply; + __u8 rx_status; + __u8 tx_status; + __u8 tx_arb_lost_cnt; + __u8 tx_nack_cnt; + __u8 tx_low_drive_cnt; + __u8 tx_error_cnt; +}; + +/** + * cec_msg_initiator - return the initiator's logical address. + * @msg: the message structure + */ +static inline __u8 cec_msg_initiator(const struct cec_msg *msg) +{ + return msg->msg[0] >> 4; +} + +/** + * cec_msg_destination - return the destination's logical address. + * @msg: the message structure + */ +static inline __u8 cec_msg_destination(const struct cec_msg *msg) +{ + return msg->msg[0] & 0xf; +} + +/** + * cec_msg_opcode - return the opcode of the message, -1 for poll + * @msg: the message structure + */ +static inline int cec_msg_opcode(const struct cec_msg *msg) +{ + return msg->len > 1 ? msg->msg[1] : -1; +} + +/** + * cec_msg_is_broadcast - return true if this is a broadcast message. + * @msg: the message structure + */ +static inline int cec_msg_is_broadcast(const struct cec_msg *msg) +{ + return (msg->msg[0] & 0xf) == 0xf; +} + +/** + * cec_msg_init - initialize the message structure. + * @msg: the message structure + * @initiator: the logical address of the initiator + * @destination:the logical address of the destination (0xf for broadcast) + * + * The whole structure is zeroed, the len field is set to 1 (i.e. a poll + * message) and the initiator and destination are filled in. + */ +static inline void cec_msg_init(struct cec_msg *msg, + __u8 initiator, __u8 destination) +{ + memset(msg, 0, sizeof(*msg)); + msg->msg[0] = (initiator << 4) | destination; + msg->len = 1; +} + +/** + * cec_msg_set_reply_to - fill in destination/initiator in a reply message. + * @msg: the message structure for the reply + * @orig: the original message structure + * + * Set the msg destination to the orig initiator and the msg initiator to the + * orig destination. Note that msg and orig may be the same pointer, in which + * case the change is done in place. + */ +static inline void cec_msg_set_reply_to(struct cec_msg *msg, + struct cec_msg *orig) +{ + /* The destination becomes the initiator and vice versa */ + msg->msg[0] = (cec_msg_destination(orig) << 4) | + cec_msg_initiator(orig); + msg->reply = msg->timeout = 0; +} + +/* cec_msg flags field */ +#define CEC_MSG_FL_REPLY_TO_FOLLOWERS (1 << 0) + +/* cec_msg tx/rx_status field */ +#define CEC_TX_STATUS_OK (1 << 0) +#define CEC_TX_STATUS_ARB_LOST (1 << 1) +#define CEC_TX_STATUS_NACK (1 << 2) +#define CEC_TX_STATUS_LOW_DRIVE (1 << 3) +#define CEC_TX_STATUS_ERROR (1 << 4) +#define CEC_TX_STATUS_MAX_RETRIES (1 << 5) + +#define CEC_RX_STATUS_OK (1 << 0) +#define CEC_RX_STATUS_TIMEOUT (1 << 1) +#define CEC_RX_STATUS_FEATURE_ABORT (1 << 2) + +static inline int cec_msg_status_is_ok(const struct cec_msg *msg) +{ + if (msg->tx_status && !(msg->tx_status & CEC_TX_STATUS_OK)) + return 0; + if (msg->rx_status && !(msg->rx_status & CEC_RX_STATUS_OK)) + return 0; + if (!msg->tx_status && !msg->rx_status) + return 0; + return !(msg->rx_status & CEC_RX_STATUS_FEATURE_ABORT); +} + +#define CEC_LOG_ADDR_INVALID 0xff +#define CEC_PHYS_ADDR_INVALID 0xffff + +/* + * The maximum number of logical addresses one device can be assigned to. + * The CEC 2.0 spec allows for only 2 logical addresses at the moment. The + * Analog Devices CEC hardware supports 3. So let's go wild and go for 4. + */ +#define CEC_MAX_LOG_ADDRS 4 + +/* The logical addresses defined by CEC 2.0 */ +#define CEC_LOG_ADDR_TV 0 +#define CEC_LOG_ADDR_RECORD_1 1 +#define CEC_LOG_ADDR_RECORD_2 2 +#define CEC_LOG_ADDR_TUNER_1 3 +#define CEC_LOG_ADDR_PLAYBACK_1 4 +#define CEC_LOG_ADDR_AUDIOSYSTEM 5 +#define CEC_LOG_ADDR_TUNER_2 6 +#define CEC_LOG_ADDR_TUNER_3 7 +#define CEC_LOG_ADDR_PLAYBACK_2 8 +#define CEC_LOG_ADDR_RECORD_3 9 +#define CEC_LOG_ADDR_TUNER_4 10 +#define CEC_LOG_ADDR_PLAYBACK_3 11 +#define CEC_LOG_ADDR_BACKUP_1 12 +#define CEC_LOG_ADDR_BACKUP_2 13 +#define CEC_LOG_ADDR_SPECIFIC 14 +#define CEC_LOG_ADDR_UNREGISTERED 15 /* as initiator address */ +#define CEC_LOG_ADDR_BROADCAST 15 /* ad destination address */ + +/* The logical address types that the CEC device wants to claim */ +#define CEC_LOG_ADDR_TYPE_TV 0 +#define CEC_LOG_ADDR_TYPE_RECORD 1 +#define CEC_LOG_ADDR_TYPE_TUNER 2 +#define CEC_LOG_ADDR_TYPE_PLAYBACK 3 +#define CEC_LOG_ADDR_TYPE_AUDIOSYSTEM 4 +#define CEC_LOG_ADDR_TYPE_SPECIFIC 5 +#define CEC_LOG_ADDR_TYPE_UNREGISTERED 6 +/* + * Switches should use UNREGISTERED. + * Processors should use SPECIFIC. + */ + +#define CEC_LOG_ADDR_MASK_TV (1 << CEC_LOG_ADDR_TV) +#define CEC_LOG_ADDR_MASK_RECORD ((1 << CEC_LOG_ADDR_RECORD_1) | \ + (1 << CEC_LOG_ADDR_RECORD_2) | \ + (1 << CEC_LOG_ADDR_RECORD_3)) +#define CEC_LOG_ADDR_MASK_TUNER ((1 << CEC_LOG_ADDR_TUNER_1) | \ + (1 << CEC_LOG_ADDR_TUNER_2) | \ + (1 << CEC_LOG_ADDR_TUNER_3) | \ + (1 << CEC_LOG_ADDR_TUNER_4)) +#define CEC_LOG_ADDR_MASK_PLAYBACK ((1 << CEC_LOG_ADDR_PLAYBACK_1) | \ + (1 << CEC_LOG_ADDR_PLAYBACK_2) | \ + (1 << CEC_LOG_ADDR_PLAYBACK_3)) +#define CEC_LOG_ADDR_MASK_AUDIOSYSTEM (1 << CEC_LOG_ADDR_AUDIOSYSTEM) +#define CEC_LOG_ADDR_MASK_BACKUP ((1 << CEC_LOG_ADDR_BACKUP_1) | \ + (1 << CEC_LOG_ADDR_BACKUP_2)) +#define CEC_LOG_ADDR_MASK_SPECIFIC (1 << CEC_LOG_ADDR_SPECIFIC) +#define CEC_LOG_ADDR_MASK_UNREGISTERED (1 << CEC_LOG_ADDR_UNREGISTERED) + +static inline int cec_has_tv(__u16 log_addr_mask) +{ + return log_addr_mask & CEC_LOG_ADDR_MASK_TV; +} + +static inline int cec_has_record(__u16 log_addr_mask) +{ + return log_addr_mask & CEC_LOG_ADDR_MASK_RECORD; +} + +static inline int cec_has_tuner(__u16 log_addr_mask) +{ + return log_addr_mask & CEC_LOG_ADDR_MASK_TUNER; +} + +static inline int cec_has_playback(__u16 log_addr_mask) +{ + return log_addr_mask & CEC_LOG_ADDR_MASK_PLAYBACK; +} + +static inline int cec_has_audiosystem(__u16 log_addr_mask) +{ + return log_addr_mask & CEC_LOG_ADDR_MASK_AUDIOSYSTEM; +} + +static inline int cec_has_backup(__u16 log_addr_mask) +{ + return log_addr_mask & CEC_LOG_ADDR_MASK_BACKUP; +} + +static inline int cec_has_specific(__u16 log_addr_mask) +{ + return log_addr_mask & CEC_LOG_ADDR_MASK_SPECIFIC; +} + +static inline int cec_is_unregistered(__u16 log_addr_mask) +{ + return log_addr_mask & CEC_LOG_ADDR_MASK_UNREGISTERED; +} + +static inline int cec_is_unconfigured(__u16 log_addr_mask) +{ + return log_addr_mask == 0; +} + +/* + * Use this if there is no vendor ID (CEC_G_VENDOR_ID) or if the vendor ID + * should be disabled (CEC_S_VENDOR_ID) + */ +#define CEC_VENDOR_ID_NONE 0xffffffff + +/* The message handling modes */ +/* Modes for initiator */ +#define CEC_MODE_NO_INITIATOR (0x0 << 0) +#define CEC_MODE_INITIATOR (0x1 << 0) +#define CEC_MODE_EXCL_INITIATOR (0x2 << 0) +#define CEC_MODE_INITIATOR_MSK 0x0f + +/* Modes for follower */ +#define CEC_MODE_NO_FOLLOWER (0x0 << 4) +#define CEC_MODE_FOLLOWER (0x1 << 4) +#define CEC_MODE_EXCL_FOLLOWER (0x2 << 4) +#define CEC_MODE_EXCL_FOLLOWER_PASSTHRU (0x3 << 4) +#define CEC_MODE_MONITOR_PIN (0xd << 4) +#define CEC_MODE_MONITOR (0xe << 4) +#define CEC_MODE_MONITOR_ALL (0xf << 4) +#define CEC_MODE_FOLLOWER_MSK 0xf0 + +/* Userspace has to configure the physical address */ +#define CEC_CAP_PHYS_ADDR (1 << 0) +/* Userspace has to configure the logical addresses */ +#define CEC_CAP_LOG_ADDRS (1 << 1) +/* Userspace can transmit messages (and thus become follower as well) */ +#define CEC_CAP_TRANSMIT (1 << 2) +/* + * Passthrough all messages instead of processing them. + */ +#define CEC_CAP_PASSTHROUGH (1 << 3) +/* Supports remote control */ +#define CEC_CAP_RC (1 << 4) +/* Hardware can monitor all messages, not just directed and broadcast. */ +#define CEC_CAP_MONITOR_ALL (1 << 5) +/* Hardware can use CEC only if the HDMI HPD pin is high. */ +#define CEC_CAP_NEEDS_HPD (1 << 6) +/* Hardware can monitor CEC pin transitions */ +#define CEC_CAP_MONITOR_PIN (1 << 7) + +/** + * struct cec_caps - CEC capabilities structure. + * @driver: name of the CEC device driver. + * @name: name of the CEC device. @driver + @name must be unique. + * @available_log_addrs: number of available logical addresses. + * @capabilities: capabilities of the CEC adapter. + * @version: version of the CEC adapter framework. + */ +struct cec_caps { + char driver[32]; + char name[32]; + __u32 available_log_addrs; + __u32 capabilities; + __u32 version; +}; + +/** + * struct cec_log_addrs - CEC logical addresses structure. + * @log_addr: the claimed logical addresses. Set by the driver. + * @log_addr_mask: current logical address mask. Set by the driver. + * @cec_version: the CEC version that the adapter should implement. Set by the + * caller. + * @num_log_addrs: how many logical addresses should be claimed. Set by the + * caller. + * @vendor_id: the vendor ID of the device. Set by the caller. + * @flags: flags. + * @osd_name: the OSD name of the device. Set by the caller. + * @primary_device_type: the primary device type for each logical address. + * Set by the caller. + * @log_addr_type: the logical address types. Set by the caller. + * @all_device_types: CEC 2.0: all device types represented by the logical + * address. Set by the caller. + * @features: CEC 2.0: The logical address features. Set by the caller. + */ +struct cec_log_addrs { + __u8 log_addr[CEC_MAX_LOG_ADDRS]; + __u16 log_addr_mask; + __u8 cec_version; + __u8 num_log_addrs; + __u32 vendor_id; + __u32 flags; + char osd_name[15]; + __u8 primary_device_type[CEC_MAX_LOG_ADDRS]; + __u8 log_addr_type[CEC_MAX_LOG_ADDRS]; + + /* CEC 2.0 */ + __u8 all_device_types[CEC_MAX_LOG_ADDRS]; + __u8 features[CEC_MAX_LOG_ADDRS][12]; +}; + +/* Allow a fallback to unregistered */ +#define CEC_LOG_ADDRS_FL_ALLOW_UNREG_FALLBACK (1 << 0) +/* Passthrough RC messages to the input subsystem */ +#define CEC_LOG_ADDRS_FL_ALLOW_RC_PASSTHRU (1 << 1) +/* CDC-Only device: supports only CDC messages */ +#define CEC_LOG_ADDRS_FL_CDC_ONLY (1 << 2) + +/* Events */ + +/* Event that occurs when the adapter state changes */ +#define CEC_EVENT_STATE_CHANGE 1 +/* + * This event is sent when messages are lost because the application + * didn't empty the message queue in time + */ +#define CEC_EVENT_LOST_MSGS 2 +#define CEC_EVENT_PIN_CEC_LOW 3 +#define CEC_EVENT_PIN_CEC_HIGH 4 +#define CEC_EVENT_PIN_HPD_LOW 5 +#define CEC_EVENT_PIN_HPD_HIGH 6 + +#define CEC_EVENT_FL_INITIAL_STATE (1 << 0) +#define CEC_EVENT_FL_DROPPED_EVENTS (1 << 1) + +/** + * struct cec_event_state_change - used when the CEC adapter changes state. + * @phys_addr: the current physical address + * @log_addr_mask: the current logical address mask + */ +struct cec_event_state_change { + __u16 phys_addr; + __u16 log_addr_mask; +}; + +/** + * struct cec_event_lost_msgs - tells you how many messages were lost. + * @lost_msgs: how many messages were lost. + */ +struct cec_event_lost_msgs { + __u32 lost_msgs; +}; + +/** + * struct cec_event - CEC event structure + * @ts: the timestamp of when the event was sent. + * @event: the event. + * array. + * @state_change: the event payload for CEC_EVENT_STATE_CHANGE. + * @lost_msgs: the event payload for CEC_EVENT_LOST_MSGS. + * @raw: array to pad the union. + */ +struct cec_event { + __u64 ts; + __u32 event; + __u32 flags; + union { + struct cec_event_state_change state_change; + struct cec_event_lost_msgs lost_msgs; + __u32 raw[16]; + }; +}; + +/* ioctls */ + +/* Adapter capabilities */ +#define CEC_ADAP_G_CAPS _IOWR('a', 0, struct cec_caps) + +/* + * phys_addr is either 0 (if this is the CEC root device) + * or a valid physical address obtained from the sink's EDID + * as read by this CEC device (if this is a source device) + * or a physical address obtained and modified from a sink + * EDID and used for a sink CEC device. + * If nothing is connected, then phys_addr is 0xffff. + * See HDMI 1.4b, section 8.7 (Physical Address). + * + * The CEC_ADAP_S_PHYS_ADDR ioctl may not be available if that is handled + * internally. + */ +#define CEC_ADAP_G_PHYS_ADDR _IOR('a', 1, __u16) +#define CEC_ADAP_S_PHYS_ADDR _IOW('a', 2, __u16) + +/* + * Configure the CEC adapter. It sets the device type and which + * logical types it will try to claim. It will return which + * logical addresses it could actually claim. + * An error is returned if the adapter is disabled or if there + * is no physical address assigned. + */ + +#define CEC_ADAP_G_LOG_ADDRS _IOR('a', 3, struct cec_log_addrs) +#define CEC_ADAP_S_LOG_ADDRS _IOWR('a', 4, struct cec_log_addrs) + +/* Transmit/receive a CEC command */ +#define CEC_TRANSMIT _IOWR('a', 5, struct cec_msg) +#define CEC_RECEIVE _IOWR('a', 6, struct cec_msg) + +/* Dequeue CEC events */ +#define CEC_DQEVENT _IOWR('a', 7, struct cec_event) + +/* + * Get and set the message handling mode for this filehandle. + */ +#define CEC_G_MODE _IOR('a', 8, __u32) +#define CEC_S_MODE _IOW('a', 9, __u32) + +/* + * The remainder of this header defines all CEC messages and operands. + * The format matters since it the cec-ctl utility parses it to generate + * code for implementing all these messages. + * + * Comments ending with 'Feature' group messages for each feature. + * If messages are part of multiple features, then the "Has also" + * comment is used to list the previously defined messages that are + * supported by the feature. + * + * Before operands are defined a comment is added that gives the + * name of the operand and in brackets the variable name of the + * corresponding argument in the cec-funcs.h function. + */ + +/* Messages */ + +/* One Touch Play Feature */ +#define CEC_MSG_ACTIVE_SOURCE 0x82 +#define CEC_MSG_IMAGE_VIEW_ON 0x04 +#define CEC_MSG_TEXT_VIEW_ON 0x0d + + +/* Routing Control Feature */ + +/* + * Has also: + * CEC_MSG_ACTIVE_SOURCE + */ + +#define CEC_MSG_INACTIVE_SOURCE 0x9d +#define CEC_MSG_REQUEST_ACTIVE_SOURCE 0x85 +#define CEC_MSG_ROUTING_CHANGE 0x80 +#define CEC_MSG_ROUTING_INFORMATION 0x81 +#define CEC_MSG_SET_STREAM_PATH 0x86 + + +/* Standby Feature */ +#define CEC_MSG_STANDBY 0x36 + + +/* One Touch Record Feature */ +#define CEC_MSG_RECORD_OFF 0x0b +#define CEC_MSG_RECORD_ON 0x09 +/* Record Source Type Operand (rec_src_type) */ +#define CEC_OP_RECORD_SRC_OWN 1 +#define CEC_OP_RECORD_SRC_DIGITAL 2 +#define CEC_OP_RECORD_SRC_ANALOG 3 +#define CEC_OP_RECORD_SRC_EXT_PLUG 4 +#define CEC_OP_RECORD_SRC_EXT_PHYS_ADDR 5 +/* Service Identification Method Operand (service_id_method) */ +#define CEC_OP_SERVICE_ID_METHOD_BY_DIG_ID 0 +#define CEC_OP_SERVICE_ID_METHOD_BY_CHANNEL 1 +/* Digital Service Broadcast System Operand (dig_bcast_system) */ +#define CEC_OP_DIG_SERVICE_BCAST_SYSTEM_ARIB_GEN 0x00 +#define CEC_OP_DIG_SERVICE_BCAST_SYSTEM_ATSC_GEN 0x01 +#define CEC_OP_DIG_SERVICE_BCAST_SYSTEM_DVB_GEN 0x02 +#define CEC_OP_DIG_SERVICE_BCAST_SYSTEM_ARIB_BS 0x08 +#define CEC_OP_DIG_SERVICE_BCAST_SYSTEM_ARIB_CS 0x09 +#define CEC_OP_DIG_SERVICE_BCAST_SYSTEM_ARIB_T 0x0a +#define CEC_OP_DIG_SERVICE_BCAST_SYSTEM_ATSC_CABLE 0x10 +#define CEC_OP_DIG_SERVICE_BCAST_SYSTEM_ATSC_SAT 0x11 +#define CEC_OP_DIG_SERVICE_BCAST_SYSTEM_ATSC_T 0x12 +#define CEC_OP_DIG_SERVICE_BCAST_SYSTEM_DVB_C 0x18 +#define CEC_OP_DIG_SERVICE_BCAST_SYSTEM_DVB_S 0x19 +#define CEC_OP_DIG_SERVICE_BCAST_SYSTEM_DVB_S2 0x1a +#define CEC_OP_DIG_SERVICE_BCAST_SYSTEM_DVB_T 0x1b +/* Analogue Broadcast Type Operand (ana_bcast_type) */ +#define CEC_OP_ANA_BCAST_TYPE_CABLE 0 +#define CEC_OP_ANA_BCAST_TYPE_SATELLITE 1 +#define CEC_OP_ANA_BCAST_TYPE_TERRESTRIAL 2 +/* Broadcast System Operand (bcast_system) */ +#define CEC_OP_BCAST_SYSTEM_PAL_BG 0x00 +#define CEC_OP_BCAST_SYSTEM_SECAM_LQ 0x01 /* SECAM L' */ +#define CEC_OP_BCAST_SYSTEM_PAL_M 0x02 +#define CEC_OP_BCAST_SYSTEM_NTSC_M 0x03 +#define CEC_OP_BCAST_SYSTEM_PAL_I 0x04 +#define CEC_OP_BCAST_SYSTEM_SECAM_DK 0x05 +#define CEC_OP_BCAST_SYSTEM_SECAM_BG 0x06 +#define CEC_OP_BCAST_SYSTEM_SECAM_L 0x07 +#define CEC_OP_BCAST_SYSTEM_PAL_DK 0x08 +#define CEC_OP_BCAST_SYSTEM_OTHER 0x1f +/* Channel Number Format Operand (channel_number_fmt) */ +#define CEC_OP_CHANNEL_NUMBER_FMT_1_PART 0x01 +#define CEC_OP_CHANNEL_NUMBER_FMT_2_PART 0x02 + +#define CEC_MSG_RECORD_STATUS 0x0a +/* Record Status Operand (rec_status) */ +#define CEC_OP_RECORD_STATUS_CUR_SRC 0x01 +#define CEC_OP_RECORD_STATUS_DIG_SERVICE 0x02 +#define CEC_OP_RECORD_STATUS_ANA_SERVICE 0x03 +#define CEC_OP_RECORD_STATUS_EXT_INPUT 0x04 +#define CEC_OP_RECORD_STATUS_NO_DIG_SERVICE 0x05 +#define CEC_OP_RECORD_STATUS_NO_ANA_SERVICE 0x06 +#define CEC_OP_RECORD_STATUS_NO_SERVICE 0x07 +#define CEC_OP_RECORD_STATUS_INVALID_EXT_PLUG 0x09 +#define CEC_OP_RECORD_STATUS_INVALID_EXT_PHYS_ADDR 0x0a +#define CEC_OP_RECORD_STATUS_UNSUP_CA 0x0b +#define CEC_OP_RECORD_STATUS_NO_CA_ENTITLEMENTS 0x0c +#define CEC_OP_RECORD_STATUS_CANT_COPY_SRC 0x0d +#define CEC_OP_RECORD_STATUS_NO_MORE_COPIES 0x0e +#define CEC_OP_RECORD_STATUS_NO_MEDIA 0x10 +#define CEC_OP_RECORD_STATUS_PLAYING 0x11 +#define CEC_OP_RECORD_STATUS_ALREADY_RECORDING 0x12 +#define CEC_OP_RECORD_STATUS_MEDIA_PROT 0x13 +#define CEC_OP_RECORD_STATUS_NO_SIGNAL 0x14 +#define CEC_OP_RECORD_STATUS_MEDIA_PROBLEM 0x15 +#define CEC_OP_RECORD_STATUS_NO_SPACE 0x16 +#define CEC_OP_RECORD_STATUS_PARENTAL_LOCK 0x17 +#define CEC_OP_RECORD_STATUS_TERMINATED_OK 0x1a +#define CEC_OP_RECORD_STATUS_ALREADY_TERM 0x1b +#define CEC_OP_RECORD_STATUS_OTHER 0x1f + +#define CEC_MSG_RECORD_TV_SCREEN 0x0f + + +/* Timer Programming Feature */ +#define CEC_MSG_CLEAR_ANALOGUE_TIMER 0x33 +/* Recording Sequence Operand (recording_seq) */ +#define CEC_OP_REC_SEQ_SUNDAY 0x01 +#define CEC_OP_REC_SEQ_MONDAY 0x02 +#define CEC_OP_REC_SEQ_TUESDAY 0x04 +#define CEC_OP_REC_SEQ_WEDNESDAY 0x08 +#define CEC_OP_REC_SEQ_THURSDAY 0x10 +#define CEC_OP_REC_SEQ_FRIDAY 0x20 +#define CEC_OP_REC_SEQ_SATERDAY 0x40 +#define CEC_OP_REC_SEQ_ONCE_ONLY 0x00 + +#define CEC_MSG_CLEAR_DIGITAL_TIMER 0x99 + +#define CEC_MSG_CLEAR_EXT_TIMER 0xa1 +/* External Source Specifier Operand (ext_src_spec) */ +#define CEC_OP_EXT_SRC_PLUG 0x04 +#define CEC_OP_EXT_SRC_PHYS_ADDR 0x05 + +#define CEC_MSG_SET_ANALOGUE_TIMER 0x34 +#define CEC_MSG_SET_DIGITAL_TIMER 0x97 +#define CEC_MSG_SET_EXT_TIMER 0xa2 + +#define CEC_MSG_SET_TIMER_PROGRAM_TITLE 0x67 +#define CEC_MSG_TIMER_CLEARED_STATUS 0x43 +/* Timer Cleared Status Data Operand (timer_cleared_status) */ +#define CEC_OP_TIMER_CLR_STAT_RECORDING 0x00 +#define CEC_OP_TIMER_CLR_STAT_NO_MATCHING 0x01 +#define CEC_OP_TIMER_CLR_STAT_NO_INFO 0x02 +#define CEC_OP_TIMER_CLR_STAT_CLEARED 0x80 + +#define CEC_MSG_TIMER_STATUS 0x35 +/* Timer Overlap Warning Operand (timer_overlap_warning) */ +#define CEC_OP_TIMER_OVERLAP_WARNING_NO_OVERLAP 0 +#define CEC_OP_TIMER_OVERLAP_WARNING_OVERLAP 1 +/* Media Info Operand (media_info) */ +#define CEC_OP_MEDIA_INFO_UNPROT_MEDIA 0 +#define CEC_OP_MEDIA_INFO_PROT_MEDIA 1 +#define CEC_OP_MEDIA_INFO_NO_MEDIA 2 +/* Programmed Indicator Operand (prog_indicator) */ +#define CEC_OP_PROG_IND_NOT_PROGRAMMED 0 +#define CEC_OP_PROG_IND_PROGRAMMED 1 +/* Programmed Info Operand (prog_info) */ +#define CEC_OP_PROG_INFO_ENOUGH_SPACE 0x08 +#define CEC_OP_PROG_INFO_NOT_ENOUGH_SPACE 0x09 +#define CEC_OP_PROG_INFO_MIGHT_NOT_BE_ENOUGH_SPACE 0x0b +#define CEC_OP_PROG_INFO_NONE_AVAILABLE 0x0a +/* Not Programmed Error Info Operand (prog_error) */ +#define CEC_OP_PROG_ERROR_NO_FREE_TIMER 0x01 +#define CEC_OP_PROG_ERROR_DATE_OUT_OF_RANGE 0x02 +#define CEC_OP_PROG_ERROR_REC_SEQ_ERROR 0x03 +#define CEC_OP_PROG_ERROR_INV_EXT_PLUG 0x04 +#define CEC_OP_PROG_ERROR_INV_EXT_PHYS_ADDR 0x05 +#define CEC_OP_PROG_ERROR_CA_UNSUPP 0x06 +#define CEC_OP_PROG_ERROR_INSUF_CA_ENTITLEMENTS 0x07 +#define CEC_OP_PROG_ERROR_RESOLUTION_UNSUPP 0x08 +#define CEC_OP_PROG_ERROR_PARENTAL_LOCK 0x09 +#define CEC_OP_PROG_ERROR_CLOCK_FAILURE 0x0a +#define CEC_OP_PROG_ERROR_DUPLICATE 0x0e + + +/* System Information Feature */ +#define CEC_MSG_CEC_VERSION 0x9e +/* CEC Version Operand (cec_version) */ +#define CEC_OP_CEC_VERSION_1_3A 4 +#define CEC_OP_CEC_VERSION_1_4 5 +#define CEC_OP_CEC_VERSION_2_0 6 + +#define CEC_MSG_GET_CEC_VERSION 0x9f +#define CEC_MSG_GIVE_PHYSICAL_ADDR 0x83 +#define CEC_MSG_GET_MENU_LANGUAGE 0x91 +#define CEC_MSG_REPORT_PHYSICAL_ADDR 0x84 +/* Primary Device Type Operand (prim_devtype) */ +#define CEC_OP_PRIM_DEVTYPE_TV 0 +#define CEC_OP_PRIM_DEVTYPE_RECORD 1 +#define CEC_OP_PRIM_DEVTYPE_TUNER 3 +#define CEC_OP_PRIM_DEVTYPE_PLAYBACK 4 +#define CEC_OP_PRIM_DEVTYPE_AUDIOSYSTEM 5 +#define CEC_OP_PRIM_DEVTYPE_SWITCH 6 +#define CEC_OP_PRIM_DEVTYPE_PROCESSOR 7 + +#define CEC_MSG_SET_MENU_LANGUAGE 0x32 +#define CEC_MSG_REPORT_FEATURES 0xa6 /* HDMI 2.0 */ +/* All Device Types Operand (all_device_types) */ +#define CEC_OP_ALL_DEVTYPE_TV 0x80 +#define CEC_OP_ALL_DEVTYPE_RECORD 0x40 +#define CEC_OP_ALL_DEVTYPE_TUNER 0x20 +#define CEC_OP_ALL_DEVTYPE_PLAYBACK 0x10 +#define CEC_OP_ALL_DEVTYPE_AUDIOSYSTEM 0x08 +#define CEC_OP_ALL_DEVTYPE_SWITCH 0x04 +/* + * And if you wondering what happened to PROCESSOR devices: those should + * be mapped to a SWITCH. + */ + +/* Valid for RC Profile and Device Feature operands */ +#define CEC_OP_FEAT_EXT 0x80 /* Extension bit */ +/* RC Profile Operand (rc_profile) */ +#define CEC_OP_FEAT_RC_TV_PROFILE_NONE 0x00 +#define CEC_OP_FEAT_RC_TV_PROFILE_1 0x02 +#define CEC_OP_FEAT_RC_TV_PROFILE_2 0x06 +#define CEC_OP_FEAT_RC_TV_PROFILE_3 0x0a +#define CEC_OP_FEAT_RC_TV_PROFILE_4 0x0e +#define CEC_OP_FEAT_RC_SRC_HAS_DEV_ROOT_MENU 0x50 +#define CEC_OP_FEAT_RC_SRC_HAS_DEV_SETUP_MENU 0x48 +#define CEC_OP_FEAT_RC_SRC_HAS_CONTENTS_MENU 0x44 +#define CEC_OP_FEAT_RC_SRC_HAS_MEDIA_TOP_MENU 0x42 +#define CEC_OP_FEAT_RC_SRC_HAS_MEDIA_CONTEXT_MENU 0x41 +/* Device Feature Operand (dev_features) */ +#define CEC_OP_FEAT_DEV_HAS_RECORD_TV_SCREEN 0x40 +#define CEC_OP_FEAT_DEV_HAS_SET_OSD_STRING 0x20 +#define CEC_OP_FEAT_DEV_HAS_DECK_CONTROL 0x10 +#define CEC_OP_FEAT_DEV_HAS_SET_AUDIO_RATE 0x08 +#define CEC_OP_FEAT_DEV_SINK_HAS_ARC_TX 0x04 +#define CEC_OP_FEAT_DEV_SOURCE_HAS_ARC_RX 0x02 + +#define CEC_MSG_GIVE_FEATURES 0xa5 /* HDMI 2.0 */ + + +/* Deck Control Feature */ +#define CEC_MSG_DECK_CONTROL 0x42 +/* Deck Control Mode Operand (deck_control_mode) */ +#define CEC_OP_DECK_CTL_MODE_SKIP_FWD 1 +#define CEC_OP_DECK_CTL_MODE_SKIP_REV 2 +#define CEC_OP_DECK_CTL_MODE_STOP 3 +#define CEC_OP_DECK_CTL_MODE_EJECT 4 + +#define CEC_MSG_DECK_STATUS 0x1b +/* Deck Info Operand (deck_info) */ +#define CEC_OP_DECK_INFO_PLAY 0x11 +#define CEC_OP_DECK_INFO_RECORD 0x12 +#define CEC_OP_DECK_INFO_PLAY_REV 0x13 +#define CEC_OP_DECK_INFO_STILL 0x14 +#define CEC_OP_DECK_INFO_SLOW 0x15 +#define CEC_OP_DECK_INFO_SLOW_REV 0x16 +#define CEC_OP_DECK_INFO_FAST_FWD 0x17 +#define CEC_OP_DECK_INFO_FAST_REV 0x18 +#define CEC_OP_DECK_INFO_NO_MEDIA 0x19 +#define CEC_OP_DECK_INFO_STOP 0x1a +#define CEC_OP_DECK_INFO_SKIP_FWD 0x1b +#define CEC_OP_DECK_INFO_SKIP_REV 0x1c +#define CEC_OP_DECK_INFO_INDEX_SEARCH_FWD 0x1d +#define CEC_OP_DECK_INFO_INDEX_SEARCH_REV 0x1e +#define CEC_OP_DECK_INFO_OTHER 0x1f + +#define CEC_MSG_GIVE_DECK_STATUS 0x1a +/* Status Request Operand (status_req) */ +#define CEC_OP_STATUS_REQ_ON 1 +#define CEC_OP_STATUS_REQ_OFF 2 +#define CEC_OP_STATUS_REQ_ONCE 3 + +#define CEC_MSG_PLAY 0x41 +/* Play Mode Operand (play_mode) */ +#define CEC_OP_PLAY_MODE_PLAY_FWD 0x24 +#define CEC_OP_PLAY_MODE_PLAY_REV 0x20 +#define CEC_OP_PLAY_MODE_PLAY_STILL 0x25 +#define CEC_OP_PLAY_MODE_PLAY_FAST_FWD_MIN 0x05 +#define CEC_OP_PLAY_MODE_PLAY_FAST_FWD_MED 0x06 +#define CEC_OP_PLAY_MODE_PLAY_FAST_FWD_MAX 0x07 +#define CEC_OP_PLAY_MODE_PLAY_FAST_REV_MIN 0x09 +#define CEC_OP_PLAY_MODE_PLAY_FAST_REV_MED 0x0a +#define CEC_OP_PLAY_MODE_PLAY_FAST_REV_MAX 0x0b +#define CEC_OP_PLAY_MODE_PLAY_SLOW_FWD_MIN 0x15 +#define CEC_OP_PLAY_MODE_PLAY_SLOW_FWD_MED 0x16 +#define CEC_OP_PLAY_MODE_PLAY_SLOW_FWD_MAX 0x17 +#define CEC_OP_PLAY_MODE_PLAY_SLOW_REV_MIN 0x19 +#define CEC_OP_PLAY_MODE_PLAY_SLOW_REV_MED 0x1a +#define CEC_OP_PLAY_MODE_PLAY_SLOW_REV_MAX 0x1b + + +/* Tuner Control Feature */ +#define CEC_MSG_GIVE_TUNER_DEVICE_STATUS 0x08 +#define CEC_MSG_SELECT_ANALOGUE_SERVICE 0x92 +#define CEC_MSG_SELECT_DIGITAL_SERVICE 0x93 +#define CEC_MSG_TUNER_DEVICE_STATUS 0x07 +/* Recording Flag Operand (rec_flag) */ +#define CEC_OP_REC_FLAG_USED 0 +#define CEC_OP_REC_FLAG_NOT_USED 1 +/* Tuner Display Info Operand (tuner_display_info) */ +#define CEC_OP_TUNER_DISPLAY_INFO_DIGITAL 0 +#define CEC_OP_TUNER_DISPLAY_INFO_NONE 1 +#define CEC_OP_TUNER_DISPLAY_INFO_ANALOGUE 2 + +#define CEC_MSG_TUNER_STEP_DECREMENT 0x06 +#define CEC_MSG_TUNER_STEP_INCREMENT 0x05 + + +/* Vendor Specific Commands Feature */ + +/* + * Has also: + * CEC_MSG_CEC_VERSION + * CEC_MSG_GET_CEC_VERSION + */ +#define CEC_MSG_DEVICE_VENDOR_ID 0x87 +#define CEC_MSG_GIVE_DEVICE_VENDOR_ID 0x8c +#define CEC_MSG_VENDOR_COMMAND 0x89 +#define CEC_MSG_VENDOR_COMMAND_WITH_ID 0xa0 +#define CEC_MSG_VENDOR_REMOTE_BUTTON_DOWN 0x8a +#define CEC_MSG_VENDOR_REMOTE_BUTTON_UP 0x8b + + +/* OSD Display Feature */ +#define CEC_MSG_SET_OSD_STRING 0x64 +/* Display Control Operand (disp_ctl) */ +#define CEC_OP_DISP_CTL_DEFAULT 0x00 +#define CEC_OP_DISP_CTL_UNTIL_CLEARED 0x40 +#define CEC_OP_DISP_CTL_CLEAR 0x80 + + +/* Device OSD Transfer Feature */ +#define CEC_MSG_GIVE_OSD_NAME 0x46 +#define CEC_MSG_SET_OSD_NAME 0x47 + + +/* Device Menu Control Feature */ +#define CEC_MSG_MENU_REQUEST 0x8d +/* Menu Request Type Operand (menu_req) */ +#define CEC_OP_MENU_REQUEST_ACTIVATE 0x00 +#define CEC_OP_MENU_REQUEST_DEACTIVATE 0x01 +#define CEC_OP_MENU_REQUEST_QUERY 0x02 + +#define CEC_MSG_MENU_STATUS 0x8e +/* Menu State Operand (menu_state) */ +#define CEC_OP_MENU_STATE_ACTIVATED 0x00 +#define CEC_OP_MENU_STATE_DEACTIVATED 0x01 + +#define CEC_MSG_USER_CONTROL_PRESSED 0x44 +/* UI Broadcast Type Operand (ui_bcast_type) */ +#define CEC_OP_UI_BCAST_TYPE_TOGGLE_ALL 0x00 +#define CEC_OP_UI_BCAST_TYPE_TOGGLE_DIG_ANA 0x01 +#define CEC_OP_UI_BCAST_TYPE_ANALOGUE 0x10 +#define CEC_OP_UI_BCAST_TYPE_ANALOGUE_T 0x20 +#define CEC_OP_UI_BCAST_TYPE_ANALOGUE_CABLE 0x30 +#define CEC_OP_UI_BCAST_TYPE_ANALOGUE_SAT 0x40 +#define CEC_OP_UI_BCAST_TYPE_DIGITAL 0x50 +#define CEC_OP_UI_BCAST_TYPE_DIGITAL_T 0x60 +#define CEC_OP_UI_BCAST_TYPE_DIGITAL_CABLE 0x70 +#define CEC_OP_UI_BCAST_TYPE_DIGITAL_SAT 0x80 +#define CEC_OP_UI_BCAST_TYPE_DIGITAL_COM_SAT 0x90 +#define CEC_OP_UI_BCAST_TYPE_DIGITAL_COM_SAT2 0x91 +#define CEC_OP_UI_BCAST_TYPE_IP 0xa0 +/* UI Sound Presentation Control Operand (ui_snd_pres_ctl) */ +#define CEC_OP_UI_SND_PRES_CTL_DUAL_MONO 0x10 +#define CEC_OP_UI_SND_PRES_CTL_KARAOKE 0x20 +#define CEC_OP_UI_SND_PRES_CTL_DOWNMIX 0x80 +#define CEC_OP_UI_SND_PRES_CTL_REVERB 0x90 +#define CEC_OP_UI_SND_PRES_CTL_EQUALIZER 0xa0 +#define CEC_OP_UI_SND_PRES_CTL_BASS_UP 0xb1 +#define CEC_OP_UI_SND_PRES_CTL_BASS_NEUTRAL 0xb2 +#define CEC_OP_UI_SND_PRES_CTL_BASS_DOWN 0xb3 +#define CEC_OP_UI_SND_PRES_CTL_TREBLE_UP 0xc1 +#define CEC_OP_UI_SND_PRES_CTL_TREBLE_NEUTRAL 0xc2 +#define CEC_OP_UI_SND_PRES_CTL_TREBLE_DOWN 0xc3 + +#define CEC_MSG_USER_CONTROL_RELEASED 0x45 + + +/* Remote Control Passthrough Feature */ + +/* + * Has also: + * CEC_MSG_USER_CONTROL_PRESSED + * CEC_MSG_USER_CONTROL_RELEASED + */ + + +/* Power Status Feature */ +#define CEC_MSG_GIVE_DEVICE_POWER_STATUS 0x8f +#define CEC_MSG_REPORT_POWER_STATUS 0x90 +/* Power Status Operand (pwr_state) */ +#define CEC_OP_POWER_STATUS_ON 0 +#define CEC_OP_POWER_STATUS_STANDBY 1 +#define CEC_OP_POWER_STATUS_TO_ON 2 +#define CEC_OP_POWER_STATUS_TO_STANDBY 3 + + +/* General Protocol Messages */ +#define CEC_MSG_FEATURE_ABORT 0x00 +/* Abort Reason Operand (reason) */ +#define CEC_OP_ABORT_UNRECOGNIZED_OP 0 +#define CEC_OP_ABORT_INCORRECT_MODE 1 +#define CEC_OP_ABORT_NO_SOURCE 2 +#define CEC_OP_ABORT_INVALID_OP 3 +#define CEC_OP_ABORT_REFUSED 4 +#define CEC_OP_ABORT_UNDETERMINED 5 + +#define CEC_MSG_ABORT 0xff + + +/* System Audio Control Feature */ + +/* + * Has also: + * CEC_MSG_USER_CONTROL_PRESSED + * CEC_MSG_USER_CONTROL_RELEASED + */ +#define CEC_MSG_GIVE_AUDIO_STATUS 0x71 +#define CEC_MSG_GIVE_SYSTEM_AUDIO_MODE_STATUS 0x7d +#define CEC_MSG_REPORT_AUDIO_STATUS 0x7a +/* Audio Mute Status Operand (aud_mute_status) */ +#define CEC_OP_AUD_MUTE_STATUS_OFF 0 +#define CEC_OP_AUD_MUTE_STATUS_ON 1 + +#define CEC_MSG_REPORT_SHORT_AUDIO_DESCRIPTOR 0xa3 +#define CEC_MSG_REQUEST_SHORT_AUDIO_DESCRIPTOR 0xa4 +#define CEC_MSG_SET_SYSTEM_AUDIO_MODE 0x72 +/* System Audio Status Operand (sys_aud_status) */ +#define CEC_OP_SYS_AUD_STATUS_OFF 0 +#define CEC_OP_SYS_AUD_STATUS_ON 1 + +#define CEC_MSG_SYSTEM_AUDIO_MODE_REQUEST 0x70 +#define CEC_MSG_SYSTEM_AUDIO_MODE_STATUS 0x7e +/* Audio Format ID Operand (audio_format_id) */ +#define CEC_OP_AUD_FMT_ID_CEA861 0 +#define CEC_OP_AUD_FMT_ID_CEA861_CXT 1 + + +/* Audio Rate Control Feature */ +#define CEC_MSG_SET_AUDIO_RATE 0x9a +/* Audio Rate Operand (audio_rate) */ +#define CEC_OP_AUD_RATE_OFF 0 +#define CEC_OP_AUD_RATE_WIDE_STD 1 +#define CEC_OP_AUD_RATE_WIDE_FAST 2 +#define CEC_OP_AUD_RATE_WIDE_SLOW 3 +#define CEC_OP_AUD_RATE_NARROW_STD 4 +#define CEC_OP_AUD_RATE_NARROW_FAST 5 +#define CEC_OP_AUD_RATE_NARROW_SLOW 6 + + +/* Audio Return Channel Control Feature */ +#define CEC_MSG_INITIATE_ARC 0xc0 +#define CEC_MSG_REPORT_ARC_INITIATED 0xc1 +#define CEC_MSG_REPORT_ARC_TERMINATED 0xc2 +#define CEC_MSG_REQUEST_ARC_INITIATION 0xc3 +#define CEC_MSG_REQUEST_ARC_TERMINATION 0xc4 +#define CEC_MSG_TERMINATE_ARC 0xc5 + + +/* Dynamic Audio Lipsync Feature */ +/* Only for CEC 2.0 and up */ +#define CEC_MSG_REQUEST_CURRENT_LATENCY 0xa7 +#define CEC_MSG_REPORT_CURRENT_LATENCY 0xa8 +/* Low Latency Mode Operand (low_latency_mode) */ +#define CEC_OP_LOW_LATENCY_MODE_OFF 0 +#define CEC_OP_LOW_LATENCY_MODE_ON 1 +/* Audio Output Compensated Operand (audio_out_compensated) */ +#define CEC_OP_AUD_OUT_COMPENSATED_NA 0 +#define CEC_OP_AUD_OUT_COMPENSATED_DELAY 1 +#define CEC_OP_AUD_OUT_COMPENSATED_NO_DELAY 2 +#define CEC_OP_AUD_OUT_COMPENSATED_PARTIAL_DELAY 3 + + +/* Capability Discovery and Control Feature */ +#define CEC_MSG_CDC_MESSAGE 0xf8 +/* Ethernet-over-HDMI: nobody ever does this... */ +#define CEC_MSG_CDC_HEC_INQUIRE_STATE 0x00 +#define CEC_MSG_CDC_HEC_REPORT_STATE 0x01 +/* HEC Functionality State Operand (hec_func_state) */ +#define CEC_OP_HEC_FUNC_STATE_NOT_SUPPORTED 0 +#define CEC_OP_HEC_FUNC_STATE_INACTIVE 1 +#define CEC_OP_HEC_FUNC_STATE_ACTIVE 2 +#define CEC_OP_HEC_FUNC_STATE_ACTIVATION_FIELD 3 +/* Host Functionality State Operand (host_func_state) */ +#define CEC_OP_HOST_FUNC_STATE_NOT_SUPPORTED 0 +#define CEC_OP_HOST_FUNC_STATE_INACTIVE 1 +#define CEC_OP_HOST_FUNC_STATE_ACTIVE 2 +/* ENC Functionality State Operand (enc_func_state) */ +#define CEC_OP_ENC_FUNC_STATE_EXT_CON_NOT_SUPPORTED 0 +#define CEC_OP_ENC_FUNC_STATE_EXT_CON_INACTIVE 1 +#define CEC_OP_ENC_FUNC_STATE_EXT_CON_ACTIVE 2 +/* CDC Error Code Operand (cdc_errcode) */ +#define CEC_OP_CDC_ERROR_CODE_NONE 0 +#define CEC_OP_CDC_ERROR_CODE_CAP_UNSUPPORTED 1 +#define CEC_OP_CDC_ERROR_CODE_WRONG_STATE 2 +#define CEC_OP_CDC_ERROR_CODE_OTHER 3 +/* HEC Support Operand (hec_support) */ +#define CEC_OP_HEC_SUPPORT_NO 0 +#define CEC_OP_HEC_SUPPORT_YES 1 +/* HEC Activation Operand (hec_activation) */ +#define CEC_OP_HEC_ACTIVATION_ON 0 +#define CEC_OP_HEC_ACTIVATION_OFF 1 + +#define CEC_MSG_CDC_HEC_SET_STATE_ADJACENT 0x02 +#define CEC_MSG_CDC_HEC_SET_STATE 0x03 +/* HEC Set State Operand (hec_set_state) */ +#define CEC_OP_HEC_SET_STATE_DEACTIVATE 0 +#define CEC_OP_HEC_SET_STATE_ACTIVATE 1 + +#define CEC_MSG_CDC_HEC_REQUEST_DEACTIVATION 0x04 +#define CEC_MSG_CDC_HEC_NOTIFY_ALIVE 0x05 +#define CEC_MSG_CDC_HEC_DISCOVER 0x06 +/* Hotplug Detect messages */ +#define CEC_MSG_CDC_HPD_SET_STATE 0x10 +/* HPD State Operand (hpd_state) */ +#define CEC_OP_HPD_STATE_CP_EDID_DISABLE 0 +#define CEC_OP_HPD_STATE_CP_EDID_ENABLE 1 +#define CEC_OP_HPD_STATE_CP_EDID_DISABLE_ENABLE 2 +#define CEC_OP_HPD_STATE_EDID_DISABLE 3 +#define CEC_OP_HPD_STATE_EDID_ENABLE 4 +#define CEC_OP_HPD_STATE_EDID_DISABLE_ENABLE 5 +#define CEC_MSG_CDC_HPD_REPORT_STATE 0x11 +/* HPD Error Code Operand (hpd_error) */ +#define CEC_OP_HPD_ERROR_NONE 0 +#define CEC_OP_HPD_ERROR_INITIATOR_NOT_CAPABLE 1 +#define CEC_OP_HPD_ERROR_INITIATOR_WRONG_STATE 2 +#define CEC_OP_HPD_ERROR_OTHER 3 +#define CEC_OP_HPD_ERROR_NONE_NO_VIDEO 4 + +/* End of Messages */ + +/* Helper functions to identify the 'special' CEC devices */ + +static inline int cec_is_2nd_tv(const struct cec_log_addrs *las) +{ + /* + * It is a second TV if the logical address is 14 or 15 and the + * primary device type is a TV. + */ + return las->num_log_addrs && + las->log_addr[0] >= CEC_LOG_ADDR_SPECIFIC && + las->primary_device_type[0] == CEC_OP_PRIM_DEVTYPE_TV; +} + +static inline int cec_is_processor(const struct cec_log_addrs *las) +{ + /* + * It is a processor if the logical address is 12-15 and the + * primary device type is a Processor. + */ + return las->num_log_addrs && + las->log_addr[0] >= CEC_LOG_ADDR_BACKUP_1 && + las->primary_device_type[0] == CEC_OP_PRIM_DEVTYPE_PROCESSOR; +} + +static inline int cec_is_switch(const struct cec_log_addrs *las) +{ + /* + * It is a switch if the logical address is 15 and the + * primary device type is a Switch and the CDC-Only flag is not set. + */ + return las->num_log_addrs == 1 && + las->log_addr[0] == CEC_LOG_ADDR_UNREGISTERED && + las->primary_device_type[0] == CEC_OP_PRIM_DEVTYPE_SWITCH && + !(las->flags & CEC_LOG_ADDRS_FL_CDC_ONLY); +} + +static inline int cec_is_cdc_only(const struct cec_log_addrs *las) +{ + /* + * It is a CDC-only device if the logical address is 15 and the + * primary device type is a Switch and the CDC-Only flag is set. + */ + return las->num_log_addrs == 1 && + las->log_addr[0] == CEC_LOG_ADDR_UNREGISTERED && + las->primary_device_type[0] == CEC_OP_PRIM_DEVTYPE_SWITCH && + (las->flags & CEC_LOG_ADDRS_FL_CDC_ONLY); +} + +#endif diff --git a/include/uapi/linux/dma-buf.h b/include/uapi/linux/dma-buf.h new file mode 100644 index 000000000000..fb0dedb7c121 --- /dev/null +++ b/include/uapi/linux/dma-buf.h @@ -0,0 +1,40 @@ +/* + * Framework for buffer objects that can be shared across devices/subsystems. + * + * Copyright(C) 2015 Intel Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _DMA_BUF_UAPI_H_ +#define _DMA_BUF_UAPI_H_ + +#include <linux/types.h> + +/* begin/end dma-buf functions used for userspace mmap. */ +struct dma_buf_sync { + __u64 flags; +}; + +#define DMA_BUF_SYNC_READ (1 << 0) +#define DMA_BUF_SYNC_WRITE (2 << 0) +#define DMA_BUF_SYNC_RW (DMA_BUF_SYNC_READ | DMA_BUF_SYNC_WRITE) +#define DMA_BUF_SYNC_START (0 << 2) +#define DMA_BUF_SYNC_END (1 << 2) +#define DMA_BUF_SYNC_VALID_FLAGS_MASK \ + (DMA_BUF_SYNC_RW | DMA_BUF_SYNC_END) + +#define DMA_BUF_BASE 'b' +#define DMA_BUF_IOCTL_SYNC _IOW(DMA_BUF_BASE, 0, struct dma_buf_sync) + +#endif diff --git a/include/uapi/linux/fb.h b/include/uapi/linux/fb.h index fb795c3b3c17..39c48cde02ec 100644 --- a/include/uapi/linux/fb.h +++ b/include/uapi/linux/fb.h @@ -34,6 +34,7 @@ #define FBIOPUT_MODEINFO 0x4617 #define FBIOGET_DISPINFO 0x4618 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32) +#define FBIOGET_DMABUF _IOR('F', 0x21, struct fb_dmabuf_export) #define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */ #define FB_TYPE_PLANES 1 /* Non interleaved planes */ @@ -398,5 +399,9 @@ struct fb_cursor { #define FB_BACKLIGHT_MAX 0xFF #endif +struct fb_dmabuf_export { + __u32 fd; + __u32 flags; +}; #endif /* _UAPI_LINUX_FB_H */ diff --git a/include/uapi/linux/iio/types.h b/include/uapi/linux/iio/types.h index 7c63bd67c36e..b06db7e3bcd6 100644 --- a/include/uapi/linux/iio/types.h +++ b/include/uapi/linux/iio/types.h @@ -37,6 +37,7 @@ enum iio_chan_type { IIO_VELOCITY, IIO_CONCENTRATION, IIO_RESISTANCE, + IIO_QUATERNION, }; enum iio_modifier { @@ -76,6 +77,7 @@ enum iio_modifier { IIO_MOD_Q, IIO_MOD_CO2, IIO_MOD_VOC, + IIO_MOD_R, }; enum iio_event_type { diff --git a/include/uapi/linux/lirc.h b/include/uapi/linux/lirc.h new file mode 100644 index 000000000000..b99c940b05d3 --- /dev/null +++ b/include/uapi/linux/lirc.h @@ -0,0 +1,222 @@ +/* + * lirc.h - linux infrared remote control header file + * last modified 2010/07/13 by Jarod Wilson + */ + +#ifndef _LINUX_LIRC_H +#define _LINUX_LIRC_H + +#include <linux/types.h> +#include <linux/ioctl.h> + +#define PULSE_BIT 0x01000000 +#define PULSE_MASK 0x00FFFFFF + +#define LIRC_MODE2_SPACE 0x00000000 +#define LIRC_MODE2_PULSE 0x01000000 +#define LIRC_MODE2_FREQUENCY 0x02000000 +#define LIRC_MODE2_TIMEOUT 0x03000000 + +#define LIRC_VALUE_MASK 0x00FFFFFF +#define LIRC_MODE2_MASK 0xFF000000 + +#define LIRC_SPACE(val) (((val)&LIRC_VALUE_MASK) | LIRC_MODE2_SPACE) +#define LIRC_PULSE(val) (((val)&LIRC_VALUE_MASK) | LIRC_MODE2_PULSE) +#define LIRC_FREQUENCY(val) (((val)&LIRC_VALUE_MASK) | LIRC_MODE2_FREQUENCY) +#define LIRC_TIMEOUT(val) (((val)&LIRC_VALUE_MASK) | LIRC_MODE2_TIMEOUT) + +#define LIRC_VALUE(val) ((val)&LIRC_VALUE_MASK) +#define LIRC_MODE2(val) ((val)&LIRC_MODE2_MASK) + +#define LIRC_IS_SPACE(val) (LIRC_MODE2(val) == LIRC_MODE2_SPACE) +#define LIRC_IS_PULSE(val) (LIRC_MODE2(val) == LIRC_MODE2_PULSE) +#define LIRC_IS_FREQUENCY(val) (LIRC_MODE2(val) == LIRC_MODE2_FREQUENCY) +#define LIRC_IS_TIMEOUT(val) (LIRC_MODE2(val) == LIRC_MODE2_TIMEOUT) + +/* used heavily by lirc userspace */ +#define lirc_t int + +/*** lirc compatible hardware features ***/ + +#define LIRC_MODE2SEND(x) (x) +#define LIRC_SEND2MODE(x) (x) +#define LIRC_MODE2REC(x) ((x) << 16) +#define LIRC_REC2MODE(x) ((x) >> 16) + +#define LIRC_MODE_RAW 0x00000001 +#define LIRC_MODE_PULSE 0x00000002 +#define LIRC_MODE_MODE2 0x00000004 +#define LIRC_MODE_SCANCODE 0x00000008 +#define LIRC_MODE_LIRCCODE 0x00000010 + + +#define LIRC_CAN_SEND_RAW LIRC_MODE2SEND(LIRC_MODE_RAW) +#define LIRC_CAN_SEND_PULSE LIRC_MODE2SEND(LIRC_MODE_PULSE) +#define LIRC_CAN_SEND_MODE2 LIRC_MODE2SEND(LIRC_MODE_MODE2) +#define LIRC_CAN_SEND_LIRCCODE LIRC_MODE2SEND(LIRC_MODE_LIRCCODE) + +#define LIRC_CAN_SEND_MASK 0x0000003f + +#define LIRC_CAN_SET_SEND_CARRIER 0x00000100 +#define LIRC_CAN_SET_SEND_DUTY_CYCLE 0x00000200 +#define LIRC_CAN_SET_TRANSMITTER_MASK 0x00000400 + +#define LIRC_CAN_REC_RAW LIRC_MODE2REC(LIRC_MODE_RAW) +#define LIRC_CAN_REC_PULSE LIRC_MODE2REC(LIRC_MODE_PULSE) +#define LIRC_CAN_REC_MODE2 LIRC_MODE2REC(LIRC_MODE_MODE2) +#define LIRC_CAN_REC_SCANCODE LIRC_MODE2REC(LIRC_MODE_SCANCODE) +#define LIRC_CAN_REC_LIRCCODE LIRC_MODE2REC(LIRC_MODE_LIRCCODE) + +#define LIRC_CAN_REC_MASK LIRC_MODE2REC(LIRC_CAN_SEND_MASK) + +#define LIRC_CAN_SET_REC_CARRIER (LIRC_CAN_SET_SEND_CARRIER << 16) +#define LIRC_CAN_SET_REC_DUTY_CYCLE (LIRC_CAN_SET_SEND_DUTY_CYCLE << 16) + +#define LIRC_CAN_SET_REC_DUTY_CYCLE_RANGE 0x40000000 +#define LIRC_CAN_SET_REC_CARRIER_RANGE 0x80000000 +#define LIRC_CAN_GET_REC_RESOLUTION 0x20000000 +#define LIRC_CAN_SET_REC_TIMEOUT 0x10000000 +#define LIRC_CAN_SET_REC_FILTER 0x08000000 + +#define LIRC_CAN_MEASURE_CARRIER 0x02000000 +#define LIRC_CAN_USE_WIDEBAND_RECEIVER 0x04000000 + +#define LIRC_CAN_SEND(x) ((x)&LIRC_CAN_SEND_MASK) +#define LIRC_CAN_REC(x) ((x)&LIRC_CAN_REC_MASK) + +#define LIRC_CAN_NOTIFY_DECODE 0x01000000 + +/*** IOCTL commands for lirc driver ***/ + +#define LIRC_GET_FEATURES _IOR('i', 0x00000000, __u32) + +#define LIRC_GET_SEND_MODE _IOR('i', 0x00000001, __u32) +#define LIRC_GET_REC_MODE _IOR('i', 0x00000002, __u32) +#define LIRC_GET_REC_RESOLUTION _IOR('i', 0x00000007, __u32) + +#define LIRC_GET_MIN_TIMEOUT _IOR('i', 0x00000008, __u32) +#define LIRC_GET_MAX_TIMEOUT _IOR('i', 0x00000009, __u32) + +/* code length in bits, currently only for LIRC_MODE_LIRCCODE */ +#define LIRC_GET_LENGTH _IOR('i', 0x0000000f, __u32) + +#define LIRC_SET_SEND_MODE _IOW('i', 0x00000011, __u32) +#define LIRC_SET_REC_MODE _IOW('i', 0x00000012, __u32) +/* Note: these can reset the according pulse_width */ +#define LIRC_SET_SEND_CARRIER _IOW('i', 0x00000013, __u32) +#define LIRC_SET_REC_CARRIER _IOW('i', 0x00000014, __u32) +#define LIRC_SET_SEND_DUTY_CYCLE _IOW('i', 0x00000015, __u32) +#define LIRC_SET_TRANSMITTER_MASK _IOW('i', 0x00000017, __u32) + +/* + * when a timeout != 0 is set the driver will send a + * LIRC_MODE2_TIMEOUT data packet, otherwise LIRC_MODE2_TIMEOUT is + * never sent, timeout is disabled by default + */ +#define LIRC_SET_REC_TIMEOUT _IOW('i', 0x00000018, __u32) + +/* 1 enables, 0 disables timeout reports in MODE2 */ +#define LIRC_SET_REC_TIMEOUT_REPORTS _IOW('i', 0x00000019, __u32) + +/* + * if enabled from the next key press on the driver will send + * LIRC_MODE2_FREQUENCY packets + */ +#define LIRC_SET_MEASURE_CARRIER_MODE _IOW('i', 0x0000001d, __u32) + +/* + * to set a range use LIRC_SET_REC_CARRIER_RANGE with the + * lower bound first and later LIRC_SET_REC_CARRIER with the upper bound + */ +#define LIRC_SET_REC_CARRIER_RANGE _IOW('i', 0x0000001f, __u32) + +#define LIRC_SET_WIDEBAND_RECEIVER _IOW('i', 0x00000023, __u32) + +/* + * Return the recording timeout, which is either set by + * the ioctl LIRC_SET_REC_TIMEOUT or by the kernel after setting the protocols. + */ +#define LIRC_GET_REC_TIMEOUT _IOR('i', 0x00000024, __u32) + +/* + * struct lirc_scancode - decoded scancode with protocol for use with + * LIRC_MODE_SCANCODE + * + * @timestamp: Timestamp in nanoseconds using CLOCK_MONOTONIC when IR + * was decoded. + * @flags: should be 0 for transmit. When receiving scancodes, + * LIRC_SCANCODE_FLAG_TOGGLE or LIRC_SCANCODE_FLAG_REPEAT can be set + * depending on the protocol + * @rc_proto: see enum rc_proto + * @keycode: the translated keycode. Set to 0 for transmit. + * @scancode: the scancode received or to be sent + */ +struct lirc_scancode { + __u64 timestamp; + __u16 flags; + __u16 rc_proto; + __u32 keycode; + __u64 scancode; +}; + +/* Set if the toggle bit of rc-5 or rc-6 is enabled */ +#define LIRC_SCANCODE_FLAG_TOGGLE 1 +/* Set if this is a nec or sanyo repeat */ +#define LIRC_SCANCODE_FLAG_REPEAT 2 + +/** + * enum rc_proto - the Remote Controller protocol + * + * @RC_PROTO_UNKNOWN: Protocol not known + * @RC_PROTO_OTHER: Protocol known but proprietary + * @RC_PROTO_RC5: Philips RC5 protocol + * @RC_PROTO_RC5X_20: Philips RC5x 20 bit protocol + * @RC_PROTO_RC5_SZ: StreamZap variant of RC5 + * @RC_PROTO_JVC: JVC protocol + * @RC_PROTO_SONY12: Sony 12 bit protocol + * @RC_PROTO_SONY15: Sony 15 bit protocol + * @RC_PROTO_SONY20: Sony 20 bit protocol + * @RC_PROTO_NEC: NEC protocol + * @RC_PROTO_NECX: Extended NEC protocol + * @RC_PROTO_NEC32: NEC 32 bit protocol + * @RC_PROTO_SANYO: Sanyo protocol + * @RC_PROTO_MCIR2_KBD: RC6-ish MCE keyboard + * @RC_PROTO_MCIR2_MSE: RC6-ish MCE mouse + * @RC_PROTO_RC6_0: Philips RC6-0-16 protocol + * @RC_PROTO_RC6_6A_20: Philips RC6-6A-20 protocol + * @RC_PROTO_RC6_6A_24: Philips RC6-6A-24 protocol + * @RC_PROTO_RC6_6A_32: Philips RC6-6A-32 protocol + * @RC_PROTO_RC6_MCE: MCE (Philips RC6-6A-32 subtype) protocol + * @RC_PROTO_SHARP: Sharp protocol + * @RC_PROTO_XMP: XMP protocol + * @RC_PROTO_CEC: CEC protocol + * @RC_PROTO_IMON: iMon Pad protocol + */ +enum rc_proto { + RC_PROTO_UNKNOWN = 0, + RC_PROTO_OTHER = 1, + RC_PROTO_RC5 = 2, + RC_PROTO_RC5X_20 = 3, + RC_PROTO_RC5_SZ = 4, + RC_PROTO_JVC = 5, + RC_PROTO_SONY12 = 6, + RC_PROTO_SONY15 = 7, + RC_PROTO_SONY20 = 8, + RC_PROTO_NEC = 9, + RC_PROTO_NECX = 10, + RC_PROTO_NEC32 = 11, + RC_PROTO_SANYO = 12, + RC_PROTO_MCIR2_KBD = 13, + RC_PROTO_MCIR2_MSE = 14, + RC_PROTO_RC6_0 = 15, + RC_PROTO_RC6_6A_20 = 16, + RC_PROTO_RC6_6A_24 = 17, + RC_PROTO_RC6_6A_32 = 18, + RC_PROTO_RC6_MCE = 19, + RC_PROTO_SHARP = 20, + RC_PROTO_XMP = 21, + RC_PROTO_CEC = 22, + RC_PROTO_IMON = 23, +}; + +#endif diff --git a/include/uapi/linux/media-bus-format.h b/include/uapi/linux/media-bus-format.h index 190d491d5b13..12ccaa6ef94c 100644 --- a/include/uapi/linux/media-bus-format.h +++ b/include/uapi/linux/media-bus-format.h @@ -33,7 +33,7 @@ #define MEDIA_BUS_FMT_FIXED 0x0001 -/* RGB - next is 0x1018 */ +/* RGB - next is 0x101b */ #define MEDIA_BUS_FMT_RGB444_1X12 0x1016 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002 @@ -57,8 +57,11 @@ #define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA 0x1012 #define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d #define MEDIA_BUS_FMT_RGB888_1X32_PADHI 0x100f +#define MEDIA_BUS_FMT_RGB101010_1X30 0x1018 +#define MEDIA_BUS_FMT_RGB121212_1X36 0x1019 +#define MEDIA_BUS_FMT_RGB161616_1X48 0x101a -/* YUV (including grey) - next is 0x2026 */ +/* YUV (including grey) - next is 0x202c */ #define MEDIA_BUS_FMT_Y8_1X8 0x2001 #define MEDIA_BUS_FMT_UV8_1X8 0x2015 #define MEDIA_BUS_FMT_UYVY8_1_5X8 0x2002 @@ -90,12 +93,18 @@ #define MEDIA_BUS_FMT_YVYU10_1X20 0x200e #define MEDIA_BUS_FMT_VUY8_1X24 0x2024 #define MEDIA_BUS_FMT_YUV8_1X24 0x2025 +#define MEDIA_BUS_FMT_UYYVYY8_0_5X24 0x2026 #define MEDIA_BUS_FMT_UYVY12_1X24 0x2020 #define MEDIA_BUS_FMT_VYUY12_1X24 0x2021 #define MEDIA_BUS_FMT_YUYV12_1X24 0x2022 #define MEDIA_BUS_FMT_YVYU12_1X24 0x2023 #define MEDIA_BUS_FMT_YUV10_1X30 0x2016 +#define MEDIA_BUS_FMT_UYYVYY10_0_5X30 0x2027 #define MEDIA_BUS_FMT_AYUV8_1X32 0x2017 +#define MEDIA_BUS_FMT_UYYVYY12_0_5X36 0x2028 +#define MEDIA_BUS_FMT_YUV12_1X36 0x2029 +#define MEDIA_BUS_FMT_YUV16_1X48 0x202a +#define MEDIA_BUS_FMT_UYYVYY16_0_5X48 0x202b /* Bayer - next is 0x3019 */ #define MEDIA_BUS_FMT_SBGGR8_1X8 0x3001 diff --git a/include/uapi/linux/rk-pcie-dma.h b/include/uapi/linux/rk-pcie-dma.h new file mode 100644 index 000000000000..d6515389629b --- /dev/null +++ b/include/uapi/linux/rk-pcie-dma.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Rockchip Electronics Co., Ltd. + */ + +enum transfer_type { + PCIE_DMA_DATA_SND, + PCIE_DMA_DATA_RCV_ACK, + PCIE_DMA_DATA_FREE_ACK, +}; + +union pcie_dma_ioctl_param { + struct { + u32 idx; + u32 l_widx; + u32 r_widx; + u32 size; + u32 type; + } in; + struct { + u32 lwa; + u32 rwa; + } out; + u32 lra; + u32 count; +}; + +#define PCIE_BASE 'P' +#define PCIE_DMA_START \ + _IOW(PCIE_BASE, 0, union pcie_dma_ioctl_param) +#define PCIE_DMA_GET_LOCAL_READ_BUFFER_INDEX \ + _IOR(PCIE_BASE, 1, union pcie_dma_ioctl_param) +#define PCIE_DMA_GET_LOCAL_REMOTE_WRITE_BUFFER_INDEX \ + _IOR(PCIE_BASE, 2, union pcie_dma_ioctl_param) +#define PCIE_DMA_SET_LOCAL_READ_BUFFER_INDEX \ + _IOW(PCIE_BASE, 3, union pcie_dma_ioctl_param) +#define PCIE_DMA_SYNC_BUFFER_FOR_CPU \ + _IOW(PCIE_BASE, 4, union pcie_dma_ioctl_param) +#define PCIE_DMA_SYNC_BUFFER_TO_DEVICE \ + _IOW(PCIE_BASE, 5, union pcie_dma_ioctl_param) +#define PCIE_DMA_WAIT_TRANSFER_COMPLETE \ + _IO(PCIE_BASE, 6) +#define PCIE_DMA_SET_LOOP_COUNT \ + _IOW(PCIE_BASE, 7, union pcie_dma_ioctl_param) + diff --git a/include/uapi/linux/rk-preisp.h b/include/uapi/linux/rk-preisp.h new file mode 100644 index 000000000000..3b58c2f7e137 --- /dev/null +++ b/include/uapi/linux/rk-preisp.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: ((GPL-2.0+ WITH Linux-syscall-note) OR MIT) */ +/* + * Rockchip preisp driver + * Copyright (C) 2018 Rockchip Electronics Co., Ltd. + */ + +#ifndef _UAPI_RKPREISP_H +#define _UAPI_RKPREISP_H + +#include <linux/types.h> + +#define PREISP_LSCTBL_SIZE 289 + +#define PREISP_CMD_SET_HDRAE_EXP \ + _IOW('V', BASE_VIDIOC_PRIVATE + 0, struct preisp_hdrae_exp_s) + +#define PREISP_CMD_SAVE_HDRAE_PARAM \ + _IOW('V', BASE_VIDIOC_PRIVATE + 1, struct preisp_hdrae_para_s) + +/** + * struct preisp_hdrae_para_s - awb and lsc para for preisp + * + * @r_gain: awb r gain + * @b_gain: awb b gain + * @gr_gain: awb gr gain + * @gb_gain: awb gb gain + * @lsc_table: lsc data of gr + */ +struct preisp_hdrae_para_s { + unsigned short r_gain; + unsigned short b_gain; + unsigned short gr_gain; + unsigned short gb_gain; + int lsc_table[PREISP_LSCTBL_SIZE]; +}; + +/** + * struct preisp_hdrae_exp_s - hdrae exposure + * + */ +struct preisp_hdrae_exp_s { + unsigned int long_exp_reg; + unsigned int long_gain_reg; + unsigned int middle_exp_reg; + unsigned int middle_gain_reg; + unsigned int short_exp_reg; + unsigned int short_gain_reg; + unsigned int long_exp_val; + unsigned int long_gain_val; + unsigned int middle_exp_val; + unsigned int middle_gain_val; + unsigned int short_exp_val; + unsigned int short_gain_val; +}; + +#endif /* _UAPI_RKPREISP_H */ diff --git a/include/uapi/linux/rkisp1-config.h b/include/uapi/linux/rkisp1-config.h new file mode 100644 index 000000000000..393f4449e1d4 --- /dev/null +++ b/include/uapi/linux/rkisp1-config.h @@ -0,0 +1,780 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Rockchip isp1 driver + * Copyright (C) 2017 Rockchip Electronics Co., Ltd. + */ + +#ifndef _UAPI_RKISP1_CONFIG_H +#define _UAPI_RKISP1_CONFIG_H + +#include <linux/types.h> +#include <linux/v4l2-controls.h> + +#define CIFISP_MODULE_DPCC (1 << 0) +#define CIFISP_MODULE_BLS (1 << 1) +#define CIFISP_MODULE_SDG (1 << 2) +#define CIFISP_MODULE_HST (1 << 3) +#define CIFISP_MODULE_LSC (1 << 4) +#define CIFISP_MODULE_AWB_GAIN (1 << 5) +#define CIFISP_MODULE_FLT (1 << 6) +#define CIFISP_MODULE_BDM (1 << 7) +#define CIFISP_MODULE_CTK (1 << 8) +#define CIFISP_MODULE_GOC (1 << 9) +#define CIFISP_MODULE_CPROC (1 << 10) +#define CIFISP_MODULE_AFC (1 << 11) +#define CIFISP_MODULE_AWB (1 << 12) +#define CIFISP_MODULE_IE (1 << 13) +#define CIFISP_MODULE_AEC (1 << 14) +#define CIFISP_MODULE_WDR (1 << 15) +#define CIFISP_MODULE_DPF (1 << 16) +#define CIFISP_MODULE_DPF_STRENGTH (1 << 17) + +#define CIFISP_CTK_COEFF_MAX 0x100 +#define CIFISP_CTK_OFFSET_MAX 0x800 + +#define CIFISP_AE_MEAN_MAX 81 +#define CIFISP_HIST_BIN_N_MAX 32 +#define CIFISP_AFM_MAX_WINDOWS 3 +#define CIFISP_DEGAMMA_CURVE_SIZE 17 + +#define CIFISP_BDM_MAX_TH 0xFF + +/* + * Black level compensation + */ +/* maximum value for horizontal start address */ +#define CIFISP_BLS_START_H_MAX 0x00000FFF +/* maximum value for horizontal stop address */ +#define CIFISP_BLS_STOP_H_MAX 0x00000FFF +/* maximum value for vertical start address */ +#define CIFISP_BLS_START_V_MAX 0x00000FFF +/* maximum value for vertical stop address */ +#define CIFISP_BLS_STOP_V_MAX 0x00000FFF +/* maximum is 2^18 = 262144*/ +#define CIFISP_BLS_SAMPLES_MAX 0x00000012 +/* maximum value for fixed black level */ +#define CIFISP_BLS_FIX_SUB_MAX 0x00000FFF +/* minimum value for fixed black level */ +#define CIFISP_BLS_FIX_SUB_MIN 0xFFFFF000 +/* 13 bit range (signed)*/ +#define CIFISP_BLS_FIX_MASK 0x00001FFF + +/* + * Automatic white balance measurments + */ +#define CIFISP_AWB_MAX_GRID 1 +#define CIFISP_AWB_MAX_FRAMES 7 + +/* + * Gamma out + */ +/* Maximum number of color samples supported */ +#define CIFISP_GAMMA_OUT_MAX_SAMPLES 34 + +/* + * Lens shade correction + */ +#define CIFISP_LSC_GRAD_TBL_SIZE 8 +#define CIFISP_LSC_SIZE_TBL_SIZE 8 +/* + * The following matches the tuning process, + * not the max capabilities of the chip. + * Last value unused. + */ +#define CIFISP_LSC_DATA_TBL_SIZE 290 + +/* + * Histogram calculation + */ +/* Last 3 values unused. */ +#define CIFISP_HISTOGRAM_WEIGHT_GRIDS_SIZE 81 + +/* + * Defect Pixel Cluster Correction + */ +#define CIFISP_DPCC_METHODS_MAX 3 + +/* + * Denoising pre filter + */ +#define CIFISP_DPF_MAX_NLF_COEFFS 17 +#define CIFISP_DPF_MAX_SPATIAL_COEFFS 6 + +/* + * Measurement types + */ +#define CIFISP_STAT_AWB (1 << 0) +#define CIFISP_STAT_AUTOEXP (1 << 1) +#define CIFISP_STAT_AFM_FIN (1 << 2) +#define CIFISP_STAT_HIST (1 << 3) +#define CIFISP_STAT_EMB_DATA (1 << 4) + +#define CIFISP_ADD_DATA_FIFO_SIZE (2048 * 4) + +/* + * private control id + */ +enum cifisp_ctrl_id { + CIFISP_CID_EMB_VC = (V4L2_CTRL_CLASS_CAMERA | 0x1001), + CIFISP_CID_EMB_DT, + CIFISP_CID_LAST +}; + +enum cifisp_histogram_mode { + CIFISP_HISTOGRAM_MODE_DISABLE, + CIFISP_HISTOGRAM_MODE_RGB_COMBINED, + CIFISP_HISTOGRAM_MODE_R_HISTOGRAM, + CIFISP_HISTOGRAM_MODE_G_HISTOGRAM, + CIFISP_HISTOGRAM_MODE_B_HISTOGRAM, + CIFISP_HISTOGRAM_MODE_Y_HISTOGRAM +}; + +enum cifisp_awb_mode_type { + CIFISP_AWB_MODE_MANUAL, + CIFISP_AWB_MODE_RGB, + CIFISP_AWB_MODE_YCBCR +}; + +enum cifisp_flt_mode { + CIFISP_FLT_STATIC_MODE, + CIFISP_FLT_DYNAMIC_MODE +}; + +/** + * enum cifisp_exp_ctrl_auotostop - stop modes + * @CIFISP_EXP_CTRL_AUTOSTOP_0: continuous measurement + * @CIFISP_EXP_CTRL_AUTOSTOP_1: stop measuring after a complete frame + */ +enum cifisp_exp_ctrl_auotostop { + CIFISP_EXP_CTRL_AUTOSTOP_0 = 0, + CIFISP_EXP_CTRL_AUTOSTOP_1 = 1, +}; + +/** + * enum cifisp_exp_meas_mode - Exposure measure mode + * @CIFISP_EXP_MEASURING_MODE_0: Y = 16 + 0.25R + 0.5G + 0.1094B + * @CIFISP_EXP_MEASURING_MODE_1: Y = (R + G + B) x (85/256) + */ +enum cifisp_exp_meas_mode { + CIFISP_EXP_MEASURING_MODE_0, + CIFISP_EXP_MEASURING_MODE_1, +}; + +/*---------- PART1: Input Parameters ------------*/ + +struct cifisp_window { + unsigned short h_offs; + unsigned short v_offs; + unsigned short h_size; + unsigned short v_size; +} __attribute__ ((packed)); + +/** + * struct cifisp_bls_fixed_val - BLS fixed subtraction values + * + * The values will be subtracted from the sensor + * values. Therefore a negative value means addition instead of subtraction! + * + * @r: Fixed (signed!) subtraction value for Bayer pattern R + * @gr: Fixed (signed!) subtraction value for Bayer pattern Gr + * @gb: Fixed (signed!) subtraction value for Bayer pattern Gb + * @b: Fixed (signed!) subtraction value for Bayer pattern B + */ +struct cifisp_bls_fixed_val { + signed short r; + signed short gr; + signed short gb; + signed short b; +} __attribute__ ((packed)); + +/** + * struct cifisp_bls_config - Configuration used by black level subtraction + * + * @enable_auto: Automatic mode activated means that the measured values + * are subtracted.Otherwise the fixed subtraction + * values will be subtracted. + * @en_windows: enabled window + * @bls_window1: Measurement window 1 size + * @bls_window2: Measurement window 2 size + * @bls_samples: Set amount of measured pixels for each Bayer position + * (A, B,C and D) to 2^bls_samples. + * @cifisp_bls_fixed_val: Fixed subtraction values + */ +struct cifisp_bls_config { + unsigned char enable_auto; + unsigned char en_windows; + struct cifisp_window bls_window1; + struct cifisp_window bls_window2; + unsigned char bls_samples; + struct cifisp_bls_fixed_val fixed_val; +} __attribute__ ((packed)); + +/** + * struct cifisp_dpcc_methods_config - Methods Configuration used by Defect Pixel Cluster Correction + * + * @method: + * @line_thresh: + * @line_mad_fac: + * @pg_fac: + * @rnd_thresh: + * @rg_fac: + */ +struct cifisp_dpcc_methods_config { + unsigned int method; + unsigned int line_thresh; + unsigned int line_mad_fac; + unsigned int pg_fac; + unsigned int rnd_thresh; + unsigned int rg_fac; +} __attribute__ ((packed)); + +/** + * struct cifisp_dpcc_methods_config - Configuration used by Defect Pixel Cluster Correction + * + * @mode: dpcc output mode + * @output_mode: whether use hard coded methods + * @set_use: stage1 methods set + * @methods: methods config + * @ro_limits: rank order limits + * @rnd_offs: differential rank offsets for rank neighbor difference + */ +struct cifisp_dpcc_config { + unsigned int mode; + unsigned int output_mode; + unsigned int set_use; + struct cifisp_dpcc_methods_config methods[CIFISP_DPCC_METHODS_MAX]; + unsigned int ro_limits; + unsigned int rnd_offs; +} __attribute__ ((packed)); + +struct cifisp_gamma_corr_curve { + unsigned short gamma_y[CIFISP_DEGAMMA_CURVE_SIZE]; +} __attribute__ ((packed)); + +struct cifisp_gamma_curve_x_axis_pnts { + unsigned int gamma_dx0; + unsigned int gamma_dx1; +} __attribute__ ((packed)); + +/** + * struct cifisp_gamma_corr_curve - Configuration used by sensor degamma + * + * @curve_x: gamma curve point definition axis for x + * @xa_pnts: x increments + */ +struct cifisp_sdg_config { + struct cifisp_gamma_corr_curve curve_r; + struct cifisp_gamma_corr_curve curve_g; + struct cifisp_gamma_corr_curve curve_b; + struct cifisp_gamma_curve_x_axis_pnts xa_pnts; +} __attribute__ ((packed)); + +/** + * struct cifisp_lsc_config - Configuration used by Lens shading correction + * + * refer to datasheet for details + */ +struct cifisp_lsc_config { + unsigned int r_data_tbl[CIFISP_LSC_DATA_TBL_SIZE]; + unsigned int gr_data_tbl[CIFISP_LSC_DATA_TBL_SIZE]; + unsigned int gb_data_tbl[CIFISP_LSC_DATA_TBL_SIZE]; + unsigned int b_data_tbl[CIFISP_LSC_DATA_TBL_SIZE]; + + unsigned int x_grad_tbl[CIFISP_LSC_GRAD_TBL_SIZE]; + unsigned int y_grad_tbl[CIFISP_LSC_GRAD_TBL_SIZE]; + + unsigned int x_size_tbl[CIFISP_LSC_SIZE_TBL_SIZE]; + unsigned int y_size_tbl[CIFISP_LSC_SIZE_TBL_SIZE]; + unsigned short config_width; + unsigned short config_height; +} __attribute__ ((packed)); + +/** + * struct cifisp_ie_config - Configuration used by image effects + * + * @eff_mat_1: 3x3 Matrix Coefficients for Emboss Effect 1 + * @eff_mat_2: 3x3 Matrix Coefficients for Emboss Effect 2 + * @eff_mat_3: 3x3 Matrix Coefficients for Emboss 3/Sketch 1 + * @eff_mat_4: 3x3 Matrix Coefficients for Sketch Effect 2 + * @eff_mat_5: 3x3 Matrix Coefficients for Sketch Effect 3 + * @eff_tint: Chrominance increment values of tint (used for sepia effect) + */ +struct cifisp_ie_config { + unsigned short effect; + unsigned short color_sel; + unsigned short eff_mat_1; + unsigned short eff_mat_2; + unsigned short eff_mat_3; + unsigned short eff_mat_4; + unsigned short eff_mat_5; + unsigned short eff_tint; +} __attribute__ ((packed)); + +/** + * struct cifisp_cproc_config - Configuration used by Color Processing + * + * @c_out_range: Chrominance pixel clipping range at output. (0 for limit, 1 for full) + * @y_in_range: Luminance pixel clipping range at output. + * @y_out_range: Luminance pixel clipping range at output. + * @contrast: 00~ff, 0.0~1.992 + * @brightness: 80~7F, -128~+127 + * @sat: saturation, 00~FF, 0.0~1.992 + * @hue: 80~7F, -90~+87.188 + */ +struct cifisp_cproc_config { + unsigned char c_out_range; + unsigned char y_in_range; + unsigned char y_out_range; + unsigned char contrast; + unsigned char brightness; + unsigned char sat; + unsigned char hue; +} __attribute__ ((packed)); + +/** + * struct cifisp_awb_meas_config - Configuration used by auto white balance + * + * @awb_wnd: white balance measurement window (in pixels) + * @max_y: only pixels values < max_y contribute to awb measurement, set to 0 to disable this feature + * @min_y: only pixels values > min_y contribute to awb measurement + * @max_csum: Chrominance sum maximum value, only consider pixels with Cb+Cr, smaller than threshold for awb measurements + * @min_c: Chrominance minimum value, only consider pixels with Cb/Cr each greater than threshold value for awb measurements + * @frames: number of frames - 1 used for mean value calculation(ucFrames=0 means 1 Frame) + * @awb_ref_cr: reference Cr value for AWB regulation, target for AWB + * @awb_ref_cb: reference Cb value for AWB regulation, target for AWB + */ +struct cifisp_awb_meas_config { + /* + * Note: currently the h and v offsets are mapped to grid offsets + */ + struct cifisp_window awb_wnd; + enum cifisp_awb_mode_type awb_mode; + unsigned char max_y; + unsigned char min_y; + unsigned char max_csum; + unsigned char min_c; + unsigned char frames; + unsigned char awb_ref_cr; + unsigned char awb_ref_cb; + bool enable_ymax_cmp; +} __attribute__ ((packed)); + +/** + * struct cifisp_awb_gain_config - Configuration used by auto white balance gain + * + * out_data_x = ( AWB_GEAIN_X * in_data + 128) >> 8 + */ +struct cifisp_awb_gain_config { + unsigned short gain_red; + unsigned short gain_green_r; + unsigned short gain_blue; + unsigned short gain_green_b; +} __attribute__ ((packed)); + +/** + * struct cifisp_flt_config - Configuration used by ISP filtering + * + * @mode: ISP_FILT_MODE register fields + * @grn_stage1: ISP_FILT_MODE register fields + * @chr_h_mode: ISP_FILT_MODE register fields + * @chr_v_mode: ISP_FILT_MODE register fields + * + * refer to datasheet for details. + */ +struct cifisp_flt_config { + enum cifisp_flt_mode mode; + unsigned char grn_stage1; + unsigned char chr_h_mode; + unsigned char chr_v_mode; + unsigned int thresh_bl0; + unsigned int thresh_bl1; + unsigned int thresh_sh0; + unsigned int thresh_sh1; + unsigned int lum_weight; + unsigned int fac_sh1; + unsigned int fac_sh0; + unsigned int fac_mid; + unsigned int fac_bl0; + unsigned int fac_bl1; +} __attribute__ ((packed)); + +/** + * struct cifisp_bdm_config - Configuration used by Bayer DeMosaic + * + * @demosaic_th: threshod for bayer demosaicing texture detection + */ +struct cifisp_bdm_config { + unsigned char demosaic_th; +} __attribute__ ((packed)); + +/** + * struct cifisp_ctk_config - Configuration used by Cross Talk correction + * + * @coeff: color correction matrix + * @ct_offset_b: offset for the crosstalk correction matrix + */ +struct cifisp_ctk_config { + unsigned short coeff0; + unsigned short coeff1; + unsigned short coeff2; + unsigned short coeff3; + unsigned short coeff4; + unsigned short coeff5; + unsigned short coeff6; + unsigned short coeff7; + unsigned short coeff8; + unsigned short ct_offset_r; + unsigned short ct_offset_g; + unsigned short ct_offset_b; +} __attribute__ ((packed)); + +enum cifisp_goc_mode { + CIFISP_GOC_MODE_LOGARITHMIC, + CIFISP_GOC_MODE_EQUIDISTANT +}; + +/** + * struct cifisp_goc_config - Configuration used by Gamma Out correction + * + * @mode: goc mode + * @gamma_y: gamma out curve y-axis for all color components + */ +struct cifisp_goc_config { + enum cifisp_goc_mode mode; + unsigned short gamma_y[CIFISP_GAMMA_OUT_MAX_SAMPLES]; +} __attribute__ ((packed)); + +/** + * struct cifisp_hst_config - Configuration used by Histogram + * + * @mode: histogram mode + * @histogram_predivider: process every stepsize pixel, all other pixels are skipped + * @meas_window: coordinates of the meas window + * @hist_weight: weighting factor for sub-windows + */ +struct cifisp_hst_config { + enum cifisp_histogram_mode mode; + unsigned char histogram_predivider; + struct cifisp_window meas_window; + unsigned char hist_weight[CIFISP_HISTOGRAM_WEIGHT_GRIDS_SIZE]; +} __attribute__ ((packed)); + +/** + * struct cifisp_aec_config - Configuration used by Auto Exposure Control + * + * @mode: Exposure measure mode + * @autostop: stop mode (from enum cifisp_exp_ctrl_auotostop) + * @meas_window: coordinates of the meas window + */ +struct cifisp_aec_config { + enum cifisp_exp_meas_mode mode; + __u32 autostop; + struct cifisp_window meas_window; +} __attribute__ ((packed)); + +/** + * struct cifisp_afc_config - Configuration used by Auto Focus Control + * + * @num_afm_win: max CIFISP_AFM_MAX_WINDOWS + * @afm_win: coordinates of the meas window + * @thres: threshold used for minimizing the influence of noise + * @var_shift: the number of bits for the shift operation at the end of the calculation chain. + */ +struct cifisp_afc_config { + unsigned char num_afm_win; + struct cifisp_window afm_win[CIFISP_AFM_MAX_WINDOWS]; + unsigned int thres; + unsigned int var_shift; +} __attribute__ ((packed)); + +/** + * enum cifisp_dpf_gain_usage - dpf gain usage + * @CIFISP_DPF_GAIN_USAGE_DISABLED: don't use any gains in preprocessing stage + * @CIFISP_DPF_GAIN_USAGE_NF_GAINS: use only the noise function gains from registers DPF_NF_GAIN_R, ... + * @CIFISP_DPF_GAIN_USAGE_LSC_GAINS: use only the gains from LSC module + * @CIFISP_DPF_GAIN_USAGE_NF_LSC_GAINS: use the noise function gains and the gains from LSC module + * @CIFISP_DPF_GAIN_USAGE_AWB_GAINS: use only the gains from AWB module + * @CIFISP_DPF_GAIN_USAGE_AWB_LSC_GAINS: use the gains from AWB and LSC module + * @CIFISP_DPF_GAIN_USAGE_MAX: upper border (only for an internal evaluation) + */ +enum cifisp_dpf_gain_usage { + CIFISP_DPF_GAIN_USAGE_DISABLED, + CIFISP_DPF_GAIN_USAGE_NF_GAINS, + CIFISP_DPF_GAIN_USAGE_LSC_GAINS, + CIFISP_DPF_GAIN_USAGE_NF_LSC_GAINS, + CIFISP_DPF_GAIN_USAGE_AWB_GAINS, + CIFISP_DPF_GAIN_USAGE_AWB_LSC_GAINS, + CIFISP_DPF_GAIN_USAGE_MAX +}; + +/** + * enum cifisp_dpf_gain_usage - dpf gain usage + * @CIFISP_DPF_RB_FILTERSIZE_13x9: red and blue filter kernel size 13x9 (means 7x5 active pixel) + * @CIFISP_DPF_RB_FILTERSIZE_9x9: red and blue filter kernel size 9x9 (means 5x5 active pixel) + */ +enum cifisp_dpf_rb_filtersize { + CIFISP_DPF_RB_FILTERSIZE_13x9, + CIFISP_DPF_RB_FILTERSIZE_9x9, +}; + +/** + * enum cifisp_dpf_nll_scale_mode - dpf noise level scale mode + * @CIFISP_NLL_SCALE_LINEAR: use a linear scaling + * @CIFISP_NLL_SCALE_LOGARITHMIC: use a logarithmic scaling + */ +enum cifisp_dpf_nll_scale_mode { + CIFISP_NLL_SCALE_LINEAR, + CIFISP_NLL_SCALE_LOGARITHMIC, +}; + +struct cifisp_dpf_nll { + unsigned short coeff[CIFISP_DPF_MAX_NLF_COEFFS]; + enum cifisp_dpf_nll_scale_mode scale_mode; +} __attribute__ ((packed)); + +struct cifisp_dpf_rb_flt { + enum cifisp_dpf_rb_filtersize fltsize; + unsigned char spatial_coeff[CIFISP_DPF_MAX_SPATIAL_COEFFS]; + bool r_enable; + bool b_enable; +} __attribute__ ((packed)); + +struct cifisp_dpf_g_flt { + unsigned char spatial_coeff[CIFISP_DPF_MAX_SPATIAL_COEFFS]; + bool gr_enable; + bool gb_enable; +} __attribute__ ((packed)); + +struct cifisp_dpf_gain { + enum cifisp_dpf_gain_usage mode; + unsigned short nf_r_gain; + unsigned short nf_b_gain; + unsigned short nf_gr_gain; + unsigned short nf_gb_gain; +} __attribute__ ((packed)); + +/** + * struct cifisp_dpf_config - Configuration used by De-noising pre-filter + * + * @gain: noise function gain + * @g_flt: green filter config + * @rb_flt: red blue filter config + * @nll: noise level lookup + */ +struct cifisp_dpf_config { + struct cifisp_dpf_gain gain; + struct cifisp_dpf_g_flt g_flt; + struct cifisp_dpf_rb_flt rb_flt; + struct cifisp_dpf_nll nll; +} __attribute__ ((packed)); + +/** + * struct cifisp_dpf_strength_config - strength of the filter + * + * @r: filter strength of the RED filter + * @g: filter strength of the GREEN filter + * @b: filter strength of the BLUE filter + */ +struct cifisp_dpf_strength_config { + unsigned char r; + unsigned char g; + unsigned char b; +} __attribute__ ((packed)); + +/** + * struct cifisp_isp_other_cfg - Parameters for some blocks in rockchip isp1 + * + * @dpcc_config: Defect Pixel Cluster Correction config + * @bls_config: Black Level Subtraction config + * @sdg_config: sensor degamma config + * @lsc_config: Lens Shade config + * @awb_gain_config: Auto White balance gain config + * @flt_config: filter config + * @bdm_config: demosaic config + * @ctk_config: cross talk config + * @goc_config: gamma out config + * @bls_config: black level suntraction config + * @dpf_config: De-noising pre-filter config + * @dpf_strength_config: dpf strength config + * @cproc_config: color process config + * @ie_config: image effects config + */ +struct cifisp_isp_other_cfg { + struct cifisp_dpcc_config dpcc_config; + struct cifisp_bls_config bls_config; + struct cifisp_sdg_config sdg_config; + struct cifisp_lsc_config lsc_config; + struct cifisp_awb_gain_config awb_gain_config; + struct cifisp_flt_config flt_config; + struct cifisp_bdm_config bdm_config; + struct cifisp_ctk_config ctk_config; + struct cifisp_goc_config goc_config; + struct cifisp_dpf_config dpf_config; + struct cifisp_dpf_strength_config dpf_strength_config; + struct cifisp_cproc_config cproc_config; + struct cifisp_ie_config ie_config; +} __attribute__ ((packed)); + +/** + * struct cifisp_isp_meas_cfg - Rockchip ISP1 Measure Parameters + * + * @awb_meas_config: auto white balance config + * @hst_config: histogram config + * @aec_config: auto exposure config + * @afc_config: auto focus config + */ +struct cifisp_isp_meas_cfg { + struct cifisp_awb_meas_config awb_meas_config; + struct cifisp_hst_config hst_config; + struct cifisp_aec_config aec_config; + struct cifisp_afc_config afc_config; +} __attribute__ ((packed)); + +/** + * struct rkisp1_isp_params_cfg - Rockchip ISP1 Input Parameters Meta Data + * + * @module_en_update: mask the enable bits of which module should be updated + * @module_ens: mask the enable value of each module, only update the module + * which correspond bit was set in module_en_update + * @module_cfg_update: mask the config bits of which module should be updated + * @meas: measurement config + * @others: other config + */ +struct rkisp1_isp_params_cfg { + unsigned int module_en_update; + unsigned int module_ens; + unsigned int module_cfg_update; + + struct cifisp_isp_meas_cfg meas; + struct cifisp_isp_other_cfg others; +} __attribute__ ((packed)); + +/*---------- PART2: Measurement Statistics ------------*/ + +/** + * struct cifisp_bls_meas_val - AWB measured values + * + * @cnt: White pixel count, number of "white pixels" found during laster measurement + * @mean_y_or_g: Mean value of Y within window and frames, Green if RGB is selected. + * @mean_cb_or_b: Mean value of Cb within window and frames, Blue if RGB is selected. + * @mean_cr_or_r: Mean value of Cr within window and frames, Red if RGB is selected. + */ +struct cifisp_awb_meas { + unsigned int cnt; + unsigned char mean_y_or_g; + unsigned char mean_cb_or_b; + unsigned char mean_cr_or_r; +} __attribute__ ((packed)); + +/** + * struct cifisp_awb_stat - statistics automatic white balance data + * + * @awb_mean: Mean measured data + */ +struct cifisp_awb_stat { + struct cifisp_awb_meas awb_mean[CIFISP_AWB_MAX_GRID]; +} __attribute__ ((packed)); + +/** + * struct cifisp_bls_meas_val - BLS measured values + * + * @meas_r: Mean measured value for Bayer pattern R + * @meas_gr: Mean measured value for Bayer pattern Gr + * @meas_gb: Mean measured value for Bayer pattern Gb + * @meas_b: Mean measured value for Bayer pattern B + */ +struct cifisp_bls_meas_val { + unsigned short meas_r; + unsigned short meas_gr; + unsigned short meas_gb; + unsigned short meas_b; +} __attribute__ ((packed)); + +/** + * struct cifisp_ae_stat - statistics auto exposure data + * + * @exp_mean: Mean luminance value of block xx + * @bls_val: available wit exposure results + * + * Image is divided into 5x5 blocks. + */ +struct cifisp_ae_stat { + unsigned char exp_mean[CIFISP_AE_MEAN_MAX]; + struct cifisp_bls_meas_val bls_val; +} __attribute__ ((packed)); + +/** + * struct cifisp_af_meas_val - AF measured values + * + * @sum: sharpness, refer to datasheet for definition + * @lum: luminance, refer to datasheet for definition + */ +struct cifisp_af_meas_val { + unsigned int sum; + unsigned int lum; +} __attribute__ ((packed)); + +/** + * struct cifisp_af_stat - statistics auto focus data + * + * @window: AF measured value of window x + * + * The module measures the sharpness in 3 windows of selectable size via + * register settings(ISP_AFM_*_A/B/C) + */ +struct cifisp_af_stat { + struct cifisp_af_meas_val window[CIFISP_AFM_MAX_WINDOWS]; +} __attribute__ ((packed)); + +/** + * struct cifisp_hist_stat - statistics histogram data + * + * @hist_bins: measured bin counters + * + * Measurement window divided into 25 sub-windows, set + * with ISP_HIST_XXX + */ +struct cifisp_hist_stat { + unsigned int hist_bins[CIFISP_HIST_BIN_N_MAX]; +} __attribute__ ((packed)); + +/** + * struct cifisp_embedded_data - embedded data + * + * @data: embedded data + * + */ +struct cifisp_embedded_data { + unsigned char data[CIFISP_ADD_DATA_FIFO_SIZE]; +} __attribute__ ((packed)); + +/** + * struct rkisp1_stat_buffer - Rockchip ISP1 Statistics Data + * + * @cifisp_awb_stat: statistics data for automatic white balance + * @cifisp_ae_stat: statistics data for auto exposure + * @cifisp_af_stat: statistics data for auto focus + * @cifisp_hist_stat: statistics histogram data + */ +struct cifisp_stat { + struct cifisp_awb_stat awb; + struct cifisp_ae_stat ae; + struct cifisp_af_stat af; + struct cifisp_hist_stat hist; + struct cifisp_embedded_data emd; +} __attribute__ ((packed)); + +/** + * struct rkisp1_stat_buffer - Rockchip ISP1 Statistics Meta Data + * + * @meas_type: measurement types (CIFISP_STAT_ definitions) + * @frame_id: frame ID for sync + * @params: statistics data + */ +struct rkisp1_stat_buffer { + unsigned int meas_type; + unsigned int frame_id; + struct cifisp_stat params; +} __attribute__ ((packed)); + +#endif /* _UAPI_RKISP1_CONFIG_H */ diff --git a/include/uapi/linux/usb/f_mtp.h b/include/uapi/linux/usb/f_mtp.h index 503291855abd..b48a74b3695c 100644 --- a/include/uapi/linux/usb/f_mtp.h +++ b/include/uapi/linux/usb/f_mtp.h @@ -4,6 +4,8 @@ * Copyright (C) 2010 Google, Inc. * Author: Mike Lockwood <lockwood@android.com> * + * Copyright (C) 2014, NVIDIA CORPORATION. All rights reserved. + * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. @@ -45,6 +47,17 @@ struct mtp_event { void *data; }; +#ifdef CONFIG_COMPAT +struct mtp_event_32 { + /* size of the event */ + compat_size_t length; + /* event data to send */ + compat_uptr_t data; +}; + +#define MTP_SEND_EVENT_32 _IOW('M', 3, struct mtp_event_32) +#endif + /* Sends the specified file range to the host */ #define MTP_SEND_FILE _IOW('M', 0, struct mtp_file_range) /* Receives data from the host and writes it to a file. diff --git a/include/uapi/linux/usbdevice_fs.h b/include/uapi/linux/usbdevice_fs.h index 019ba1e0799a..ecbd17650e6c 100644 --- a/include/uapi/linux/usbdevice_fs.h +++ b/include/uapi/linux/usbdevice_fs.h @@ -134,6 +134,7 @@ struct usbdevfs_hub_portinfo { #define USBDEVFS_CAP_NO_PACKET_SIZE_LIM 0x04 #define USBDEVFS_CAP_BULK_SCATTER_GATHER 0x08 #define USBDEVFS_CAP_REAP_AFTER_DISCONNECT 0x10 +#define USBDEVFS_CAP_MMAP 0x20 /* USBDEVFS_DISCONNECT_CLAIM flags & struct */ diff --git a/include/uapi/linux/uvcvideo.h b/include/uapi/linux/uvcvideo.h index 3b081862b9e8..8381ca7c2ba5 100644 --- a/include/uapi/linux/uvcvideo.h +++ b/include/uapi/linux/uvcvideo.h @@ -67,4 +67,30 @@ struct uvc_xu_control_query { #define UVCIOC_CTRL_MAP _IOWR('u', 0x20, struct uvc_xu_control_mapping) #define UVCIOC_CTRL_QUERY _IOWR('u', 0x21, struct uvc_xu_control_query) +/* + * Metadata node + */ + +/** + * struct uvc_meta_buf - metadata buffer building block + * @ns - system timestamp of the payload in nanoseconds + * @sof - USB Frame Number + * @length - length of the payload header + * @flags - payload header flags + * @buf - optional device-specific header data + * + * UVC metadata nodes fill buffers with possibly multiple instances of this + * struct. The first two fields are added by the driver, they can be used for + * clock synchronisation. The rest is an exact copy of a UVC payload header. + * Only complete objects with complete buffers are included. Therefore it's + * always sizeof(meta->ts) + sizeof(meta->sof) + meta->length bytes large. + */ +struct uvc_meta_buf { + __u64 ns; + __u16 sof; + __u8 length; + __u8 flags; + __u8 buf[]; +} __packed; + #endif diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h index 1bdce501ad6b..3fbffa78ca17 100644 --- a/include/uapi/linux/v4l2-controls.h +++ b/include/uapi/linux/v4l2-controls.h @@ -49,6 +49,8 @@ #ifndef __LINUX_V4L2_CONTROLS_H #define __LINUX_V4L2_CONTROLS_H +#include <linux/types.h> + /* Control classes */ #define V4L2_CTRL_CLASS_USER 0x00980000 /* Old-style 'user' controls */ #define V4L2_CTRL_CLASS_MPEG 0x00990000 /* MPEG-compression controls */ @@ -174,9 +176,9 @@ enum v4l2_colorfx { * We reserve 16 controls for this driver. */ #define V4L2_CID_USER_ADV7180_BASE (V4L2_CID_USER_BASE + 0x1070) -/* The base for the tc358743 driver controls. +/* The base for the tc35874x driver controls. * We reserve 16 controls for this driver. */ -#define V4L2_CID_USER_TC358743_BASE (V4L2_CID_USER_BASE + 0x1080) +#define V4L2_CID_USER_TC35874X_BASE (V4L2_CID_USER_BASE + 0x1080) /* MPEG-class control IDs */ /* The MPEG controls are applicable to all codec controls @@ -388,6 +390,7 @@ enum v4l2_mpeg_video_multi_slice_mode { #define V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER (V4L2_CID_MPEG_BASE+226) #define V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE (V4L2_CID_MPEG_BASE+227) #define V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE (V4L2_CID_MPEG_BASE+228) +#define V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME (V4L2_CID_MPEG_BASE+229) #define V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP (V4L2_CID_MPEG_BASE+300) #define V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP (V4L2_CID_MPEG_BASE+301) @@ -518,6 +521,12 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type { }; #define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER (V4L2_CID_MPEG_BASE+381) #define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP (V4L2_CID_MPEG_BASE+382) +#define V4L2_CID_MPEG_VIDEO_H264_SPS (V4L2_CID_MPEG_BASE+383) +#define V4L2_CID_MPEG_VIDEO_H264_PPS (V4L2_CID_MPEG_BASE+384) +#define V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX (V4L2_CID_MPEG_BASE+385) +#define V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAM (V4L2_CID_MPEG_BASE+386) +#define V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAM (V4L2_CID_MPEG_BASE+387) + #define V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP (V4L2_CID_MPEG_BASE+400) #define V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP (V4L2_CID_MPEG_BASE+401) #define V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP (V4L2_CID_MPEG_BASE+402) @@ -576,6 +585,8 @@ enum v4l2_vp8_golden_frame_sel { #define V4L2_CID_MPEG_VIDEO_VPX_P_FRAME_QP (V4L2_CID_MPEG_BASE+510) #define V4L2_CID_MPEG_VIDEO_VPX_PROFILE (V4L2_CID_MPEG_BASE+511) +#define V4L2_CID_MPEG_VIDEO_VP8_FRAME_HDR (V4L2_CID_MPEG_BASE+512) + /* MPEG-class control IDs specific to the CX2341x driver as defined by V4L2 */ #define V4L2_CID_MPEG_CX2341X_BASE (V4L2_CTRL_CLASS_MPEG | 0x1000) #define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE (V4L2_CID_MPEG_CX2341X_BASE+0) @@ -672,6 +683,27 @@ enum v4l2_exposure_auto_type { #define V4L2_CID_FOCUS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+11) #define V4L2_CID_FOCUS_AUTO (V4L2_CID_CAMERA_CLASS_BASE+12) +/* ddl@rock-chips.com : Add ioctrl - V4L2_CID_SCENE for camera scene control */ +#define V4L2_CID_CAMERA_CLASS_BASE_ROCK (V4L2_CID_CAMERA_CLASS_BASE + 40) +#define V4L2_CID_SCENE (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 1) +#define V4L2_CID_EFFECT (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 2) +#define V4L2_CID_FLASH (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 3) +#define V4L2_CID_FOCUS_CONTINUOUS (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 4) +#define V4L2_CID_FOCUSZONE (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 5) +#define V4L2_CID_FACEDETECT (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 6) +#define V4L2_CID_HDR (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 7) +#define V4L2_CID_ISO (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 8) +#define V4L2_CID_ANTIBANDING (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 9) +#define V4L2_CID_WHITEBALANCE_LOCK (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 10) +#define V4L2_CID_EXPOSURE_LOCK (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 11) +#define V4L2_CID_METERING_AREAS (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 12) +#define V4L2_CID_WDR (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 13) +#define V4L2_CID_EDGE (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 14) +#define V4L2_CID_JPEG_EXIF (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 15) +#define V4L2_CID_DEINTERLACE (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 16) +#define V4L2_CID_CHANNEL (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 17) +#define V4L2_CID_VIDEO_STATE (V4L2_CID_CAMERA_CLASS_BASE_ROCK + 18) + #define V4L2_CID_ZOOM_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+13) #define V4L2_CID_ZOOM_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+14) #define V4L2_CID_ZOOM_CONTINUOUS (V4L2_CID_CAMERA_CLASS_BASE+15) @@ -890,6 +922,21 @@ enum v4l2_jpeg_chroma_subsampling { #define V4L2_CID_PIXEL_RATE (V4L2_CID_IMAGE_PROC_CLASS_BASE + 2) #define V4L2_CID_TEST_PATTERN (V4L2_CID_IMAGE_PROC_CLASS_BASE + 3) +#define V4L2_CID_PORTER_DUFF_MODE (V4L2_CID_IMAGE_PROC_CLASS_BASE + 5) +enum v4l2_porter_duff_mode { + V4L2_PORTER_DUFF_SRC = 0, + V4L2_PORTER_DUFF_SRCATOP = 1, + V4L2_PORTER_DUFF_SRCIN = 2, + V4L2_PORTER_DUFF_SRCOUT = 3, + V4L2_PORTER_DUFF_SRCOVER = 4, + V4L2_PORTER_DUFF_DST = 5, + V4L2_PORTER_DUFF_DSTATOP = 6, + V4L2_PORTER_DUFF_DSTIN = 7, + V4L2_PORTER_DUFF_DSTOUT = 8, + V4L2_PORTER_DUFF_DSTOVER = 9, + V4L2_PORTER_DUFF_ADD = 10, + V4L2_PORTER_DUFF_CLEAR = 11, +}; /* DV-class control IDs defined by V4L2 */ #define V4L2_CID_DV_CLASS_BASE (V4L2_CTRL_CLASS_DV | 0x900) @@ -961,4 +1008,245 @@ enum v4l2_detect_md_mode { #define V4L2_CID_DETECT_MD_THRESHOLD_GRID (V4L2_CID_DETECT_CLASS_BASE + 3) #define V4L2_CID_DETECT_MD_REGION_GRID (V4L2_CID_DETECT_CLASS_BASE + 4) + +/* Complex controls */ + +#define V4L2_H264_SPS_CONSTRAINT_SET0_FLAG 0x01 +#define V4L2_H264_SPS_CONSTRAINT_SET1_FLAG 0x02 +#define V4L2_H264_SPS_CONSTRAINT_SET2_FLAG 0x04 +#define V4L2_H264_SPS_CONSTRAINT_SET3_FLAG 0x08 +#define V4L2_H264_SPS_CONSTRAINT_SET4_FLAG 0x10 +#define V4L2_H264_SPS_CONSTRAINT_SET5_FLAG 0x20 + +#define V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE 0x01 +#define V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS 0x02 +#define V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO 0x04 +#define V4L2_H264_SPS_FLAG_GAPS_IN_FRAME_NUM_VALUE_ALLOWED 0x08 +#define V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY 0x10 +#define V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD 0x20 +#define V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE 0x40 +struct v4l2_ctrl_h264_sps { + __u8 profile_idc; + __u8 constraint_set_flags; + __u8 level_idc; + __u8 seq_parameter_set_id; + __u8 chroma_format_idc; + __u8 bit_depth_luma_minus8; + __u8 bit_depth_chroma_minus8; + __u8 log2_max_frame_num_minus4; + __u8 pic_order_cnt_type; + __u8 log2_max_pic_order_cnt_lsb_minus4; + __s32 offset_for_non_ref_pic; + __s32 offset_for_top_to_bottom_field; + __u8 num_ref_frames_in_pic_order_cnt_cycle; + __s32 offset_for_ref_frame[255]; + __u8 max_num_ref_frames; + __u16 pic_width_in_mbs_minus1; + __u16 pic_height_in_map_units_minus1; + __u8 flags; +}; + +#define V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE 0x0001 +#define V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT 0x0002 +#define V4L2_H264_PPS_FLAG_WEIGHTED_PRED 0x0004 +#define V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT 0x0008 +#define V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED 0x0010 +#define V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT 0x0020 +#define V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE 0x0040 +#define V4L2_H264_PPS_FLAG_PIC_SCALING_MATRIX_PRESENT 0x0080 +struct v4l2_ctrl_h264_pps { + __u8 pic_parameter_set_id; + __u8 seq_parameter_set_id; + __u8 num_slice_groups_minus1; + __u8 num_ref_idx_l0_default_active_minus1; + __u8 num_ref_idx_l1_default_active_minus1; + __u8 weighted_bipred_idc; + __s8 pic_init_qp_minus26; + __s8 pic_init_qs_minus26; + __s8 chroma_qp_index_offset; + __s8 second_chroma_qp_index_offset; + __u8 flags; +}; + +struct v4l2_ctrl_h264_scaling_matrix { + __u8 scaling_list_4x4[6][16]; + __u8 scaling_list_8x8[6][64]; +}; + +struct v4l2_h264_weight_factors { + __s8 luma_weight[32]; + __s8 luma_offset[32]; + __s8 chroma_weight[32][2]; + __s8 chroma_offset[32][2]; +}; + +struct v4l2_h264_pred_weight_table { + __u8 luma_log2_weight_denom; + __u8 chroma_log2_weight_denom; + struct v4l2_h264_weight_factors weight_factors[2]; +}; + +#define V4L2_SLICE_FLAG_FIELD_PIC 0x01 +#define V4L2_SLICE_FLAG_BOTTOM_FIELD 0x02 +#define V4L2_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED 0x04 +#define V4L2_SLICE_FLAG_SP_FOR_SWITCH 0x08 +struct v4l2_ctrl_h264_slice_param { + /* Size in bytes, including header */ + __u32 size; + /* Offset in bits to slice_data() from the beginning of this slice. */ + __u32 header_bit_size; + + __u16 first_mb_in_slice; + __u8 slice_type; + __u8 pic_parameter_set_id; + __u8 colour_plane_id; + __u16 frame_num; + __u16 idr_pic_id; + __u16 pic_order_cnt_lsb; + __s32 delta_pic_order_cnt_bottom; + __s32 delta_pic_order_cnt0; + __s32 delta_pic_order_cnt1; + __u8 redundant_pic_cnt; + + struct v4l2_h264_pred_weight_table pred_weight_table; + /* Size in bits of dec_ref_pic_marking() syntax element. */ + __u32 dec_ref_pic_marking_bit_size; + /* Size in bits of pic order count syntax. */ + __u32 pic_order_cnt_bit_size; + + __u8 cabac_init_idc; + __s8 slice_qp_delta; + __s8 slice_qs_delta; + __u8 disable_deblocking_filter_idc; + __s8 slice_alpha_c0_offset_div2; + __s8 slice_beta_offset_div2; + __u32 slice_group_change_cycle; + + __u8 num_ref_idx_l0_active_minus1; + __u8 num_ref_idx_l1_active_minus1; + /* Entries on each list are indices + * into v4l2_ctrl_h264_decode_param.dpb[]. */ + __u8 ref_pic_list0[32]; + __u8 ref_pic_list1[32]; + + __u8 flags; +}; + +/* If not set, this entry is unused for reference. */ +#define V4L2_H264_DPB_ENTRY_FLAG_ACTIVE 0x01 +#define V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM 0x02 +struct v4l2_h264_dpb_entry { + __u32 buf_index; /* v4l2_buffer index */ + __u16 frame_num; + __u16 pic_num; + /* Note that field is indicated by v4l2_buffer.field */ + __s32 top_field_order_cnt; + __s32 bottom_field_order_cnt; + __u8 flags; /* V4L2_H264_DPB_ENTRY_FLAG_* */ +}; + +struct v4l2_ctrl_h264_decode_param { + __u32 num_slices; + __u8 idr_pic_flag; + __u8 nal_ref_idc; + __s32 top_field_order_cnt; + __s32 bottom_field_order_cnt; + __u8 ref_pic_list_p0[32]; + __u8 ref_pic_list_b0[32]; + __u8 ref_pic_list_b1[32]; + struct v4l2_h264_dpb_entry dpb[16]; +}; + +#define V4L2_VP8_SEGMNT_HDR_FLAG_ENABLED 0x01 +#define V4L2_VP8_SEGMNT_HDR_FLAG_UPDATE_MAP 0x02 +#define V4L2_VP8_SEGMNT_HDR_FLAG_UPDATE_FEATURE_DATA 0x04 +struct v4l2_vp8_sgmnt_hdr { + __u8 segment_feature_mode; + + __s8 quant_update[4]; + __s8 lf_update[4]; + __u8 segment_probs[3]; + + __u8 flags; +}; + +#define V4L2_VP8_LF_HDR_ADJ_ENABLE 0x01 +#define V4L2_VP8_LF_HDR_DELTA_UPDATE 0x02 +struct v4l2_vp8_loopfilter_hdr { + __u8 type; + __u8 level; + __u8 sharpness_level; + __s8 ref_frm_delta_magnitude[4]; + __s8 mb_mode_delta_magnitude[4]; + + __u8 flags; +}; + +struct v4l2_vp8_quantization_hdr { + __u8 y_ac_qi; + __s8 y_dc_delta; + __s8 y2_dc_delta; + __s8 y2_ac_delta; + __s8 uv_dc_delta; + __s8 uv_ac_delta; + __u16 dequant_factors[4][3][2]; +}; + +struct v4l2_vp8_entropy_hdr { + __u8 coeff_probs[4][8][3][11]; + __u8 y_mode_probs[4]; + __u8 uv_mode_probs[3]; + __u8 mv_probs[2][19]; +}; + +#define V4L2_VP8_FRAME_HDR_FLAG_EXPERIMENTAL 0x01 +#define V4L2_VP8_FRAME_HDR_FLAG_SHOW_FRAME 0x02 +#define V4L2_VP8_FRAME_HDR_FLAG_MB_NO_SKIP_COEFF 0x04 +struct v4l2_ctrl_vp8_frame_hdr { + /* 0: keyframe, 1: not a keyframe */ + __u8 key_frame; + __u8 version; + + /* Populated also if not a key frame */ + __u16 width; + __u8 horizontal_scale; + __u16 height; + __u8 vertical_scale; + + struct v4l2_vp8_sgmnt_hdr sgmnt_hdr; + struct v4l2_vp8_loopfilter_hdr lf_hdr; + struct v4l2_vp8_quantization_hdr quant_hdr; + struct v4l2_vp8_entropy_hdr entropy_hdr; + + __u8 sign_bias_golden; + __u8 sign_bias_alternate; + + __u8 prob_skip_false; + __u8 prob_intra; + __u8 prob_last; + __u8 prob_gf; + + __u32 first_part_size; + __u32 first_part_offset; + /* + * Offset in bits of MB data in first partition, + * i.e. bit offset starting from first_part_offset. + */ + __u32 macroblock_bit_offset; + + __u8 num_dct_parts; + __u32 dct_part_sizes[8]; + + __u8 bool_dec_range; + __u8 bool_dec_value; + __u8 bool_dec_count; + + /* v4l2_buffer indices of reference frames */ + __u32 last_frame; + __u32 golden_frame; + __u32 alt_frame; + + __u8 flags; +}; + #endif diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index 421d27413731..049b20b9ab15 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -146,6 +146,8 @@ enum v4l2_buf_type { V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE = 10, V4L2_BUF_TYPE_SDR_CAPTURE = 11, V4L2_BUF_TYPE_SDR_OUTPUT = 12, + V4L2_BUF_TYPE_META_CAPTURE = 13, + V4L2_BUF_TYPE_META_OUTPUT = 14, /* Deprecated, do not use */ V4L2_BUF_TYPE_PRIVATE = 0x80, }; @@ -438,10 +440,12 @@ struct v4l2_capability { #define V4L2_CAP_SDR_CAPTURE 0x00100000 /* Is a SDR capture device */ #define V4L2_CAP_EXT_PIX_FORMAT 0x00200000 /* Supports the extended pixel format */ #define V4L2_CAP_SDR_OUTPUT 0x00400000 /* Is a SDR output device */ +#define V4L2_CAP_META_CAPTURE 0x00800000 /* Is a metadata capture device */ #define V4L2_CAP_READWRITE 0x01000000 /* read/write systemcalls */ #define V4L2_CAP_ASYNCIO 0x02000000 /* async I/O */ #define V4L2_CAP_STREAMING 0x04000000 /* streaming I/O ioctls */ +#define V4L2_CAP_META_OUTPUT 0x08000000 /* Is a metadata output device */ #define V4L2_CAP_DEVICE_CAPS 0x80000000 /* sets device capabilities field */ @@ -546,6 +550,10 @@ struct v4l2_pix_format { /* three non contiguous planes - Y, Cb, Cr */ #define V4L2_PIX_FMT_YUV420M v4l2_fourcc('Y', 'M', '1', '2') /* 12 YUV420 planar */ #define V4L2_PIX_FMT_YVU420M v4l2_fourcc('Y', 'M', '2', '1') /* 12 YVU420 planar */ +#define V4L2_PIX_FMT_YUV422M v4l2_fourcc('Y', 'M', '1', '6') /* 16 YUV422 planar */ +#define V4L2_PIX_FMT_YVU422M v4l2_fourcc('Y', 'M', '6', '1') /* 16 YVU422 planar */ +#define V4L2_PIX_FMT_YUV444M v4l2_fourcc('Y', 'M', '2', '4') /* 24 YUV444 planar */ +#define V4L2_PIX_FMT_YVU444M v4l2_fourcc('Y', 'M', '4', '2') /* 24 YVU444 planar */ /* Bayer formats - see http://www.siliconimaging.com/RGB%20Bayer.htm */ #define V4L2_PIX_FMT_SBGGR8 v4l2_fourcc('B', 'A', '8', '1') /* 8 BGBG.. GRGR.. */ @@ -585,6 +593,7 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_H264 v4l2_fourcc('H', '2', '6', '4') /* H264 with start codes */ #define V4L2_PIX_FMT_H264_NO_SC v4l2_fourcc('A', 'V', 'C', '1') /* H264 without start codes */ #define V4L2_PIX_FMT_H264_MVC v4l2_fourcc('M', '2', '6', '4') /* H264 MVC */ +#define V4L2_PIX_FMT_H264_SLICE v4l2_fourcc('S', '2', '6', '4') /* H264 parsed slices */ #define V4L2_PIX_FMT_H263 v4l2_fourcc('H', '2', '6', '3') /* H263 */ #define V4L2_PIX_FMT_MPEG1 v4l2_fourcc('M', 'P', 'G', '1') /* MPEG-1 ES */ #define V4L2_PIX_FMT_MPEG2 v4l2_fourcc('M', 'P', 'G', '2') /* MPEG-2 ES */ @@ -593,6 +602,7 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_VC1_ANNEX_G v4l2_fourcc('V', 'C', '1', 'G') /* SMPTE 421M Annex G compliant stream */ #define V4L2_PIX_FMT_VC1_ANNEX_L v4l2_fourcc('V', 'C', '1', 'L') /* SMPTE 421M Annex L compliant stream */ #define V4L2_PIX_FMT_VP8 v4l2_fourcc('V', 'P', '8', '0') /* VP8 */ +#define V4L2_PIX_FMT_VP8_FRAME v4l2_fourcc('V', 'P', '8', 'F') /* VP8 parsed frames */ /* Vendor-specific formats */ #define V4L2_PIX_FMT_CPIA1 v4l2_fourcc('C', 'P', 'I', 'A') /* cpia1 YUV */ @@ -632,6 +642,13 @@ struct v4l2_pix_format { #define V4L2_SDR_FMT_CS14LE v4l2_fourcc('C', 'S', '1', '4') /* complex s14le */ #define V4L2_SDR_FMT_RU12LE v4l2_fourcc('R', 'U', '1', '2') /* real u12le */ +/* Vendor specific - used for Rockchip ISP1 camera sub-system */ +#define V4L2_META_FMT_RK_ISP1_PARAMS v4l2_fourcc('R', 'K', '1', 'P') /* Rockchip ISP1 params */ +#define V4L2_META_FMT_RK_ISP1_STAT_3A v4l2_fourcc('R', 'K', '1', 'S') /* Rockchip ISP1 3A statistics */ + +/* Meta-data formats */ +#define V4L2_META_FMT_UVC v4l2_fourcc('U', 'V', 'C', 'H') /* UVC Payload Header metadata */ + /* priv field value to indicates that subsequent fields are valid. */ #define V4L2_PIX_FMT_PRIV_MAGIC 0xfeedcafe @@ -847,6 +864,7 @@ struct v4l2_plane { * @length: size in bytes of the buffer (NOT its payload) for single-plane * buffers (when type != *_MPLANE); number of elements in the * planes array for multi-plane buffers + * @config_store: this buffer should use this configuration store * * Contains data exchanged by application and driver using one of the Streaming * I/O methods. @@ -870,7 +888,7 @@ struct v4l2_buffer { __s32 fd; } m; __u32 length; - __u32 reserved2; + __u32 config_store; __u32 reserved; }; @@ -1474,12 +1492,25 @@ struct v4l2_ext_control { __u8 __user *p_u8; __u16 __user *p_u16; __u32 __user *p_u32; + struct v4l2_ctrl_h264_sps __user *p_h264_sps; + struct v4l2_ctrl_h264_pps __user *p_h264_pps; + struct v4l2_ctrl_h264_scaling_matrix __user *p_h264_scal_mtrx; + struct v4l2_ctrl_h264_slice_param __user *p_h264_slice_param; + struct v4l2_ctrl_h264_decode_param __user *p_h264_decode_param; + struct v4l2_ctrl_vp8_frame_hdr __user *p_vp8_frame_hdr; void __user *ptr; }; + __s32 rect[4];/*rockchip add for focus zone*/ } __attribute__ ((packed)); struct v4l2_ext_controls { - __u32 ctrl_class; + union { +#ifndef __KERNEL__ + __u32 ctrl_class; +#endif + __u32 which; + __u32 config_store; + }; __u32 count; __u32 error_idx; __u32 reserved[2]; @@ -1487,9 +1518,14 @@ struct v4l2_ext_controls { }; #define V4L2_CTRL_ID_MASK (0x0fffffff) +#ifndef __KERNEL__ #define V4L2_CTRL_ID2CLASS(id) ((id) & 0x0fff0000UL) +#endif +#define V4L2_CTRL_ID2WHICH(id) ((id) & 0x0fff0000UL) #define V4L2_CTRL_DRIVER_PRIV(id) (((id) & 0xffff) >= 0x1000) #define V4L2_CTRL_MAX_DIMS (4) +#define V4L2_CTRL_WHICH_CUR_VAL 0 +#define V4L2_CTRL_WHICH_DEF_VAL 0x0f000000 enum v4l2_ctrl_type { V4L2_CTRL_TYPE_INTEGER = 1, @@ -1507,6 +1543,14 @@ enum v4l2_ctrl_type { V4L2_CTRL_TYPE_U8 = 0x0100, V4L2_CTRL_TYPE_U16 = 0x0101, V4L2_CTRL_TYPE_U32 = 0x0102, + V4L2_CTRL_TYPE_H264_SPS = 0x0103, + V4L2_CTRL_TYPE_H264_PPS = 0x0104, + V4L2_CTRL_TYPE_H264_SCALING_MATRIX = 0x0105, + V4L2_CTRL_TYPE_H264_SLICE_PARAM = 0x0106, + V4L2_CTRL_TYPE_H264_DECODE_PARAM = 0x0107, + V4L2_CTRL_TYPE_VP8_FRAME_HDR = 0x108, + + V4L2_CTRL_TYPE_PRIVATE = 0xffff, }; /* Used in the VIDIOC_QUERYCTRL ioctl for querying controls */ @@ -1561,6 +1605,7 @@ struct v4l2_querymenu { #define V4L2_CTRL_FLAG_VOLATILE 0x0080 #define V4L2_CTRL_FLAG_HAS_PAYLOAD 0x0100 #define V4L2_CTRL_FLAG_EXECUTE_ON_WRITE 0x0200 +#define V4L2_CTRL_FLAG_CAN_STORE 0x0400 /* Query flags, to be ORed with the control ID */ #define V4L2_CTRL_FLAG_NEXT_CTRL 0x80000000 @@ -1993,6 +2038,16 @@ struct v4l2_sdr_format { } __attribute__ ((packed)); /** + * struct v4l2_meta_format - metadata format definition + * @dataformat: little endian four character code (fourcc) + * @buffersize: maximum size in bytes required for data + */ +struct v4l2_meta_format { + __u32 dataformat; + __u32 buffersize; +} __attribute__ ((packed)); + +/** * struct v4l2_format - stream data format * @type: enum v4l2_buf_type; type of the data stream * @pix: definition of an image format @@ -2011,6 +2066,7 @@ struct v4l2_format { struct v4l2_vbi_format vbi; /* V4L2_BUF_TYPE_VBI_CAPTURE */ struct v4l2_sliced_vbi_format sliced; /* V4L2_BUF_TYPE_SLICED_VBI_CAPTURE */ struct v4l2_sdr_format sdr; /* V4L2_BUF_TYPE_SDR_CAPTURE */ + struct v4l2_meta_format meta; /* V4L2_BUF_TYPE_META_CAPTURE */ __u8 raw_data[200]; /* user-defined */ } fmt; }; @@ -2097,7 +2153,11 @@ struct v4l2_event { struct v4l2_event_frame_sync frame_sync; struct v4l2_event_src_change src_change; struct v4l2_event_motion_det motion_det; +#ifdef CONFIG_USB_CONFIGFS_F_UVC_ROCKCHIP + __u8 data[4100]; +#else __u8 data[64]; +#endif } u; __u32 pending; __u32 sequence; diff --git a/include/uapi/misc/rkflash_vendor_storage.h b/include/uapi/misc/rkflash_vendor_storage.h new file mode 100644 index 000000000000..e897330ccda2 --- /dev/null +++ b/include/uapi/misc/rkflash_vendor_storage.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +/* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd */ + +#ifndef _RKFLASH_VENDOR_STORAGE +#define _RKFLASH_VENDOR_STORAGE + +struct RK_VENDOR_REQ { + __u32 tag; + __u16 id; + __u16 len; + __u8 data[1024]; +}; + +#define VENDOR_REQ_TAG 0x56524551 +#define VENDOR_READ_IO _IOW('v', 0x01, __u32) +#define VENDOR_WRITE_IO _IOW('v', 0x02, __u32) + +#endif diff --git a/include/uapi/video/Kbuild b/include/uapi/video/Kbuild index ac7203bb32cc..3b2e989f4615 100644 --- a/include/uapi/video/Kbuild +++ b/include/uapi/video/Kbuild @@ -2,3 +2,4 @@ header-y += edid.h header-y += sisfb.h header-y += uvesafb.h +header-y += rk_vpu_service.h diff --git a/include/uapi/video/rk_vpu_service.h b/include/uapi/video/rk_vpu_service.h new file mode 100644 index 000000000000..b75e03c391c7 --- /dev/null +++ b/include/uapi/video/rk_vpu_service.h @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2015 Fuzhou Rockchip Electronics Co., Ltd + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __UAPI_LINUX_RK_VPU_SERVICE_H__ +#define __UAPI_LINUX_RK_VPU_SERVICE_H__ + +#include <linux/types.h> +#include <asm/ioctl.h> + +/* + * Ioctl definitions + */ + +/* Use 'l' as magic number */ +#define VPU_IOC_MAGIC 'l' + +#define VPU_IOC_SET_CLIENT_TYPE _IOW(VPU_IOC_MAGIC, 1, __u32) +#define VPU_IOC_GET_HW_FUSE_STATUS _IOW(VPU_IOC_MAGIC, 2, unsigned long) + +#define VPU_IOC_SET_REG _IOW(VPU_IOC_MAGIC, 3, unsigned long) +#define VPU_IOC_GET_REG _IOW(VPU_IOC_MAGIC, 4, unsigned long) + +#define VPU_IOC_PROBE_IOMMU_STATUS _IOR(VPU_IOC_MAGIC, 5, __u32) +#define VPU_IOC_SET_DRIVER_DATA _IOW(VPU_IOC_MAGIC, 64, u32) + +struct vpu_request { + __u32 *req; + __u32 size; +}; + +/* Hardware decoder configuration description */ +struct vpu_dec_config { + /* Maximum video decoding width supported */ + __u32 max_dec_pic_width; + /* Maximum output width of Post-Processor */ + __u32 max_pp_out_pic_width; + /* HW supports h.264 */ + __u32 h264_support; + /* HW supports JPEG */ + __u32 jpeg_support; + /* HW supports MPEG-4 */ + __u32 mpeg4_support; + /* HW supports custom MPEG-4 features */ + __u32 custom_mpeg4_support; + /* HW supports VC-1 Simple */ + __u32 vc1_support; + /* HW supports MPEG-2 */ + __u32 mpeg2_support; + /* HW supports post-processor */ + __u32 pp_support; + /* HW post-processor functions bitmask */ + __u32 pp_config; + /* HW supports Sorenson Spark */ + __u32 sorenson_support; + /* HW supports reference picture buffering */ + __u32 ref_buf_support; + /* HW supports VP6 */ + __u32 vp6_support; + /* HW supports VP7 */ + __u32 vp7_support; + /* HW supports VP8 */ + __u32 vp8_support; + /* HW supports AVS */ + __u32 avs_support; + /* HW supports JPEG extensions */ + __u32 jpeg_ext_support; + __u32 reserve; + /* HW supports H264 MVC extension */ + __u32 mvc_support; +}; + +/* Hardware encoder configuration description */ +struct vpu_enc_config { + /* Maximum supported width for video encoding (not JPEG) */ + __u32 max_encoded_width; + /* HW supports H.264 */ + __u32 h264_enabled; + /* HW supports JPEG */ + __u32 jpeg_enabled; + /* HW supports MPEG-4 */ + __u32 mpeg4_enabled; + /* HW supports video stabilization */ + __u32 vs_enabled; + /* HW supports RGB input */ + __u32 rgb_enabled; + __u32 reg_size; + __u32 reserv[2]; +}; + +#endif diff --git a/include/video/display_timing.h b/include/video/display_timing.h index 28d9d0d566ca..e9e168a56c5c 100644 --- a/include/video/display_timing.h +++ b/include/video/display_timing.h @@ -28,6 +28,11 @@ enum display_flags { DISPLAY_FLAGS_INTERLACED = BIT(8), DISPLAY_FLAGS_DOUBLESCAN = BIT(9), DISPLAY_FLAGS_DOUBLECLK = BIT(10), +#if defined(CONFIG_FB_ROCKCHIP) + DISPLAY_FLAGS_SWAP_GB = BIT(16), + DISPLAY_FLAGS_SWAP_RG = BIT(17), + DISPLAY_FLAGS_SWAP_RB = BIT(18), +#endif }; /* @@ -71,6 +76,18 @@ struct display_timing { struct timing_entry vsync_len; /* ver. sync len */ enum display_flags flags; /* display flags */ +#if defined(CONFIG_FB_ROCKCHIP) + u16 screen_type; /*screen type*/ + u16 refresh_mode; /* 0: video mode 1: cmd mode */ + u16 screen_widt; /* screen physical size */ + u16 screen_hight; + u16 lvds_format; /*lvds data format for lvds screen*/ + u16 face; /*display output interface format:24bit 18bit 16bit*/ + u16 color_mode; /* input color mode: RGB or YUV */ + u32 *dsp_lut; + u32 *cabc_lut; + u32 *cabc_gamma_base; +#endif }; /* diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h index ddcc8ca7316b..49a53ef8da96 100644 --- a/include/video/mipi_display.h +++ b/include/video/mipi_display.h @@ -38,6 +38,9 @@ enum { MIPI_DSI_DCS_READ = 0x06, + MIPI_DSI_DCS_COMPRESSION_MODE = 0x07, + MIPI_DSI_PPS_LONG_WRITE = 0x0A, + MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, MIPI_DSI_END_OF_TRANSMISSION = 0x08, @@ -115,6 +118,14 @@ enum { MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E, MIPI_DCS_SET_TEAR_SCANLINE = 0x44, MIPI_DCS_GET_SCANLINE = 0x45, + MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */ + MIPI_DCS_GET_DISPLAY_BRIGHTNESS = 0x52, /* MIPI DCS 1.3 */ + MIPI_DCS_WRITE_CONTROL_DISPLAY = 0x53, /* MIPI DCS 1.3 */ + MIPI_DCS_GET_CONTROL_DISPLAY = 0x54, /* MIPI DCS 1.3 */ + MIPI_DCS_WRITE_POWER_SAVE = 0x55, /* MIPI DCS 1.3 */ + MIPI_DCS_GET_POWER_SAVE = 0x56, /* MIPI DCS 1.3 */ + MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E, /* MIPI DCS 1.3 */ + MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F, /* MIPI DCS 1.3 */ MIPI_DCS_READ_DDB_START = 0xA1, MIPI_DCS_READ_DDB_CONTINUE = 0xA8, }; |