diff options
Diffstat (limited to 'include/dt-bindings')
86 files changed, 13175 insertions, 12 deletions
diff --git a/include/dt-bindings/clock/px30-cru.h b/include/dt-bindings/clock/px30-cru.h new file mode 100644 index 000000000000..644d1f5d26d0 --- /dev/null +++ b/include/dt-bindings/clock/px30-cru.h @@ -0,0 +1,406 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Author: Elaine <zhangqing@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H +#define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_NPLL 4 +#define APLL_BOOST_H 5 +#define APLL_BOOST_L 6 +#define ARMCLK 7 + +/* sclk gates (special clocks) */ +#define USB480M 14 +#define SCLK_PDM 15 +#define SCLK_I2S0_TX 16 +#define SCLK_I2S0_TX_OUT 17 +#define SCLK_I2S0_RX 18 +#define SCLK_I2S0_RX_OUT 19 +#define SCLK_I2S1 20 +#define SCLK_I2S1_OUT 21 +#define SCLK_I2S2 22 +#define SCLK_I2S2_OUT 23 +#define SCLK_UART1 24 +#define SCLK_UART2 25 +#define SCLK_UART3 26 +#define SCLK_UART4 27 +#define SCLK_UART5 28 +#define SCLK_I2C0 29 +#define SCLK_I2C1 30 +#define SCLK_I2C2 31 +#define SCLK_I2C3 32 +#define SCLK_I2C4 33 +#define SCLK_PWM0 34 +#define SCLK_PWM1 35 +#define SCLK_SPI0 36 +#define SCLK_SPI1 37 +#define SCLK_TIMER0 38 +#define SCLK_TIMER1 39 +#define SCLK_TIMER2 40 +#define SCLK_TIMER3 41 +#define SCLK_TIMER4 42 +#define SCLK_TIMER5 43 +#define SCLK_TSADC 44 +#define SCLK_SARADC 45 +#define SCLK_OTP 46 +#define SCLK_OTP_USR 47 +#define SCLK_CRYPTO 48 +#define SCLK_CRYPTO_APK 49 +#define SCLK_DDRC 50 +#define SCLK_ISP 51 +#define SCLK_CIF_OUT 52 +#define SCLK_RGA_CORE 53 +#define SCLK_VOPB_PWM 54 +#define SCLK_NANDC 55 +#define SCLK_SDIO 56 +#define SCLK_EMMC 57 +#define SCLK_SFC 58 +#define SCLK_SDMMC 59 +#define SCLK_OTG_ADP 60 +#define SCLK_GMAC_SRC 61 +#define SCLK_GMAC 62 +#define SCLK_GMAC_RX_TX 63 +#define SCLK_MAC_REF 64 +#define SCLK_MAC_REFOUT 65 +#define SCLK_MAC_OUT 66 +#define SCLK_SDMMC_DRV 67 +#define SCLK_SDMMC_SAMPLE 68 +#define SCLK_SDIO_DRV 69 +#define SCLK_SDIO_SAMPLE 70 +#define SCLK_EMMC_DRV 71 +#define SCLK_EMMC_SAMPLE 72 +#define SCLK_GPU 73 +#define SCLK_PVTM 74 +#define SCLK_CORE_VPU 75 +#define SCLK_GMAC_RMII 76 +#define SCLK_UART2_SRC 77 +#define SCLK_NANDC_DIV 78 +#define SCLK_NANDC_DIV50 79 +#define SCLK_SDIO_DIV 80 +#define SCLK_SDIO_DIV50 81 +#define SCLK_EMMC_DIV 82 +#define SCLK_EMMC_DIV50 83 +#define SCLK_DDRCLK 84 +#define SCLK_UART1_SRC 85 +#define SCLK_SDMMC_DIV 86 +#define SCLK_SDMMC_DIV50 87 +#define SCLK_I2S0_TX_MUX 88 +#define SCLK_I2S0_RX_MUX 89 + +/* dclk gates */ +#define DCLK_VOPB 150 +#define DCLK_VOPL 151 + +/* aclk gates */ +#define ACLK_GPU 170 +#define ACLK_BUS_PRE 171 +#define ACLK_CRYPTO 172 +#define ACLK_VI_PRE 173 +#define ACLK_VO_PRE 174 +#define ACLK_VPU 175 +#define ACLK_PERI_PRE 176 +#define ACLK_GMAC 178 +#define ACLK_CIF 179 +#define ACLK_ISP 180 +#define ACLK_VOPB 181 +#define ACLK_VOPL 182 +#define ACLK_RGA 183 +#define ACLK_GIC 184 +#define ACLK_DCF 186 +#define ACLK_DMAC 187 +#define ACLK_BUS_SRC 188 +#define ACLK_PERI_SRC 189 + +/* hclk gates */ +#define HCLK_BUS_PRE 240 +#define HCLK_CRYPTO 241 +#define HCLK_VI_PRE 242 +#define HCLK_VO_PRE 243 +#define HCLK_VPU 244 +#define HCLK_PERI_PRE 245 +#define HCLK_MMC_NAND 246 +#define HCLK_SDMMC 247 +#define HCLK_USB 248 +#define HCLK_CIF 249 +#define HCLK_ISP 250 +#define HCLK_VOPB 251 +#define HCLK_VOPL 252 +#define HCLK_RGA 253 +#define HCLK_NANDC 254 +#define HCLK_SDIO 255 +#define HCLK_EMMC 256 +#define HCLK_SFC 257 +#define HCLK_OTG 258 +#define HCLK_HOST 259 +#define HCLK_HOST_ARB 260 +#define HCLK_PDM 261 +#define HCLK_I2S0 262 +#define HCLK_I2S1 263 +#define HCLK_I2S2 264 + +/* pclk gates */ +#define PCLK_BUS_PRE 320 +#define PCLK_DDR 321 +#define PCLK_VO_PRE 322 +#define PCLK_GMAC 323 +#define PCLK_MIPI_DSI 324 +#define PCLK_MIPIDSIPHY 325 +#define PCLK_MIPICSIPHY 326 +#define PCLK_USB_GRF 327 +#define PCLK_DCF 328 +#define PCLK_UART1 329 +#define PCLK_UART2 330 +#define PCLK_UART3 331 +#define PCLK_UART4 332 +#define PCLK_UART5 333 +#define PCLK_I2C0 334 +#define PCLK_I2C1 335 +#define PCLK_I2C2 336 +#define PCLK_I2C3 337 +#define PCLK_I2C4 338 +#define PCLK_PWM0 339 +#define PCLK_PWM1 340 +#define PCLK_SPI0 341 +#define PCLK_SPI1 342 +#define PCLK_SARADC 343 +#define PCLK_TSADC 344 +#define PCLK_TIMER 345 +#define PCLK_OTP_NS 346 +#define PCLK_WDT_NS 347 +#define PCLK_GPIO1 348 +#define PCLK_GPIO2 349 +#define PCLK_GPIO3 350 +#define PCLK_ISP 351 +#define PCLK_CIF 352 +#define PCLK_OTP_PHY 353 + +#define CLK_NR_CLKS (PCLK_OTP_PHY + 1) + +/* pmu-clocks indices */ + +#define PLL_GPLL 1 + +#define SCLK_RTC32K_PMU 4 +#define SCLK_WIFI_PMU 5 +#define SCLK_UART0_PMU 6 +#define SCLK_PVTM_PMU 7 +#define PCLK_PMU_PRE 8 +#define SCLK_REF24M_PMU 9 +#define SCLK_USBPHY_REF 10 +#define SCLK_MIPIDSIPHY_REF 11 + +#define XIN24M_DIV 12 + +#define PCLK_GPIO0_PMU 20 +#define PCLK_UART0_PMU 21 + +#define CLKPMU_NR_CLKS (PCLK_UART0_PMU + 1) + +/* soft-reset indices */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_CORE_NOC 13 +#define SRST_STRC_A 14 +#define SRST_L2C 15 + +#define SRST_DAP 16 +#define SRST_CORE_PVTM 17 +#define SRST_GPU 18 +#define SRST_GPU_NIU 19 +#define SRST_UPCTL2 20 +#define SRST_UPCTL2_A 21 +#define SRST_UPCTL2_P 22 +#define SRST_MSCH 23 +#define SRST_MSCH_P 24 +#define SRST_DDRMON_P 25 +#define SRST_DDRSTDBY_P 26 +#define SRST_DDRSTDBY 27 +#define SRST_DDRGRF_p 28 +#define SRST_AXI_SPLIT_A 29 +#define SRST_AXI_CMD_A 30 +#define SRST_AXI_CMD_P 31 + +#define SRST_DDRPHY 32 +#define SRST_DDRPHYDIV 33 +#define SRST_DDRPHY_P 34 +#define SRST_VPU_A 36 +#define SRST_VPU_NIU_A 37 +#define SRST_VPU_H 38 +#define SRST_VPU_NIU_H 39 +#define SRST_VI_NIU_A 40 +#define SRST_VI_NIU_H 41 +#define SRST_ISP_H 42 +#define SRST_ISP 43 +#define SRST_CIF_A 44 +#define SRST_CIF_H 45 +#define SRST_CIF_PCLKIN 46 +#define SRST_MIPICSIPHY_P 47 + +#define SRST_VO_NIU_A 48 +#define SRST_VO_NIU_H 49 +#define SRST_VO_NIU_P 50 +#define SRST_VOPB_A 51 +#define SRST_VOPB_H 52 +#define SRST_VOPB 53 +#define SRST_PWM_VOPB 54 +#define SRST_VOPL_A 55 +#define SRST_VOPL_H 56 +#define SRST_VOPL 57 +#define SRST_RGA_A 58 +#define SRST_RGA_H 59 +#define SRST_RGA 60 +#define SRST_MIPIDSI_HOST_P 61 +#define SRST_MIPIDSIPHY_P 62 +#define SRST_VPU_CORE 63 + +#define SRST_PERI_NIU_A 64 +#define SRST_USB_NIU_H 65 +#define SRST_USB2OTG_H 66 +#define SRST_USB2OTG 67 +#define SRST_USB2OTG_ADP 68 +#define SRST_USB2HOST_H 69 +#define SRST_USB2HOST_ARB_H 70 +#define SRST_USB2HOST_AUX_H 71 +#define SRST_USB2HOST_EHCI 72 +#define SRST_USB2HOST 73 +#define SRST_USBPHYPOR 74 +#define SRST_USBPHY_OTG_PORT 75 +#define SRST_USBPHY_HOST_PORT 76 +#define SRST_USBPHY_GRF 77 +#define SRST_CPU_BOOST_P 78 +#define SRST_CPU_BOOST 79 + +#define SRST_MMC_NAND_NIU_H 80 +#define SRST_SDIO_H 81 +#define SRST_EMMC_H 82 +#define SRST_SFC_H 83 +#define SRST_SFC 84 +#define SRST_SDCARD_NIU_H 85 +#define SRST_SDMMC_H 86 +#define SRST_NANDC_H 89 +#define SRST_NANDC 90 +#define SRST_GMAC_NIU_A 92 +#define SRST_GMAC_NIU_P 93 +#define SRST_GMAC_A 94 + +#define SRST_PMU_NIU_P 96 +#define SRST_PMU_SGRF_P 97 +#define SRST_PMU_GRF_P 98 +#define SRST_PMU 99 +#define SRST_PMU_MEM_P 100 +#define SRST_PMU_GPIO0_P 101 +#define SRST_PMU_UART0_P 102 +#define SRST_PMU_CRU_P 103 +#define SRST_PMU_PVTM 104 +#define SRST_PMU_UART 105 +#define SRST_PMU_NIU_H 106 +#define SRST_PMU_DDR_FAIL_SAVE 107 +#define SRST_PMU_CORE_PERF_A 108 +#define SRST_PMU_CORE_GRF_P 109 +#define SRST_PMU_GPU_PERF_A 110 +#define SRST_PMU_GPU_GRF_P 111 + +#define SRST_CRYPTO_NIU_A 112 +#define SRST_CRYPTO_NIU_H 113 +#define SRST_CRYPTO_A 114 +#define SRST_CRYPTO_H 115 +#define SRST_CRYPTO 116 +#define SRST_CRYPTO_APK 117 +#define SRST_BUS_NIU_H 120 +#define SRST_USB_NIU_P 121 +#define SRST_BUS_TOP_NIU_P 122 +#define SRST_INTMEM_A 123 +#define SRST_GIC_A 124 +#define SRST_ROM_H 126 +#define SRST_DCF_A 127 + +#define SRST_DCF_P 128 +#define SRST_PDM_H 129 +#define SRST_PDM 130 +#define SRST_I2S0_H 131 +#define SRST_I2S0_TX 132 +#define SRST_I2S1_H 133 +#define SRST_I2S1 134 +#define SRST_I2S2_H 135 +#define SRST_I2S2 136 +#define SRST_UART1_P 137 +#define SRST_UART1 138 +#define SRST_UART2_P 139 +#define SRST_UART2 140 +#define SRST_UART3_P 141 +#define SRST_UART3 142 +#define SRST_UART4_P 143 + +#define SRST_UART4 144 +#define SRST_UART5_P 145 +#define SRST_UART5 146 +#define SRST_I2C0_P 147 +#define SRST_I2C0 148 +#define SRST_I2C1_P 149 +#define SRST_I2C1 150 +#define SRST_I2C2_P 151 +#define SRST_I2C2 152 +#define SRST_I2C3_P 153 +#define SRST_I2C3 154 +#define SRST_PWM0_P 157 +#define SRST_PWM0 158 +#define SRST_PWM1_P 159 + +#define SRST_PWM1 160 +#define SRST_SPI0_P 161 +#define SRST_SPI0 162 +#define SRST_SPI1_P 163 +#define SRST_SPI1 164 +#define SRST_SARADC_P 165 +#define SRST_SARADC 166 +#define SRST_TSADC_P 167 +#define SRST_TSADC 168 +#define SRST_TIMER_P 169 +#define SRST_TIMER0 170 +#define SRST_TIMER1 171 +#define SRST_TIMER2 172 +#define SRST_TIMER3 173 +#define SRST_TIMER4 174 +#define SRST_TIMER5 175 + +#define SRST_OTP_NS_P 176 +#define SRST_OTP_NS_SBPI 177 +#define SRST_OTP_NS_USR 178 +#define SRST_OTP_PHY_P 179 +#define SRST_OTP_PHY 180 +#define SRST_WDT_NS_P 181 +#define SRST_GPIO1_P 182 +#define SRST_GPIO2_P 183 +#define SRST_GPIO3_P 184 +#define SRST_SGRF_P 185 +#define SRST_GRF_P 186 +#define SRST_I2S0_RX 191 + +#endif diff --git a/include/dt-bindings/clock/rk1808-cru.h b/include/dt-bindings/clock/rk1808-cru.h new file mode 100644 index 000000000000..3dd5c76d5295 --- /dev/null +++ b/include/dt-bindings/clock/rk1808-cru.h @@ -0,0 +1,472 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK1808_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK1808_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define PLL_NPLL 5 +#define PLL_PPLL 6 +#define ARMCLK 7 + +#define DCLK_VOPRAW 10 +#define DCLK_VOPLITE 11 +#define DCLK_CIF 12 +#define XIN24M_DIV 13 + +/* sclk (special clocks) */ +#define USB480M 20 +#define SCLK_PVTM_CORE 21 +#define SCLK_NPU 22 +#define SCLK_PVTM_NPU 23 +#define SCLK_DDRCLK 24 +#define SCLK_I2S0_8CH_TX_MUX 25 +#define SCLK_I2S0_8CH_RX_MUX 26 +#define SCLK_RTC32K_PMU 27 +#define SCLK_TXESC 28 +#define SCLK_RGA 29 +#define SCLK_ISP 30 +#define SCLK_CIF_OUT 31 +#define SCLK_PCIE_AUX 32 +#define SCLK_USB3_OTG0_REF 33 +#define SCLK_USB3_OTG0_SUSPEND 34 +#define SCLK_SDIO_DIV 35 +#define SCLK_SDIO_DIV50 36 +#define SCLK_SDIO 37 +#define SCLK_SDIO_DRV 38 +#define SCLK_SDIO_SAMPLE 39 +#define SCLK_EMMC_DIV 40 +#define SCLK_EMMC_DIV50 41 +#define SCLK_EMMC 42 +#define SCLK_EMMC_DRV 43 +#define SCLK_EMMC_SAMPLE 44 +#define SCLK_SDMMC_DIV 45 +#define SCLK_SDMMC_DIV50 46 +#define SCLK_SDMMC 47 +#define SCLK_SDMMC_DRV 48 +#define SCLK_SDMMC_SAMPLE 49 +#define SCLK_SFC 50 +#define SCLK_GMAC_OUT 51 +#define SCLK_GMAC_SRC 52 +#define SCLK_GMAC 53 +#define SCLK_GMAC_REF 54 +#define SCLK_GMAC_REFOUT 55 +#define SCLK_GMAC_RGMII_SPEED 56 +#define SCLK_GMAC_RMII_SPEED 57 +#define SCLK_GMAC_RX_TX 58 +#define SCLK_CRYPTO 59 +#define SCLK_CRYPTO_APK 60 +#define SCLK_UART1 61 +#define SCLK_UART2 62 +#define SCLK_UART3 63 +#define SCLK_UART4 64 +#define SCLK_UART5 65 +#define SCLK_UART6 66 +#define SCLK_UART7 67 +#define SCLK_I2C1 68 +#define SCLK_I2C2 69 +#define SCLK_I2C3 70 +#define SCLK_I2C4 71 +#define SCLK_I2C5 72 +#define SCLK_SPI0 73 +#define SCLK_SPI1 74 +#define SCLK_SPI2 75 +#define SCLK_TSADC 76 +#define SCLK_SARADC 77 +#define SCLK_EFUSE_S 78 +#define SCLK_EFUSE_NS 79 +#define DBCLK_GPIO1 80 +#define DBCLK_GPIO2 81 +#define DBCLK_GPIO3 82 +#define DBCLK_GPIO4 83 +#define SCLK_PWM0 84 +#define SCLK_PWM1 85 +#define SCLK_PWM2 86 +#define SCLK_TIMER0 87 +#define SCLK_TIMER1 88 +#define SCLK_TIMER2 89 +#define SCLK_TIMER3 90 +#define SCLK_TIMER4 91 +#define SCLK_TIMER5 92 +#define SCLK_PDM 93 +#define SCLK_I2S0_8CH_TX_SRC 94 +#define SCLK_I2S0_8CH_TX 95 +#define SCLK_I2S0_8CH_TX_OUT 96 +#define SCLK_I2S0_8CH_RX_SRC 97 +#define SCLK_I2S0_8CH_RX 98 +#define SCLK_I2S0_8CH_RX_OUT 99 +#define SCLK_I2S1_2CH_SRC 100 +#define SCLK_I2S1_2CH 101 +#define SCLK_I2S1_2CH_OUT 102 +#define SCLK_WIFI_PMU 103 +#define SCLK_UART0_PMU 104 +#define SCLK_PVTM_PMU 105 +#define SCLK_PMU_I2C0 106 +#define DBCLK_PMU_GPIO0 107 +#define SCLK_REF24M_PMU 108 +#define SCLK_USBPHY_REF 109 +#define SCLK_MIPIDSIPHY_REF 110 +#define SCLK_PCIEPHY_REF 111 +#define SCLK_RTC32K_FRAC 112 + +/* aclk gates */ +#define ACLK_GIC_PRE 145 +#define ACLK_GIC 146 +#define ACLK_VPU 147 +#define ACLK_NPU 148 +#define ACLK_IMEM_PRE 153 +#define ACLK_IMEM0 154 +#define ACLK_IMEM1 155 +#define ACLK_IMEM2 156 +#define ACLK_IMEM3 157 +#define HSCLK_VIO 158 +#define ACLK_VOPRAW 159 +#define ACLK_VOPLITE 160 +#define ACLK_RGA 161 +#define ACLK_ISP 162 +#define ACLK_CIF 163 +#define HSCLK_PCIE 164 +#define ACLK_USB3OTG 165 +#define ACLK_PCIE 166 +#define ACLK_PCIE_MST 167 +#define ACLK_PCIE_SLV 168 +#define MSCLK_PERI 169 +#define ACLK_GMAC 170 +#define HSCLK_BUS_PRE 171 +#define ACLK_CRYPTO 172 +#define ACLK_DCF 173 +#define ACLK_DMAC 174 + +/* hclk gates */ +#define HCLK_NPU 199 +#define HCLK_VPU 200 +#define LSCLK_VIO 201 +#define HCLK_VOPRAW 202 +#define HCLK_VOPLITE 203 +#define HCLK_RGA 204 +#define HCLK_ISP 205 +#define LSCLK_PCIE 206 +#define HCLK_HOST 207 +#define LSCLK_PERI 208 +#define HCLK_SDIO 209 +#define HCLK_EMMC 210 +#define HCLK_SDMMC 211 +#define HCLK_SFC 212 +#define MSCLK_BUS_PRE 213 +#define HCLK_ROM 214 +#define HCLK_CRYPTO 215 +#define HCLK_VAD 216 +#define HCLK_PDM 217 +#define HCLK_I2S0_8CH 218 +#define HCLK_I2S1_2CH 219 +#define MSCLK_CORE_NIU 220 +#define HSCLK_IMEM 221 +#define HCLK_HOST_ARB 222 +#define HCLK_CIF 223 + +/* pclk gates */ +#define PCLK_DDR 250 +#define PCLK_DSI_TX 251 +#define PCLK_CSI_TX 252 +#define PCLK_CSI2HOST 253 +#define PCLK_PCIE 254 +#define PCLK_GMAC 255 +#define LSCLK_BUS_PRE 256 +#define PCLK_DCF 257 +#define PCLK_UART1 258 +#define PCLK_UART2 259 +#define PCLK_UART3 260 +#define PCLK_UART4 261 +#define PCLK_UART5 262 +#define PCLK_UART6 263 +#define PCLK_UART7 264 +#define PCLK_I2C1 265 +#define PCLK_I2C2 266 +#define PCLK_I2C3 267 +#define PCLK_I2C4 268 +#define PCLK_I2C5 269 +#define PCLK_SPI0 270 +#define PCLK_SPI1 271 +#define PCLK_SPI2 272 +#define PCLK_TSADC 273 +#define PCLK_SARADC 274 +#define PCLK_EFUSE 275 +#define PCLK_GPIO1 276 +#define PCLK_GPIO2 277 +#define PCLK_GPIO3 278 +#define PCLK_GPIO4 279 +#define PCLK_PWM0 280 +#define PCLK_PWM1 281 +#define PCLK_PWM2 282 +#define PCLK_TIMER 283 +#define PCLK_WDT 284 +#define PCLK_MIPIDSIPHY 285 +#define PCLK_MIPICSIPHY 286 +#define PCLK_DDRMON 287 +#define PCLK_DDRC 289 +#define PCLK_MSCH 290 +#define PCLK_STDBY 291 +#define PCLK_GPIO0_PMU 292 +#define PCLK_UART0_PMU 293 +#define PCLK_I2C0_PMU 294 +#define PCLK_USB3PHY_PIPE 295 +#define PCLK_PMU_PRE 296 + +#define CLK_NR_CLKS (PCLK_PMU_PRE + 1) + +/* soft-reset indices */ + +/* cru_softrst_con0 */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE0 2 +#define SRST_CORE1 3 +#define SRST_CORE0_DBG 4 +#define SRST_CORE1_DBG 5 +#define SRST_TOPDBG 6 +#define SRST_CORE_NOC 7 +#define SRST_STRC_A 8 +#define SRST_L2C 9 +#define SRST_DAP 10 +#define SRST_CORE_MSNIU 11 +#define SRST_GIC2CORE 12 +#define SRST_CORE2GIC 13 +#define SRST_CORE_PRF_A 14 +#define SRST_CORE_GRF_P 15 + +/* cru_softrst_con1 */ +#define SRST_DDRPHY 16 +#define SRST_DDRPHY_P 18 +#define SRST_UPCTL2 20 +#define SRST_UPCTL2_A 21 +#define SRST_UPCTL2_P 22 +#define SRST_MSCH 23 +#define SRST_MSCH_P 24 +#define SRST_DDRMON_P 25 +#define SRST_DDRSTDBY_P 26 +#define SRST_DDRSTDBY 27 +#define SRST_DDRGRF_P 28 +#define SRST_AXI_SPLIT_A 29 +#define SRST_DDRDFI_CTL 30 +#define SRST_DDRDFI_CTL_P 31 + +/* cru_softrst_con2 */ +#define SRST_GIC500_NIU_A 32 +#define SRST_GIC500_A 33 +#define SRST_GIC_CORE2GIC 34 +#define SRST_GIC_GIC2CORE 35 +#define SRST_NPU_CORE 36 +#define SRST_NPU_A 37 +#define SRST_NPU_H 38 +#define SRST_NPU_NIU_A 39 +#define SRST_NPU_NIU_H 40 +#define SRST_NPU2MEM_A 41 +#define SRST_NPU_PVTM 42 +#define SRST_CORE_PVTM 43 +#define SRST_GIC_SPINLOCK_A 47 + +/* cru_softrst_con3 */ +#define SRST_PCIE_NIU_H 48 +#define SRST_PCIE_NIU_L 49 +#define SRST_PCIEGRF_P 50 +#define SRST_PCIECTL_P 51 +#define SRST_PCIECTL_POWERUP 52 +#define SRST_PCIECTL_MST_A 53 +#define SRST_PCIECTL_SLV_A 54 +#define SRST_PCIECTL_DBI_A 55 +#define SRST_PCIECTL_BUTTON 56 +#define SRST_PCIECTL_PE 57 +#define SRST_PCIECTL_CORE 58 +#define SRST_PCIECTL_NSTICKY 59 +#define SRST_PCIECTL_STICKY 60 +#define SRST_PCIECTL_PWR 61 +#define SRST_PCIE_NIU_A 62 +#define SRST_PCIE_NIU_P 63 + +/* cru_softrst_con4 */ +#define SRST_PCIEPHY_POR 64 +#define SRST_PCIEPHY_P 65 +#define SRST_PCIEPHY_PIPE 66 +#define SRST_USBPHY_POR 67 +#define SRST_USBPHY_OTG_PORT 68 +#define SRST_USBPHY_HOST_PORT 69 +#define SRST_USB3PHY_GRF_P 70 +#define SRST_USB2PHY_GRF_P 71 +#define SRST_USB3_OTG_A 72 +#define SRST_USB2HOST_H 73 +#define SRST_USB2HOST_ARB_H 74 +#define SRSTUSB2HOST_UTMI 75 + +/* cru_softrst_con5 */ +#define SRST_IMEM0_A 80 +#define SRST_IMEM1_A 81 +#define SRST_IMEM2_A 82 +#define SRST_IMEM3_A 83 +#define SRST_IMEM0_NIU_A 84 +#define SRST_IMEM1_NIU_A 85 +#define SRST_IMEM2_NIU_A 86 +#define SRST_IMEM3_NIU_A 87 +#define SRST_IMEM_NIU_H 88 +#define SRST_VPU_NIU_A 92 +#define SRST_VPU_NIU_H 93 +#define SRST_VPU_A 94 +#define SRST_VPU_H 95 + +/* cru_softrst_con6 */ +#define SRST_VIO_NIU_H 96 +#define SRST_VIO_NIU_L 97 +#define SRST_VOPRAW_A 98 +#define SRST_VOPRAW_H 99 +#define SRST_VOPRAW_D 100 +#define SRST_VOPLITE_A 101 +#define SRST_VOPLITE_H 102 +#define SRST_VOPLITE_D 103 +#define SRST_MIPIDSI_HOST_P 104 +#define SRST_CSITX_P 105 +#define SRST_CSITX_TXBYTEHS 106 +#define SRST_CSITX_TXESC 107 +#define SRST_CSITX_CAM 108 +#define SRST_CSITX_I 109 + +/* cru_softrst_con7 */ +#define SRST_RGA_A 112 +#define SRST_RGA_H 113 +#define SRST_RGA 114 +#define SRST_CSI2HOST_P 115 +#define SRST_CIF_A 116 +#define SRST_CIF_H 117 +#define SRST_CIF_I 118 +#define SRST_CIF_PCLKIN 119 +#define SRST_CIF_D 120 +#define SRST_ISP_H 121 +#define SRST_ISP 122 +#define SRST_MIPICSIPHY_P 124 +#define SRST_MIPIDSIPHY_P 125 + +/* cru_softrst_con8 */ +#define SRST_PERI_NIU_H 128 +#define SRST_PERI_NIU_L 129 +#define SRST_PDMMC_NIU_H 132 +#define SRST_SDMMC_H 133 +#define SRST_SDIO_H 134 +#define SRST_EMMC_H 135 +#define SRST_SFC_H 136 +#define SRST_SFC 137 +#define SRST_GMAC_NIU_A 140 +#define SRST_GMAC_NIU_H 141 +#define SRST_GMAC_NIU_P 142 +#define SRST_GAMC_A 143 + +/* cru_softrst_con9 */ +#define SRST_PMU_NIU_P 144 +#define SRST_PMU_SGRF_P 145 +#define SRST_PMU_GRF_P 146 +#define SRST_PMU_PMU 147 +#define SRST_PMU_MEM_P 148 +#define SRST_PMU_GPIO0_P 149 +#define SRST_PMU_UART0_P 150 +#define SRST_PMU_CRU 151 +#define SRST_PMU_PVTM 152 +#define SRST_PMU_UART0 153 +#define SRST_PMU_NIU_H 154 +#define SRST_PMU_DDR_FAIL_SAVE 155 +#define SRST_PMU_I2C0_P 156 +#define SRST_PMU_I2C0 157 +#define SRST_PMU_GPIO0_DB 158 + +/* cru_softrst_con10 */ +#define SRST_AUDIO_NIU_H 160 +#define SRST_VAD_H 161 +#define SRST_PDM_H 162 +#define SRST_PDM 163 +#define SRST_I2S0_H 164 +#define SRST_I2S0_TX 165 +#define SRST_I2S1_H 166 +#define SRST_I2S1 167 +#define SRST_I2S0_RX 168 + +/* cru_softrst_con11 */ +#define SRST_BUS_NIU_M 176 +#define SRST_BUS_NIU_L 177 +#define SRST_TOP_NIU_P 178 +#define SRST_ROM_H 179 +#define SRST_CRYPTO_A 180 +#define SRST_CRYPTO_H 181 +#define SRST_CRYPTO_CORE 182 +#define SRST_CRYPTO_APK 183 +#define SRST_DCF_A 184 +#define SRST_DCF_P 185 +#define SRST_UART1_P 186 +#define SRST_UART1 187 +#define SRST_UART2_P 188 +#define SRST_UART2 189 +#define SRST_UART3_P 190 +#define SRST_UART3 191 + +/* cru_softrst_con12 */ +#define SRST_UART4_P 192 +#define SRST_UART4 193 +#define SRST_UART5_P 194 +#define SRST_UART5 195 +#define SRST_UART6_P 196 +#define SRST_UART6 197 +#define SRST_UART7_P 198 +#define SRST_UART7 199 +#define SRST_I2C1_P 200 +#define SRST_I2C1 201 +#define SRST_I2C2_P 202 +#define SRST_I2C2 203 +#define SRST_I2C3_P 204 +#define SRST_I2C3 205 +#define SRST_PWM0_P 206 +#define SRST_PWM0 207 + +/* cru_softrst_con13 */ +#define SRST_PWM1_P 208 +#define SRST_PWM1 209 +#define SRST_PWM2_P 210 +#define SRST_PWM2 211 +#define SRST_SPI0_P 212 +#define SRST_SPI0 213 +#define SRST_SPI1_P 214 +#define SRST_SPI1 215 +#define SRST_SPI2_P 216 +#define SRST_SPI2 217 +#define SRST_BUS_SGRF_P 218 +#define SRST_BUS_GRF_P 219 +#define SRST_TIMER_P 220 +#define SRST_TIMER0 221 +#define SRST_TIMER1 222 +#define SRST_TIMER2 223 + +/* cru_softrst_con14 */ +#define SRST_TIMER3 224 +#define SRST_TIMER4 225 +#define SRST_TIMER5 226 +#define SRST_WDT_NS_P 227 +#define SRST_EFUSE_NS_P 228 +#define SRST_EFUSE_NS 229 +#define SRST_GPIO1_P 230 +#define SRST_GPIO1_DB 231 +#define SRST_GPIO2_P 232 +#define SRST_GPIO2_DB 233 +#define SRST_GPIO3_P 234 +#define SRST_GPIO3_DB 235 +#define SRST_GPIO4_P 236 +#define SRST_GPIO4_DB 237 +#define SRST_BUS_SUB_NIU_M 238 + +/* cru_softrst_con15 */ +#define SRST_I2C4_P 240 +#define SRST_I2C4 241 +#define SRST_I2C5_P 242 +#define SRST_I2C5 243 +#define SRST_SARADC 252 +#define SRST_SARADC_P 253 +#define SRST_TSADC_P 254 +#define SRST_TSADC 255 + +#endif diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h new file mode 100644 index 000000000000..658413a6feb3 --- /dev/null +++ b/include/dt-bindings/clock/rk3036-cru.h @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Xing Zheng <zhengxing@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_GPLL 3 +#define ARMCLK 4 + +/* sclk gates (special clocks) */ +#define SCLK_GPU 64 +#define SCLK_SPI 65 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_NANDC 76 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_I2S 82 +#define SCLK_SPDIF 83 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_OTGPHY0 93 +#define SCLK_LCDC 100 +#define SCLK_HDMI 109 +#define SCLK_HEVC 111 +#define SCLK_I2S_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_PVTM_CORE 123 +#define SCLK_PVTM_GPU 124 +#define SCLK_PVTM_VIDEO 125 +#define SCLK_I2S_FRAC 126 +#define SCLK_I2S_PRE 127 +#define SCLK_MAC 151 +#define SCLK_MACREF 152 +#define SCLK_MACPLL 153 +#define SCLK_SFC 160 + +/* aclk gates */ +#define ACLK_DMAC2 194 +#define ACLK_LCDC 197 +#define ACLK_VIO 203 +#define ACLK_VCODEC 208 +#define ACLK_CPU 209 +#define ACLK_PERI 210 +#define ACLK_HEVC 211 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GRF 329 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_SPI 338 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_PWM 350 +#define PCLK_TIMER 353 +#define PCLK_HDMI 360 +#define PCLK_CPU 362 +#define PCLK_PERI 363 +#define PCLK_DDRUPCTL 364 +#define PCLK_WDT 368 +#define PCLK_ACODEC 369 + +/* hclk gates */ +#define HCLK_OTG0 449 +#define HCLK_OTG1 450 +#define HCLK_NANDC 453 +#define HCLK_SFC 454 +#define HCLK_SDMMC 456 +#define HCLK_SDIO 457 +#define HCLK_EMMC 459 +#define HCLK_MAC 460 +#define HCLK_I2S 462 +#define HCLK_LCDC 465 +#define HCLK_ROM 467 +#define HCLK_VIO_BUS 472 +#define HCLK_VCODEC 476 +#define HCLK_CPU 477 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE0 0 +#define SRST_CORE1 1 +#define SRST_CORE0_DBG 4 +#define SRST_CORE1_DBG 5 +#define SRST_CORE0_POR 8 +#define SRST_CORE1_POR 9 +#define SRST_L2C 12 +#define SRST_TOPDBG 13 +#define SRST_STRC_SYS_A 14 +#define SRST_PD_CORE_NIU 15 + +#define SRST_TIMER2 16 +#define SRST_CPUSYS_H 17 +#define SRST_AHB2APB_H 19 +#define SRST_TIMER3 20 +#define SRST_INTMEM 21 +#define SRST_ROM 22 +#define SRST_PERI_NIU 23 +#define SRST_I2S 24 +#define SRST_DDR_PLL 25 +#define SRST_GPU_DLL 26 +#define SRST_TIMER0 27 +#define SRST_TIMER1 28 +#define SRST_CORE_DLL 29 +#define SRST_EFUSE_P 30 +#define SRST_ACODEC_P 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_UART0 39 +#define SRST_UART1 40 +#define SRST_UART2 41 +#define SRST_I2C0 43 +#define SRST_I2C1 44 +#define SRST_I2C2 45 +#define SRST_SFC 47 + +#define SRST_PWM0 48 +#define SRST_DAP 51 +#define SRST_DAP_SYS 52 +#define SRST_GRF 55 +#define SRST_PERIPHSYS_A 57 +#define SRST_PERIPHSYS_H 58 +#define SRST_PERIPHSYS_P 59 +#define SRST_CPU_PERI 61 +#define SRST_EMEM_PERI 62 +#define SRST_USB_PERI 63 + +#define SRST_DMA2 64 +#define SRST_MAC 66 +#define SRST_NANDC 68 +#define SRST_USBOTG0 69 +#define SRST_OTGC0 71 +#define SRST_USBOTG1 72 +#define SRST_OTGC1 74 +#define SRST_DDRMSCH 79 + +#define SRST_MMC0 81 +#define SRST_SDIO 82 +#define SRST_EMMC 83 +#define SRST_SPI0 84 +#define SRST_WDT 86 +#define SRST_DDRPHY 88 +#define SRST_DDRPHY_P 89 +#define SRST_DDRCTRL 90 +#define SRST_DDRCTRL_P 91 + +#define SRST_HDMI_P 96 +#define SRST_VIO_BUS_H 99 +#define SRST_UTMI0 103 +#define SRST_UTMI1 104 +#define SRST_USBPOR 105 + +#define SRST_VCODEC_A 112 +#define SRST_VCODEC_H 113 +#define SRST_VIO1_A 114 +#define SRST_HEVC 115 +#define SRST_VCODEC_NIU_A 116 +#define SRST_LCDC1_A 117 +#define SRST_LCDC1_H 118 +#define SRST_LCDC1_D 119 +#define SRST_GPU 120 +#define SRST_GPU_NIU_A 122 + +#define SRST_DBG_P 131 + +#endif diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h new file mode 100644 index 000000000000..7d3b5ca8a62c --- /dev/null +++ b/include/dt-bindings/clock/rk3128-cru.h @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Author: Elaine <zhangqing@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define ARMCLK 5 +#define PLL_GPLL_DIV2 6 +#define PLL_GPLL_DIV3 7 + +/* sclk gates (special clocks) */ +#define SCLK_SPI0 65 +#define SCLK_NANDC 67 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_I2S0 80 +#define SCLK_I2S1 81 +#define SCLK_SPDIF 83 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_TIMER4 89 +#define SCLK_TIMER5 90 +#define SCLK_SARADC 91 +#define SCLK_I2S_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_VOP 122 +#define SCLK_MAC_SRC 124 +#define SCLK_MAC 126 +#define SCLK_MAC_REFOUT 127 +#define SCLK_MAC_REF 128 +#define SCLK_MAC_RX 129 +#define SCLK_MAC_TX 130 +#define SCLK_HEVC_CORE 134 +#define SCLK_RGA 135 +#define SCLK_CRYPTO 138 +#define SCLK_TSP 139 +#define SCLK_OTGPHY0 142 +#define SCLK_OTGPHY1 143 +#define SCLK_DDRC 144 +#define SCLK_PVTM_FUNC 145 +#define SCLK_PVTM_CORE 146 +#define SCLK_PVTM_GPU 147 +#define SCLK_MIPI_24M 148 +#define SCLK_PVTM 149 +#define SCLK_CIF_SRC 150 +#define SCLK_CIF_OUT_SRC 151 +#define SCLK_CIF_OUT 152 +#define SCLK_SFC 153 +#define SCLK_USB480M 154 +#define SCLK_HSADC_TSP 155 + +/* dclk gates */ +#define DCLK_VOP 190 +#define DCLK_EBC 191 + +/* aclk gates */ +#define ACLK_VIO0 192 +#define ACLK_VIO1 193 +#define ACLK_DMAC 194 +#define ACLK_CPU 195 +#define ACLK_VEPU 196 +#define ACLK_VDPU 197 +#define ACLK_CIF 198 +#define ACLK_IEP 199 +#define ACLK_LCDC0 204 +#define ACLK_RGA 205 +#define ACLK_PERI 210 +#define ACLK_VOP 211 +#define ACLK_GMAC 212 +#define ACLK_GPU 213 + +/* pclk gates */ +#define PCLK_SARADC 318 +#define PCLK_WDT 319 +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GPIO3 323 +#define PCLK_VIO_H2P 324 +#define PCLK_MIPI 325 +#define PCLK_EFUSE 326 +#define PCLK_HDMI 327 +#define PCLK_ACODEC 328 +#define PCLK_GRF 329 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_I2C3 335 +#define PCLK_SPI0 338 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_TSADC 344 +#define PCLK_PWM 350 +#define PCLK_TIMER 353 +#define PCLK_CPU 354 +#define PCLK_PERI 363 +#define PCLK_GMAC 367 +#define PCLK_PMU_PRE 368 +#define PCLK_SIM_CARD 369 +#define PCLK_MIPIPHY 370 + +/* hclk gates */ +#define HCLK_SFC 439 +#define HCLK_SPDIF 440 +#define HCLK_GPS 441 +#define HCLK_USBHOST 442 +#define HCLK_I2S_8CH 443 +#define HCLK_I2S_2CH 444 +#define HCLK_VOP 452 +#define HCLK_NANDC 453 +#define HCLK_SDMMC 456 +#define HCLK_SDIO 457 +#define HCLK_EMMC 459 +#define HCLK_CPU 460 +#define HCLK_VEPU 461 +#define HCLK_VDPU 462 +#define HCLK_LCDC0 463 +#define HCLK_EBC 465 +#define HCLK_VIO 466 +#define HCLK_RGA 467 +#define HCLK_IEP 468 +#define HCLK_VIO_H2P 469 +#define HCLK_CIF 470 +#define HCLK_HOST2 473 +#define HCLK_OTG 474 +#define HCLK_TSP 475 +#define HCLK_CRYPTO 476 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_ACLK_CORE 13 +#define SRST_STRC_SYS_A 14 +#define SRST_L2C 15 + +#define SRST_CPUSYS_H 18 +#define SRST_AHB2APBSYS_H 19 +#define SRST_SPDIF 20 +#define SRST_INTMEM 21 +#define SRST_ROM 22 +#define SRST_PERI_NIU 23 +#define SRST_I2S_2CH 24 +#define SRST_I2S_8CH 25 +#define SRST_GPU_PVTM 26 +#define SRST_FUNC_PVTM 27 +#define SRST_CORE_PVTM 29 +#define SRST_EFUSE_P 30 +#define SRST_ACODEC_P 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_GPIO3 35 +#define SRST_MIPIPHY_P 36 +#define SRST_UART0 39 +#define SRST_UART1 40 +#define SRST_UART2 41 +#define SRST_I2C0 43 +#define SRST_I2C1 44 +#define SRST_I2C2 45 +#define SRST_I2C3 46 +#define SRST_SFC 47 + +#define SRST_PWM 48 +#define SRST_DAP_PO 50 +#define SRST_DAP 51 +#define SRST_DAP_SYS 52 +#define SRST_CRYPTO 53 +#define SRST_GRF 55 +#define SRST_GMAC 56 +#define SRST_PERIPH_SYS_A 57 +#define SRST_PERIPH_SYS_H 58 +#define SRST_PERIPH_SYS_P 59 +#define SRST_SMART_CARD 60 +#define SRST_CPU_PERI 61 +#define SRST_EMEM_PERI 62 +#define SRST_USB_PERI 63 + +#define SRST_DMA 64 +#define SRST_GPS 67 +#define SRST_NANDC 68 +#define SRST_USBOTG0 69 +#define SRST_OTGC0 71 +#define SRST_USBOTG1 72 +#define SRST_OTGC1 74 +#define SRST_DDRMSCH 79 + +#define SRST_SDMMC 81 +#define SRST_SDIO 82 +#define SRST_EMMC 83 +#define SRST_SPI 84 +#define SRST_WDT 86 +#define SRST_SARADC 87 +#define SRST_DDRPHY 88 +#define SRST_DDRPHY_P 89 +#define SRST_DDRCTRL 90 +#define SRST_DDRCTRL_P 91 +#define SRST_TSP 92 +#define SRST_TSP_CLKIN 93 +#define SRST_HOST0_ECHI 94 + +#define SRST_HDMI_P 96 +#define SRST_VIO_ARBI_H 97 +#define SRST_VIO0_A 98 +#define SRST_VIO_BUS_H 99 +#define SRST_VOP_A 100 +#define SRST_VOP_H 101 +#define SRST_VOP_D 102 +#define SRST_UTMI0 103 +#define SRST_UTMI1 104 +#define SRST_USBPOR 105 +#define SRST_IEP_A 106 +#define SRST_IEP_H 107 +#define SRST_RGA_A 108 +#define SRST_RGA_H 109 +#define SRST_CIF0 110 +#define SRST_PMU 111 + +#define SRST_VCODEC_A 112 +#define SRST_VCODEC_H 113 +#define SRST_VIO1_A 114 +#define SRST_HEVC_CORE 115 +#define SRST_VCODEC_NIU_A 116 +#define SRST_PMU_NIU_P 117 +#define SRST_LCDC0_S 119 +#define SRST_GPU 120 +#define SRST_GPU_NIU_A 122 +#define SRST_EBC_A 123 +#define SRST_EBC_H 124 + +#define SRST_CORE_DBG 128 +#define SRST_DBG_P 129 +#define SRST_TIMER0 130 +#define SRST_TIMER1 131 +#define SRST_TIMER2 132 +#define SRST_TIMER3 133 +#define SRST_TIMER4 134 +#define SRST_TIMER5 135 +#define SRST_VIO_H2P 136 +#define SRST_VIO_MIPI_DSI 137 + +#endif diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h index 8df77a7c030b..9d3ef39defb7 100644 --- a/include/dt-bindings/clock/rk3188-cru-common.h +++ b/include/dt-bindings/clock/rk3188-cru-common.h @@ -71,6 +71,11 @@ #define ACLK_IPP 200 #define ACLK_RGA 201 #define ACLK_CIF0 202 +#define ACLK_VEPU 203 +#define ACLK_VDPU 204 +#define ACLK_CPU 205 +#define ACLK_PERI 206 +#define ACLK_CIF1 207 /* pclk gates */ #define PCLK_GRF 320 @@ -103,6 +108,10 @@ #define PCLK_EFUSE 347 #define PCLK_TZPC 348 #define PCLK_TSADC 349 +#define PCLK_CPU 350 +#define PCLK_PERI 351 +#define PCLK_CIF0 352 +#define PCLK_CIF1 353 /* hclk gates */ #define HCLK_SDMMC 448 @@ -111,9 +120,9 @@ #define HCLK_OTG0 451 #define HCLK_EMAC 452 #define HCLK_SPDIF 453 -#define HCLK_I2S0 454 -#define HCLK_I2S1 455 -#define HCLK_I2S2 456 +#define HCLK_I2S0_2CH 454 +#define HCLK_I2S1_2CH 455 +#define HCLK_I2S_8CH 456 #define HCLK_OTG1 457 #define HCLK_HSIC 458 #define HCLK_HSADC 459 @@ -125,8 +134,14 @@ #define HCLK_IPP 465 #define HCLK_RGA 466 #define HCLK_NANDC0 467 +#define HCLK_VEPU 468 +#define HCLK_VDPU 469 +#define HCLK_CPU 470 +#define HCLK_PERI 471 +#define HCLK_CIF1 472 +#define HCLK_HDMI 473 -#define CLK_NR_CLKS (HCLK_NANDC0 + 1) +#define CLK_NR_CLKS (HCLK_HDMI + 1) /* soft-reset indices */ #define SRST_MCORE 2 diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h new file mode 100644 index 000000000000..2f22a7b1538d --- /dev/null +++ b/include/dt-bindings/clock/rk3228-cru.h @@ -0,0 +1,298 @@ +/* + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Jeffy Chen <jeffy.chen@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define ARMCLK 5 + +/* sclk gates (special clocks) */ +#define SCLK_SPI0 65 +#define SCLK_NANDC 67 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_TSADC 72 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_I2S0 80 +#define SCLK_I2S1 81 +#define SCLK_I2S2 82 +#define SCLK_SPDIF 83 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_TIMER4 89 +#define SCLK_TIMER5 90 +#define SCLK_I2S_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO_SAMPLE 119 +#define SCLK_SDIO_SRC 120 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_VOP 122 +#define SCLK_HDMI_HDCP 123 +#define SCLK_MAC_SRC 124 +#define SCLK_MAC_EXTCLK 125 +#define SCLK_MAC 126 +#define SCLK_MAC_REFOUT 127 +#define SCLK_MAC_REF 128 +#define SCLK_MAC_RX 129 +#define SCLK_MAC_TX 130 +#define SCLK_MAC_PHY 131 +#define SCLK_MAC_OUT 132 +#define SCLK_VDEC_CABAC 133 +#define SCLK_VDEC_CORE 134 +#define SCLK_RGA 135 +#define SCLK_HDCP 136 +#define SCLK_HDMI_CEC 137 +#define SCLK_CRYPTO 138 +#define SCLK_TSP 139 +#define SCLK_HSADC 140 +#define SCLK_WIFI 141 +#define SCLK_OTGPHY0 142 +#define SCLK_OTGPHY1 143 +#define SCLK_DDRC 144 + +/* dclk gates */ +#define DCLK_VOP 190 +#define DCLK_HDMI_PHY 191 +#define HDMIPHY 192 + +/* aclk gates */ +#define ACLK_DMAC 194 +#define ACLK_CPU 195 +#define ACLK_VPU_PRE 196 +#define ACLK_RKVDEC_PRE 197 +#define ACLK_RGA_PRE 198 +#define ACLK_IEP_PRE 199 +#define ACLK_HDCP_PRE 200 +#define ACLK_VOP_PRE 201 +#define ACLK_VPU 202 +#define ACLK_RKVDEC 203 +#define ACLK_IEP 204 +#define ACLK_RGA 205 +#define ACLK_HDCP 206 +#define ACLK_PERI 210 +#define ACLK_VOP 211 +#define ACLK_GMAC 212 +#define ACLK_GPU 213 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GPIO3 323 +#define PCLK_VIO_H2P 324 +#define PCLK_HDCP 325 +#define PCLK_EFUSE_1024 326 +#define PCLK_EFUSE_256 327 +#define PCLK_GRF 329 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_I2C3 335 +#define PCLK_SPI0 338 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_TSADC 344 +#define PCLK_PWM 350 +#define PCLK_TIMER 353 +#define PCLK_CPU 354 +#define PCLK_PERI 363 +#define PCLK_HDMI_CTRL 364 +#define PCLK_HDMI_PHY 365 +#define PCLK_GMAC 367 +#define PCLK_ACODECPHY 368 + +/* hclk gates */ +#define HCLK_I2S0_8CH 442 +#define HCLK_I2S1_8CH 443 +#define HCLK_I2S2_2CH 444 +#define HCLK_SPDIF_8CH 445 +#define HCLK_VOP 452 +#define HCLK_NANDC 453 +#define HCLK_SDMMC 456 +#define HCLK_SDIO 457 +#define HCLK_EMMC 459 +#define HCLK_CPU 460 +#define HCLK_VPU_PRE 461 +#define HCLK_RKVDEC_PRE 462 +#define HCLK_VIO_PRE 463 +#define HCLK_VPU 464 +#define HCLK_RKVDEC 465 +#define HCLK_VIO 466 +#define HCLK_RGA 467 +#define HCLK_IEP 468 +#define HCLK_VIO_H2P 469 +#define HCLK_HDCP_MMU 470 +#define HCLK_HOST0 471 +#define HCLK_HOST1 472 +#define HCLK_HOST2 473 +#define HCLK_OTG 474 +#define HCLK_TSP 475 +#define HCLK_M_CRYPTO 476 +#define HCLK_S_CRYPTO 477 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_ACLK_CORE 13 +#define SRST_NOC 14 +#define SRST_L2C 15 + +#define SRST_CPUSYS_H 18 +#define SRST_BUSSYS_H 19 +#define SRST_SPDIF 20 +#define SRST_INTMEM 21 +#define SRST_ROM 22 +#define SRST_OTG_ADP 23 +#define SRST_I2S0 24 +#define SRST_I2S1 25 +#define SRST_I2S2 26 +#define SRST_ACODEC_P 27 +#define SRST_DFIMON 28 +#define SRST_MSCH 29 +#define SRST_EFUSE1024 30 +#define SRST_EFUSE256 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_GPIO3 35 +#define SRST_PERIPH_NOC_A 36 +#define SRST_PERIPH_NOC_BUS_H 37 +#define SRST_PERIPH_NOC_P 38 +#define SRST_UART0 39 +#define SRST_UART1 40 +#define SRST_UART2 41 +#define SRST_PHYNOC 42 +#define SRST_I2C0 43 +#define SRST_I2C1 44 +#define SRST_I2C2 45 +#define SRST_I2C3 46 + +#define SRST_PWM 48 +#define SRST_A53_GIC 49 +#define SRST_DAP 51 +#define SRST_DAP_NOC 52 +#define SRST_CRYPTO 53 +#define SRST_SGRF 54 +#define SRST_GRF 55 +#define SRST_GMAC 56 +#define SRST_PERIPH_NOC_H 58 +#define SRST_MACPHY 63 + +#define SRST_DMA 64 +#define SRST_NANDC 68 +#define SRST_USBOTG 69 +#define SRST_OTGC 70 +#define SRST_USBHOST0 71 +#define SRST_HOST_CTRL0 72 +#define SRST_USBHOST1 73 +#define SRST_HOST_CTRL1 74 +#define SRST_USBHOST2 75 +#define SRST_HOST_CTRL2 76 +#define SRST_USBPOR0 77 +#define SRST_USBPOR1 78 +#define SRST_DDRMSCH 79 + +#define SRST_SMART_CARD 80 +#define SRST_SDMMC 81 +#define SRST_SDIO 82 +#define SRST_EMMC 83 +#define SRST_SPI 84 +#define SRST_TSP_H 85 +#define SRST_TSP 86 +#define SRST_TSADC 87 +#define SRST_DDRPHY 88 +#define SRST_DDRPHY_P 89 +#define SRST_DDRCTRL 90 +#define SRST_DDRCTRL_P 91 +#define SRST_HOST0_ECHI 92 +#define SRST_HOST1_ECHI 93 +#define SRST_HOST2_ECHI 94 +#define SRST_VOP_NOC_A 95 + +#define SRST_HDMI_P 96 +#define SRST_VIO_ARBI_H 97 +#define SRST_IEP_NOC_A 98 +#define SRST_VIO_NOC_H 99 +#define SRST_VOP_A 100 +#define SRST_VOP_H 101 +#define SRST_VOP_D 102 +#define SRST_UTMI0 103 +#define SRST_UTMI1 104 +#define SRST_UTMI2 105 +#define SRST_UTMI3 106 +#define SRST_RGA 107 +#define SRST_RGA_NOC_A 108 +#define SRST_RGA_A 109 +#define SRST_RGA_H 110 +#define SRST_HDCP_A 111 + +#define SRST_VPU_A 112 +#define SRST_VPU_H 113 +#define SRST_VPU_NOC_A 116 +#define SRST_VPU_NOC_H 117 +#define SRST_RKVDEC_A 118 +#define SRST_RKVDEC_NOC_A 119 +#define SRST_RKVDEC_H 120 +#define SRST_RKVDEC_NOC_H 121 +#define SRST_RKVDEC_CORE 122 +#define SRST_RKVDEC_CABAC 123 +#define SRST_IEP_A 124 +#define SRST_IEP_H 125 +#define SRST_GPU_A 126 +#define SRST_GPU_NOC_A 127 + +#define SRST_CORE_DBG 128 +#define SRST_DBG_P 129 +#define SRST_TIMER0 130 +#define SRST_TIMER1 131 +#define SRST_TIMER2 132 +#define SRST_TIMER3 133 +#define SRST_TIMER4 134 +#define SRST_TIMER5 135 +#define SRST_VIO_H2P 136 +#define SRST_HDMIPHY 139 +#define SRST_VDAC 140 +#define SRST_TIMER_6CH_P 141 + +#endif diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h index c719aacef14f..1f9c62f07389 100644 --- a/include/dt-bindings/clock/rk3288-cru.h +++ b/include/dt-bindings/clock/rk3288-cru.h @@ -86,7 +86,18 @@ #define SCLK_USBPHY480M_SRC 122 #define SCLK_PVTM_CORE 123 #define SCLK_PVTM_GPU 124 +#define SCLK_CRYPTO 125 +#define SCLK_MIPIDSI_24M 126 +#define SCLK_VIP_OUT 127 +#define SCLK_DDRCLK 128 +#define SCLK_I2S_SRC 129 +#define SCLK_TSPOUT 130 +#define SCLK_TSP 131 +#define SCLK_HSADC0_TSP 132 +#define SCLK_HSADC1_TSP 133 +#define SCLK_27M_TSP 134 +#define SCLK_MAC_PLL 150 #define SCLK_MAC 151 #define SCLK_MACREF_OUT 152 @@ -113,6 +124,8 @@ #define ACLK_VCODEC 208 #define ACLK_CPU 209 #define ACLK_PERI 210 +#define ACLK_VIO0 211 +#define ACLK_VIO1 212 /* pclk gates */ #define PCLK_GPIO0 320 @@ -164,6 +177,13 @@ #define PCLK_DDRUPCTL1 366 #define PCLK_PUBL1 367 #define PCLK_WDT 368 +#define PCLK_EFUSE256 369 +#define PCLK_EFUSE1024 370 +#define PCLK_ISP_IN 371 +#define PCLK_VIP 372 +#define PCLK_VIP_IN 373 +#define PCLK_PD_ALIVE 374 +#define PCLK_PD_PMU 375 /* hclk gates */ #define HCLK_GPS 448 @@ -197,8 +217,10 @@ #define HCLK_VCODEC 476 #define HCLK_CPU 477 #define HCLK_PERI 478 +#define HCLK_USB_PERI 479 +#define HCLK_VIO 480 -#define CLK_NR_CLKS (HCLK_PERI + 1) +#define CLK_NR_CLKS (HCLK_VIO + 1) /* soft-reset indices */ #define SRST_CORE0 0 diff --git a/include/dt-bindings/clock/rk3308-cru.h b/include/dt-bindings/clock/rk3308-cru.h new file mode 100644 index 000000000000..5088a0f6fb02 --- /dev/null +++ b/include/dt-bindings/clock/rk3308-cru.h @@ -0,0 +1,396 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Author: Finley Xiao <finley.xiao@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_VPLL0 3 +#define PLL_VPLL1 4 +#define ARMCLK 5 + +/* sclk (special clocks) */ +#define USB480M 14 +#define SCLK_RTC32K 15 +#define SCLK_PVTM_CORE 16 +#define SCLK_UART0 17 +#define SCLK_UART1 18 +#define SCLK_UART2 19 +#define SCLK_UART3 20 +#define SCLK_UART4 21 +#define SCLK_I2C0 22 +#define SCLK_I2C1 23 +#define SCLK_I2C2 24 +#define SCLK_I2C3 25 +#define SCLK_PWM0 26 +#define SCLK_SPI0 27 +#define SCLK_SPI1 28 +#define SCLK_SPI2 29 +#define SCLK_TIMER0 30 +#define SCLK_TIMER1 31 +#define SCLK_TIMER2 32 +#define SCLK_TIMER3 33 +#define SCLK_TIMER4 34 +#define SCLK_TIMER5 35 +#define SCLK_TSADC 36 +#define SCLK_SARADC 37 +#define SCLK_OTP 38 +#define SCLK_OTP_USR 39 +#define SCLK_CPU_BOOST 40 +#define SCLK_CRYPTO 41 +#define SCLK_CRYPTO_APK 42 +#define SCLK_NANDC_DIV 43 +#define SCLK_NANDC_DIV50 44 +#define SCLK_NANDC 45 +#define SCLK_SDMMC_DIV 46 +#define SCLK_SDMMC_DIV50 47 +#define SCLK_SDMMC 48 +#define SCLK_SDMMC_DRV 49 +#define SCLK_SDMMC_SAMPLE 50 +#define SCLK_SDIO_DIV 51 +#define SCLK_SDIO_DIV50 52 +#define SCLK_SDIO 53 +#define SCLK_SDIO_DRV 54 +#define SCLK_SDIO_SAMPLE 55 +#define SCLK_EMMC_DIV 56 +#define SCLK_EMMC_DIV50 57 +#define SCLK_EMMC 58 +#define SCLK_EMMC_DRV 59 +#define SCLK_EMMC_SAMPLE 60 +#define SCLK_SFC 61 +#define SCLK_OTG_ADP 62 +#define SCLK_MAC_SRC 63 +#define SCLK_MAC 64 +#define SCLK_MAC_REF 65 +#define SCLK_MAC_RX_TX 66 +#define SCLK_MAC_RMII 67 +#define SCLK_DDR_MON_TIMER 68 +#define SCLK_DDR_MON 69 +#define SCLK_DDRCLK 70 +#define SCLK_PMU 71 +#define SCLK_USBPHY_REF 72 +#define SCLK_WIFI 73 +#define SCLK_PVTM_PMU 74 +#define SCLK_PDM 75 +#define SCLK_I2S0_8CH_TX 76 +#define SCLK_I2S0_8CH_TX_OUT 77 +#define SCLK_I2S0_8CH_RX 78 +#define SCLK_I2S0_8CH_RX_OUT 79 +#define SCLK_I2S1_8CH_TX 80 +#define SCLK_I2S1_8CH_TX_OUT 81 +#define SCLK_I2S1_8CH_RX 82 +#define SCLK_I2S1_8CH_RX_OUT 83 +#define SCLK_I2S2_8CH_TX 84 +#define SCLK_I2S2_8CH_TX_OUT 85 +#define SCLK_I2S2_8CH_RX 86 +#define SCLK_I2S2_8CH_RX_OUT 87 +#define SCLK_I2S3_8CH_TX 88 +#define SCLK_I2S3_8CH_TX_OUT 89 +#define SCLK_I2S3_8CH_RX 90 +#define SCLK_I2S3_8CH_RX_OUT 91 +#define SCLK_I2S0_2CH 92 +#define SCLK_I2S0_2CH_OUT 93 +#define SCLK_I2S1_2CH 94 +#define SCLK_I2S1_2CH_OUT 95 +#define SCLK_SPDIF_TX_DIV 96 +#define SCLK_SPDIF_TX_DIV50 97 +#define SCLK_SPDIF_TX 98 +#define SCLK_SPDIF_RX_DIV 99 +#define SCLK_SPDIF_RX_DIV50 100 +#define SCLK_SPDIF_RX 101 +#define SCLK_I2S0_8CH_TX_MUX 102 +#define SCLK_I2S0_8CH_RX_MUX 103 +#define SCLK_I2S1_8CH_TX_MUX 104 +#define SCLK_I2S1_8CH_RX_MUX 105 +#define SCLK_I2S2_8CH_TX_MUX 106 +#define SCLK_I2S2_8CH_RX_MUX 107 +#define SCLK_I2S3_8CH_TX_MUX 108 +#define SCLK_I2S3_8CH_RX_MUX 109 +#define SCLK_I2S0_8CH_TX_SRC 110 +#define SCLK_I2S0_8CH_RX_SRC 111 +#define SCLK_I2S1_8CH_TX_SRC 112 +#define SCLK_I2S1_8CH_RX_SRC 113 +#define SCLK_I2S2_8CH_TX_SRC 114 +#define SCLK_I2S2_8CH_RX_SRC 115 +#define SCLK_I2S3_8CH_TX_SRC 116 +#define SCLK_I2S3_8CH_RX_SRC 117 +#define SCLK_I2S0_2CH_SRC 118 +#define SCLK_I2S1_2CH_SRC 119 +#define SCLK_PWM1 120 +#define SCLK_PWM2 121 +#define SCLK_OWIRE 122 + +/* dclk */ +#define DCLK_VOP 125 + +/* aclk */ +#define ACLK_BUS_SRC 130 +#define ACLK_BUS 131 +#define ACLK_PERI_SRC 132 +#define ACLK_PERI 133 +#define ACLK_MAC 134 +#define ACLK_CRYPTO 135 +#define ACLK_VOP 136 +#define ACLK_GIC 137 +#define ACLK_DMAC0 138 +#define ACLK_DMAC1 139 + +/* hclk */ +#define HCLK_BUS 150 +#define HCLK_PERI 151 +#define HCLK_AUDIO 152 +#define HCLK_NANDC 153 +#define HCLK_SDMMC 154 +#define HCLK_SDIO 155 +#define HCLK_EMMC 156 +#define HCLK_SFC 157 +#define HCLK_OTG 158 +#define HCLK_HOST 159 +#define HCLK_HOST_ARB 160 +#define HCLK_PDM 161 +#define HCLK_SPDIFTX 162 +#define HCLK_SPDIFRX 163 +#define HCLK_I2S0_8CH 164 +#define HCLK_I2S1_8CH 165 +#define HCLK_I2S2_8CH 166 +#define HCLK_I2S3_8CH 167 +#define HCLK_I2S0_2CH 168 +#define HCLK_I2S1_2CH 169 +#define HCLK_VAD 170 +#define HCLK_CRYPTO 171 +#define HCLK_VOP 172 + +/* pclk */ +#define PCLK_BUS 190 +#define PCLK_DDR 191 +#define PCLK_PERI 192 +#define PCLK_PMU 193 +#define PCLK_AUDIO 194 +#define PCLK_MAC 195 +#define PCLK_ACODEC 196 +#define PCLK_UART0 197 +#define PCLK_UART1 198 +#define PCLK_UART2 199 +#define PCLK_UART3 200 +#define PCLK_UART4 201 +#define PCLK_I2C0 202 +#define PCLK_I2C1 203 +#define PCLK_I2C2 204 +#define PCLK_I2C3 205 +#define PCLK_PWM0 206 +#define PCLK_SPI0 207 +#define PCLK_SPI1 208 +#define PCLK_SPI2 209 +#define PCLK_SARADC 210 +#define PCLK_TSADC 211 +#define PCLK_TIMER 212 +#define PCLK_OTP_NS 213 +#define PCLK_WDT 214 +#define PCLK_GPIO0 215 +#define PCLK_GPIO1 216 +#define PCLK_GPIO2 217 +#define PCLK_GPIO3 218 +#define PCLK_GPIO4 219 +#define PCLK_SGRF 220 +#define PCLK_GRF 221 +#define PCLK_USBSD_DET 222 +#define PCLK_DDR_UPCTL 223 +#define PCLK_DDR_MON 224 +#define PCLK_DDRPHY 225 +#define PCLK_DDR_STDBY 226 +#define PCLK_USB_GRF 227 +#define PCLK_CRU 228 +#define PCLK_OTP_PHY 229 +#define PCLK_CPU_BOOST 230 +#define PCLK_PWM1 231 +#define PCLK_PWM2 232 +#define PCLK_CAN 233 +#define PCLK_OWIRE 234 + +#define CLK_NR_CLKS (PCLK_OWIRE + 1) + +/* soft-reset indices */ + +/* cru_softrst_con0 */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_CORE_NOC 13 +#define SRST_STRC_A 14 +#define SRST_L2C 15 + +/* cru_softrst_con1 */ +#define SRST_DAP 16 +#define SRST_CORE_PVTM 17 +#define SRST_CORE_PRF 18 +#define SRST_CORE_GRF 19 +#define SRST_DDRUPCTL 20 +#define SRST_DDRUPCTL_P 22 +#define SRST_MSCH 23 +#define SRST_DDRMON_P 25 +#define SRST_DDRSTDBY_P 26 +#define SRST_DDRSTDBY 27 +#define SRST_DDRPHY 28 +#define SRST_DDRPHY_DIV 29 +#define SRST_DDRPHY_P 30 + +/* cru_softrst_con2 */ +#define SRST_BUS_NIU_H 32 +#define SRST_USB_NIU_P 33 +#define SRST_CRYPTO_A 34 +#define SRST_CRYPTO_H 35 +#define SRST_CRYPTO 36 +#define SRST_CRYPTO_APK 37 +#define SRST_VOP_A 38 +#define SRST_VOP_H 39 +#define SRST_VOP_D 40 +#define SRST_INTMEM_A 41 +#define SRST_ROM_H 42 +#define SRST_GIC_A 43 +#define SRST_UART0_P 44 +#define SRST_UART0 45 +#define SRST_UART1_P 46 +#define SRST_UART1 47 + +/* cru_softrst_con3 */ +#define SRST_UART2_P 48 +#define SRST_UART2 49 +#define SRST_UART3_P 50 +#define SRST_UART3 51 +#define SRST_UART4_P 52 +#define SRST_UART4 53 +#define SRST_I2C0_P 54 +#define SRST_I2C0 55 +#define SRST_I2C1_P 56 +#define SRST_I2C1 57 +#define SRST_I2C2_P 58 +#define SRST_I2C2 59 +#define SRST_I2C3_P 60 +#define SRST_I2C3 61 +#define SRST_PWM0_P 62 +#define SRST_PWM0 63 + +/* cru_softrst_con4 */ +#define SRST_SPI0_P 64 +#define SRST_SPI0 65 +#define SRST_SPI1_P 66 +#define SRST_SPI1 67 +#define SRST_SPI2_P 68 +#define SRST_SPI2 69 +#define SRST_SARADC_P 70 +#define SRST_TSADC_P 71 +#define SRST_TSADC 72 +#define SRST_TIMER0_P 73 +#define SRST_TIMER0 74 +#define SRST_TIMER1 75 +#define SRST_TIMER2 76 +#define SRST_TIMER3 77 +#define SRST_TIMER4 78 +#define SRST_TIMER5 79 + +/* cru_softrst_con5 */ +#define SRST_OTP_NS_P 80 +#define SRST_OTP_NS_SBPI 81 +#define SRST_OTP_NS_USR 82 +#define SRST_OTP_PHY_P 83 +#define SRST_OTP_PHY 84 +#define SRST_GPIO0_P 86 +#define SRST_GPIO1_P 87 +#define SRST_GPIO2_P 88 +#define SRST_GPIO3_P 89 +#define SRST_GPIO4_P 90 +#define SRST_GRF_P 91 +#define SRST_USBSD_DET_P 92 +#define SRST_PMU 93 +#define SRST_PMU_PVTM 94 +#define SRST_USB_GRF_P 95 + +/* cru_softrst_con6 */ +#define SRST_CPU_BOOST 96 +#define SRST_CPU_BOOST_P 97 +#define SRST_PWM1_P 98 +#define SRST_PWM1 99 +#define SRST_PWM2_P 100 +#define SRST_PWM2 101 +#define SRST_PERI_NIU_A 104 +#define SRST_PERI_NIU_H 105 +#define SRST_PERI_NIU_p 106 +#define SRST_USB2OTG_H 107 +#define SRST_USB2OTG 108 +#define SRST_USB2OTG_ADP 109 +#define SRST_USB2HOST_H 110 +#define SRST_USB2HOST_ARB_H 111 + +/* cru_softrst_con7 */ +#define SRST_USB2HOST_AUX_H 112 +#define SRST_USB2HOST_EHCI 113 +#define SRST_USB2HOST 114 +#define SRST_USBPHYPOR 115 +#define SRST_UTMI0 116 +#define SRST_UTMI1 117 +#define SRST_SDIO_H 118 +#define SRST_EMMC_H 119 +#define SRST_SFC_H 120 +#define SRST_SFC 121 +#define SRST_SD_H 122 +#define SRST_NANDC_H 123 +#define SRST_NANDC_N 124 +#define SRST_MAC_A 125 +#define SRST_CAN_P 126 +#define SRST_OWIRE_P 127 + +/* cru_softrst_con8 */ +#define SRST_AUDIO_NIU_H 128 +#define SRST_AUDIO_NIU_P 129 +#define SRST_PDM_H 130 +#define SRST_PDM_M 131 +#define SRST_SPDIFTX_H 132 +#define SRST_SPDIFTX_M 133 +#define SRST_SPDIFRX_H 134 +#define SRST_SPDIFRX_M 135 +#define SRST_I2S0_8CH_H 136 +#define SRST_I2S0_8CH_TX_M 137 +#define SRST_I2S0_8CH_RX_M 138 +#define SRST_I2S1_8CH_H 139 +#define SRST_I2S1_8CH_TX_M 140 +#define SRST_I2S1_8CH_RX_M 141 +#define SRST_I2S2_8CH_H 142 +#define SRST_I2S2_8CH_TX_M 143 + +/* cru_softrst_con9 */ +#define SRST_I2S2_8CH_RX_M 144 +#define SRST_I2S3_8CH_H 145 +#define SRST_I2S3_8CH_TX_M 146 +#define SRST_I2S3_8CH_RX_M 147 +#define SRST_I2S0_2CH_H 148 +#define SRST_I2S0_2CH_M 149 +#define SRST_I2S1_2CH_H 150 +#define SRST_I2S1_2CH_M 151 +#define SRST_VAD_H 152 +#define SRST_ACODEC_P 153 + +#endif diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h new file mode 100644 index 000000000000..62479fddb96b --- /dev/null +++ b/include/dt-bindings/clock/rk3328-cru.h @@ -0,0 +1,402 @@ +/* + * Copyright (c) 2016 Rockchip Electronics Co. Ltd. + * Author: Elaine <zhangqing@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define PLL_NPLL 5 +#define ARMCLK 6 + +/* sclk gates (special clocks) */ +#define SCLK_RTC32K 30 +#define SCLK_SDMMC_EXT 31 +#define SCLK_SPI 32 +#define SCLK_SDMMC 33 +#define SCLK_SDIO 34 +#define SCLK_EMMC 35 +#define SCLK_TSADC 36 +#define SCLK_SARADC 37 +#define SCLK_UART0 38 +#define SCLK_UART1 39 +#define SCLK_UART2 40 +#define SCLK_I2S0 41 +#define SCLK_I2S1 42 +#define SCLK_I2S2 43 +#define SCLK_I2S1_OUT 44 +#define SCLK_I2S2_OUT 45 +#define SCLK_SPDIF 46 +#define SCLK_TIMER0 47 +#define SCLK_TIMER1 48 +#define SCLK_TIMER2 49 +#define SCLK_TIMER3 50 +#define SCLK_TIMER4 51 +#define SCLK_TIMER5 52 +#define SCLK_WIFI 53 +#define SCLK_CIF_OUT 54 +#define SCLK_I2C0 55 +#define SCLK_I2C1 56 +#define SCLK_I2C2 57 +#define SCLK_I2C3 58 +#define SCLK_CRYPTO 59 +#define SCLK_PWM 60 +#define SCLK_PDM 61 +#define SCLK_EFUSE 62 +#define SCLK_OTP 63 +#define SCLK_DDRCLK 64 +#define SCLK_VDEC_CABAC 65 +#define SCLK_VDEC_CORE 66 +#define SCLK_VENC_DSP 67 +#define SCLK_VENC_CORE 68 +#define SCLK_RGA 69 +#define SCLK_HDMI_SFC 70 +#define SCLK_HDMI_CEC 71 +#define SCLK_USB3_REF 72 +#define SCLK_USB3_SUSPEND 73 +#define SCLK_SDMMC_DRV 74 +#define SCLK_SDIO_DRV 75 +#define SCLK_EMMC_DRV 76 +#define SCLK_SDMMC_EXT_DRV 77 +#define SCLK_SDMMC_SAMPLE 78 +#define SCLK_SDIO_SAMPLE 79 +#define SCLK_EMMC_SAMPLE 80 +#define SCLK_SDMMC_EXT_SAMPLE 81 +#define SCLK_VOP 82 +#define SCLK_MAC2PHY_RXTX 83 +#define SCLK_MAC2PHY_SRC 84 +#define SCLK_MAC2PHY_REF 85 +#define SCLK_MAC2PHY_OUT 86 +#define SCLK_MAC2IO_RX 87 +#define SCLK_MAC2IO_TX 88 +#define SCLK_MAC2IO_REFOUT 89 +#define SCLK_MAC2IO_REF 90 +#define SCLK_MAC2IO_OUT 91 +#define SCLK_TSP 92 +#define SCLK_HSADC_TSP 93 +#define SCLK_USB3PHY_REF 94 +#define SCLK_REF_USB3OTG 95 +#define SCLK_USB3OTG_REF 96 +#define SCLK_USB3OTG_SUSPEND 97 +#define SCLK_REF_USB3OTG_SRC 98 +#define SCLK_MAC2IO_SRC 99 +#define SCLK_MAC2IO 100 +#define SCLK_MAC2PHY 101 +#define SCLK_MAC2IO_EXT 102 + +/* dclk gates */ +#define DCLK_LCDC 120 +#define DCLK_HDMIPHY 121 +#define HDMIPHY 122 +#define USB480M 123 +#define DCLK_LCDC_SRC 124 + +/* aclk gates */ +#define ACLK_AXISRAM 130 +#define ACLK_VOP_PRE 131 +#define ACLK_USB3OTG 132 +#define ACLK_RGA_PRE 133 +#define ACLK_DMAC 134 +#define ACLK_GPU 135 +#define ACLK_BUS_PRE 136 +#define ACLK_PERI_PRE 137 +#define ACLK_RKVDEC_PRE 138 +#define ACLK_RKVDEC 139 +#define ACLK_RKVENC 140 +#define ACLK_VPU_PRE 141 +#define ACLK_VIO_PRE 142 +#define ACLK_VPU 143 +#define ACLK_VIO 144 +#define ACLK_VOP 145 +#define ACLK_GMAC 146 +#define ACLK_H265 147 +#define ACLK_H264 148 +#define ACLK_MAC2PHY 149 +#define ACLK_MAC2IO 150 +#define ACLK_DCF 151 +#define ACLK_TSP 152 +#define ACLK_PERI 153 +#define ACLK_RGA 154 +#define ACLK_IEP 155 +#define ACLK_CIF 156 +#define ACLK_HDCP 157 + +/* pclk gates */ +#define PCLK_GPIO0 200 +#define PCLK_GPIO1 201 +#define PCLK_GPIO2 202 +#define PCLK_GPIO3 203 +#define PCLK_GRF 204 +#define PCLK_I2C0 205 +#define PCLK_I2C1 206 +#define PCLK_I2C2 207 +#define PCLK_I2C3 208 +#define PCLK_SPI 209 +#define PCLK_UART0 210 +#define PCLK_UART1 211 +#define PCLK_UART2 212 +#define PCLK_TSADC 213 +#define PCLK_PWM 214 +#define PCLK_TIMER 215 +#define PCLK_BUS_PRE 216 +#define PCLK_PERI_PRE 217 +#define PCLK_HDMI_CTRL 218 +#define PCLK_HDMI_PHY 219 +#define PCLK_GMAC 220 +#define PCLK_H265 221 +#define PCLK_MAC2PHY 222 +#define PCLK_MAC2IO 223 +#define PCLK_USB3PHY_OTG 224 +#define PCLK_USB3PHY_PIPE 225 +#define PCLK_USB3_GRF 226 +#define PCLK_USB2_GRF 227 +#define PCLK_HDMIPHY 228 +#define PCLK_DDR 229 +#define PCLK_PERI 230 +#define PCLK_HDMI 231 +#define PCLK_HDCP 232 +#define PCLK_DCF 233 +#define PCLK_SARADC 234 +#define PCLK_ACODEC 235 + +/* hclk gates */ +#define HCLK_PERI 308 +#define HCLK_TSP 309 +#define HCLK_GMAC 310 +#define HCLK_I2S0_8CH 311 +#define HCLK_I2S1_8CH 312 +#define HCLK_I2S2_2CH 313 +#define HCLK_SPDIF_8CH 314 +#define HCLK_VOP 315 +#define HCLK_NANDC 316 +#define HCLK_SDMMC 317 +#define HCLK_SDIO 318 +#define HCLK_EMMC 319 +#define HCLK_SDMMC_EXT 320 +#define HCLK_RKVDEC_PRE 321 +#define HCLK_RKVDEC 322 +#define HCLK_RKVENC 323 +#define HCLK_VPU_PRE 324 +#define HCLK_VIO_PRE 325 +#define HCLK_VPU 326 +#define HCLK_VIO 327 +#define HCLK_BUS_PRE 328 +#define HCLK_PERI_PRE 329 +#define HCLK_H264 330 +#define HCLK_CIF 331 +#define HCLK_OTG_PMU 332 +#define HCLK_OTG 333 +#define HCLK_HOST0 334 +#define HCLK_HOST0_ARB 335 +#define HCLK_CRYPTO_MST 336 +#define HCLK_CRYPTO_SLV 337 +#define HCLK_PDM 338 +#define HCLK_IEP 339 +#define HCLK_RGA 340 +#define HCLK_HDCP 341 + +#define CLK_NR_CLKS (HCLK_HDCP + 1) + +/* soft-reset indices */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_CORE_NIU 13 +#define SRST_STRC_A 14 +#define SRST_L2C 15 + +#define SRST_A53_GIC 18 +#define SRST_DAP 19 +#define SRST_PMU_P 21 +#define SRST_EFUSE 22 +#define SRST_BUSSYS_H 23 +#define SRST_BUSSYS_P 24 +#define SRST_SPDIF 25 +#define SRST_INTMEM 26 +#define SRST_ROM 27 +#define SRST_GPIO0 28 +#define SRST_GPIO1 29 +#define SRST_GPIO2 30 +#define SRST_GPIO3 31 + +#define SRST_I2S0 32 +#define SRST_I2S1 33 +#define SRST_I2S2 34 +#define SRST_I2S0_H 35 +#define SRST_I2S1_H 36 +#define SRST_I2S2_H 37 +#define SRST_UART0 38 +#define SRST_UART1 39 +#define SRST_UART2 40 +#define SRST_UART0_P 41 +#define SRST_UART1_P 42 +#define SRST_UART2_P 43 +#define SRST_I2C0 44 +#define SRST_I2C1 45 +#define SRST_I2C2 46 +#define SRST_I2C3 47 + +#define SRST_I2C0_P 48 +#define SRST_I2C1_P 49 +#define SRST_I2C2_P 50 +#define SRST_I2C3_P 51 +#define SRST_EFUSE_SE_P 52 +#define SRST_EFUSE_NS_P 53 +#define SRST_PWM0 54 +#define SRST_PWM0_P 55 +#define SRST_DMA 56 +#define SRST_TSP_A 57 +#define SRST_TSP_H 58 +#define SRST_TSP 59 +#define SRST_TSP_HSADC 60 +#define SRST_DCF_A 61 +#define SRST_DCF_P 62 + +#define SRST_SCR 64 +#define SRST_SPI 65 +#define SRST_TSADC 66 +#define SRST_TSADC_P 67 +#define SRST_CRYPTO 68 +#define SRST_SGRF 69 +#define SRST_GRF 70 +#define SRST_USB_GRF 71 +#define SRST_TIMER_6CH_P 72 +#define SRST_TIMER0 73 +#define SRST_TIMER1 74 +#define SRST_TIMER2 75 +#define SRST_TIMER3 76 +#define SRST_TIMER4 77 +#define SRST_TIMER5 78 +#define SRST_USB3GRF 79 + +#define SRST_PHYNIU 80 +#define SRST_HDMIPHY 81 +#define SRST_VDAC 82 +#define SRST_ACODEC_p 83 +#define SRST_SARADC 85 +#define SRST_SARADC_P 86 +#define SRST_GRF_DDR 87 +#define SRST_DFIMON 88 +#define SRST_MSCH 89 +#define SRST_DDRMSCH 91 +#define SRST_DDRCTRL 92 +#define SRST_DDRCTRL_P 93 +#define SRST_DDRPHY 94 +#define SRST_DDRPHY_P 95 + +#define SRST_GMAC_NIU_A 96 +#define SRST_GMAC_NIU_P 97 +#define SRST_GMAC2PHY_A 98 +#define SRST_GMAC2IO_A 99 +#define SRST_MACPHY 100 +#define SRST_OTP_PHY 101 +#define SRST_GPU_A 102 +#define SRST_GPU_NIU_A 103 +#define SRST_SDMMCEXT 104 +#define SRST_PERIPH_NIU_A 105 +#define SRST_PERIHP_NIU_H 106 +#define SRST_PERIHP_P 107 +#define SRST_PERIPHSYS_H 108 +#define SRST_MMC0 109 +#define SRST_SDIO 110 +#define SRST_EMMC 111 + +#define SRST_USB2OTG_H 112 +#define SRST_USB2OTG 113 +#define SRST_USB2OTG_ADP 114 +#define SRST_USB2HOST_H 115 +#define SRST_USB2HOST_ARB 116 +#define SRST_USB2HOST_AUX 117 +#define SRST_USB2HOST_EHCIPHY 118 +#define SRST_USB2HOST_UTMI 119 +#define SRST_USB3OTG 120 +#define SRST_USBPOR 121 +#define SRST_USB2OTG_UTMI 122 +#define SRST_USB2HOST_PHY_UTMI 123 +#define SRST_USB3OTG_UTMI 124 +#define SRST_USB3PHY_U2 125 +#define SRST_USB3PHY_U3 126 +#define SRST_USB3PHY_PIPE 127 + +#define SRST_VIO_A 128 +#define SRST_VIO_BUS_H 129 +#define SRST_VIO_H2P_H 130 +#define SRST_VIO_ARBI_H 131 +#define SRST_VOP_NIU_A 132 +#define SRST_VOP_A 133 +#define SRST_VOP_H 134 +#define SRST_VOP_D 135 +#define SRST_RGA 136 +#define SRST_RGA_NIU_A 137 +#define SRST_RGA_A 138 +#define SRST_RGA_H 139 +#define SRST_IEP_A 140 +#define SRST_IEP_H 141 +#define SRST_HDMI 142 +#define SRST_HDMI_P 143 + +#define SRST_HDCP_A 144 +#define SRST_HDCP 145 +#define SRST_HDCP_H 146 +#define SRST_CIF_A 147 +#define SRST_CIF_H 148 +#define SRST_CIF_P 149 +#define SRST_OTP_P 150 +#define SRST_OTP_SBPI 151 +#define SRST_OTP_USER 152 +#define SRST_DDRCTRL_A 153 +#define SRST_DDRSTDY_P 154 +#define SRST_DDRSTDY 155 +#define SRST_PDM_H 156 +#define SRST_PDM 157 +#define SRST_USB3PHY_OTG_P 158 +#define SRST_USB3PHY_PIPE_P 159 + +#define SRST_VCODEC_A 160 +#define SRST_VCODEC_NIU_A 161 +#define SRST_VCODEC_H 162 +#define SRST_VCODEC_NIU_H 163 +#define SRST_VDEC_A 164 +#define SRST_VDEC_NIU_A 165 +#define SRST_VDEC_H 166 +#define SRST_VDEC_NIU_H 167 +#define SRST_VDEC_CORE 168 +#define SRST_VDEC_CABAC 169 +#define SRST_DDRPHYDIV 175 + +#define SRST_RKVENC_NIU_A 176 +#define SRST_RKVENC_NIU_H 177 +#define SRST_RKVENC_H265_A 178 +#define SRST_RKVENC_H265_P 179 +#define SRST_RKVENC_H265_CORE 180 +#define SRST_RKVENC_H265_DSP 181 +#define SRST_RKVENC_H264_A 182 +#define SRST_RKVENC_H264_H 183 +#define SRST_RKVENC_INTMEM 184 + +#endif diff --git a/include/dt-bindings/clock/rk3366-cru.h b/include/dt-bindings/clock/rk3366-cru.h new file mode 100644 index 000000000000..31ae3993b123 --- /dev/null +++ b/include/dt-bindings/clock/rk3366-cru.h @@ -0,0 +1,424 @@ +/* + * Copyright (c) 2016 Rockchip Electronics Co. Ltd. + * Author: Xiao Feng <xf@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3366_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3366_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define PLL_NPLL 5 +#define PLL_MPLL 6 +#define PLL_WPLL 7 +#define PLL_BPLL 8 +#define ARMCLK 9 + +/* sclk gates (special clocks) */ +#define SCLK_CRYPTO 64 +#define SCLK_I2S_8CH_OUT 65 +#define SCLK_I2S_8CH 66 +#define SCLK_I2S_2CH 67 +#define SCLK_SPDIF_8CH 68 +#define SCLK_RGA 69 +#define SCLK_VOP_FULL_PWM 70 +#define SCLK_ISP 71 +#define SCLK_HDMI_HDCP 72 +#define SCLK_HDMI_CEC 73 +#define SCLK_HDCP 75 +#define SCLK_PVTM_CORE 76 +#define SCLK_PVTM_GPU 77 +#define SCLK_SPI0 78 +#define SCLK_SPI1 79 +#define SCLK_SPI2 80 +#define SCLK_SDMMC 81 +#define SCLK_SDIO0 82 +#define SCLK_SDIO1 83 +#define SCLK_EMMC 84 +#define SCLK_SDMMC_DRV 85 +#define SCLK_SDMMC_SAMPLE 86 +#define SCLK_SDIO0_DRV 87 +#define SCLK_SDIO0_SAMPLE 88 +#define SCLK_SDIO1_DRV 89 +#define SCLK_SDIO1_SAMPLE 90 +#define SCLK_EMMC_DRV 91 +#define SCLK_EMMC_SAMPLE 92 +#define SCLK_OTG_PHY0 93 +#define SCLK_OTG_PHY1 94 +#define SCLK_OTG_ADP 95 +#define SCLK_USB3_REF 96 +#define SCLK_USB3_SUSPEND 97 +#define SCLK_TSADC 98 +#define SCLK_SARADC 99 +#define SCLK_NANDC0 100 +#define SCLK_SFC 101 +#define SCLK_UART0 102 +#define SCLK_UART1 103 +#define SCLK_UART2 104 +#define SCLK_UART3 105 +#define SCLK_UART4 106 +#define SCLK_MAC 107 +#define SCLK_MACREF_OUT 108 +#define SCLK_MACREF 109 +#define SCLK_MAC_RX 110 +#define SCLK_MAC_TX 111 +#define SCLK_BT_52 112 +#define SCLK_BT_M0 113 +#define SCLK_WIFIDSP 114 +#define SCLK_TIMER0 115 +#define SCLK_TIMER1 116 +#define SCLK_TIMER2 117 +#define SCLK_TIMER3 118 +#define SCLK_TIMER4 119 +#define SCLK_TIMER5 120 +#define SCLK_USBPHY480M 121 +#define SCLK_WIFI_WPLL 122 +#define SCLK_WIFI_USBPHY480M 123 +#define SCLK_MIPIDSI_24M 124 +#define SCLK_HEVC_CABAC 125 +#define SCLK_HEVC_CORE 126 +#define SCLK_VIP_SRC 127 +#define SCLK_VIP_OUT 128 +#define SCLK_PVTM_PMU 129 +#define SCLK_MPLL_SRC 130 +#define SCLK_32K_INTR 131 +#define SCLK_32K 132 +#define SCLK_I2S_8CH_SRC 133 +#define SCLK_I2S_2CH_SRC 134 +#define SCLK_SPDIF_8CH_SRC 135 + +#define DCLK_VOP_FULL 170 +#define DCLK_VOP_LITE 171 +#define DCLK_HDMIPHY 172 +#define MCLK_CRYPTO 173 + +/* aclk gates */ +#define ACLK_DMAC_BUS 194 +#define ACLK_DFC 195 +#define ACLK_GPU 196 +#define ACLK_GPU_NOC 197 +#define ACLK_USB3 198 +#define ACLK_GMAC 199 +#define ACLK_DMAC_PERI 200 +#define ACLK_VIDEO 201 +#define ACLK_RKVDEC 202 +#define ACLK_RGA 203 +#define ACLK_IEP 204 +#define ACLK_VOP_LITE 205 +#define ACLK_VOP_FULL 206 +#define ACLK_VOP_IEP 207 +#define ACLK_ISP 208 +#define ACLK_HDCP 209 +#define ACLK_BUS 210 +#define ACLK_PERI0 211 +#define ACLK_PERI1 212 + +/* pclk gates */ +#define PCLK_PMU 322 +#define PCLK_SGRF 323 +#define PCLK_PMUGRF 324 +#define PCLK_GPIO0 325 +#define PCLK_GPIO1 326 +#define PCLK_GPIO2 327 +#define PCLK_GPIO3 328 +#define PCLK_GPIO4 329 +#define PCLK_GPIO5 330 +#define PCLK_GRF 331 +#define PCLK_DPHYRX 332 +#define PCLK_DPHYTX 333 +#define PCLK_TIMER0 334 +#define PCLK_DMFIMON 335 +#define PCLK_MAILBOX 336 +#define PCLK_DFC 337 +#define PCLK_DDRUPCTL 338 +#define PCLK_DDRPHY 339 +#define PCLK_RKPWM 340 +#define PCLK_GMAC 341 +#define PCLK_SPI0 342 +#define PCLK_SPI1 343 +#define PCLK_I2C0 344 +#define PCLK_I2C1 345 +#define PCLK_I2C2 346 +#define PCLK_I2C3 347 +#define PCLK_I2C4 348 +#define PCLK_I2C5 349 +#define PCLK_UART0 350 +#define PCLK_UART2 351 +#define PCLK_UART3 352 +#define PCLK_SARADC 353 +#define PCLK_TSADC 354 +#define PCLK_SIM 355 +#define PCLK_HDCP 356 +#define PCLK_HDMI_CTRL 357 +#define PCLK_VIO_H2P 358 +#define PCLK_WDT 359 +#define PCLK_BUS 361 +#define PCLK_PERI0 362 +#define PCLK_PERI1 363 +#define PCLK_MIPI_DSI0 364 +#define PCLK_ISP 365 +#define PCLK_EFUSE_1024 366 +#define PCLK_EFUSE_256 367 + +/* hclk gates */ +#define HCLK_I2S_8CH 448 +#define HCLK_I2S_2CH 449 +#define HCLK_SPDIF 450 +#define HCLK_ROM 451 +#define HCLK_CRYPTO 452 +#define HCLK_OTG 453 +#define HCLK_HOST 454 +#define HCLK_SDMMC 455 +#define HCLK_SDIO 456 +#define HCLK_EMMC 457 +#define HCLK_NANDC0 458 +#define HCLK_SFC 459 +#define HCLK_VIDEO 460 +#define HCLK_RKVDEC 461 +#define HCLK_ISP 462 +#define HCLK_RGA 463 +#define HCLK_IEP 464 +#define HCLK_VOP_FULL 465 +#define HCLK_VOP_LITE 466 +#define HCLK_VIO_AHB_ARBITER 467 +#define HCLK_VIO_NOC 468 +#define HCLK_VIO_H2P 469 +#define HCLK_VIO_HDCPMMU 470 +#define HCLK_BUS 471 +#define HCLK_PERI0 472 +#define HCLK_PERI1 473 + +#define CLK_NR_CLKS (HCLK_PERI1 + 1) + +/* soft-reset indices */ + +/* cru_softrst0_con */ +#define SRST_CORE0 0 +#define SRST_CORE1 1 +#define SRST_CORE2 2 +#define SRST_CORE3 3 +#define SRST_CORE0_PO 4 +#define SRST_CORE1_PO 5 +#define SRST_CORE2_PO 6 +#define SRST_CORE3_PO 7 +#define SRST_SOCDBG 14 +#define SRST_CORE_DBG 15 + +/* cru_softrst1_con */ +#define SRST_DCF_AXI 16 +#define SRST_DCF_APB 17 +#define SRST_DMAC1 18 +#define SRST_INTMEM 19 +#define SRST_ROM 20 +#define SRST_SPDIF8CH 21 +#define SRST_I2S8CH 23 +#define SRST_MAILBOX 24 +#define SRST_I2S2CH 25 +#define SRST_EFUSE_256 26 +#define SRST_MCU_SYS 28 +#define SRST_MCU_PO 29 +#define SRST_MCU_NOC 30 +#define SRST_EFUSE 31 + +/* cru_softrst2_con */ +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_GPIO3 35 +#define SRST_GPIO4 36 +#define SRST_GPIO5 37 +#define SRST_PMUGRF 41 +#define SRST_I2C0 42 +#define SRST_I2C1 43 +#define SRST_I2C2 44 +#define SRST_I2C3 45 +#define SRST_I2C4 46 +#define SRST_I2C5 47 + +/* cru_softrst3_con */ +#define SRST_DWPWM 48 +#define SRST_PERIPH1_AXI 50 +#define SRST_PERIPH1_AHB 51 +#define SRST_PERIPH1_APB 52 +#define SRST_PERIPH1_NIU 53 +#define SRST_PERI_AHB_ARBI1 54 +#define SRST_GRF 55 +#define SRST_PMU 56 +#define SRST_PERIPH0_AXI 57 +#define SRST_PERIPH0_AHB 58 +#define SRST_PERIPH0_APB 59 +#define SRST_PERIPH0_NIU 60 +#define SRST_PDPERI_AHB_ARBI0 61 +#define SRST_USBHOST0_ARBI 62 + +/* cru_softrst4_con */ +#define SRST_DMAC2 64 +#define SRST_MAC 66 +#define SRST_USB3 67 +#define SRST_USB3PHY 68 +#define SRST_RKPWM 69 +#define SRST_USBHOST0 72 +#define SRST_HSADC 76 +#define SRST_NANDC0 77 +#define SRST_SFC 79 + +/* cru_softrst5_con */ +#define SRST_TZPC 80 +#define SRST_SPI0 83 +#define SRST_SPI1 84 +#define SRST_SARADC 87 +#define SRST_PDALIVE_NIU 88 +#define SRST_PDPMU_INTMEM 89 +#define SRST_PDPMU_NIU 90 +#define SRST_SGRF 91 +#define SRST_VOP1_AXI 93 +#define SRST_VOP1_AHB 94 +#define SRST_VOP1_DCLK 95 + +/* cru_softrst6_con */ +#define SRST_VIO_ARBI 96 +#define SRST_RGA_NIU 97 +#define SRST_VIO0_NIU_AXI 98 +#define SRST_VIO_NIU_AHB 99 +#define SRST_VOP0_AXI 100 +#define SRST_VOP0_AHB 101 +#define SRST_VOP0_DCLK 102 +#define SRST_HDCP_NIU 103 +#define SRST_VIP 104 +#define SRST_RGA_CORE 105 +#define SRST_IEP_AXI 106 +#define SRST_IEP_AHB 107 +#define SRST_RGA_AXI 108 +#define SRST_RGA_AHB 109 +#define SRST_ISP 110 + +/* cru_softrst7_con */ +#define SRST_VIDEO_AXI 112 +#define SRST_VIDEO_AHB 113 +#define SRST_MIPIDPHYTX 114 +#define SRST_MIPIDSI0 115 +#define SRST_MIPIDPHYRX 116 +#define SRST_MIPICSI 117 +#define SRST_LVDS_CON 119 +#define SRST_GPU 120 +#define SRST_HDMI 121 +#define SRST_RGA_H2P 122 +#define SRST_PMU_PVTM 123 +#define SRST_CORE_PVTM 124 +#define SRST_GPU_PVTM 125 +#define SRST_GPU_NOC 126 + +/* cru_softrst8_con */ +#define SRST_MMC0 128 +#define SRST_SDIO0 129 +#define SRST_EMMC 131 +#define SRST_USBOTG_AHB 132 +#define SRST_USBOTG_PHY 133 +#define SRST_USBOTG_CON 134 +#define SRST_USBHOST0_AHB 135 +#define SRST_USBHPHY1 136 +#define SRST_USBHOST0_CON 137 +#define SRST_USBOTG_UTMI 138 +#define SRST_USBHOST0_UTMI 139 +#define SRST_USB_ADP 141 +#define SRST_TSADC 142 + +/* cru_softrst9_con */ +#define SRST_CORESIGHT 144 +#define SRST_PD_CORE_AHB_NOC 145 +#define SRST_PD_CORE_APB_NOC 146 +#define SRST_RKVDEC_NIU_AHB 147 +#define SRST_GIC 148 +#define SRST_LCDC_PWM0 149 +#define SRST_RKVDEC 150 +#define SRST_RKVDEC_NIU 151 +#define SRST_RKVDEC_AHB 152 +#define SRST_RKVDEC_CABAC 154 +#define SRST_RKVDEC_CORE 155 +#define SRST_GPU_CFG_NIU 157 +#define SRST_DFIMON 158 +#define SRST_TSADC_APB 159 + +/* cru_softrst10_con */ +#define SRST_DDRPHY0 160 +#define SRST_DDRPHY0_APB 161 +#define SRST_DDRCTRL0 162 +#define SRST_DDRCTRL0_APB 163 +#define SRST_DDRPHY0_CTL 164 +#define SRST_VIDEO_NIU 165 +#define SRST_VIDEO_NIU_AHB 167 +#define SRST_DDRMSCH0 170 +#define SRST_PDBUS_AHB 173 +#define SRST_CRYPTO 174 +#define SRST_DDR_NOC 175 + +/* cru_softrst11_con */ +#define SRST_PSPVTM_TOP 176 +#define SRST_PSPVTM_CORE 177 +#define SRST_PSPVTM_GPU 178 +#define SRST_UART0 179 +#define SRST_UART1 180 +#define SRST_UART2 181 +#define SRST_UART3 182 +#define SRST_UART4 183 +#define SRST_PSPVTM_VIDEO 184 +#define SRST_PSPVTM_VIO 185 +#define SRST_SIMC 186 +#define SRST_PSPVTM_PERI 187 + +/* cru_softrst12_con */ +#define SRST_WIFI_MAC_CORE 192 +#define SRST_WIFI_MAC_WT 193 +#define SRST_WIFI_MPIF 194 +#define SRST_WIFI_EXT 195 +#define SRST_WIFI_AHB 196 +#define SRST_WIFI_DSP 197 +#define SRST_BT_FAST_AHB 198 +#define SRST_BT_SLOW_AHB 199 +#define SRST_BT_SLOW_APB 200 +#define SRST_BT_MODEM 201 +#define SRST_BT_MCU 202 +#define SRST_BT_DM 203 +#define SRST_WIFI_LP 204 +#define SRST_BT_LP 205 +#define SRST_BT_MCU_SYS 206 +#define SRST_WIFI_DSP_ORSTN 207 + +/* cru_softrst13_con */ +#define SRST_CORE0_WFI 208 +#define SRST_CORE0_PO_WFI 209 +#define SRST_CORE_L2 210 +#define SRST_PD_CORE_NIU 212 +#define SRST_PDBUS_STRSYS 213 +#define SRST_TRACE 222 + +/* cru_softrst14_con */ +#define SRST_TIMER00 224 +#define SRST_TIMER01 225 +#define SRST_TIMER02 226 +#define SRST_TIMER03 227 +#define SRST_TIMER04 228 +#define SRST_TIMER05 229 +#define SRST_TIMER10 230 +#define SRST_TIMER11 231 +#define SRST_TIMER12 232 +#define SRST_TIMER13 233 +#define SRST_TIMER14 234 +#define SRST_TIMER15 235 +#define SRST_TIMER0_APB 236 +#define SRST_TIMER1_APB 237 + +#endif diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h index 9c5dd9ba2f6c..5d3531686790 100644 --- a/include/dt-bindings/clock/rk3368-cru.h +++ b/include/dt-bindings/clock/rk3368-cru.h @@ -44,13 +44,12 @@ #define SCLK_I2S_8CH 82 #define SCLK_SPDIF_8CH 83 #define SCLK_I2S_2CH 84 -#define SCLK_TIMER0 85 -#define SCLK_TIMER1 86 -#define SCLK_TIMER2 87 -#define SCLK_TIMER3 88 -#define SCLK_TIMER4 89 -#define SCLK_TIMER5 90 -#define SCLK_TIMER6 91 +#define SCLK_TIMER00 85 +#define SCLK_TIMER01 86 +#define SCLK_TIMER02 87 +#define SCLK_TIMER03 88 +#define SCLK_TIMER04 89 +#define SCLK_TIMER05 90 #define SCLK_OTGPHY0 93 #define SCLK_OTG_ADP 96 #define SCLK_HSICPHY480M 97 @@ -82,6 +81,19 @@ #define SCLK_SFC 126 #define SCLK_MAC 127 #define SCLK_MACREF_OUT 128 +#define SCLK_MIPIDSI_24M 129 +#define SCLK_CRYPTO 130 +#define SCLK_VIP_SRC 131 +#define SCLK_VIP_OUT 132 +#define SCLK_TIMER10 133 +#define SCLK_TIMER11 134 +#define SCLK_TIMER12 135 +#define SCLK_TIMER13 136 +#define SCLK_TIMER14 137 +#define SCLK_TIMER15 138 +#define SCLK_DDRCLK 139 +#define SCLK_TSP 140 +#define SCLK_HSADC_TSP 141 #define DCLK_VOP 190 #define MCLK_CRYPTO 191 @@ -105,6 +117,7 @@ #define ACLK_VIDEO 208 #define ACLK_BUS 209 #define ACLK_PERI 210 +#define ACLK_CCI_PRE 211 /* pclk gates */ #define PCLK_GPIO0 320 @@ -151,8 +164,13 @@ #define PCLK_ISP 366 #define PCLK_VIP 367 #define PCLK_WDT 368 +#define PCLK_DPHYRX 369 +#define PCLK_DPHYTX0 370 +#define PCLK_EFUSE256 371 +#define PCLK_EFUSE1024 372 /* hclk gates */ +#define HCLK_USB_PERI 447 #define HCLK_SFC 448 #define HCLK_OTG0 449 #define HCLK_HOST0 450 diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h new file mode 100644 index 000000000000..a2aa50c8d3ab --- /dev/null +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -0,0 +1,773 @@ +/* + * Copyright (c) 2016 Rockchip Electronics Co. Ltd. + * Author: Xing Zheng <zhengxing@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H + +#define RK3399_TWO_PLL_FOR_VOP + +/* core clocks */ +#define PLL_APLLL 1 +#define PLL_APLLB 2 +#define PLL_DPLL 3 +#define PLL_CPLL 4 +#define PLL_GPLL 5 +#define PLL_NPLL 6 +#define PLL_VPLL 7 +#define ARMCLKL 8 +#define ARMCLKB 9 + +/* sclk gates (special clocks) */ +#define SCLK_I2SOUT_SRC 64 +#define SCLK_I2C1 65 +#define SCLK_I2C2 66 +#define SCLK_I2C3 67 +#define SCLK_I2C5 68 +#define SCLK_I2C6 69 +#define SCLK_I2C7 70 +#define SCLK_SPI0 71 +#define SCLK_SPI1 72 +#define SCLK_SPI2 73 +#define SCLK_SPI4 74 +#define SCLK_SPI5 75 +#define SCLK_SDMMC 76 +#define SCLK_SDIO 77 +#define SCLK_EMMC 78 +#define SCLK_TSADC 79 +#define SCLK_SARADC 80 +#define SCLK_UART0 81 +#define SCLK_UART1 82 +#define SCLK_UART2 83 +#define SCLK_UART3 84 +#define SCLK_SPDIF_8CH 85 +#define SCLK_I2S0_8CH 86 +#define SCLK_I2S1_8CH 87 +#define SCLK_I2S2_8CH 88 +#define SCLK_I2S_8CH_OUT 89 +#define SCLK_TIMER00 90 +#define SCLK_TIMER01 91 +#define SCLK_TIMER02 92 +#define SCLK_TIMER03 93 +#define SCLK_TIMER04 94 +#define SCLK_TIMER05 95 +#define SCLK_TIMER06 96 +#define SCLK_TIMER07 97 +#define SCLK_TIMER08 98 +#define SCLK_TIMER09 99 +#define SCLK_TIMER10 100 +#define SCLK_TIMER11 101 +#define SCLK_MACREF 102 +#define SCLK_MAC_RX 103 +#define SCLK_MAC_TX 104 +#define SCLK_MAC 105 +#define SCLK_MACREF_OUT 106 +#define SCLK_VOP0_PWM 107 +#define SCLK_VOP1_PWM 108 +#define SCLK_RGA_CORE 109 +#define SCLK_ISP0 110 +#define SCLK_ISP1 111 +#define SCLK_HDMI_CEC 112 +#define SCLK_HDMI_SFR 113 +#define SCLK_DP_CORE 114 +#define SCLK_PVTM_CORE_L 115 +#define SCLK_PVTM_CORE_B 116 +#define SCLK_PVTM_GPU 117 +#define SCLK_PVTM_DDR 118 +#define SCLK_MIPIDPHY_REF 119 +#define SCLK_MIPIDPHY_CFG 120 +#define SCLK_HSICPHY 121 +#define SCLK_USBPHY480M 122 +#define SCLK_USB2PHY0_REF 123 +#define SCLK_USB2PHY1_REF 124 +#define SCLK_UPHY0_TCPDPHY_REF 125 +#define SCLK_UPHY0_TCPDCORE 126 +#define SCLK_UPHY1_TCPDPHY_REF 127 +#define SCLK_UPHY1_TCPDCORE 128 +#define SCLK_USB3OTG0_REF 129 +#define SCLK_USB3OTG1_REF 130 +#define SCLK_USB3OTG0_SUSPEND 131 +#define SCLK_USB3OTG1_SUSPEND 132 +#define SCLK_CRYPTO0 133 +#define SCLK_CRYPTO1 134 +#define SCLK_CCI_TRACE 135 +#define SCLK_CS 136 +#define SCLK_CIF_OUT 137 +#define SCLK_PCIEPHY_REF 138 +#define SCLK_PCIE_CORE 139 +#define SCLK_M0_PERILP 140 +#define SCLK_M0_PERILP_DEC 141 +#define SCLK_CM0S 142 +#define SCLK_DBG_NOC 143 +#define SCLK_DBG_PD_CORE_B 144 +#define SCLK_DBG_PD_CORE_L 145 +#define SCLK_DFIMON0_TIMER 146 +#define SCLK_DFIMON1_TIMER 147 +#define SCLK_INTMEM0 148 +#define SCLK_INTMEM1 149 +#define SCLK_INTMEM2 150 +#define SCLK_INTMEM3 151 +#define SCLK_INTMEM4 152 +#define SCLK_INTMEM5 153 +#define SCLK_SDMMC_DRV 154 +#define SCLK_SDMMC_SAMPLE 155 +#define SCLK_SDIO_DRV 156 +#define SCLK_SDIO_SAMPLE 157 +#define SCLK_VDU_CORE 158 +#define SCLK_VDU_CA 159 +#define SCLK_PCIE_PM 160 +#define SCLK_SPDIF_REC_DPTX 161 +#define SCLK_DPHY_PLL 162 +#define SCLK_DPHY_TX0_CFG 163 +#define SCLK_DPHY_TX1RX1_CFG 164 +#define SCLK_DPHY_RX0_CFG 165 +#define SCLK_RMII_SRC 166 +#define SCLK_PCIEPHY_REF100M 167 +#define SCLK_USBPHY0_480M_SRC 168 +#define SCLK_USBPHY1_480M_SRC 169 +#define SCLK_DDRCLK 170 +#define SCLK_TESTCLKOUT2 171 +#define SCLK_UART0_SRC 172 +#define SCLK_UART_SRC 173 +#define SCLK_I2S0_DIV 174 +#define SCLK_I2S1_DIV 175 +#define SCLK_I2S2_DIV 176 +#define SCLK_SPDIF_DIV 177 +#define SCLK_CIF_OUT_SRC 178 +#define SCLK_TESTCLKOUT1 179 + +#define DCLK_VOP0 180 +#define DCLK_VOP1 181 +#define DCLK_VOP0_DIV 182 +#define DCLK_VOP1_DIV 183 +#define DCLK_M0_PERILP 184 +#define DCLK_VOP0_FRAC 185 +#define DCLK_VOP1_FRAC 186 + +#define FCLK_CM0S 190 + +/* aclk gates */ +#define ACLK_PERIHP 192 +#define ACLK_PERIHP_NOC 193 +#define ACLK_PERILP0 194 +#define ACLK_PERILP0_NOC 195 +#define ACLK_PERF_PCIE 196 +#define ACLK_PCIE 197 +#define ACLK_INTMEM 198 +#define ACLK_TZMA 199 +#define ACLK_DCF 200 +#define ACLK_CCI 201 +#define ACLK_CCI_NOC0 202 +#define ACLK_CCI_NOC1 203 +#define ACLK_CCI_GRF 204 +#define ACLK_CENTER 205 +#define ACLK_CENTER_MAIN_NOC 206 +#define ACLK_CENTER_PERI_NOC 207 +#define ACLK_GPU 208 +#define ACLK_PERF_GPU 209 +#define ACLK_GPU_GRF 210 +#define ACLK_DMAC0_PERILP 211 +#define ACLK_DMAC1_PERILP 212 +#define ACLK_GMAC 213 +#define ACLK_GMAC_NOC 214 +#define ACLK_PERF_GMAC 215 +#define ACLK_VOP0_NOC 216 +#define ACLK_VOP0 217 +#define ACLK_VOP1_NOC 218 +#define ACLK_VOP1 219 +#define ACLK_RGA 220 +#define ACLK_RGA_NOC 221 +#define ACLK_HDCP 222 +#define ACLK_HDCP_NOC 223 +#define ACLK_HDCP22 224 +#define ACLK_IEP 225 +#define ACLK_IEP_NOC 226 +#define ACLK_VIO 227 +#define ACLK_VIO_NOC 228 +#define ACLK_ISP0 229 +#define ACLK_ISP1 230 +#define ACLK_ISP0_NOC 231 +#define ACLK_ISP1_NOC 232 +#define ACLK_ISP0_WRAPPER 233 +#define ACLK_ISP1_WRAPPER 234 +#define ACLK_VCODEC 235 +#define ACLK_VCODEC_NOC 236 +#define ACLK_VDU 237 +#define ACLK_VDU_NOC 238 +#define ACLK_PERI 239 +#define ACLK_EMMC 240 +#define ACLK_EMMC_CORE 241 +#define ACLK_EMMC_NOC 242 +#define ACLK_EMMC_GRF 243 +#define ACLK_USB3 244 +#define ACLK_USB3_NOC 245 +#define ACLK_USB3OTG0 246 +#define ACLK_USB3OTG1 247 +#define ACLK_USB3_RKSOC_AXI_PERF 248 +#define ACLK_USB3_GRF 249 +#define ACLK_GIC 250 +#define ACLK_GIC_NOC 251 +#define ACLK_GIC_ADB400_CORE_L_2_GIC 252 +#define ACLK_GIC_ADB400_CORE_B_2_GIC 253 +#define ACLK_GIC_ADB400_GIC_2_CORE_L 254 +#define ACLK_GIC_ADB400_GIC_2_CORE_B 255 +#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256 +#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257 +#define ACLK_ADB400M_PD_CORE_L 258 +#define ACLK_ADB400M_PD_CORE_B 259 +#define ACLK_PERF_CORE_L 260 +#define ACLK_PERF_CORE_B 261 +#define ACLK_GIC_PRE 262 +#define ACLK_VOP0_PRE 263 +#define ACLK_VOP1_PRE 264 + +/* pclk gates */ +#define PCLK_PERIHP 320 +#define PCLK_PERIHP_NOC 321 +#define PCLK_PERILP0 322 +#define PCLK_PERILP1 323 +#define PCLK_PERILP1_NOC 324 +#define PCLK_PERILP_SGRF 325 +#define PCLK_PERIHP_GRF 326 +#define PCLK_PCIE 327 +#define PCLK_SGRF 328 +#define PCLK_INTR_ARB 329 +#define PCLK_CENTER_MAIN_NOC 330 +#define PCLK_CIC 331 +#define PCLK_COREDBG_B 332 +#define PCLK_COREDBG_L 333 +#define PCLK_DBG_CXCS_PD_CORE_B 334 +#define PCLK_DCF 335 +#define PCLK_GPIO2 336 +#define PCLK_GPIO3 337 +#define PCLK_GPIO4 338 +#define PCLK_GRF 339 +#define PCLK_HSICPHY 340 +#define PCLK_I2C1 341 +#define PCLK_I2C2 342 +#define PCLK_I2C3 343 +#define PCLK_I2C5 344 +#define PCLK_I2C6 345 +#define PCLK_I2C7 346 +#define PCLK_SPI0 347 +#define PCLK_SPI1 348 +#define PCLK_SPI2 349 +#define PCLK_SPI4 350 +#define PCLK_SPI5 351 +#define PCLK_UART0 352 +#define PCLK_UART1 353 +#define PCLK_UART2 354 +#define PCLK_UART3 355 +#define PCLK_TSADC 356 +#define PCLK_SARADC 357 +#define PCLK_GMAC 358 +#define PCLK_GMAC_NOC 359 +#define PCLK_TIMER0 360 +#define PCLK_TIMER1 361 +#define PCLK_EDP 362 +#define PCLK_EDP_NOC 363 +#define PCLK_EDP_CTRL 364 +#define PCLK_VIO 365 +#define PCLK_VIO_NOC 366 +#define PCLK_VIO_GRF 367 +#define PCLK_MIPI_DSI0 368 +#define PCLK_MIPI_DSI1 369 +#define PCLK_HDCP 370 +#define PCLK_HDCP_NOC 371 +#define PCLK_HDMI_CTRL 372 +#define PCLK_DP_CTRL 373 +#define PCLK_HDCP22 374 +#define PCLK_GASKET 375 +#define PCLK_DDR 376 +#define PCLK_DDR_MON 377 +#define PCLK_DDR_SGRF 378 +#define PCLK_ISP1_WRAPPER 379 +#define PCLK_WDT 380 +#define PCLK_EFUSE1024NS 381 +#define PCLK_EFUSE1024S 382 +#define PCLK_PMU_INTR_ARB 383 +#define PCLK_MAILBOX0 384 +#define PCLK_USBPHY_MUX_G 385 +#define PCLK_UPHY0_TCPHY_G 386 +#define PCLK_UPHY0_TCPD_G 387 +#define PCLK_UPHY1_TCPHY_G 388 +#define PCLK_UPHY1_TCPD_G 389 +#define PCLK_ALIVE 390 + +/* hclk gates */ +#define HCLK_PERIHP 448 +#define HCLK_PERILP0 449 +#define HCLK_PERILP1 450 +#define HCLK_PERILP0_NOC 451 +#define HCLK_PERILP1_NOC 452 +#define HCLK_M0_PERILP 453 +#define HCLK_M0_PERILP_NOC 454 +#define HCLK_AHB1TOM 455 +#define HCLK_HOST0 456 +#define HCLK_HOST0_ARB 457 +#define HCLK_HOST1 458 +#define HCLK_HOST1_ARB 459 +#define HCLK_HSIC 460 +#define HCLK_SD 461 +#define HCLK_SDMMC 462 +#define HCLK_SDMMC_NOC 463 +#define HCLK_M_CRYPTO0 464 +#define HCLK_M_CRYPTO1 465 +#define HCLK_S_CRYPTO0 466 +#define HCLK_S_CRYPTO1 467 +#define HCLK_I2S0_8CH 468 +#define HCLK_I2S1_8CH 469 +#define HCLK_I2S2_8CH 470 +#define HCLK_SPDIF 471 +#define HCLK_VOP0_NOC 472 +#define HCLK_VOP0 473 +#define HCLK_VOP1_NOC 474 +#define HCLK_VOP1 475 +#define HCLK_ROM 476 +#define HCLK_IEP 477 +#define HCLK_IEP_NOC 478 +#define HCLK_ISP0 479 +#define HCLK_ISP1 480 +#define HCLK_ISP0_NOC 481 +#define HCLK_ISP1_NOC 482 +#define HCLK_ISP0_WRAPPER 483 +#define HCLK_ISP1_WRAPPER 484 +#define HCLK_RGA 485 +#define HCLK_RGA_NOC 486 +#define HCLK_HDCP 487 +#define HCLK_HDCP_NOC 488 +#define HCLK_HDCP22 489 +#define HCLK_VCODEC 490 +#define HCLK_VCODEC_NOC 491 +#define HCLK_VDU 492 +#define HCLK_VDU_NOC 493 +#define HCLK_SDIO 494 +#define HCLK_SDIO_NOC 495 +#define HCLK_SDIOAUDIO_NOC 496 + +#define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1) + +/* pmu-clocks indices */ + +#define PLL_PPLL 1 + +#define SCLK_32K_SUSPEND_PMU 2 +#define SCLK_SPI3_PMU 3 +#define SCLK_TIMER12_PMU 4 +#define SCLK_TIMER13_PMU 5 +#define SCLK_UART4_PMU 6 +#define SCLK_PVTM_PMU 7 +#define SCLK_WIFI_PMU 8 +#define SCLK_I2C0_PMU 9 +#define SCLK_I2C4_PMU 10 +#define SCLK_I2C8_PMU 11 +#define SCLK_UART4_SRC 12 + +#define PCLK_SRC_PMU 19 +#define PCLK_PMU 20 +#define PCLK_PMUGRF_PMU 21 +#define PCLK_INTMEM1_PMU 22 +#define PCLK_GPIO0_PMU 23 +#define PCLK_GPIO1_PMU 24 +#define PCLK_SGRF_PMU 25 +#define PCLK_NOC_PMU 26 +#define PCLK_I2C0_PMU 27 +#define PCLK_I2C4_PMU 28 +#define PCLK_I2C8_PMU 29 +#define PCLK_RKPWM_PMU 30 +#define PCLK_SPI3_PMU 31 +#define PCLK_TIMER_PMU 32 +#define PCLK_MAILBOX_PMU 33 +#define PCLK_UART4_PMU 34 +#define PCLK_WDT_M0_PMU 35 + +#define FCLK_CM0S_SRC_PMU 44 +#define FCLK_CM0S_PMU 45 +#define SCLK_CM0S_PMU 46 +#define HCLK_CM0S_PMU 47 +#define DCLK_CM0S_PMU 48 +#define PCLK_INTR_ARB_PMU 49 +#define HCLK_NOC_PMU 50 + +#define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1) + +/* soft-reset indices */ + +/* cru_softrst_con0 */ +#define SRST_CORE_L0 0 +#define SRST_CORE_B0 1 +#define SRST_CORE_PO_L0 2 +#define SRST_CORE_PO_B0 3 +#define SRST_L2_L 4 +#define SRST_L2_B 5 +#define SRST_ADB_L 6 +#define SRST_ADB_B 7 +#define SRST_A_CCI 8 +#define SRST_A_CCIM0_NOC 9 +#define SRST_A_CCIM1_NOC 10 +#define SRST_DBG_NOC 11 + +/* cru_softrst_con1 */ +#define SRST_CORE_L0_T 16 +#define SRST_CORE_L1 17 +#define SRST_CORE_L2 18 +#define SRST_CORE_L3 19 +#define SRST_CORE_PO_L0_T 20 +#define SRST_CORE_PO_L1 21 +#define SRST_CORE_PO_L2 22 +#define SRST_CORE_PO_L3 23 +#define SRST_A_ADB400_GIC2COREL 24 +#define SRST_A_ADB400_COREL2GIC 25 +#define SRST_P_DBG_L 26 +#define SRST_L2_L_T 28 +#define SRST_ADB_L_T 29 +#define SRST_A_RKPERF_L 30 +#define SRST_PVTM_CORE_L 31 + +/* cru_softrst_con2 */ +#define SRST_CORE_B0_T 32 +#define SRST_CORE_B1 33 +#define SRST_CORE_PO_B0_T 36 +#define SRST_CORE_PO_B1 37 +#define SRST_A_ADB400_GIC2COREB 40 +#define SRST_A_ADB400_COREB2GIC 41 +#define SRST_P_DBG_B 42 +#define SRST_L2_B_T 44 +#define SRST_ADB_B_T 45 +#define SRST_A_RKPERF_B 46 +#define SRST_PVTM_CORE_B 47 + +/* cru_softrst_con3 */ +#define SRST_A_CCI_T 50 +#define SRST_A_CCIM0_NOC_T 51 +#define SRST_A_CCIM1_NOC_T 52 +#define SRST_A_ADB400M_PD_CORE_B_T 53 +#define SRST_A_ADB400M_PD_CORE_L_T 54 +#define SRST_DBG_NOC_T 55 +#define SRST_DBG_CXCS 56 +#define SRST_CCI_TRACE 57 +#define SRST_P_CCI_GRF 58 + +/* cru_softrst_con4 */ +#define SRST_A_CENTER_MAIN_NOC 64 +#define SRST_A_CENTER_PERI_NOC 65 +#define SRST_P_CENTER_MAIN 66 +#define SRST_P_DDRMON 67 +#define SRST_P_CIC 68 +#define SRST_P_CENTER_SGRF 69 +#define SRST_DDR0_MSCH 70 +#define SRST_DDRCFG0_MSCH 71 +#define SRST_DDR0 72 +#define SRST_DDRPHY0 73 +#define SRST_DDR1_MSCH 74 +#define SRST_DDRCFG1_MSCH 75 +#define SRST_DDR1 76 +#define SRST_DDRPHY1 77 +#define SRST_DDR_CIC 78 +#define SRST_PVTM_DDR 79 + +/* cru_softrst_con5 */ +#define SRST_A_VCODEC_NOC 80 +#define SRST_A_VCODEC 81 +#define SRST_H_VCODEC_NOC 82 +#define SRST_H_VCODEC 83 +#define SRST_A_VDU_NOC 88 +#define SRST_A_VDU 89 +#define SRST_H_VDU_NOC 90 +#define SRST_H_VDU 91 +#define SRST_VDU_CORE 92 +#define SRST_VDU_CA 93 + +/* cru_softrst_con6 */ +#define SRST_A_IEP_NOC 96 +#define SRST_A_VOP_IEP 97 +#define SRST_A_IEP 98 +#define SRST_H_IEP_NOC 99 +#define SRST_H_IEP 100 +#define SRST_A_RGA_NOC 102 +#define SRST_A_RGA 103 +#define SRST_H_RGA_NOC 104 +#define SRST_H_RGA 105 +#define SRST_RGA_CORE 106 +#define SRST_EMMC_NOC 108 +#define SRST_EMMC 109 +#define SRST_EMMC_GRF 110 + +/* cru_softrst_con7 */ +#define SRST_A_PERIHP_NOC 112 +#define SRST_P_PERIHP_GRF 113 +#define SRST_H_PERIHP_NOC 114 +#define SRST_USBHOST0 115 +#define SRST_HOSTC0_AUX 116 +#define SRST_HOST0_ARB 117 +#define SRST_USBHOST1 118 +#define SRST_HOSTC1_AUX 119 +#define SRST_HOST1_ARB 120 +#define SRST_SDIO0 121 +#define SRST_SDMMC 122 +#define SRST_HSIC 123 +#define SRST_HSIC_AUX 124 +#define SRST_AHB1TOM 125 +#define SRST_P_PERIHP_NOC 126 +#define SRST_HSICPHY 127 + +/* cru_softrst_con8 */ +#define SRST_A_PCIE 128 +#define SRST_P_PCIE 129 +#define SRST_PCIE_CORE 130 +#define SRST_PCIE_MGMT 131 +#define SRST_PCIE_MGMT_STICKY 132 +#define SRST_PCIE_PIPE 133 +#define SRST_PCIE_PM 134 +#define SRST_PCIEPHY 135 +#define SRST_A_GMAC_NOC 136 +#define SRST_A_GMAC 137 +#define SRST_P_GMAC_NOC 138 +#define SRST_P_GMAC_GRF 140 +#define SRST_HSICPHY_POR 142 +#define SRST_HSICPHY_UTMI 143 + +/* cru_softrst_con9 */ +#define SRST_USB2PHY0_POR 144 +#define SRST_USB2PHY0_UTMI_PORT0 145 +#define SRST_USB2PHY0_UTMI_PORT1 146 +#define SRST_USB2PHY0_EHCIPHY 147 +#define SRST_UPHY0_PIPE_L00 148 +#define SRST_UPHY0 149 +#define SRST_UPHY0_TCPDPWRUP 150 +#define SRST_USB2PHY1_POR 152 +#define SRST_USB2PHY1_UTMI_PORT0 153 +#define SRST_USB2PHY1_UTMI_PORT1 154 +#define SRST_USB2PHY1_EHCIPHY 155 +#define SRST_UPHY1_PIPE_L00 156 +#define SRST_UPHY1 157 +#define SRST_UPHY1_TCPDPWRUP 158 + +/* cru_softrst_con10 */ +#define SRST_A_PERILP0_NOC 160 +#define SRST_A_DCF 161 +#define SRST_GIC500 162 +#define SRST_DMAC0_PERILP0 163 +#define SRST_DMAC1_PERILP0 164 +#define SRST_TZMA 165 +#define SRST_INTMEM 166 +#define SRST_ADB400_MST0 167 +#define SRST_ADB400_MST1 168 +#define SRST_ADB400_SLV0 169 +#define SRST_ADB400_SLV1 170 +#define SRST_H_PERILP0 171 +#define SRST_H_PERILP0_NOC 172 +#define SRST_ROM 173 +#define SRST_CRYPTO_S 174 +#define SRST_CRYPTO_M 175 + +/* cru_softrst_con11 */ +#define SRST_P_DCF 176 +#define SRST_CM0S_NOC 177 +#define SRST_CM0S 178 +#define SRST_CM0S_DBG 179 +#define SRST_CM0S_PO 180 +#define SRST_CRYPTO 181 +#define SRST_P_PERILP1_SGRF 182 +#define SRST_P_PERILP1_GRF 183 +#define SRST_CRYPTO1_S 184 +#define SRST_CRYPTO1_M 185 +#define SRST_CRYPTO1 186 +#define SRST_GIC_NOC 188 +#define SRST_SD_NOC 189 +#define SRST_SDIOAUDIO_BRG 190 + +/* cru_softrst_con12 */ +#define SRST_H_PERILP1 192 +#define SRST_H_PERILP1_NOC 193 +#define SRST_H_I2S0_8CH 194 +#define SRST_H_I2S1_8CH 195 +#define SRST_H_I2S2_8CH 196 +#define SRST_H_SPDIF_8CH 197 +#define SRST_P_PERILP1_NOC 198 +#define SRST_P_EFUSE_1024 199 +#define SRST_P_EFUSE_1024S 200 +#define SRST_P_I2C0 201 +#define SRST_P_I2C1 202 +#define SRST_P_I2C2 203 +#define SRST_P_I2C3 204 +#define SRST_P_I2C4 205 +#define SRST_P_I2C5 206 +#define SRST_P_MAILBOX0 207 + +/* cru_softrst_con13 */ +#define SRST_P_UART0 208 +#define SRST_P_UART1 209 +#define SRST_P_UART2 210 +#define SRST_P_UART3 211 +#define SRST_P_SARADC 212 +#define SRST_P_TSADC 213 +#define SRST_P_SPI0 214 +#define SRST_P_SPI1 215 +#define SRST_P_SPI2 216 +#define SRST_P_SPI4 217 +#define SRST_P_SPI5 218 +#define SRST_SPI0 219 +#define SRST_SPI1 220 +#define SRST_SPI2 221 +#define SRST_SPI4 222 +#define SRST_SPI5 223 + +/* cru_softrst_con14 */ +#define SRST_I2S0_8CH 224 +#define SRST_I2S1_8CH 225 +#define SRST_I2S2_8CH 226 +#define SRST_SPDIF_8CH 227 +#define SRST_UART0 228 +#define SRST_UART1 229 +#define SRST_UART2 230 +#define SRST_UART3 231 +#define SRST_TSADC 232 +#define SRST_I2C0 233 +#define SRST_I2C1 234 +#define SRST_I2C2 235 +#define SRST_I2C3 236 +#define SRST_I2C4 237 +#define SRST_I2C5 238 +#define SRST_SDIOAUDIO_NOC 239 + +/* cru_softrst_con15 */ +#define SRST_A_VIO_NOC 240 +#define SRST_A_HDCP_NOC 241 +#define SRST_A_HDCP 242 +#define SRST_H_HDCP_NOC 243 +#define SRST_H_HDCP 244 +#define SRST_P_HDCP_NOC 245 +#define SRST_P_HDCP 246 +#define SRST_P_HDMI_CTRL 247 +#define SRST_P_DP_CTRL 248 +#define SRST_S_DP_CTRL 249 +#define SRST_C_DP_CTRL 250 +#define SRST_P_MIPI_DSI0 251 +#define SRST_P_MIPI_DSI1 252 +#define SRST_DP_CORE 253 +#define SRST_DP_I2S 254 + +/* cru_softrst_con16 */ +#define SRST_GASKET 256 +#define SRST_VIO_GRF 258 +#define SRST_DPTX_SPDIF_REC 259 +#define SRST_HDMI_CTRL 260 +#define SRST_HDCP_CTRL 261 +#define SRST_A_ISP0_NOC 262 +#define SRST_A_ISP1_NOC 263 +#define SRST_H_ISP0_NOC 266 +#define SRST_H_ISP1_NOC 267 +#define SRST_H_ISP0 268 +#define SRST_H_ISP1 269 +#define SRST_ISP0 270 +#define SRST_ISP1 271 + +/* cru_softrst_con17 */ +#define SRST_A_VOP0_NOC 272 +#define SRST_A_VOP1_NOC 273 +#define SRST_A_VOP0 274 +#define SRST_A_VOP1 275 +#define SRST_H_VOP0_NOC 276 +#define SRST_H_VOP1_NOC 277 +#define SRST_H_VOP0 278 +#define SRST_H_VOP1 279 +#define SRST_D_VOP0 280 +#define SRST_D_VOP1 281 +#define SRST_VOP0_PWM 282 +#define SRST_VOP1_PWM 283 +#define SRST_P_EDP_NOC 284 +#define SRST_P_EDP_CTRL 285 + +/* cru_softrst_con18 */ +#define SRST_A_GPU 288 +#define SRST_A_GPU_NOC 289 +#define SRST_A_GPU_GRF 290 +#define SRST_PVTM_GPU 291 +#define SRST_A_USB3_NOC 292 +#define SRST_A_USB3_OTG0 293 +#define SRST_A_USB3_OTG1 294 +#define SRST_A_USB3_GRF 295 +#define SRST_PMU 296 + +/* cru_softrst_con19 */ +#define SRST_P_TIMER0_5 304 +#define SRST_TIMER0 305 +#define SRST_TIMER1 306 +#define SRST_TIMER2 307 +#define SRST_TIMER3 308 +#define SRST_TIMER4 309 +#define SRST_TIMER5 310 +#define SRST_P_TIMER6_11 311 +#define SRST_TIMER6 312 +#define SRST_TIMER7 313 +#define SRST_TIMER8 314 +#define SRST_TIMER9 315 +#define SRST_TIMER10 316 +#define SRST_TIMER11 317 +#define SRST_P_INTR_ARB_PMU 318 +#define SRST_P_ALIVE_SGRF 319 + +/* cru_softrst_con20 */ +#define SRST_P_GPIO2 320 +#define SRST_P_GPIO3 321 +#define SRST_P_GPIO4 322 +#define SRST_P_GRF 323 +#define SRST_P_ALIVE_NOC 324 +#define SRST_P_WDT0 325 +#define SRST_P_WDT1 326 +#define SRST_P_INTR_ARB 327 +#define SRST_P_UPHY0_DPTX 328 +#define SRST_P_UPHY0_APB 330 +#define SRST_P_UPHY0_TCPHY 332 +#define SRST_P_UPHY1_TCPHY 333 +#define SRST_P_UPHY0_TCPDCTRL 334 +#define SRST_P_UPHY1_TCPDCTRL 335 + +/* pmu soft-reset indices */ + +/* pmu_cru_softrst_con0 */ +#define SRST_P_NOC 0 +#define SRST_P_INTMEM 1 +#define SRST_H_CM0S 2 +#define SRST_H_CM0S_NOC 3 +#define SRST_DBG_CM0S 4 +#define SRST_PO_CM0S 5 +#define SRST_P_SPI3 6 +#define SRST_SPI3 7 +#define SRST_P_TIMER_0_1 8 +#define SRST_P_TIMER_0 9 +#define SRST_P_TIMER_1 10 +#define SRST_P_UART4 11 +#define SRST_UART4 12 +#define SRST_P_WDT 13 + +/* pmu_cru_softrst_con1 */ +#define SRST_P_I2C6 16 +#define SRST_P_I2C7 17 +#define SRST_P_I2C8 18 +#define SRST_P_MAILBOX 19 +#define SRST_P_RKPWM 20 +#define SRST_P_PMUGRF 21 +#define SRST_P_SGRF 22 +#define SRST_P_GPIO0 23 +#define SRST_P_GPIO1 24 +#define SRST_P_CRU 25 +#define SRST_P_INTR 26 +#define SRST_PVTM 27 +#define SRST_I2C6 28 +#define SRST_I2C7 29 +#define SRST_I2C8 30 + +#endif diff --git a/include/dt-bindings/clock/rk618-cru.h b/include/dt-bindings/clock/rk618-cru.h new file mode 100644 index 000000000000..72ae0aef1378 --- /dev/null +++ b/include/dt-bindings/clock/rk618-cru.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_RK618_CRU_H +#define _DT_BINDINGS_CLK_RK618_CRU_H + +#define LCDC0_CLK 1 +#define LCDC1_CLK 2 +#define VIF_PLLIN_CLK 3 +#define SCALER_PLLIN_CLK 4 +#define VIF_PLL_CLK 5 +#define SCALER_PLL_CLK 6 +#define VIF0_CLK 7 +#define VIF1_CLK 8 +#define SCALER_IN_CLK 9 +#define SCALER_CLK 10 +#define DITHER_CLK 11 +#define HDMI_CLK 12 +#define MIPI_CLK 13 +#define LVDS_CLK 14 +#define LVTTL_CLK 15 +#define RGB_CLK 16 +#define VIF0_PRE_CLK 17 +#define VIF1_PRE_CLK 18 +#define CODEC_CLK 19 + +#endif diff --git a/include/dt-bindings/clock/rk_system_status.h b/include/dt-bindings/clock/rk_system_status.h new file mode 100644 index 000000000000..381447b4fbe0 --- /dev/null +++ b/include/dt-bindings/clock/rk_system_status.h @@ -0,0 +1,38 @@ +/* + * + * Copyright (C) 2011-2014 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ROCKCHIP_SYSTEM_STATUS_H +#define __ROCKCHIP_SYSTEM_STATUS_H + +#define SYS_STATUS_NORMAL (1<<0) +#define SYS_STATUS_SUSPEND (1<<1) +#define SYS_STATUS_IDLE (1<<2) +#define SYS_STATUS_REBOOT (1<<3) +#define SYS_STATUS_VIDEO_4K (1<<4) +#define SYS_STATUS_VIDEO_1080P (1<<5) +#define SYS_STATUS_GPU (1<<6) +#define SYS_STATUS_RGA (1<<7) +#define SYS_STATUS_CIF0 (1<<8) +#define SYS_STATUS_CIF1 (1<<9) +#define SYS_STATUS_LCDC0 (1<<10) +#define SYS_STATUS_LCDC1 (1<<11) +#define SYS_STATUS_BOOST (1<<12) +#define SYS_STATUS_PERFORMANCE (1<<13) +#define SYS_STATUS_ISP (1<<14) +#define SYS_STATUS_HDMI (1<<15) + +#define SYS_STATUS_DUALVIEW (SYS_STATUS_LCDC0|SYS_STATUS_LCDC1) + +#endif diff --git a/include/dt-bindings/clock/rockchip,rk3036.h b/include/dt-bindings/clock/rockchip,rk3036.h new file mode 100644 index 000000000000..019550c7d0c1 --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk3036.h @@ -0,0 +1,155 @@ +#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_RK3036_H +#define _DT_BINDINGS_CLOCK_ROCKCHIP_RK3036_H + +#include "rockchip.h" + +/* pll id */ +#define RK3036_APLL_ID 0 +#define RK3036_DPLL_ID 1 +#define RK3036_GPLL_ID 2 +#define RK3036_END_PLL_ID 3 + +/* reset id */ +#define RK3036_RST_CORE0 0 +#define RK3036_RST_CORE1 1 +#define RK3036_RST_0RES2 2 +#define RK3036_RST_0RES3 3 +#define RK3036_RST_CORE0_DBG 4 +#define RK3036_RST_CORE1_DBG 5 +#define RK3036_RST_0RES6 6 +#define RK3036_RST_0RES7 7 +#define RK3036_RST_CORE0_POR 8 +#define RK3036_RST_CORE1_POR 9 +#define RK3036_RST_0RES10 10 +#define RK3036_RST_0RES11 11 +#define RK3036_RST_L2C 12 +#define RK3036_RST_TOPDBG 13 +#define RK3036_RST_STRC_SYS_A 14 +#define RK3036_RST_PD_CORE_NIU 15 + +#define RK3036_RST_TIMER2 16 +#define RK3036_RST_CPUSYS_H 17 +#define RK3036_RST_1RES2 18 +#define RK3036_RST_AHB2APB_H 19 +#define RK3036_RST_TIMER3 20 +#define RK3036_RST_INTMEM 21 +#define RK3036_RST_ROM 22 +#define RK3036_RST_PERI_NIU 23 +#define RK3036_RST_I2S 24 +#define RK3036_RST_DDR_PLL 25 +#define RK3036_RST_GPU_DLL 26 +#define RK3036_RST_TIMER0 27 +#define RK3036_RST_TIMER1 28 +#define RK3036_RST_CORE_DLL 29 +#define RK3036_RST_EFUSE_P 30 +#define RK3036_RST_ACODEC_P 31 + +#define RK3036_RST_GPIO0 32 +#define RK3036_RST_GPIO1 33 +#define RK3036_RST_GPIO2 34 +#define RK3036_RST_2RES3 35 +#define RK3036_RST_2RES4 36 +#define RK3036_RST_2RES5 37 +#define RK3036_RST_2RES6 38 +#define RK3036_RST_UART0 39 +#define RK3036_RST_UART1 40 +#define RK3036_RST_UART2 41 +#define RK3036_RST_2RES10 42 +#define RK3036_RST_I2C0 43 +#define RK3036_RST_I2C1 44 +#define RK3036_RST_I2C2 45 +#define RK3036_RST_2RES14 46 +#define RK3036_RST_SFC 47 + +#define RK3036_RST_PWM0 48 +#define RK3036_RST_3RES1 49 +#define RK3036_RST_3RES2 50 +#define RK3036_RST_DAP 51 +#define RK3036_RST_DAP_SYS 52 +#define RK3036_RST_3RES5 53 +#define RK3036_RST_3RES6 54 +#define RK3036_RST_GRF 55 +#define RK3036_RST_3RES8 56 +#define RK3036_RST_PERIPHSYS_A 57 +#define RK3036_RST_PERIPHSYS_H 58 +#define RK3036_RST_PERIPHSYS_P 59 +#define RK3036_RST_3RES12 60 +#define RK3036_RST_CPU_PERI 61 +#define RK3036_RST_EMEM_PERI 62 +#define RK3036_RST_USB_PERI 63 + +#define RK3036_RST_DMA2 64 +#define RK3036_RST_4RES1 65 +#define RK3036_RST_MAC 66 +#define RK3036_RST_4RES3 67 +#define RK3036_RST_NANDC 68 +#define RK3036_RST_USBOTG0 69 +#define RK3036_RST_4RES6 70 +#define RK3036_RST_OTGC0 71 +#define RK3036_RST_USBOTG1 72 +#define RK3036_RST_4RES9 73 +#define RK3036_RST_OTGC1 74 +#define RK3036_RST_4RES11 75 +#define RK3036_RST_4RES12 76 +#define RK3036_RST_4RES13 77 +#define RK3036_RST_4RES14 78 +#define RK3036_RST_DDRMSCH 79 + +#define RK3036_RST_5RES0 80 +#define RK3036_RST_MMC0 81 +#define RK3036_RST_SDIO 82 +#define RK3036_RST_EMMC 83 +#define RK3036_RST_SPI0 84 +#define RK3036_RST_5RES5 85 +#define RK3036_RST_WDT 86 +#define RK3036_RST_5RES7 87 +#define RK3036_RST_DDRPHY 88 +#define RK3036_RST_DDRPHY_P 89 +#define RK3036_RST_DDRCTRL 90 +#define RK3036_RST_DDRCTRL_P 91 +#define RK3036_RST_5RES12 92 +#define RK3036_RST_5RES13 93 +#define RK3036_RST_5RES14 94 +#define RK3036_RST_5RES15 95 + +#define RK3036_RST_HDMI_P 96 +#define RK3036_RST_6RES1 97 +#define RK3036_RST_6RES2 98 +#define RK3036_RST_VIO_BUS_H 99 +#define RK3036_RST_6RES4 100 +#define RK3036_RST_6RES5 101 +#define RK3036_RST_6RES6 102 +#define RK3036_RST_UTMI0 103 +#define RK3036_RST_UTMI1 104 +#define RK3036_RST_USBPOR 105 +#define RK3036_RST_6RES10 106 +#define RK3036_RST_6RES11 107 +#define RK3036_RST_6RES12 108 +#define RK3036_RST_6RES13 109 +#define RK3036_RST_6RES14 110 +#define RK3036_RST_6RES15 111 + +#define RK3036_RST_VCODEC_A 112 +#define RK3036_RST_VCODEC_H 113 +#define RK3036_RST_VIO1_A 114 +#define RK3036_RST_HEVC 115 +#define RK3036_RST_VCODEC_NIU_A 116 +#define RK3036_RST_LCDC1_A 117 +#define RK3036_RST_LCDC1_H 118 +#define RK3036_RST_LCDC1_D 119 +#define RK3036_RST_GPU 120 +#define RK3036_RST_7RES9 121 +#define RK3036_RST_GPU_NIU_A 122 +#define RK3036_RST_7RES11 123 +#define RK3036_RST_7RES12 124 +#define RK3036_RST_7RES13 125 +#define RK3036_RST_7RES14 126 +#define RK3036_RST_7RES15 127 + +#define RK3036_RST_8RES0 128 +#define RK3036_RST_8RES1 129 +#define RK3036_RST_8RES2 130 +#define RK3036_RST_DBG_P 131 +/* con8[15:4] is reserved */ + +#endif /* _DT_BINDINGS_CLOCK_ROCKCHIP_RK3036_H */ diff --git a/include/dt-bindings/clock/rockchip,rk312x.h b/include/dt-bindings/clock/rockchip,rk312x.h new file mode 100755 index 000000000000..0af5abca3470 --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk312x.h @@ -0,0 +1,167 @@ +#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_RK3128_H +#define _DT_BINDINGS_CLOCK_ROCKCHIP_RK3128_H + +#include "rockchip.h" + +/* pll id */ +#define RK3128_APLL_ID 0 +#define RK3128_DPLL_ID 1 +#define RK3128_CPLL_ID 2 +#define RK3128_GPLL_ID 3 +#define RK3128_END_PLL_ID 4 + +/* reset id */ +#define RK3128_RST_CORE0_PO 0 +#define RK3128_RST_CORE1_PO 1 +#define RK3128_RST_CORE2_PO 2 +#define RK3128_RST_CORE3_PO 3 +#define RK3128_RST_CORE0 4 +#define RK3128_RST_CORE1 5 +#define RK3128_RST_CORE2 6 +#define RK3128_RST_CORE3 7 +#define RK3128_RST_CORE0_DBG 8 +#define RK3128_RST_CORE1_DBG 9 +#define RK3128_RST_CORE2_DBG 10 +#define RK3128_RST_CORE3_DBG 11 +#define RK3128_RST_TOPDBG 12 +#define RK3128_RST_ACLK_CORE 13 +#define RK3128_RST_STRC_SYS_A 14 +#define RK3128_RST_L2C 15 + +#define RK3128_RST_1RES0 16 +#define RK3128_RST_1RES1 17 +#define RK3128_RST_CPUSYS_H 18 +#define RK3128_RST_AHB2APB_H 19 +#define RK3128_RST_SPDIF 20 +#define RK3128_RST_INTMEM 21 +#define RK3128_RST_ROM 22 +#define RK3128_RST_PERI_NIU 23 +#define RK3128_RST_I2S_2CH 24 +#define RK3128_RST_I2S_8CH 25 +#define RK3128_RST_GPU_PVTM 26 +#define RK3128_RST_FUNC_PVTM 27 +#define RK3128_RST_1RES12 28 +#define RK3128_RST_CORE_PVTM 29 +#define RK3128_RST_EFUSE_P 30 +#define RK3128_RST_ACODEC_P 31 + +#define RK3128_RST_GPIO0 32 +#define RK3128_RST_GPIO1 33 +#define RK3128_RST_GPIO2 34 +#define RK3128_RST_GPIO3 35 +#define RK3128_RST_MIPIPHY 36 +#define RK3128_RST_2RES5 37 +#define RK3128_RST_2RES6 38 +#define RK3128_RST_UART0 39 +#define RK3128_RST_UART1 40 +#define RK3128_RST_UART2 41 +#define RK3128_RST_2RES10 42 +#define RK3128_RST_I2C0 43 +#define RK3128_RST_I2C1 44 +#define RK3128_RST_I2C2 45 +#define RK3128_RST_I2C3 46 +#define RK3128_RST_SFC 47 + +#define RK3128_RST_PWM0 48 +#define RK3128_RST_3RES1 49 +#define RK3128_RST_DAP_P 50 +#define RK3128_RST_DAP 51 +#define RK3128_RST_DAP_SYS 52 +#define RK3128_RST_CRYPTO 53 +#define RK3128_RST_3RES6 54 +#define RK3128_RST_GRF 55 +#define RK3128_RST_GMAC 56 +#define RK3128_RST_PERIPHSYS_A 57 +#define RK3128_RST_PERIPHSYS_H 58 +#define RK3128_RST_PERIPHSYS_P 59 +#define RK3128_RST_SMART_CARD 60 +#define RK3128_RST_CPU_PERI 61 +#define RK3128_RST_EMEM_PERI 62 +#define RK3128_RST_USB_PERI 63 + +#define RK3128_RST_DMA2 64 +#define RK3128_RST_4RES1 65 +#define RK3128_RST_4RES2 66 +#define RK3128_RST_GPS 67 +#define RK3128_RST_NANDC 68 +#define RK3128_RST_USBOTG0 69 +#define RK3128_RST_4RES6 70 +#define RK3128_RST_OTGC0 71 +#define RK3128_RST_USBOTG1 72 +#define RK3128_RST_4RES9 73 +#define RK3128_RST_OTGC1 74 +#define RK3128_RST_4RES11 75 +#define RK3128_RST_4RES12 76 +#define RK3128_RST_4RES13 77 +#define RK3128_RST_4RES14 78 +#define RK3128_RST_DDRMSCH 79 + +#define RK3128_RST_5RES0 80 +#define RK3128_RST_MMC0 81 +#define RK3128_RST_SDIO 82 +#define RK3128_RST_EMMC 83 +#define RK3128_RST_SPI0 84 +#define RK3128_RST_5RES5 85 +#define RK3128_RST_WDT 86 +#define RK3128_RST_SARADC 87 +#define RK3128_RST_DDRPHY 88 +#define RK3128_RST_DDRPHY_P 89 +#define RK3128_RST_DDRCTRL 90 +#define RK3128_RST_DDRCTRL_P 91 +#define RK3128_RST_TSP 92 +#define RK3128_RST_TSP_CLKIN0 93 +#define RK3128_RST_USBHOST0_EHCI 94 +#define RK3128_RST_5RES15 95 + +#define RK3128_RST_HDMI_P 96 +#define RK3128_RST_VIO_ARBI_H 97 +#define RK3128_RST_VIO_A 98 +#define RK3128_RST_VIO_BUS_H 99 +#define RK3128_RST_LCDC0_A 100 +#define RK3128_RST_LCDC0_H 101 +#define RK3128_RST_LCDC0_D 102 +#define RK3128_RST_UTMI0 103 +#define RK3128_RST_UTMI1 104 +#define RK3128_RST_USBPOR 105 +#define RK3128_RST_IEP_A 106 +#define RK3128_RST_IEP_H 107 +#define RK3128_RST_RGA_A 108 +#define RK3128_RST_RGA_H 109 +#define RK3128_RST_CIF0 110 +#define RK3128_RST_PMU 111 + +#define RK3128_RST_VCODEC_A 112 +#define RK3128_RST_VCODEC_H 113 +#define RK3128_RST_VIO1_A 114 +#define RK3128_RST_HEVC 115 +#define RK3128_RST_VCODEC_NIU_A 116 +#define RK3128_RST_PMU_NIU 117 +#define RK3128_RST_7RES6 118 +#define RK3128_RST_LCDC0_S 119 +#define RK3128_RST_GPU 120 +#define RK3128_RST_7RES9 121 +#define RK3128_RST_GPU_NIU_A 122 +#define RK3128_RST_EBC_A 123 +#define RK3128_RST_EBC_H 124 +#define RK3128_RST_7RES13 125 +#define RK3128_RST_7RES14 126 +#define RK3128_RST_7RES15 127 + +#define RK3128_RST_CORE_DBG 128 +#define RK3128_RST_DBG_P 129 +#define RK3128_RST_TIMER0 130 +#define RK3128_RST_TIMER1 131 +#define RK3128_RST_TIMER2 132 +#define RK3128_RST_TIMER3 133 +#define RK3128_RST_TIMER4 134 +#define RK3128_RST_TIMER5 135 +#define RK3128_RST_VIO_H2P 136 +#define RK3128_RST_VIO_MIPI_DSI 137 +#define RK3128_RST_8RES10 138 +#define RK3128_RST_8RES11 139 +#define RK3128_RST_8RES12 140 +#define RK3128_RST_8RES13 141 +#define RK3128_RST_8RES14 142 +#define RK3128_RST_8RES15 143 + +#endif /* _DT_BINDINGS_CLOCK_ROCKCHIP_RK3128_H */ diff --git a/include/dt-bindings/clock/rockchip,rk3188.h b/include/dt-bindings/clock/rockchip,rk3188.h new file mode 100644 index 000000000000..b8c57e1cfed8 --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk3188.h @@ -0,0 +1,13 @@ +#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_RK3188_H +#define _DT_BINDINGS_CLOCK_ROCKCHIP_RK3188_H + +#include "rockchip.h" + +/* pll id */ +#define RK3188_APLL_ID 0 +#define RK3188_DPLL_ID 1 +#define RK3188_CPLL_ID 2 +#define RK3188_GPLL_ID 3 +#define RK3188_END_PLL_ID 4 + +#endif /* _DT_BINDINGS_CLOCK_ROCKCHIP_RK3188_H */ diff --git a/include/dt-bindings/clock/rockchip,rk3228.h b/include/dt-bindings/clock/rockchip,rk3228.h new file mode 100644 index 000000000000..b86e44536722 --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk3228.h @@ -0,0 +1,167 @@ +#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_RK3228_H +#define _DT_BINDINGS_CLOCK_ROCKCHIP_RK3228_H + +#include "rockchip.h" + +/* pll id */ +#define RK3228_APLL_ID 0 +#define RK3228_DPLL_ID 1 +#define RK3228_CPLL_ID 2 +#define RK3228_GPLL_ID 3 +#define RK3228_END_PLL_ID 4 + +/* reset id */ +#define RK3228_RST_CORE0_PO 0 +#define RK3228_RST_CORE1_PO 1 +#define RK3228_RST_CORE2_PO 2 +#define RK3228_RST_CORE3_PO 3 +#define RK3228_RST_CORE0 4 +#define RK3228_RST_CORE1 5 +#define RK3228_RST_CORE2 6 +#define RK3228_RST_CORE3 7 +#define RK3228_RST_CORE0_DBG 8 +#define RK3228_RST_CORE1_DBG 9 +#define RK3228_RST_CORE2_DBG 10 +#define RK3228_RST_CORE3_DBG 11 +#define RK3228_RST_TOPDBG 12 +#define RK3228_RST_ACLK_CORE 13 +#define RK3228_RST_NOC_A 14 +#define RK3228_RST_L2C 15 + +#define RK3228_RST_1RES0 16 +#define RK3228_RST_1RES1 17 +#define RK3228_RST_CPUSYS_H 18 +#define RK3228_RST_BUSSYS_H 19 +#define RK3228_RST_SPDIF 20 +#define RK3228_RST_INTMEM 21 +#define RK3228_RST_ROM 22 +#define RK3228_RST_OTG_ADP 23 +#define RK3228_RST_I2S0 24 +#define RK3228_RST_I2S1 25 +#define RK3228_RST_I2S2 26 +#define RK3228_RST_ACODEC_P 27 +#define RK3228_RST_DFIMON 28 +#define RK3228_RST_MSCH 29 +#define RK3228_RST_EFUSE_1024 30 +#define RK3228_RST_EFUSE_256 31 + +#define RK3228_RST_GPIO0 32 +#define RK3228_RST_GPIO1 33 +#define RK3228_RST_GPIO2 34 +#define RK3228_RST_GPIO3 35 +#define RK3228_RST_PERIPH_NOC_A 36 +#define RK3228_RST_PERIPH_NOC_H 37 +#define RK3228_RST_PERIPH_NOC_P 38 +#define RK3228_RST_UART0 39 +#define RK3228_RST_UART1 40 +#define RK3228_RST_UART2 41 +#define RK3228_RST_PHYNOC 42 +#define RK3228_RST_I2C0 43 +#define RK3228_RST_I2C1 44 +#define RK3228_RST_I2C2 45 +#define RK3228_RST_I2C3 46 +#define RK3228_RST_2RES15 47 + +#define RK3228_RST_PWM0 48 +#define RK3228_RST_A53_GIC 49 +#define RK3228_RST_3RES2 50 +#define RK3228_RST_DAP 51 +#define RK3228_RST_DAP_NOC 52 +#define RK3228_RST_CRYPTO 53 +#define RK3228_RST_SGRF 54 +#define RK3228_RST_GRF 55 +#define RK3228_RST_GMAC 56 +#define RK3228_RST_3RES9 57 +#define RK3228_RST_PERIPHSYS_A 58 +#define RK3228_RST_3RES11 59 +#define RK3228_RST_3RES12 60 +#define RK3228_RST_3RES13 61 +#define RK3228_RST_3RES14 62 +#define RK3228_RST_MACPHY 63 + +#define RK3228_RST_4RES0 64 +#define RK3228_RST_4RES1 65 +#define RK3228_RST_4RES2 66 +#define RK3228_RST_4RES3 67 +#define RK3228_RST_NANDC 68 +#define RK3228_RST_USBOTG0 69 +#define RK3228_RST_OTGC0 70 +#define RK3228_RST_USBHOST0 71 +#define RK3228_RST_HOST_CTRL0 72 +#define RK3228_RST_USBHOST1 73 +#define RK3228_RST_HOST_CTRL1 74 +#define RK3228_RST_USBHOST2 75 +#define RK3228_RST_HOST_CTRL2 76 +#define RK3228_RST_USBPOR0 77 +#define RK3228_RST_USBPOR1 78 +#define RK3228_RST_DDRMSCH 79 + +#define RK3228_RST_SMART_CARD 80 +#define RK3228_RST_SDMMC0 81 +#define RK3228_RST_SDIO 82 +#define RK3228_RST_EMMC 83 +#define RK3228_RST_SPI0 84 +#define RK3228_RST_TSP_H 85 +#define RK3228_RST_TSP 86 +#define RK3228_RST_TSADC 87 +#define RK3228_RST_DDRPHY 88 +#define RK3228_RST_DDRPHY_P 89 +#define RK3228_RST_DDRCTRL 90 +#define RK3228_RST_DDRCTRL_P 91 +#define RK3228_RST_HOST0_ECHI 92 +#define RK3228_RST_HOST1_ECHI 93 +#define RK3228_RST_HOST2_ECHI 94 +#define RK3228_RST_VOP 95 + +#define RK3228_RST_HDMI_P 96 +#define RK3228_RST_VIO_ARBI_H 97 +#define RK3228_RST_IEP_NOC_A 98 +#define RK3228_RST_VIO_NOC_H 99 +#define RK3228_RST_VOP_A 100 +#define RK3228_RST_VOP_H 101 +#define RK3228_RST_VOP_D 102 +#define RK3228_RST_UTMI0 103 +#define RK3228_RST_UTMI1 104 +#define RK3228_RST_UTMI2 105 +#define RK3228_RST_UTMI3 106 +#define RK3228_RST_RGA 107 +#define RK3228_RST_RGA_NOC_A 108 +#define RK3228_RST_RGA_A 109 +#define RK3228_RST_RGA_H 110 +#define RK3228_RST_HDCP_A 111 + +#define RK3228_RST_VPU_A 112 +#define RK3228_RST_VPU_H 113 +#define RK3228_RST_7RES2 114 +#define RK3228_RST_7RES3 115 +#define RK3228_RST_VPU_NOC_A 116 +#define RK3228_RST_VPU_NOC_H 117 +#define RK3228_RST_RKVDEC_A 118 +#define RK3228_RST_RKVDEC_NOC_A 119 +#define RK3228_RST_RKVDEC_H 120 +#define RK3228_RST_RKVDEC_NOC_H 121 +#define RK3228_RST_RKVDEC_CORE 122 +#define RK3228_RST_RKVDEC_CABAC 123 +#define RK3228_RST_IEP_A 124 +#define RK3228_RST_IEP_H 125 +#define RK3228_RST_GPU_A 126 +#define RK3228_RST_GPU_NOC_A 127 + +#define RK3228_RST_CORE_DBG 128 +#define RK3228_RST_DBG_P 129 +#define RK3228_RST_TIMER0 130 +#define RK3228_RST_TIMER1 131 +#define RK3228_RST_TIMER2 132 +#define RK3228_RST_TIMER3 133 +#define RK3228_RST_TIMER4 134 +#define RK3228_RST_TIMER5 135 +#define RK3228_RST_VIO_H2P 136 +#define RK3228_RST_8RES9 137 +#define RK3228_RST_8RES10 138 +#define RK3228_RST_HDMIPHY 139 +#define RK3228_RST_VDAC 140 +#define RK3228_RST_TIMER_6CH 141 +#define RK3228_RST_8RES14 142 +#define RK3228_RST_8RES15 143 + +#endif /* _DT_BINDINGS_CLOCK_ROCKCHIP_RK3228_H */ diff --git a/include/dt-bindings/clock/rockchip,rk3288.h b/include/dt-bindings/clock/rockchip,rk3288.h new file mode 100644 index 000000000000..1a2803c4f168 --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk3288.h @@ -0,0 +1,220 @@ +#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_RK3288_H +#define _DT_BINDINGS_CLOCK_ROCKCHIP_RK3288_H + +#include "rockchip.h" + +/* pll id */ +#define RK3288_APLL_ID 0 +#define RK3288_DPLL_ID 1 +#define RK3288_CPLL_ID 2 +#define RK3288_GPLL_ID 3 +#define RK3288_NPLL_ID 4 +#define RK3288_END_PLL_ID 5 + +/* reset id */ +#define RK3288_SOFT_RST_CORE0 0 +#define RK3288_SOFT_RST_CORE1 1 +#define RK3288_SOFT_RST_CORE2 2 +#define RK3288_SOFT_RST_CORE3 3 +#define RK3288_SOFT_RST_CORE0_PO 4 +#define RK3288_SOFT_RST_CORE1_PO 5 +#define RK3288_SOFT_RST_CORE2_PO 6 +#define RK3288_SOFT_RST_CORE3_PO 7 +#define RK3288_SOFT_RST_PD_CORE_STR_SYS_A 8 +#define RK3288_SOFT_RST_PD_BUS_STR_SYS_A 9 +#define RK3288_SOFT_RST_L2C 10 +#define RK3288_SOFT_RST_TOPDBG 11 +#define RK3288_SOFT_RST_CORE0_DBG 12 +#define RK3288_SOFT_RST_CORE1_DBG 13 +#define RK3288_SOFT_RST_CORE2_DBG 14 +#define RK3288_SOFT_RST_CORE3_DBG 15 + +#define RK3288_SOFT_RST_PD_BUS_AHB_ARBITOR 16 +#define RK3288_SOFT_RST_EFUSE_256BIT_P 17 +#define RK3288_SOFT_RST_DMA1 18 +#define RK3288_SOFT_RST_INTMEM 19 +#define RK3288_SOFT_RST_ROM 20 +#define RK3288_SOFT_RST_SPDIF_8CH 21 +#define RK3288_SOFT_RST_TIMER_P 22 +#define RK3288_SOFT_RST_I2S 23 +#define RK3288_SOFT_RST_SPDIF 24 +#define RK3288_SOFT_RST_TIMER0 25 +#define RK3288_SOFT_RST_TIMER1 26 +#define RK3288_SOFT_RST_TIMER2 27 +#define RK3288_SOFT_RST_TIMER3 28 +#define RK3288_SOFT_RST_TIMER4 29 +#define RK3288_SOFT_RST_TIMER5 30 +#define RK3288_SOFT_RST_EFUSE_P 31 + +#define RK3288_SOFT_RST_GPIO0 32 +#define RK3288_SOFT_RST_GPIO1 33 +#define RK3288_SOFT_RST_GPIO2 34 +#define RK3288_SOFT_RST_GPIO3 35 +#define RK3288_SOFT_RST_GPIO4 36 +#define RK3288_SOFT_RST_GPIO5 37 +#define RK3288_SOFT_RST_GPIO6 38 +#define RK3288_SOFT_RST_GPIO7 39 +#define RK3288_SOFT_RST_GPIO8 40 +#define RK3288_SOFT_RST_2RES9 41 +#define RK3288_SOFT_RST_I2C0 42 +#define RK3288_SOFT_RST_I2C1 43 +#define RK3288_SOFT_RST_I2C2 44 +#define RK3288_SOFT_RST_I2C3 45 +#define RK3288_SOFT_RST_I2C4 46 +#define RK3288_SOFT_RST_I2C5 47 + +#define RK3288_SOFT_RST_DW_PWM 48 +#define RK3288_SOFT_RST_MMC_PERI 49 +#define RK3288_SOFT_RST_PERIPH_MMU 50 +#define RK3288_SOFT_RST_DAP 51 +#define RK3288_SOFT_RST_DAP_SYS 52 +#define RK3288_SOFT_RST_TPIU_AT 53 +#define RK3288_SOFT_RST_PMU_P 54 +#define RK3288_SOFT_RST_GRF 55 +#define RK3288_SOFT_RST_PMU 56 +#define RK3288_SOFT_RST_PERIPHSYS_A 57 +#define RK3288_SOFT_RST_PERIPHSYS_H 58 +#define RK3288_SOFT_RST_PERIPHSYS_P 59 +#define RK3288_SOFT_RST_PERIPH_NIU 60 +#define RK3288_SOFT_RST_PD_PERI_AHB_ARBITOR 61 +#define RK3288_SOFT_RST_EMEM_PERI 62 +#define RK3288_SOFT_RST_USB_PERI 63 + +#define RK3288_SOFT_RST_DMA2 64 +#define RK3288_SOFT_RST_4RES1 65 +#define RK3288_SOFT_RST_MAC 66 +#define RK3288_SOFT_RST_GPS 67 +#define RK3288_SOFT_RST_4RES4 68 +#define RK3288_SOFT_RST_RK_PWM 69 +#define RK3288_SOFT_RST_4RES6 70 +#define RK3288_SOFT_RST_CCP 71 +#define RK3288_SOFT_RST_USB_HOST0 72 +#define RK3288_SOFT_RST_EHCI1 73 +#define RK3288_SOFT_RST_EHCI1_AUX 74 +#define RK3288_SOFT_RST_EHCI1PHY 75 +#define RK3288_SOFT_RST_HSADC 76 +#define RK3288_SOFT_RST_NANDC0 77 +#define RK3288_SOFT_RST_NANDC1 78 +#define RK3288_SOFT_RST_4RES15 79 + +#define RK3288_SOFT_RST_TZPC 80 +#define RK3288_SOFT_RST_5RES1 81 +#define RK3288_SOFT_RST_5RES2 82 +#define RK3288_SOFT_RST_SPI0 83 +#define RK3288_SOFT_RST_SPI1 84 +#define RK3288_SOFT_RST_SPI2 85 +#define RK3288_SOFT_RST_5RES6 86 +#define RK3288_SOFT_RST_SARADC 87 +#define RK3288_SOFT_RST_PD_ALIVE_NIU_P 88 +#define RK3288_SOFT_RST_PD_PMU_INTMEM_P 89 +#define RK3288_SOFT_RST_PD_PMU_NIU_P 90 +#define RK3288_SOFT_RST_SECURITY_GRF_P 91 +#define RK3288_SOFT_RST_5RES12 92 +#define RK3288_SOFT_RST_5RES13 93 +#define RK3288_SOFT_RST_5RES14 94 +#define RK3288_SOFT_RST_5RES15 95 + +#define RK3288_SOFT_RST_VIO_ARBI_H 96 +#define RK3288_SOFT_RST_RGA_NIU_A 97 +#define RK3288_SOFT_RST_VIO0_NIU_A 98 +#define RK3288_SOFT_RST_VIO_NIU_H 99 +#define RK3288_SOFT_RST_LCDC0_A 100 +#define RK3288_SOFT_RST_LCDC0_H 101 +#define RK3288_SOFT_RST_LCDC0_D 102 +#define RK3288_SOFT_RST_VIO1_NIU_A 103 +#define RK3288_SOFT_RST_VIP 104 +#define RK3288_SOFT_RST_RGA_CORE 105 +#define RK3288_SOFT_RST_IEP_A 106 +#define RK3288_SOFT_RST_IEP_H 107 +#define RK3288_SOFT_RST_RGA_A 108 +#define RK3288_SOFT_RST_RGA_H 109 +#define RK3288_SOFT_RST_ISP 110 +#define RK3288_SOFT_RST_EDP 111 + +#define RK3288_SOFT_RST_VCODEC_A 112 +#define RK3288_SOFT_RST_VCODEC_H 113 +#define RK3288_SOFT_RST_VIO_H2P_H 114 +#define RK3288_SOFT_RST_MIPIDSI0_P 115 +#define RK3288_SOFT_RST_MIPIDSI1_P 116 +#define RK3288_SOFT_RST_MIPICSI_P 117 +#define RK3288_SOFT_RST_LVDS_PHY_P 118 +#define RK3288_SOFT_RST_LVDS_CON 119 +#define RK3288_SOFT_RST_GPU 120 +#define RK3288_SOFT_RST_HDMI 121 +#define RK3288_SOFT_RST_7RES10 122 +#define RK3288_SOFT_RST_7RES11 123 +#define RK3288_SOFT_RST_CORE_PVTM 124 +#define RK3288_SOFT_RST_GPU_PVTM 125 +#define RK3288_SOFT_RST_7RES14 126 +#define RK3288_SOFT_RST_7RES15 127 + +#define RK3288_SOFT_RST_MMC0 128 +#define RK3288_SOFT_RST_SDIO0 129 +#define RK3288_SOFT_RST_SDIO1 130 +#define RK3288_SOFT_RST_EMMC 131 +#define RK3288_SOFT_RST_USBOTG_H 132 +#define RK3288_SOFT_RST_USBOTGPHY 133 +#define RK3288_SOFT_RST_USBOTGC 134 +#define RK3288_SOFT_RST_USBHOST0_H 135 +#define RK3288_SOFT_RST_USBHOST0PHY 136 +#define RK3288_SOFT_RST_USBHOST0C 137 +#define RK3288_SOFT_RST_USBHOST1_H 138 +#define RK3288_SOFT_RST_USBHOST1PHY 139 +#define RK3288_SOFT_RST_USBHOST1C 140 +#define RK3288_SOFT_RST_USB_ADP 141 +#define RK3288_SOFT_RST_ACC_EFUSE 142 +#define RK3288_SOFT_RST_8RES15 143 + +#define RK3288_SOFT_RST_CORESIGHT 144 +#define RK3288_SOFT_RST_PD_CORE_AHB_NOC 145 +#define RK3288_SOFT_RST_PD_CORE_APB_NOC 146 +#define RK3288_SOFT_RST_PD_CORE_MP_AXI 147 +#define RK3288_SOFT_RST_GIC 148 +#define RK3288_SOFT_RST_LCDCPWM0 149 +#define RK3288_SOFT_RST_LCDCPWM1 150 +#define RK3288_SOFT_RST_VIO0_H2P_BRG 151 +#define RK3288_SOFT_RST_VIO1_H2P_BRG 152 +#define RK3288_SOFT_RST_RGA_H2P_BRG 153 +#define RK3288_SOFT_RST_HEVC 154 +#define RK3288_SOFT_RST_9RES11 155 +#define RK3288_SOFT_RST_9RES12 156 +#define RK3288_SOFT_RST_9RES13 157 +#define RK3288_SOFT_RST_9RES14 158 +#define RK3288_SOFT_RST_TSADC_P 159 + +#define RK3288_SOFT_RST_DDRPHY0 160 +#define RK3288_SOFT_RST_DDRPHY0_P 161 +#define RK3288_SOFT_RST_DDRCTRL0 162 +#define RK3288_SOFT_RST_DDRCTRL0_P 163 +#define RK3288_SOFT_RST_DDRPHY0_CTL 164 +#define RK3288_SOFT_RST_DDRPHY1 165 +#define RK3288_SOFT_RST_DDRPHY1_P 166 +#define RK3288_SOFT_RST_DDRCTRL1 167 +#define RK3288_SOFT_RST_DDRCTRL1_P 168 +#define RK3288_SOFT_RST_DDRPHY1_CTL 169 +#define RK3288_SOFT_RST_DDRMSCH0 170 +#define RK3288_SOFT_RST_DDRMSCH1 171 +#define RK3288_SOFT_RST_10RES12 172 +#define RK3288_SOFT_RST_10RES13 173 +#define RK3288_SOFT_RST_CRYPTO 174 +#define RK3288_SOFT_RST_C2C_HOST 175 + +#define RK3288_SOFT_RST_LCDC1_A 176 +#define RK3288_SOFT_RST_LCDC1_H 177 +#define RK3288_SOFT_RST_LCDC1_D 178 +#define RK3288_SOFT_RST_UART0 179 +#define RK3288_SOFT_RST_UART1 180 +#define RK3288_SOFT_RST_UART2 181 +#define RK3288_SOFT_RST_UART3 182 +#define RK3288_SOFT_RST_UART4 183 +#define RK3288_SOFT_RST_11RES8 184 +#define RK3288_SOFT_RST_11RES9 185 +#define RK3288_SOFT_RST_SIMC 186 +#define RK3288_SOFT_RST_PS2C 187 +#define RK3288_SOFT_RST_TSP 188 +#define RK3288_SOFT_RST_TSP_CLKIN0 189 +#define RK3288_SOFT_RST_TSP_CLKIN1 190 +#define RK3288_SOFT_RST_TSP_27M 191 + + +#endif /* _DT_BINDINGS_CLOCK_ROCKCHIP_RK3288_H */ diff --git a/include/dt-bindings/clock/rockchip,rk3368.h b/include/dt-bindings/clock/rockchip,rk3368.h new file mode 100644 index 000000000000..76630794b4d9 --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk3368.h @@ -0,0 +1,263 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_RK3368_H +#define _DT_BINDINGS_CLOCK_ROCKCHIP_RK3368_H + +#include "rockchip.h" + +/* reset id */ +#define RK3368_SRST_CORE_B_0_SC 0 +#define RK3368_SRST_CORE_B_1 1 +#define RK3368_SRST_CORE_B_2 2 +#define RK3368_SRST_CORE_B_3 3 +#define RK3368_SRST_CORE_B_PO0_SC 4 +#define RK3368_SRST_CORE_B_PO1 5 +#define RK3368_SRST_CORE_B_PO2 6 +#define RK3368_SRST_CORE_B_PO3 7 +#define RK3368_SRST_L2_B_SC 8 +#define RK3368_SRST_ADB_B_SC 9 +#define RK3368_SRST_PD_CORE_B_NIU 10 +#define RK3368_SRST_STRC_SYS_A_SC 11 +#define RK3368_SRST_0RES12 12 +#define RK3368_SRST_0RES13 13 +#define RK3368_SRST_SOCDBG_B 14 +#define RK3368_SRST_CORE_B_DBG 15 + +#define RK3368_SRST_1RES0 16 +#define RK3368_SRST_1RES1 17 +#define RK3368_SRST_DMA1 18 +#define RK3368_SRST_INTMEM 19 +#define RK3368_SRST_ROM 20 +#define RK3368_SRST_SPDIF_8CH 21 +#define RK3368_SRST_1RES6 22 +#define RK3368_SRST_I2S 23 +#define RK3368_SRST_MAILBOX 24 +#define RK3368_SRST_I2S_2CH 25 +#define RK3368_SRST_EFUSE_256_P 26 +#define RK3368_SRST_1RES11 27 +#define RK3368_SRST_MCU_SYS 28 +#define RK3368_SRST_MCU_PO 29 +#define RK3368_SRST_MCU_NOC_H 30 +#define RK3368_SRST_EFUSE_P 31 + +#define RK3368_SRST_GPIO0 32 +#define RK3368_SRST_GPIO1 33 +#define RK3368_SRST_GPIO2 34 +#define RK3368_SRST_GPIO3 35 +#define RK3368_SRST_GPIO4 36 +#define RK3368_SRST_2RES5 37 +#define RK3368_SRST_2RES6 38 +#define RK3368_SRST_2RES7 39 +#define RK3368_SRST_2RES8 40 +#define RK3368_SRST_PMUGRF_P 41 +#define RK3368_SRST_I2C0 42 +#define RK3368_SRST_I2C1 43 +#define RK3368_SRST_I2C2 44 +#define RK3368_SRST_I2C3 45 +#define RK3368_SRST_I2C4 46 +#define RK3368_SRST_I2C5 47 + +#define RK3368_SRST_DW_PWM 48 +#define RK3368_SRST_MMC_PERI 49 +#define RK3368_SRST_PERIPH_MMU 50 +#define RK3368_SRST_3RES3 51 +#define RK3368_SRST_3RES4 52 +#define RK3368_SRST_3RES5 53 +#define RK3368_SRST_3RES6 54 +#define RK3368_SRST_GRF 55 +#define RK3368_SRST_PMU 56 +#define RK3368_SRST_PERIPH_SYS_A 57 +#define RK3368_SRST_PERIPH_SYS_H 58 +#define RK3368_SRST_PERIPH_SYS_P 59 +#define RK3368_SRST_PERIPH_NIU 60 +#define RK3368_SRST_PD_PERI_AHB_ARBITOR 61 +#define RK3368_SRST_EMEM_PERI 62 +#define RK3368_SRST_USB_PERI 63 + +#define RK3368_SRST_DMA2 64 +#define RK3368_SRST_4RES1 65 +#define RK3368_SRST_MAC 66 +#define RK3368_SRST_GPS 67 +#define RK3368_SRST_4RES4 68 +#define RK3368_SRST_RK_PWM 69 +#define RK3368_SRST_4RES6 70 +#define RK3368_SRST_4RES7 71 +#define RK3368_SRST_HOST0_H 72 +#define RK3368_SRST_EHCI1 73 +#define RK3368_SRST_EHCI1_AUX 74 +#define RK3368_SRST_EHCI1PHY 75 +#define RK3368_SRST_HSADC_H 76 +#define RK3368_SRST_NANDC0 77 +#define RK3368_SRST_4RES14 78 +#define RK3368_SRST_SFC 79 + +#define RK3368_SRST_5RES0 80 +#define RK3368_SRST_5RES1 81 +#define RK3368_SRST_5RES2 82 +#define RK3368_SRST_SPI0 83 +#define RK3368_SRST_SPI1 84 +#define RK3368_SRST_SPI2 85 +#define RK3368_SRST_5RES6 86 +#define RK3368_SRST_SARADC 87 +#define RK3368_SRST_PD_ALIVE_NIU_P 88 +#define RK3368_SRST_PD_PMU_INTMEM_P 89 +#define RK3368_SRST_PD_PMU_NIU_P 90 +#define RK3368_SRST_SGRF_P 91 +#define RK3368_SRST_5RES12 92 +#define RK3368_SRST_5RES13 93 +#define RK3368_SRST_5RES14 94 +#define RK3368_SRST_5RES15 95 + +#define RK3368_SRST_VIO_ARBI_H 96 +#define RK3368_SRST_RGA_NIU_A 97 +#define RK3368_SRST_VIO0_NIU_A 98 +#define RK3368_SRST_VIO0_BUS_H 99 +#define RK3368_SRST_LCDC0_A 100 +#define RK3368_SRST_LCDC0_H 101 +#define RK3368_SRST_LCDC0_D 102 +#define RK3368_SRST_6RES7 103 +#define RK3368_SRST_VIP 104 +#define RK3368_SRST_RGA_CORE 105 +#define RK3368_SRST_IEP_A 106 +#define RK3368_SRST_IEP_H 107 +#define RK3368_SRST_RGA_A 108 +#define RK3368_SRST_RGA_H 109 +#define RK3368_SRST_ISP 110 +#define RK3368_SRST_EDP_24M 111 + +#define RK3368_SRST_VIDEO_A 112 +#define RK3368_SRST_VIDEO_H 113 +#define RK3368_SRST_MIPIDPHYTX_P 114 +#define RK3368_SRST_MIPIDSI0_P 115 +#define RK3368_SRST_MIPIDPHYRX_P 116 +#define RK3368_SRST_MIPICSI_P 117 +#define RK3368_SRST_7RES6 118 +#define RK3368_SRST_7RES7 119 +#define RK3368_SRST_GPU_CORE 120 +#define RK3368_SRST_HDMI 121 +#define RK3368_SRST_EDP_P 122 +#define RK3368_SRST_PMU_PVTM 123 +#define RK3368_SRST_CORE_PVTM 124 +#define RK3368_SRST_GPU_PVTM 125 +#define RK3368_SRST_GPU_SYS_A 126 +#define RK3368_SRST_GPU_MEM_NIU_A 127 + +#define RK3368_SRST_MMC0 128 +#define RK3368_SRST_SDIO0 129 +#define RK3368_SRST_8RES2 130 +#define RK3368_SRST_EMMC 131 +#define RK3368_SRST_USBOTG0_H 132 +#define RK3368_SRST_USBOTGPHY0 133 +#define RK3368_SRST_USBOTGC0 134 +#define RK3368_SRST_USBHOSTC0_H 135 +#define RK3368_SRST_USBOTGPHY1 136 +#define RK3368_SRST_USBHOSTC0 137 +#define RK3368_SRST_USBPHY0_UTMI 138 +#define RK3368_SRST_USBPHY1_UTMI 139 +#define RK3368_SRST_8RES12 140 +#define RK3368_SRST_USB_ADP 141 +#define RK3368_SRST_8RES14 142 +#define RK3368_SRST_8RES15 143 + +#define RK3368_SRST_DBG 144 +#define RK3368_SRST_PD_CORE_AHB_NOC 145 +#define RK3368_SRST_PD_CORE_APB_NOC 146 +#define RK3368_SRST_9RES3 147 +#define RK3368_SRST_GIC 148 +#define RK3368_SRST_LCDCPWM0 149 +#define RK3368_SRST_9RES6 150 +#define RK3368_SRST_9RES7 151 +#define RK3368_SRST_9RES8 152 +#define RK3368_SRST_RGA_H2P_BRG 153 +#define RK3368_SRST_VIDEO 154 +#define RK3368_SRST_9RES11 155 +#define RK3368_SRST_9RES12 156 +#define RK3368_SRST_GPU_CFG_NIU_A 157 +#define RK3368_SRST_9RES14 158 +#define RK3368_SRST_TSADC_P 159 + +#define RK3368_SRST_DDRPHY0 160 +#define RK3368_SRST_DDRPHY0_P 161 +#define RK3368_SRST_DDRCTRL0 162 +#define RK3368_SRST_DDRCTRL0_P 163 +#define RK3368_SRST_10RES4 164 +#define RK3368_SRST_VIDEO_NIU_A 165 +#define RK3368_SRST_10RES6 166 +#define RK3368_SRST_VIDEO_NIU_H 167 +#define RK3368_SRST_10RES8 168 +#define RK3368_SRST_10RES9 169 +#define RK3368_SRST_DDRMSCH0 170 +#define RK3368_SRST_10RES11 171 +#define RK3368_SRST_10RES12 172 +#define RK3368_SRST_SYS_BUS 173 +#define RK3368_SRST_CRYPTO 174 +#define RK3368_SRST_10RES15 175 + +#define RK3368_SRST_11RES0 176 +#define RK3368_SRST_11RES1 177 +#define RK3368_SRST_11RES2 178 +#define RK3368_SRST_UART0 179 +#define RK3368_SRST_UART1 180 +#define RK3368_SRST_UART2 181 +#define RK3368_SRST_UART3 182 +#define RK3368_SRST_UART4 183 +#define RK3368_SRST_11RES8 184 +#define RK3368_SRST_11RES9 185 +#define RK3368_SRST_SIMC_P 186 +#define RK3368_SRST_11RES11 187 +#define RK3368_SRST_TSP_H 188 +#define RK3368_SRST_TSP_CLKIN0 189 +#define RK3368_SRST_11RES14 190 +#define RK3368_SRST_11RES15 191 + +#define RK3368_SRST_CORE_L_0_SC 192 +#define RK3368_SRST_CORE_L_1 193 +#define RK3368_SRST_CORE_L_2 194 +#define RK3368_SRST_CORE_L_3 195 +#define RK3368_SRST_CORE_L_PO0_SC 196 +#define RK3368_SRST_CORE_L_PO1 197 +#define RK3368_SRST_CORE_L_PO2 198 +#define RK3368_SRST_CORE_L_PO3 199 +#define RK3368_SRST_L2_L_SC 200 +#define RK3368_SRST_ADB_L_SC 201 +#define RK3368_SRST_PD_CORE_L_NIU_A_SC 202 +#define RK3368_SRST_CCI400_SYS_SC 203 +#define RK3368_SRST_CCI400_DDR_SC 204 +#define RK3368_SRST_CCI400_SC 205 +#define RK3368_SRST_SOCDBG_L 206 +#define RK3368_SRST_CORE_L_DBG 207 + +#define RK3368_SRST_CORE_B_0 208 +#define RK3368_SRST_CORE_B_PO0 209 +#define RK3368_SRST_L2_B 210 +#define RK3368_SRST_ADB_B 211 +#define RK3368_SRST_PD_CORE_B_NIU_A 212 +#define RK3368_SRST_STRC_SYS_A 213 +#define RK3368_SRST_CORE_L_0 214 +#define RK3368_SRST_CORE_L_PO0 215 +#define RK3368_SRST_L2_L 216 +#define RK3368_SRST_ADB_L 217 +#define RK3368_SRST_PD_CORE_L_NIU_A 218 +#define RK3368_SRST_CCI400_SYS 219 +#define RK3368_SRST_CCI400_DDR 220 +#define RK3368_SRST_CCI400 221 +#define RK3368_SRST_TRACE 222 +#define RK3368_SRST_13RES15 223 + +#define RK3368_SRST_TIMER00 224 +#define RK3368_SRST_TIMER01 225 +#define RK3368_SRST_TIMER02 226 +#define RK3368_SRST_TIMER03 227 +#define RK3368_SRST_TIMER04 228 +#define RK3368_SRST_TIMER05 229 +#define RK3368_SRST_TIMER10 230 +#define RK3368_SRST_TIMER11 231 +#define RK3368_SRST_TIMER12 232 +#define RK3368_SRST_TIMER13 233 +#define RK3368_SRST_TIMER14 234 +#define RK3368_SRST_TIMER15 235 +#define RK3368_SRST_TIMER0_P 236 +#define RK3368_SRST_TIMER1_P 237 +#define RK3368_SRST_14RES14 238 +#define RK3368_SRST_14RES15 239 + +#endif /* _DT_BINDINGS_CLOCK_ROCKCHIP_RK3368_H */ diff --git a/include/dt-bindings/clock/rockchip-ddr.h b/include/dt-bindings/clock/rockchip-ddr.h new file mode 100644 index 000000000000..b065432e7793 --- /dev/null +++ b/include/dt-bindings/clock/rockchip-ddr.h @@ -0,0 +1,63 @@ +/* + * + * Copyright (C) 2017 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H +#define _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H + +#define DDR2_DEFAULT (0) + +#define DDR3_800D (0) /* 5-5-5 */ +#define DDR3_800E (1) /* 6-6-6 */ +#define DDR3_1066E (2) /* 6-6-6 */ +#define DDR3_1066F (3) /* 7-7-7 */ +#define DDR3_1066G (4) /* 8-8-8 */ +#define DDR3_1333F (5) /* 7-7-7 */ +#define DDR3_1333G (6) /* 8-8-8 */ +#define DDR3_1333H (7) /* 9-9-9 */ +#define DDR3_1333J (8) /* 10-10-10 */ +#define DDR3_1600G (9) /* 8-8-8 */ +#define DDR3_1600H (10) /* 9-9-9 */ +#define DDR3_1600J (11) /* 10-10-10 */ +#define DDR3_1600K (12) /* 11-11-11 */ +#define DDR3_1866J (13) /* 10-10-10 */ +#define DDR3_1866K (14) /* 11-11-11 */ +#define DDR3_1866L (15) /* 12-12-12 */ +#define DDR3_1866M (16) /* 13-13-13 */ +#define DDR3_2133K (17) /* 11-11-11 */ +#define DDR3_2133L (18) /* 12-12-12 */ +#define DDR3_2133M (19) /* 13-13-13 */ +#define DDR3_2133N (20) /* 14-14-14 */ +#define DDR3_DEFAULT (21) +#define DDR_DDR2 (22) +#define DDR_LPDDR (23) +#define DDR_LPDDR2 (24) + +#define DDR4_1600J (0) /* 10-10-10 */ +#define DDR4_1600K (1) /* 11-11-11 */ +#define DDR4_1600L (2) /* 12-12-12 */ +#define DDR4_1866L (3) /* 12-12-12 */ +#define DDR4_1866M (4) /* 13-13-13 */ +#define DDR4_1866N (5) /* 14-14-14 */ +#define DDR4_2133N (6) /* 14-14-14 */ +#define DDR4_2133P (7) /* 15-15-15 */ +#define DDR4_2133R (8) /* 16-16-16 */ +#define DDR4_2400P (9) /* 15-15-15 */ +#define DDR4_2400R (10) /* 16-16-16 */ +#define DDR4_2400U (11) /* 18-18-18 */ +#define DDR4_DEFAULT (12) + +#define PAUSE_CPU_STACK_SIZE 16 + +#endif diff --git a/include/dt-bindings/clock/rockchip.h b/include/dt-bindings/clock/rockchip.h new file mode 100644 index 000000000000..b438f7bd4083 --- /dev/null +++ b/include/dt-bindings/clock/rockchip.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_H +#define _DT_BINDINGS_CLOCK_ROCKCHIP_H + +#ifndef BIT +#define BIT(nr) (1 << (nr)) +#endif + +#define CLK_DIVIDER_PLUS_ONE (0) +#define CLK_DIVIDER_ONE_BASED BIT(0) +#define CLK_DIVIDER_POWER_OF_TWO BIT(1) +#define CLK_DIVIDER_ALLOW_ZERO BIT(2) +#define CLK_DIVIDER_HIWORD_MASK BIT(3) + +/* Rockchip special defined */ +//#define CLK_DIVIDER_FIXED BIT(6) +#define CLK_DIVIDER_USER_DEFINE BIT(7) + +/* + * flags used across common struct clk. these flags should only affect the + * top-level framework. custom flags for dealing with hardware specifics + * belong in struct clk_foo + */ +#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ +#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ +#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ +#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ +#define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ +#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ +#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ +#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ +#define CLK_SET_RATE_PARENT_IN_ORDER BIT(8) /* consider the order of re-parent + and set_div on rate change */ + + + +/* Rockchip pll flags */ +#define CLK_PLL_3188 BIT(0) +#define CLK_PLL_3188_APLL BIT(1) +#define CLK_PLL_3188PLUS BIT(2) +#define CLK_PLL_3188PLUS_APLL BIT(3) +#define CLK_PLL_3288_APLL BIT(4) +#define CLK_PLL_3188PLUS_AUTO BIT(5) +#define CLK_PLL_3036_APLL BIT(6) +#define CLK_PLL_3036PLUS_AUTO BIT(7) +#define CLK_PLL_312XPLUS BIT(8) +#define CLK_PLL_3368_APLLB BIT(9) +#define CLK_PLL_3368_APLLL BIT(10) +#define CLK_PLL_3368_LOW_JITTER BIT(11) + + +/* rate_ops index */ +#define CLKOPS_RATE_MUX_DIV 1 +#define CLKOPS_RATE_EVENDIV 2 +#define CLKOPS_RATE_MUX_EVENDIV 3 +#define CLKOPS_RATE_I2S_FRAC 4 +#define CLKOPS_RATE_FRAC 5 +#define CLKOPS_RATE_I2S 6 +#define CLKOPS_RATE_CIFOUT 7 +#define CLKOPS_RATE_UART 8 +#define CLKOPS_RATE_HSADC 9 +#define CLKOPS_RATE_MAC_REF 10 +#define CLKOPS_RATE_CORE 11 +#define CLKOPS_RATE_CORE_CHILD 12 +#define CLKOPS_RATE_DDR 13 +#define CLKOPS_RATE_RK3288_I2S 14 +#define CLKOPS_RATE_RK3288_USB480M 15 +#define CLKOPS_RATE_RK3288_DCLK_LCDC0 16 +#define CLKOPS_RATE_RK3288_DCLK_LCDC1 17 +#define CLKOPS_RATE_DDR_DIV2 18 +#define CLKOPS_RATE_DDR_DIV4 19 +#define CLKOPS_RATE_RK3368_MUX_DIV_NPLL 20 +#define CLKOPS_RATE_RK3368_DCLK_LCDC 21 +#define CLKOPS_RATE_RK3368_DDR 22 + +#define CLKOPS_TABLE_END (~0) + +/* pd id */ +#define CLK_PD_BCPU 0 +#define CLK_PD_BDSP 1 +#define CLK_PD_BUS 2 +#define CLK_PD_CPU_0 3 +#define CLK_PD_CPU_1 4 +#define CLK_PD_CPU_2 5 +#define CLK_PD_CPU_3 6 +#define CLK_PD_CS 7 +#define CLK_PD_GPU 8 +#define CLK_PD_HEVC 9 +#define CLK_PD_PERI 10 +#define CLK_PD_SCU 11 +#define CLK_PD_VIDEO 12 +#define CLK_PD_VIO 13 +#define CLK_PD_GPU_0 14 +#define CLK_PD_GPU_1 15 + +#define CLK_PD_VIRT 255 + +/* reset flag */ +#define ROCKCHIP_RESET_HIWORD_MASK BIT(0) + +#endif /* _DT_BINDINGS_CLOCK_ROCKCHIP_H */ diff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h new file mode 100644 index 000000000000..d8d0e0456dc2 --- /dev/null +++ b/include/dt-bindings/clock/rv1108-cru.h @@ -0,0 +1,362 @@ +/* + * Copyright (c) 2016 Rockchip Electronics Co. Ltd. + * Author: Shawn Lin <shawn.lin@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H + +/* pll id */ +#define PLL_APLL 0 +#define PLL_DPLL 1 +#define PLL_GPLL 2 +#define ARMCLK 3 + +/* sclk gates (special clocks) */ +#define SCLK_SPI0 65 +#define SCLK_NANDC 67 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_UART0 72 +#define SCLK_UART1 73 +#define SCLK_UART2 74 +#define SCLK_I2S0 75 +#define SCLK_I2S1 76 +#define SCLK_I2S2 77 +#define SCLK_TIMER0 78 +#define SCLK_TIMER1 79 +#define SCLK_SFC 80 +#define SCLK_SDMMC_DRV 81 +#define SCLK_SDIO_DRV 82 +#define SCLK_EMMC_DRV 83 +#define SCLK_SDMMC_SAMPLE 84 +#define SCLK_SDIO_SAMPLE 85 +#define SCLK_EMMC_SAMPLE 86 +#define SCLK_VENC_CORE 87 +#define SCLK_HEVC_CORE 88 +#define SCLK_HEVC_CABAC 89 +#define SCLK_PWM0_PMU 90 +#define SCLK_I2C0_PMU 91 +#define SCLK_WIFI 92 +#define SCLK_CIFOUT 93 +#define SCLK_MIPI_CSI_OUT 94 +#define SCLK_CIF0 95 +#define SCLK_CIF1 96 +#define SCLK_CIF2 97 +#define SCLK_CIF3 98 +#define SCLK_DSP 99 +#define SCLK_DSP_IOP 100 +#define SCLK_DSP_EPP 101 +#define SCLK_DSP_EDP 102 +#define SCLK_DSP_EDAP 103 +#define SCLK_CVBS_HOST 104 +#define SCLK_HDMI_SFR 105 +#define SCLK_HDMI_CEC 106 +#define SCLK_CRYPTO 107 +#define SCLK_SPI 108 +#define SCLK_SARADC 109 +#define SCLK_TSADC 110 +#define SCLK_MAC_PRE 111 +#define SCLK_MAC 112 +#define SCLK_MAC_RX 113 +#define SCLK_MAC_REF 114 +#define SCLK_MAC_REFOUT 115 +#define SCLK_DSP_PFM 116 +#define SCLK_RGA 117 +#define SCLK_I2C1 118 +#define SCLK_I2C2 119 +#define SCLK_I2C3 120 +#define SCLK_PWM 121 +#define SCLK_ISP 122 +#define SCLK_USBPHY 123 +#define SCLK_I2S0_SRC 124 +#define SCLK_I2S1_SRC 125 +#define SCLK_I2S2_SRC 126 +#define SCLK_UART0_SRC 127 +#define SCLK_UART1_SRC 128 +#define SCLK_UART2_SRC 129 + +#define DCLK_VOP_SRC 185 +#define DCLK_HDMIPHY 186 +#define DCLK_VOP 187 + +/* aclk gates */ +#define ACLK_DMAC 192 +#define ACLK_PRE 193 +#define ACLK_CORE 194 +#define ACLK_ENMCORE 195 +#define ACLK_RKVENC 196 +#define ACLK_RKVDEC 197 +#define ACLK_VPU 198 +#define ACLK_CIF0 199 +#define ACLK_VIO0 200 +#define ACLK_VIO1 201 +#define ACLK_VOP 202 +#define ACLK_IEP 203 +#define ACLK_RGA 204 +#define ACLK_ISP 205 +#define ACLK_CIF1 206 +#define ACLK_CIF2 207 +#define ACLK_CIF3 208 +#define ACLK_PERI 209 +#define ACLK_GMAC 210 + +/* pclk gates */ +#define PCLK_GPIO1 256 +#define PCLK_GPIO2 257 +#define PCLK_GPIO3 258 +#define PCLK_GRF 259 +#define PCLK_I2C1 260 +#define PCLK_I2C2 261 +#define PCLK_I2C3 262 +#define PCLK_SPI 263 +#define PCLK_SFC 264 +#define PCLK_UART0 265 +#define PCLK_UART1 266 +#define PCLK_UART2 267 +#define PCLK_TSADC 268 +#define PCLK_PWM 269 +#define PCLK_TIMER 270 +#define PCLK_PERI 271 +#define PCLK_GPIO0_PMU 272 +#define PCLK_I2C0_PMU 273 +#define PCLK_PWM0_PMU 274 +#define PCLK_ISP 275 +#define PCLK_VIO 276 +#define PCLK_MIPI_DSI 277 +#define PCLK_HDMI_CTRL 278 +#define PCLK_SARADC 279 +#define PCLK_DSP_CFG 280 +#define PCLK_BUS 281 +#define PCLK_EFUSE0 282 +#define PCLK_EFUSE1 283 +#define PCLK_WDT 284 +#define PCLK_GMAC 285 + +/* hclk gates */ +#define HCLK_I2S0_8CH 320 +#define HCLK_I2S1_2CH 321 +#define HCLK_I2S2_2CH 322 +#define HCLK_NANDC 323 +#define HCLK_SDMMC 324 +#define HCLK_SDIO 325 +#define HCLK_EMMC 326 +#define HCLK_PERI 327 +#define HCLK_SFC 328 +#define HCLK_RKVENC 329 +#define HCLK_RKVDEC 330 +#define HCLK_CIF0 331 +#define HCLK_VIO 332 +#define HCLK_VOP 333 +#define HCLK_IEP 334 +#define HCLK_RGA 335 +#define HCLK_ISP 336 +#define HCLK_CRYPTO_MST 337 +#define HCLK_CRYPTO_SLV 338 +#define HCLK_HOST0 339 +#define HCLK_OTG 340 +#define HCLK_CIF1 341 +#define HCLK_CIF2 342 +#define HCLK_CIF3 343 +#define HCLK_BUS 344 +#define HCLK_VPU 345 + +#define CLK_NR_CLKS (HCLK_VPU + 1) + +/* reset id */ +#define SRST_CORE_PO_AD 0 +#define SRST_CORE_AD 1 +#define SRST_L2_AD 2 +#define SRST_CPU_NIU_AD 3 +#define SRST_CORE_PO 4 +#define SRST_CORE 5 +#define SRST_L2 6 +#define SRST_CORE_DBG 8 +#define PRST_DBG 9 +#define RST_DAP 10 +#define PRST_DBG_NIU 11 +#define ARST_STRC_SYS_AD 15 + +#define SRST_DDRPHY_CLKDIV 16 +#define SRST_DDRPHY 17 +#define PRST_DDRPHY 18 +#define PRST_HDMIPHY 19 +#define PRST_VDACPHY 20 +#define PRST_VADCPHY 21 +#define PRST_MIPI_CSI_PHY 22 +#define PRST_MIPI_DSI_PHY 23 +#define PRST_ACODEC 24 +#define ARST_BUS_NIU 25 +#define PRST_TOP_NIU 26 +#define ARST_INTMEM 27 +#define HRST_ROM 28 +#define ARST_DMAC 29 +#define SRST_MSCH_NIU 30 +#define PRST_MSCH_NIU 31 + +#define PRST_DDRUPCTL 32 +#define NRST_DDRUPCTL 33 +#define PRST_DDRMON 34 +#define HRST_I2S0_8CH 35 +#define MRST_I2S0_8CH 36 +#define HRST_I2S1_2CH 37 +#define MRST_IS21_2CH 38 +#define HRST_I2S2_2CH 39 +#define MRST_I2S2_2CH 40 +#define HRST_CRYPTO 41 +#define SRST_CRYPTO 42 +#define PRST_SPI 43 +#define SRST_SPI 44 +#define PRST_UART0 45 +#define PRST_UART1 46 +#define PRST_UART2 47 + +#define SRST_UART0 48 +#define SRST_UART1 49 +#define SRST_UART2 50 +#define PRST_I2C1 51 +#define PRST_I2C2 52 +#define PRST_I2C3 53 +#define SRST_I2C1 54 +#define SRST_I2C2 55 +#define SRST_I2C3 56 +#define PRST_PWM1 58 +#define SRST_PWM1 60 +#define PRST_WDT 61 +#define PRST_GPIO1 62 +#define PRST_GPIO2 63 + +#define PRST_GPIO3 64 +#define PRST_GRF 65 +#define PRST_EFUSE 66 +#define PRST_EFUSE512 67 +#define PRST_TIMER0 68 +#define SRST_TIMER0 69 +#define SRST_TIMER1 70 +#define PRST_TSADC 71 +#define SRST_TSADC 72 +#define PRST_SARADC 73 +#define SRST_SARADC 74 +#define HRST_SYSBUS 75 +#define PRST_USBGRF 76 + +#define ARST_PERIPH_NIU 80 +#define HRST_PERIPH_NIU 81 +#define PRST_PERIPH_NIU 82 +#define HRST_PERIPH 83 +#define HRST_SDMMC 84 +#define HRST_SDIO 85 +#define HRST_EMMC 86 +#define HRST_NANDC 87 +#define NRST_NANDC 88 +#define HRST_SFC 89 +#define SRST_SFC 90 +#define ARST_GMAC 91 +#define HRST_OTG 92 +#define SRST_OTG 93 +#define SRST_OTG_ADP 94 +#define HRST_HOST0 95 + +#define HRST_HOST0_AUX 96 +#define HRST_HOST0_ARB 97 +#define SRST_HOST0_EHCIPHY 98 +#define SRST_HOST0_UTMI 99 +#define SRST_USBPOR 100 +#define SRST_UTMI0 101 +#define SRST_UTMI1 102 + +#define ARST_VIO0_NIU 102 +#define ARST_VIO1_NIU 103 +#define HRST_VIO_NIU 104 +#define PRST_VIO_NIU 105 +#define ARST_VOP 106 +#define HRST_VOP 107 +#define DRST_VOP 108 +#define ARST_IEP 109 +#define HRST_IEP 110 +#define ARST_RGA 111 +#define HRST_RGA 112 +#define SRST_RGA 113 +#define PRST_CVBS 114 +#define PRST_HDMI 115 +#define SRST_HDMI 116 +#define PRST_MIPI_DSI 117 + +#define ARST_ISP_NIU 118 +#define HRST_ISP_NIU 119 +#define HRST_ISP 120 +#define SRST_ISP 121 +#define ARST_VIP0 122 +#define HRST_VIP0 123 +#define PRST_VIP0 124 +#define ARST_VIP1 125 +#define HRST_VIP1 126 +#define PRST_VIP1 127 +#define ARST_VIP2 128 +#define HRST_VIP2 129 +#define PRST_VIP2 120 +#define ARST_VIP3 121 +#define HRST_VIP3 122 +#define PRST_VIP4 123 + +#define PRST_CIF1TO4 124 +#define SRST_CVBS_CLK 125 +#define HRST_CVBS 126 + +#define ARST_VPU_NIU 140 +#define HRST_VPU_NIU 141 +#define ARST_VPU 142 +#define HRST_VPU 143 +#define ARST_RKVDEC_NIU 144 +#define HRST_RKVDEC_NIU 145 +#define ARST_RKVDEC 146 +#define HRST_RKVDEC 147 +#define SRST_RKVDEC_CABAC 148 +#define SRST_RKVDEC_CORE 149 +#define ARST_RKVENC_NIU 150 +#define HRST_RKVENC_NIU 151 +#define ARST_RKVENC 152 +#define HRST_RKVENC 153 +#define SRST_RKVENC_CORE 154 + +#define SRST_DSP_CORE 156 +#define SRST_DSP_SYS 157 +#define SRST_DSP_GLOBAL 158 +#define SRST_DSP_OECM 159 +#define PRST_DSP_IOP_NIU 160 +#define ARST_DSP_EPP_NIU 161 +#define ARST_DSP_EDP_NIU 162 +#define PRST_DSP_DBG_NIU 163 +#define PRST_DSP_CFG_NIU 164 +#define PRST_DSP_GRF 165 +#define PRST_DSP_MAILBOX 166 +#define PRST_DSP_INTC 167 +#define PRST_DSP_PFM_MON 169 +#define SRST_DSP_PFM_MON 170 +#define ARST_DSP_EDAP_NIU 171 + +#define SRST_PMU 172 +#define SRST_PMU_I2C0 173 +#define PRST_PMU_I2C0 174 +#define PRST_PMU_GPIO0 175 +#define PRST_PMU_INTMEM 176 +#define PRST_PMU_PWM0 177 +#define SRST_PMU_PWM0 178 +#define PRST_PMU_GRF 179 +#define SRST_PMU_NIU 180 +#define SRST_PMU_PVTM 181 +#define ARST_DSP_EDP_PERF 184 +#define ARST_DSP_EPP_PERF 185 + +#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */ diff --git a/include/dt-bindings/display/drm_mipi_dsi.h b/include/dt-bindings/display/drm_mipi_dsi.h new file mode 100644 index 000000000000..bc24ce4ddd08 --- /dev/null +++ b/include/dt-bindings/display/drm_mipi_dsi.h @@ -0,0 +1,53 @@ +/* + * MIPI DSI Bus + * + * Copyright (c) Fuzhou Rockchip Electronics Co.Ltd + * Authors: + * Mark Yao <yzq@rock-chips.com> + * + * based on include/drm/drm_mipi_dsi.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _DRM_MIPI_DSI_H__ +#define _DRM_MIPI_DSI_H__ + +/* DSI mode flags */ + +/* video mode */ +#define MIPI_DSI_MODE_VIDEO (1 << 0) +/* video burst mode */ +#define MIPI_DSI_MODE_VIDEO_BURST (1 << 1) +/* video pulse mode */ +#define MIPI_DSI_MODE_VIDEO_SYNC_PULSE (1 << 2) +/* enable auto vertical count mode */ +#define MIPI_DSI_MODE_VIDEO_AUTO_VERT (1 << 3) +/* enable hsync-end packets in vsync-pulse and v-porch area */ +#define MIPI_DSI_MODE_VIDEO_HSE (1 << 4) +/* disable hfront-porch area */ +#define MIPI_DSI_MODE_VIDEO_HFP (1 << 5) +/* disable hback-porch area */ +#define MIPI_DSI_MODE_VIDEO_HBP (1 << 6) +/* disable hsync-active area */ +#define MIPI_DSI_MODE_VIDEO_HSA (1 << 7) +/* flush display FIFO on vsync pulse */ +#define MIPI_DSI_MODE_VSYNC_FLUSH (1 << 8) +/* disable EoT packets in HS mode */ +#define MIPI_DSI_MODE_EOT_PACKET (1 << 9) +/* device supports non-continuous clock behavior (DSI spec 5.6.1) */ +#define MIPI_DSI_CLOCK_NON_CONTINUOUS (1 << 10) +/* transmit data in low power */ +#define MIPI_DSI_MODE_LPM (1 << 11) + +#define MIPI_DSI_FMT_RGB888 0 +#define MIPI_DSI_FMT_RGB666 1 +#define MIPI_DSI_FMT_RGB666_PACKED 2 +#define MIPI_DSI_FMT_RGB565 3 + +#define MIPI_CSI_FMT_RAW8 0x10 +#define MIPI_CSI_FMT_RAW10 0x11 + +#endif /* __DRM_MIPI_DSI__ */ diff --git a/include/dt-bindings/display/media-bus-format.h b/include/dt-bindings/display/media-bus-format.h new file mode 100644 index 000000000000..190d491d5b13 --- /dev/null +++ b/include/dt-bindings/display/media-bus-format.h @@ -0,0 +1,137 @@ +/* + * Media Bus API header + * + * Copyright (C) 2009, Guennadi Liakhovetski <g.liakhovetski@gmx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_MEDIA_BUS_FORMAT_H +#define __LINUX_MEDIA_BUS_FORMAT_H + +/* + * These bus formats uniquely identify data formats on the data bus. Format 0 + * is reserved, MEDIA_BUS_FMT_FIXED shall be used by host-client pairs, where + * the data format is fixed. Additionally, "2X8" means that one pixel is + * transferred in two 8-bit samples, "BE" or "LE" specify in which order those + * samples are transferred over the bus: "LE" means that the least significant + * bits are transferred first, "BE" means that the most significant bits are + * transferred first, and "PADHI" and "PADLO" define which bits - low or high, + * in the incomplete high byte, are filled with padding bits. + * + * The bus formats are grouped by type, bus_width, bits per component, samples + * per pixel and order of subsamples. Numerical values are sorted using generic + * numerical sort order (8 thus comes before 10). + * + * As their value can't change when a new bus format is inserted in the + * enumeration, the bus formats are explicitly given a numerical value. The next + * free values for each category are listed below, update them when inserting + * new pixel codes. + */ + +#define MEDIA_BUS_FMT_FIXED 0x0001 + +/* RGB - next is 0x1018 */ +#define MEDIA_BUS_FMT_RGB444_1X12 0x1016 +#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001 +#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002 +#define MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE 0x1003 +#define MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE 0x1004 +#define MEDIA_BUS_FMT_RGB565_1X16 0x1017 +#define MEDIA_BUS_FMT_BGR565_2X8_BE 0x1005 +#define MEDIA_BUS_FMT_BGR565_2X8_LE 0x1006 +#define MEDIA_BUS_FMT_RGB565_2X8_BE 0x1007 +#define MEDIA_BUS_FMT_RGB565_2X8_LE 0x1008 +#define MEDIA_BUS_FMT_RGB666_1X18 0x1009 +#define MEDIA_BUS_FMT_RBG888_1X24 0x100e +#define MEDIA_BUS_FMT_RGB666_1X24_CPADHI 0x1015 +#define MEDIA_BUS_FMT_RGB666_1X7X3_SPWG 0x1010 +#define MEDIA_BUS_FMT_BGR888_1X24 0x1013 +#define MEDIA_BUS_FMT_GBR888_1X24 0x1014 +#define MEDIA_BUS_FMT_RGB888_1X24 0x100a +#define MEDIA_BUS_FMT_RGB888_2X12_BE 0x100b +#define MEDIA_BUS_FMT_RGB888_2X12_LE 0x100c +#define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG 0x1011 +#define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA 0x1012 +#define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d +#define MEDIA_BUS_FMT_RGB888_1X32_PADHI 0x100f + +/* YUV (including grey) - next is 0x2026 */ +#define MEDIA_BUS_FMT_Y8_1X8 0x2001 +#define MEDIA_BUS_FMT_UV8_1X8 0x2015 +#define MEDIA_BUS_FMT_UYVY8_1_5X8 0x2002 +#define MEDIA_BUS_FMT_VYUY8_1_5X8 0x2003 +#define MEDIA_BUS_FMT_YUYV8_1_5X8 0x2004 +#define MEDIA_BUS_FMT_YVYU8_1_5X8 0x2005 +#define MEDIA_BUS_FMT_UYVY8_2X8 0x2006 +#define MEDIA_BUS_FMT_VYUY8_2X8 0x2007 +#define MEDIA_BUS_FMT_YUYV8_2X8 0x2008 +#define MEDIA_BUS_FMT_YVYU8_2X8 0x2009 +#define MEDIA_BUS_FMT_Y10_1X10 0x200a +#define MEDIA_BUS_FMT_UYVY10_2X10 0x2018 +#define MEDIA_BUS_FMT_VYUY10_2X10 0x2019 +#define MEDIA_BUS_FMT_YUYV10_2X10 0x200b +#define MEDIA_BUS_FMT_YVYU10_2X10 0x200c +#define MEDIA_BUS_FMT_Y12_1X12 0x2013 +#define MEDIA_BUS_FMT_UYVY12_2X12 0x201c +#define MEDIA_BUS_FMT_VYUY12_2X12 0x201d +#define MEDIA_BUS_FMT_YUYV12_2X12 0x201e +#define MEDIA_BUS_FMT_YVYU12_2X12 0x201f +#define MEDIA_BUS_FMT_UYVY8_1X16 0x200f +#define MEDIA_BUS_FMT_VYUY8_1X16 0x2010 +#define MEDIA_BUS_FMT_YUYV8_1X16 0x2011 +#define MEDIA_BUS_FMT_YVYU8_1X16 0x2012 +#define MEDIA_BUS_FMT_YDYUYDYV8_1X16 0x2014 +#define MEDIA_BUS_FMT_UYVY10_1X20 0x201a +#define MEDIA_BUS_FMT_VYUY10_1X20 0x201b +#define MEDIA_BUS_FMT_YUYV10_1X20 0x200d +#define MEDIA_BUS_FMT_YVYU10_1X20 0x200e +#define MEDIA_BUS_FMT_VUY8_1X24 0x2024 +#define MEDIA_BUS_FMT_YUV8_1X24 0x2025 +#define MEDIA_BUS_FMT_UYVY12_1X24 0x2020 +#define MEDIA_BUS_FMT_VYUY12_1X24 0x2021 +#define MEDIA_BUS_FMT_YUYV12_1X24 0x2022 +#define MEDIA_BUS_FMT_YVYU12_1X24 0x2023 +#define MEDIA_BUS_FMT_YUV10_1X30 0x2016 +#define MEDIA_BUS_FMT_AYUV8_1X32 0x2017 + +/* Bayer - next is 0x3019 */ +#define MEDIA_BUS_FMT_SBGGR8_1X8 0x3001 +#define MEDIA_BUS_FMT_SGBRG8_1X8 0x3013 +#define MEDIA_BUS_FMT_SGRBG8_1X8 0x3002 +#define MEDIA_BUS_FMT_SRGGB8_1X8 0x3014 +#define MEDIA_BUS_FMT_SBGGR10_ALAW8_1X8 0x3015 +#define MEDIA_BUS_FMT_SGBRG10_ALAW8_1X8 0x3016 +#define MEDIA_BUS_FMT_SGRBG10_ALAW8_1X8 0x3017 +#define MEDIA_BUS_FMT_SRGGB10_ALAW8_1X8 0x3018 +#define MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8 0x300b +#define MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8 0x300c +#define MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8 0x3009 +#define MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8 0x300d +#define MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE 0x3003 +#define MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE 0x3004 +#define MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE 0x3005 +#define MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE 0x3006 +#define MEDIA_BUS_FMT_SBGGR10_1X10 0x3007 +#define MEDIA_BUS_FMT_SGBRG10_1X10 0x300e +#define MEDIA_BUS_FMT_SGRBG10_1X10 0x300a +#define MEDIA_BUS_FMT_SRGGB10_1X10 0x300f +#define MEDIA_BUS_FMT_SBGGR12_1X12 0x3008 +#define MEDIA_BUS_FMT_SGBRG12_1X12 0x3010 +#define MEDIA_BUS_FMT_SGRBG12_1X12 0x3011 +#define MEDIA_BUS_FMT_SRGGB12_1X12 0x3012 + +/* JPEG compressed formats - next is 0x4002 */ +#define MEDIA_BUS_FMT_JPEG_1X8 0x4001 + +/* Vendor specific formats - next is 0x5002 */ + +/* S5C73M3 sensor specific interleaved UYVY and JPEG */ +#define MEDIA_BUS_FMT_S5C_UYVY_JPEG_1X8 0x5001 + +/* HSV - next is 0x6002 */ +#define MEDIA_BUS_FMT_AHSV8888_1X32 0x6001 + +#endif /* __LINUX_MEDIA_BUS_FORMAT_H */ diff --git a/include/dt-bindings/display/mipi_dsi.h b/include/dt-bindings/display/mipi_dsi.h new file mode 100644 index 000000000000..38aeee0ed51d --- /dev/null +++ b/include/dt-bindings/display/mipi_dsi.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +drivers/video/rockchip/transmitter/mipi_dsi.h +*/ +#ifndef MIPI_DSI_H_ +#define MIPI_DSI_H_ + +#ifdef CONFIG_MIPI_DSI_FT +#include "..\..\common\config.h" +#endif + +//DSI DATA TYPE +#define DTYPE_DCS_SWRITE_0P 0x05 +#define DTYPE_DCS_SWRITE_1P 0x15 +#define DTYPE_DCS_LWRITE 0x39 +#define DTYPE_GEN_LWRITE 0x29 +#define DTYPE_GEN_SWRITE_2P 0x23 +#define DTYPE_GEN_SWRITE_1P 0x13 +#define DTYPE_GEN_SWRITE_0P 0x03 + +//command transmit mode +#define HSDT 0x00 +#define LPDT 0x01 + +//DSI DATA TYPE FLAG +#define DATA_TYPE_DCS 0x00 +#define DATA_TYPE_GEN 0x01 + +//Video Mode +#define VM_NBMWSP 0x00 //Non burst mode with sync pulses +#define VM_NBMWSE 0x01 //Non burst mode with sync events +#define VM_BM 0x02 //Burst mode + +//Video Pixel Format +#define VPF_16BPP 0x00 +#define VPF_18BPP 0x01 //packed +#define VPF_18BPPL 0x02 //loosely packed +#define VPF_24BPP 0x03 + +//Display Command Set +#define dcs_enter_idle_mode 0x39 +#define dcs_enter_invert_mode 0x21 +#define dcs_enter_normal_mode 0x13 +#define dcs_enter_partial_mode 0x12 +#define dcs_enter_sleep_mode 0x10 +#define dcs_exit_idle_mode 0x38 +#define dcs_exit_invert_mode 0x20 +#define dcs_exit_sleep_mode 0x11 +#define dcs_get_address_mode 0x0b +#define dcs_get_blue_channel 0x08 +#define dcs_get_diagnostic_result 0x0f +#define dcs_get_display_mode 0x0d +#define dcs_get_green_channel 0x07 +#define dcs_get_pixel_format 0x0c +#define dcs_get_power_mode 0x0a +#define dcs_get_red_channel 0x06 +#define dcs_get_scanline 0x45 +#define dcs_get_signal_mode 0x0e +#define dcs_nop 0x00 +#define dcs_read_DDB_continue 0xa8 +#define dcs_read_DDB_start 0xa1 +#define dcs_read_memory_continue 0x3e +#define dcs_read_memory_start 0x2e +#define dcs_set_address_mode 0x36 +#define dcs_set_column_address 0x2a +#define dcs_set_display_off 0x28 +#define dcs_set_display_on 0x29 +#define dcs_set_gamma_curve 0x26 +#define dcs_set_page_address 0x2b +#define dcs_set_partial_area 0x30 +#define dcs_set_pixel_format 0x3a +#define dcs_set_scroll_area 0x33 +#define dcs_set_scroll_start 0x37 +#define dcs_set_tear_off 0x34 +#define dcs_set_tear_on 0x35 +#define dcs_set_tear_scanline 0x44 +#define dcs_soft_reset 0x01 +#define dcs_write_LUT 0x2d +#define dcs_write_memory_continue 0x3c +#define dcs_write_memory_start 0x2c + +#ifndef MHz +#define MHz 1000000 +#endif + + +#if 0 +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long s64; +typedef unsigned long u64; +#endif + + +//iomux +#define OLD_RK_IOMUX 0 + + +#endif /* end of MIPI_DSI_H_ */ diff --git a/include/dt-bindings/display/rk_fb.h b/include/dt-bindings/display/rk_fb.h new file mode 100644 index 000000000000..0b4594b2b055 --- /dev/null +++ b/include/dt-bindings/display/rk_fb.h @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _DT_BINDINGS_RKFB_H_ +#define _DT_BINDINGS_RKFB_H_ +#define GPIO 0 +#define REGULATOR 1 + +#define PRMRY 1 /*primary display device*/ +#define EXTEND 2 /*extend display device*/ + +#define DISPLAY_SOURCE_LCDC0 0 +#define DISPLAY_SOURCE_LCDC1 1 + +#define NO_DUAL 0 +#define ONE_DUAL 1 +#define DUAL 2 +#define DUAL_LCD 3 + +#define DEFAULT_MODE 0 +#define ONE_VOP_DUAL_MIPI_HOR_SCAN 1 +#define ONE_VOP_DUAL_MIPI_VER_SCAN 2 +#define TWO_VOP_TWO_SCREEN 3 + +/******************************************************************** +** display output interface supported by rockchip ** +********************************************************************/ +#define OUT_P888 0 //24bit screen,connect to lcdc D0~D23 +#define OUT_P666 1 //18bit screen,connect to lcdc D0~D17 +#define OUT_P565 2 +#define OUT_S888x 4 +#define OUT_CCIR656 6 +#define OUT_S888 8 +#define OUT_S888DUMY 12 +#define OUT_YUV_420 14 +#define OUT_P101010 15 +#define OUT_YUV_420_10BIT 16 +#define OUT_YUV_422 12 +#define OUT_YUV_422_10BIT 17 +#define OUT_P16BPP4 24 +#define OUT_D888_P666 0x21 //18bit screen,connect to lcdc D2~D7, D10~D15, D18~D23 +#define OUT_D888_P565 0x22 + +#define SCREEN_NULL 0 +#define SCREEN_RGB 1 +#define SCREEN_LVDS 2 +#define SCREEN_DUAL_LVDS 3 +#define SCREEN_MCU 4 +#define SCREEN_TVOUT 5 +#define SCREEN_HDMI 6 +#define SCREEN_MIPI 7 +#define SCREEN_DUAL_MIPI 8 +#define SCREEN_EDP 9 +#define SCREEN_TVOUT_TEST 10 +#define SCREEN_LVDS_10BIT 11 +#define SCREEN_DUAL_LVDS_10BIT 12 +#define SCREEN_DP 13 + +#define LVDS_8BIT_1 0 +#define LVDS_8BIT_2 1 +#define LVDS_8BIT_3 2 +#define LVDS_6BIT 3 +#define LVDS_10BIT_1 4 +#define LVDS_10BIT_2 5 + +/* x y mirror or rotate mode */ +#define NO_MIRROR 0 +#define X_MIRROR 1 /* up-down flip*/ +#define Y_MIRROR 2 /* left-right flip */ +#define X_Y_MIRROR 3 /* the same as rotate 180 degrees */ +#define ROTATE_90 4 /* clockwise rotate 90 degrees */ +#define ROTATE_180 8 /* rotate 180 degrees + * It is recommended to use X_Y_MIRROR + * rather than ROTATE_180 + */ +#define ROTATE_270 12/* clockwise rotate 270 degrees */ + +#define COLOR_RGB 0 +#define COLOR_RGB_BT2020 1 +/* default colorspace is bt601 */ +#define COLOR_YCBCR 2 +#define COLOR_YCBCR_BT709 3 +#define COLOR_YCBCR_BT2020 4 + +#define IS_YUV_COLOR(x) ((x) >= COLOR_YCBCR) + +#define SCREEN_VIDEO_MODE 0 +#define SCREEN_CMD_MODE 1 + +/* fb win map */ +#define FB_DEFAULT_ORDER 0 +#define FB0_WIN2_FB1_WIN1_FB2_WIN0 12 +#define FB0_WIN1_FB1_WIN2_FB2_WIN0 21 +#define FB0_WIN2_FB1_WIN0_FB2_WIN1 102 +#define FB0_WIN0_FB1_WIN2_FB2_WIN1 120 +#define FB0_WIN0_FB1_WIN1_FB2_WIN2 210 +#define FB0_WIN1_FB1_WIN0_FB2_WIN2 201 +#define FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3 3210 +#define FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3_FB4_HWC 43210 + +#define DISPLAY_POLICY_SDK 0 +#define DISPLAY_POLICY_BOX 1 + +/* lvds connect config + * + * LVDS_8BIT_1 LVDS_8BIT_2 LVDS_8BIT_3 LVDS_6BIT +---------------------------------------------------------------------- + TX0 R0 R2 R2 R0 + TX1 R1 R3 R3 R1 + TX2 R2 R4 R4 R2 +Y TX3 R3 R5 R5 R3 +0 TX4 R4 R6 R6 R4 + TX6 R5 R7 R7 R5 + TX7 G0 G2 G2 G0 +---------------------------------------------------------------------- + TX8 G1 G3 G3 G1 + TX9 G2 G4 G4 G2 +Y TX12 G3 G5 G5 G3 +1 TX13 G4 G6 G6 G4 + TX14 G5 G7 G7 G5 + TX15 B0 B2 B2 B0 + TX18 B1 B3 B3 B1 +---------------------------------------------------------------------- + TX19 B2 B4 B4 B2 + TX20 B3 B5 B5 B3 + TX21 B4 B6 B6 B4 +Y TX22 B5 B7 B7 B5 +2 TX24 HSYNC HSYNC HSYNC HSYNC + TX25 VSYNC VSYNC VSYNC VSYNC + TX26 ENABLE ENABLE ENABLE ENABLE +---------------------------------------------------------------------- + TX27 R6 R0 GND GND + TX5 R7 R1 GND GND + TX10 G6 G0 GND GND +Y TX11 G7 G1 GND GND +3 TX16 B6 B0 GND GND + TX17 B7 B1 GND GND + TX23 RSVD RSVD RSVD RSVD +---------------------------------------------------------------------- + + * LVDS_10BIT_1 LVDS_10BIT_2 +---------------------------------------------------------------------- + TX0 R0 R4 + TX1 R1 R5 + TX2 R2 R6 +Y TX3 R3 R7 +0 TX4 R4 R8 + TX6 R5 R9 + TX7 G0 G4 +---------------------------------------------------------------------- + TX8 G1 G5 + TX9 G2 G6 +Y TX12 G3 G7 +1 TX13 G4 G8 + TX14 G5 G9 + TX15 B0 B4 + TX18 B1 B5 +---------------------------------------------------------------------- + TX19 B2 B6 + TX20 B3 B7 + TX21 B4 B8 +Y TX22 B5 B9 +2 TX24 HSYNC HSYNC + TX25 VSYNC VSYNC + TX26 ENABLE ENABLE +---------------------------------------------------------------------- + TX27 R6 R2 + TX5 R7 R3 + TX10 G6 G2 +Y TX11 G7 G3 +3 TX16 B6 B2 + TX17 B7 B3 + TX23 GND GND +---------------------------------------------------------------------- + TX27 R8 R0 + TX5 R9 R1 + TX10 G8 G0 +Y TX11 G9 G1 +4 TX16 B8 B0 + TX17 B9 B1 + TX23 GND GND +------------------------------------------------------------------------ +*/ + +#endif diff --git a/include/dt-bindings/display/screen-timing/lcd-86v-rgb1024x600.dtsi b/include/dt-bindings/display/screen-timing/lcd-86v-rgb1024x600.dtsi new file mode 100644 index 000000000000..dcca65671ffb --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-86v-rgb1024x600.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RockChip. LCD_RGB1024x600 FOR 86V + * + */ + + +disp_timings: display-timings { + native-mode = <&timing0>; + timing0: timing0 { + screen-type = <SCREEN_RGB>; + out-face = <OUT_P666>; + clock-frequency = <60000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <100>; + hfront-porch = <120>; + vback-porch = <10>; + vfront-porch = <15>; + hsync-len = <100>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-F402.dtsi b/include/dt-bindings/display/screen-timing/lcd-F402.dtsi new file mode 100644 index 000000000000..0a7a45ad935e --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-F402.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RockChip. DisplayPort screen LP097QX1 + * + */ + + +disp_timings: display-timings { + native-mode = <&timing0>; + timing0: timing0 { + screen-type = <SCREEN_EDP>; + out-face = <OUT_P666>; + clock-frequency = <205000000>; + hactive = <1536>; + vactive = <2048>; + hback-porch = <48>; + hfront-porch = <12>; + vback-porch = <8>; + vfront-porch = <8>; + hsync-len = <16>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + dsp-lut = <0x00000000 0x00010101 0x00020202 0x00030303 0x00040404 0x00050505 0x00060606 0x00070707 0x00080808 0x00090909 + 0x000a0a0a 0x000b0b0b 0x000c0c0c 0x000d0d0d 0x000e0e0e 0x000f0f0f 0x00101010 0x00111111 0x00121212 0x00131313 + 0x00141414 0x00151515 0x00161616 0x00171717 0x00181818 0x00191919 0x001a1a1a 0x001b1b1b 0x001c1c1c 0x001d1d1d + 0x001e1e1e 0x001f1f1f 0x00202020 0x00212121 0x00222222 0x00232323 0x00242424 0x00252525 0x00262626 0x00272727 + 0x00282828 0x00292929 0x002a2a2a 0x002b2b2b 0x002c2c2c 0x002d2d2d 0x002e2e2e 0x002f2f2f 0x00303030 0x00313131 + 0x00323232 0x00333333 0x00343434 0x00353535 0x00363636 0x00373737 0x00383838 0x00393939 0x003a3a3a 0x003b3b3b + 0x003c3c3c 0x003d3d3d 0x003e3e3e 0x003f3f3f 0x00404040 0x00414141 0x00424242 0x00434343 0x00444444 0x00454545 + 0x00464646 0x00474747 0x00484848 0x00494949 0x004a4a4a 0x004b4b4b 0x004c4c4c 0x004d4d4d 0x004e4e4e 0x004f4f4f + 0x00505050 0x00515151 0x00525252 0x00535353 0x00545454 0x00555555 0x00565656 0x00575757 0x00585858 0x00595959 + 0x005a5a5a 0x005b5b5b 0x005c5c5c 0x005d5d5d 0x005e5e5e 0x005f5f5f 0x00606060 0x00616161 0x00626262 0x00636363 + 0x00646464 0x00656565 0x00666666 0x00676767 0x00686868 0x00696969 0x006a6a6a 0x006b6b6b 0x006c6c6c 0x006d6d6d + 0x006e6e6e 0x006f6f6f 0x00707070 0x00717171 0x00727272 0x00737373 0x00747474 0x00757575 0x00767676 0x00777777 + 0x00787878 0x00797979 0x007a7a7a 0x007b7b7b 0x007c7c7c 0x007d7d7d 0x007e7e7e 0x007f7f7f 0x00808080 0x00818181 + 0x00828282 0x00838383 0x00848484 0x00858585 0x00868686 0x00878787 0x00888888 0x00898989 0x008a8a8a 0x008b8b8b + 0x008c8c8c 0x008d8d8d 0x008e8e8e 0x008f8f8f 0x00909090 0x00919191 0x00929292 0x00939393 0x00949494 0x00959595 + 0x00969696 0x00979797 0x00989898 0x00999999 0x009a9a9a 0x009b9b9b 0x009c9c9c 0x009d9d9d 0x009e9e9e 0x009f9f9f + 0x00a0a0a0 0x00a1a1a1 0x00a2a2a2 0x00a3a3a3 0x00a4a4a4 0x00a5a5a5 0x00a6a6a6 0x00a7a7a7 0x00a8a8a8 0x00a9a9a9 + 0x00aaaaaa 0x00ababab 0x00acacac 0x00adadad 0x00aeaeae 0x00afafaf 0x00b0b0b0 0x00b1b1b1 0x00b2b2b2 0x00b3b3b3 + 0x00b4b4b4 0x00b5b5b5 0x00b6b6b6 0x00b7b7b7 0x00b8b8b8 0x00b9b9b9 0x00bababa 0x00bbbbbb 0x00bcbcbc 0x00bdbdbd + 0x00bebebe 0x00bfbfbf 0x00c0c0c0 0x00c1c1c1 0x00c2c2c2 0x00c3c3c3 0x00c4c4c4 0x00c5c5c5 0x00c6c6c6 0x00c7c7c7 + 0x00c8c8c8 0x00c9c9c9 0x00cacaca 0x00cbcbcb 0x00cccccc 0x00cdcdcd 0x00cecece 0x00cfcfcf 0x00d0d0d0 0x00d1d1d1 + 0x00d2d2d2 0x00d3d3d3 0x00d4d4d4 0x00d5d5d5 0x00d6d6d6 0x00d7d7d7 0x00d8d8d8 0x00d9d9d9 0x00dadada 0x00dbdbdb + 0x00dcdcdc 0x00dddddd 0x00dedede 0x00dfdfdf 0x00e0e0e0 0x00e1e1e1 0x00e2e2e2 0x00e3e3e3 0x00e4e4e4 0x00e5e5e5 + 0x00e6e6e6 0x00e7e7e7 0x00e8e8e8 0x00e9e9e9 0x00eaeaea 0x00ebebeb 0x00ececec 0x00ededed 0x00eeeeee 0x00efefef + 0x00f0f0f0 0x00f1f1f1 0x00f2f2f2 0x00f3f3f3 0x00f4f4f4 0x00f5f5f5 0x00f6f6f6 0x00f7f7f7 0x00f8f8f8 0x00f9f9f9 + 0x00fafafa 0x00fbfbfb 0x00fcfcfc 0x00fdfdfd 0x00fefefe 0x00ffffff>; + cabc-lut = < + /*gamma = 2.2*/ + 0x00000383 0x00000392 0x000003a2 0x000003b2 0x000003c2 0x000003d2 0x000003e2 0x000003f3 + 0x00000403 0x00000414 0x00000425 0x00000436 0x00000447 0x00000458 0x0000046a 0x0000047b + 0x0000048d 0x0000049f 0x000004b1 0x000004c3 0x000004d5 0x000004e8 0x000004fa 0x0000050d + 0x00000520 0x00000533 0x00000546 0x0000055a 0x0000056d 0x00000581 0x00000595 0x000005a9 + 0x000005bd 0x000005d1 0x000005e5 0x000005fa 0x0000060f 0x00000624 0x00000639 0x0000064e + 0x00000663 0x00000679 0x0000068e 0x000006a4 0x000006ba 0x000006d0 0x000006e6 0x000006fd + 0x00000713 0x0000072a 0x00000741 0x00000758 0x0000076f 0x00000786 0x0000079e 0x000007b6 + 0x000007cd 0x000007e5 0x000007fd 0x00000816 0x0000082e 0x00000847 0x0000085f 0x00000878 + 0x00000891 0x000008ab 0x000008c4 0x000008de 0x000008f7 0x00000911 0x0000092b 0x00000945 + 0x00000960 0x0000097a 0x00000995 0x000009af 0x000009ca 0x000009e6 0x00000a01 0x00000a1c + 0x00000a38 0x00000a54 0x00000a6f 0x00000a8c 0x00000aa8 0x00000ac4 0x00000ae1 0x00000afd + 0x00000b1a 0x00000b37 0x00000b54 0x00000b72 0x00000b8f 0x00000bad 0x00000bcb 0x00000be9 + 0x00000c07 0x00000c25 0x00000c44 0x00000c62 0x00000c81 0x00000ca0 0x00000cbf 0x00000cdf + 0x00000cfe 0x00000d1e 0x00000d3e 0x00000d5d 0x00000d7e 0x00000d9e 0x00000dbe 0x00000ddf + 0x00000e00 0x00000e21 0x00000e42 0x00000e63 0x00000e84 0x00000ea6 0x00000ec8 0x00000eea + 0x00000f0c 0x00000f2e 0x00000f50 0x00000f73 0x00000f96 0x00000fb9 0x00000fdc 0x00000fff + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; + cabc-gamma-base = < + /*gamma = 2.2*/ + 0x00010000 0x0000fdd0 0x0000fba8 0x0000f986 0x0000f76a 0x0000f556 0x0000f347 0x0000f140 + 0x0000ef3e 0x0000ed43 0x0000eb4e 0x0000e95e 0x0000e775 0x0000e592 0x0000e3b4 0x0000e1dc + 0x0000e009 0x0000de3c 0x0000dc74 0x0000dab2 0x0000d8f4 0x0000d73c 0x0000d589 0x0000d3db + 0x0000d232 0x0000d08d 0x0000ceee 0x0000cd53 0x0000cbbc 0x0000ca2b 0x0000c89d 0x0000c714 + 0x0000c590 0x0000c410 0x0000c294 0x0000c11c 0x0000bfa8 0x0000be39 0x0000bccd 0x0000bb65 + 0x0000ba01 0x0000b8a1 0x0000b745 0x0000b5ed 0x0000b498 0x0000b347 0x0000b1f9 0x0000b0af + 0x0000af68 0x0000ae25 0x0000ace5 0x0000aba8 0x0000aa6f 0x0000a939 0x0000a806 0x0000a6d7 + 0x0000a5aa 0x0000a480 0x0000a35a 0x0000a236 0x0000a116 0x00009ff8 0x00009edd 0x00009dc5 + 0x00009cb0 0x00009b9e 0x00009a8e 0x00009981 0x00009877 0x0000976f 0x0000966a 0x00009567 + 0x00009467 0x0000936a 0x0000926f 0x00009176 0x00009080 0x00008f8c 0x00008e9a 0x00008dab + 0x00008cbe 0x00008bd3 0x00008aea 0x00008a04 0x00008920 0x0000883e 0x0000875e 0x00008680 + 0x000085a4 0x000084ca 0x000083f3 0x0000831d 0x00008249 0x00008177 0x000080a7 0x00007fd9 + 0x00007f0d 0x00007e42 0x00007d7a 0x00007cb3 0x00007bee 0x00007b2b 0x00007a6a 0x000079aa + 0x000078ec 0x0000782f 0x00007775 0x000076bc 0x00007604 0x0000754f 0x0000749a 0x000073e8 + 0x00007337 0x00007287 0x000071d9 0x0000712c 0x00007081 0x00006fd8 0x00006f30 0x00006e89 + 0x00006de4 0x00006d40 0x00006c9d 0x00006bfc 0x00006b5c 0x00006abe 0x00006a21 0x00006985 + 0x000068ea 0x00006851 0x000067b9 0x00006722 0x0000668d 0x000065f9 0x00006566 0x000064d4 + 0x00006443 0x000063b4 0x00006325 0x00006298 0x0000620c 0x00006181 0x000060f8 0x0000606f + 0x00005fe7 0x00005f61 0x00005edb 0x00005e57 0x00005dd4 0x00005d51 0x00005cd0 0x00005c50 + 0x00005bd1 0x00005b52 0x00005ad5 0x00005a59 0x000059de 0x00005963 0x000058ea 0x00005871 + 0x000057fa 0x00005783 0x0000570d 0x00005699 0x00005625 0x000055b2 0x0000553f 0x000054ce + 0x0000545d 0x000053ee 0x0000537f 0x00005311 0x000052a4 0x00005238 0x000051cc 0x00005161 + 0x000050f7 0x0000508e 0x00005026 0x00004fbe 0x00004f57 0x00004ef1 0x00004e8c 0x00004e27 + 0x00004dc3 0x00004d60 0x00004cfe 0x00004c9c 0x00004c3b 0x00004bdb 0x00004b7b 0x00004b1c + 0x00004abe 0x00004a60 0x00004a03 0x000049a7 0x0000494b 0x000048f0 0x00004896 0x0000483c + 0x000047e3 0x0000478a 0x00004733 0x000046db 0x00004685 0x0000462f 0x000045d9 0x00004584 + 0x00004530 0x000044dc 0x00004489 0x00004437 0x000043e5 0x00004393 0x00004342 0x000042f2 + 0x000042a2 0x00004253 0x00004204 0x000041b6 0x00004169 0x0000411b 0x000040cf 0x00004083 + 0x00004037 0x00003fec 0x00003fa1 0x00003f57 0x00003f0e 0x00003ec5 0x00003e7c 0x00003e34 + 0x00003dec 0x00003da5 0x00003d5e 0x00003d18 0x00003cd2 0x00003c8c 0x00003c48 0x00003c03 + 0x00003bbf 0x00003b7b 0x00003b38 0x00003af5 0x00003ab3 0x00003a71 0x00003a30 0x000039ef + 0x000039ae 0x0000396e 0x0000392e 0x000038ee 0x000038af 0x00003871 0x00003832 0x000037f5>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-LP097Qx1.dtsi b/include/dt-bindings/display/screen-timing/lcd-LP097Qx1.dtsi new file mode 100644 index 000000000000..9a11edbdd84e --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-LP097Qx1.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RockChip. DisplayPort screen LP097QX1 + * + */ + + +disp_timings: display-timings { + native-mode = <&timing0>; + timing0: timing0 { + screen-type = <SCREEN_EDP>; + out-face = <OUT_P666>; + clock-frequency = <205000000>; + hactive = <2048>; + vactive = <1536>; + hback-porch = <5>; + hfront-porch = <150>; + vback-porch = <9>; + vfront-porch = <3>; + hsync-len = <5>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-LP097Qx2.dtsi b/include/dt-bindings/display/screen-timing/lcd-LP097Qx2.dtsi new file mode 100644 index 000000000000..64f99e8f308f --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-LP097Qx2.dtsi @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * include/dt-bindings/display/screen-timing/lcd-LP097QX2.dtsi + * author: xbl@rock-chips.com + * create date: 2016-05-16 + * screen type: edp + * lcd model: lp097qx2 + * resolution: 1536 * 2048 + */ + +disp_timings: display-timings { + native-mode = <&timing0>; + timing0: timing0 { + screen-type = <SCREEN_EDP>; + out-face = <OUT_P888>; + clock-frequency = <200000000>; + hactive = <1536>; + vactive = <2048>; + hback-porch = <52>; + hfront-porch = <16>; + vback-porch = <3>; + vfront-porch = <7>; + hsync-len = <15>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + cabc-lut = < + /*gamma = 2.2*/ + 0x00000383 0x00000392 0x000003a2 0x000003b2 0x000003c2 0x000003d2 0x000003e2 0x000003f3 + 0x00000403 0x00000414 0x00000425 0x00000436 0x00000447 0x00000458 0x0000046a 0x0000047b + 0x0000048d 0x0000049f 0x000004b1 0x000004c3 0x000004d5 0x000004e8 0x000004fa 0x0000050d + 0x00000520 0x00000533 0x00000546 0x0000055a 0x0000056d 0x00000581 0x00000595 0x000005a9 + 0x000005bd 0x000005d1 0x000005e5 0x000005fa 0x0000060f 0x00000624 0x00000639 0x0000064e + 0x00000663 0x00000679 0x0000068e 0x000006a4 0x000006ba 0x000006d0 0x000006e6 0x000006fd + 0x00000713 0x0000072a 0x00000741 0x00000758 0x0000076f 0x00000786 0x0000079e 0x000007b6 + 0x000007cd 0x000007e5 0x000007fd 0x00000816 0x0000082e 0x00000847 0x0000085f 0x00000878 + 0x00000891 0x000008ab 0x000008c4 0x000008de 0x000008f7 0x00000911 0x0000092b 0x00000945 + 0x00000960 0x0000097a 0x00000995 0x000009af 0x000009ca 0x000009e6 0x00000a01 0x00000a1c + 0x00000a38 0x00000a54 0x00000a6f 0x00000a8c 0x00000aa8 0x00000ac4 0x00000ae1 0x00000afd + 0x00000b1a 0x00000b37 0x00000b54 0x00000b72 0x00000b8f 0x00000bad 0x00000bcb 0x00000be9 + 0x00000c07 0x00000c25 0x00000c44 0x00000c62 0x00000c81 0x00000ca0 0x00000cbf 0x00000cdf + 0x00000cfe 0x00000d1e 0x00000d3e 0x00000d5d 0x00000d7e 0x00000d9e 0x00000dbe 0x00000ddf + 0x00000e00 0x00000e21 0x00000e42 0x00000e63 0x00000e84 0x00000ea6 0x00000ec8 0x00000eea + 0x00000f0c 0x00000f2e 0x00000f50 0x00000f73 0x00000f96 0x00000fb9 0x00000fdc 0x00000fff + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-b080xan03.0-mipi.dtsi b/include/dt-bindings/display/screen-timing/lcd-b080xan03.0-mipi.dtsi new file mode 100644 index 000000000000..2d3010ae3c89 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-b080xan03.0-mipi.dtsi @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2014 ROCKCHIP, Inc. + * Licensed under GPLv2 or later. + * arch/arm/boot/dts/lcd-b080xan03.0-mipi.dtsi + * author: chenyf@rock-chips.com + * create date: 2014-09-11 + * lcd model: b080xan03.0 + * resolution: 768 X 1024 + * mipi channel: single + */ + +/* about mipi */ +disp_mipi_init: mipi_dsi_init{ + compatible = "rockchip,mipi_dsi_init"; + rockchip,screen_init = <0>; + rockchip,dsi_lane = <4>; + rockchip,dsi_hs_clk = <528>; + rockchip,mipi_dsi_num = <1>; +}; +disp_mipi_power_ctr: mipi_power_ctr { + compatible = "rockchip,mipi_power_ctr"; + mipi_lcd_rst:mipi_lcd_rst{ + compatible = "rockchip,lcd_rst"; + rockchip,gpios = <&gpio2 GPIO_C2 GPIO_ACTIVE_HIGH>; + rockchip,delay = <20>; + }; + /* mipi_lcd_en:mipi_lcd_en { + compatible = "rockchip,lcd_en"; + rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>; + rockchip,delay = <100>; + };*/ +}; +disp_mipi_init_cmds: screen-on-cmds { + compatible = "rockchip,screen-on-cmds"; + /*rockchip,cmd_debug = <1>; + rockchip,on-cmds1 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <HSDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0xb0 0x02>; + rockchip,cmd_delay = <0>; + }; + */ +}; + + +disp_timings: display-timings { + native-mode = <&timing0>; + compatible = "rockchip,display-timings"; + timing0: timing0 { + screen-type = <SCREEN_MIPI>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_P666>; + clock-frequency = <67000000>; + hactive = <768>; + vactive = <1024>; + hback-porch = <56>; + hfront-porch = <60>; + vback-porch = <30>; + vfront-porch = <36>; + hsync-len = <64>; + vsync-len = <14>; + + /* + hactive = <1024>; + vactive = <768>; + hback-porch = <56>; + hfront-porch = <60>; + vback-porch = <30>; + vfront-porch = <36>; + hsync-len = <64>; + vsync-len = <14>; + */ + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-b101ew05.dtsi b/include/dt-bindings/display/screen-timing/lcd-b101ew05.dtsi new file mode 100644 index 000000000000..ff15d837e166 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-b101ew05.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RockChip. LCD_B101ew05 + * + */ + + +disp_timings: display-timings { + native-mode = <&timing0>; + timing0: timing0 { + screen-type = <SCREEN_LVDS>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_D888_P666>; + color-mode = <COLOR_RGB>; + clock-frequency = <71000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <100>; + hfront-porch = <18>; + vback-porch = <8>; + vfront-porch = <6>; + hsync-len = <10>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + cabc-lut = < + /*gamma = 2.0*/ + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000002 + 0x00000002 0x00000002 0x00000002 0x00000002 0x00000003 0x00000003 0x00000003 0x00000003 + 0x00000004 0x00000004 0x00000004 0x00000004 0x00000005 0x00000005 0x00000005 0x00000005 + 0x00000006 0x00000006 0x00000006 0x00000007 0x00000007 0x00000007 0x00000008 0x00000008 + 0x00000009 0x00000009 0x00000009 0x0000000a 0x0000000a 0x0000000b 0x0000000b 0x0000000b + 0x0000000c 0x0000000c 0x0000000d 0x0000000d 0x0000000e 0x0000000e 0x0000000f 0x0000000f + 0x00000010 0x00000010 0x00000011 0x00000011 0x00000012 0x00000012 0x00000013 0x00000013 + 0x00000014 0x00000014 0x00000015 0x00000016 0x00000016 0x00000017 0x00000017 0x00000018 + 0x00000019 0x00000019 0x0000001a 0x0000001b 0x0000001b 0x0000001c 0x0000001d 0x0000001d + 0x0000001e 0x0000001f 0x0000001f 0x00000020 0x00000021 0x00000021 0x00000022 0x00000023 + 0x00000024 0x00000024 0x00000025 0x00000026 0x00000027 0x00000028 0x00000028 0x00000029 + 0x0000002a 0x0000002b 0x0000002c 0x0000002c 0x0000002d 0x0000002e 0x0000002f 0x00000030 + 0x00000031 0x00000032 0x00000032 0x00000033 0x00000034 0x00000035 0x00000036 0x00000037 + 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d 0x0000003e 0x0000003f + 0x00000040 0x00000041 0x00000042 0x00000043 0x00000044 0x00000045 0x00000046 0x00000047 + 0x00000048 0x00000049 0x0000004a 0x0000004b 0x0000004c 0x0000004d 0x0000004f 0x00000050 + 0x00000051 0x00000052 0x00000053 0x00000054 0x00000055 0x00000057 0x00000058 0x00000059 + 0x0000005a 0x0000005b 0x0000005d 0x0000005e 0x0000005f 0x00000060 0x00000061 0x00000063 + 0x00000064 0x00000065 0x00000066 0x00000068 0x00000069 0x0000006a 0x0000006c 0x0000006d + 0x0000006e 0x00000070 0x00000071 0x00000072 0x00000074 0x00000075 0x00000076 0x00000078 + 0x00000079 0x0000007a 0x0000007c 0x0000007d 0x0000007f 0x00000080 0x00000081 0x00000083 + 0x00000084 0x00000086 0x00000087 0x00000089 0x0000008a 0x0000008c 0x0000008d 0x0000008f + 0x00000090 0x00000092 0x00000093 0x00000095 0x00000096 0x00000098 0x00000099 0x0000009b + 0x0000009c 0x0000009e 0x000000a0 0x000000a1 0x000000a3 0x000000a4 0x000000a6 0x000000a8 + 0x000000a9 0x000000ab 0x000000ac 0x000000ae 0x000000b0 0x000000b1 0x000000b3 0x000000b5 + 0x000000b6 0x000000b8 0x000000ba 0x000000bc 0x000000bd 0x000000bf 0x000000c1 0x000000c3 + 0x000000c4 0x000000c6 0x000000c8 0x000000ca 0x000000cb 0x000000cd 0x000000cf 0x000000d1 + 0x000000d3 0x000000d4 0x000000d6 0x000000d8 0x000000da 0x000000dc 0x000000de 0x000000e0 + 0x000000e1 0x000000e3 0x000000e5 0x000000e7 0x000000e9 0x000000eb 0x000000ed 0x000000ef + 0x000000f1 0x000000f3 0x000000f5 0x000000f7 0x000000f9 0x000000fb 0x000000fd 0x000000ff>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-box.dtsi b/include/dt-bindings/display/screen-timing/lcd-box.dtsi new file mode 100644 index 000000000000..25368db39d29 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-box.dtsi @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RockChip. LCD_BOX + * + */ + + disp_power_ctr: power_ctr { + /* rockchip,debug = <0>; + lcd_en:lcd_en { + rockchip,power_type = <GPIO>; + gpios = <&gpio0 GPIO_B0 GPIO_ACTIVE_HIGH>; + rockchip,delay = <10>; + }; + + bl_en:bl_en { + rockchip,power_type = <GPIO>; + gpios = <&gpio0 GPIO_A2 GPIO_ACTIVE_HIGH>; + rockchip,delay = <10>; + }; + + bl_ctr:bl_ctr { + rockchip,power_type = <GPIO>; + gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>; + rockchip,delay = <10>; + }; + + lcd_rst:lcd_rst { + rockchip,power_type = <REGULATOR>; + rockchip,delay = <5>; + };*/ + +}; + +disp_timings: display-timings { + native-mode = <&timing0>; + timing0: timing0 { + screen-type = <SCREEN_RGB>; + out-face = <OUT_P888>; + color-mode = <COLOR_YCBCR>; + clock-frequency = <74250000>; + hactive = <1280>; + vactive = <720>; + hback-porch = <220>; + hfront-porch = <110>; + vback-porch = <20>; + vfront-porch = <5>; + hsync-len = <40>; + vsync-len = <5>; + hsync-active = <1>; + vsync-active = <1>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; + timing1: timing1 { + screen-type = <SCREEN_RGB>; + out-face = <OUT_P888>; + color-mode = <COLOR_YCBCR>; + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <148>; + hfront-porch = <88>; + vback-porch = <36>; + vfront-porch = <4>; + hsync-len = <44>; + vsync-len = <5>; + hsync-active = <1>; + vsync-active = <1>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; + timing2: timing2 { + screen-type = <SCREEN_RGB>; + out-face = <OUT_P888>; + color-mode = <COLOR_YCBCR>; + clock-frequency = <297000000>; + hactive = <3840>; + vactive = <2160>; + hback-porch = <296>; + hfront-porch = <176>; + vback-porch = <72>; + vfront-porch = <8>; + hsync-len = <88>; + vsync-len = <10>; + hsync-active = <1>; + vsync-active = <1>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-fpga-800x480-rgb.dtsi b/include/dt-bindings/display/screen-timing/lcd-fpga-800x480-rgb.dtsi new file mode 100644 index 000000000000..798262d3654f --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-fpga-800x480-rgb.dtsi @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +disp_timings: display-timings { + native-mode = <&timing0>; + timing0: timing0 { + screen-type = <SCREEN_RGB>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_D888_P666>; + color-mode = <COLOR_RGB>; + clock-frequency = <71000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <206>; + hfront-porch = <1>; + vback-porch = <25>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + cabc-lut = < + /*gamma = 2.0*/ + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000002 + 0x00000002 0x00000002 0x00000002 0x00000002 0x00000003 0x00000003 0x00000003 0x00000003 + 0x00000004 0x00000004 0x00000004 0x00000004 0x00000005 0x00000005 0x00000005 0x00000005 + 0x00000006 0x00000006 0x00000006 0x00000007 0x00000007 0x00000007 0x00000008 0x00000008 + 0x00000009 0x00000009 0x00000009 0x0000000a 0x0000000a 0x0000000b 0x0000000b 0x0000000b + 0x0000000c 0x0000000c 0x0000000d 0x0000000d 0x0000000e 0x0000000e 0x0000000f 0x0000000f + 0x00000010 0x00000010 0x00000011 0x00000011 0x00000012 0x00000012 0x00000013 0x00000013 + 0x00000014 0x00000014 0x00000015 0x00000016 0x00000016 0x00000017 0x00000017 0x00000018 + 0x00000019 0x00000019 0x0000001a 0x0000001b 0x0000001b 0x0000001c 0x0000001d 0x0000001d + 0x0000001e 0x0000001f 0x0000001f 0x00000020 0x00000021 0x00000021 0x00000022 0x00000023 + 0x00000024 0x00000024 0x00000025 0x00000026 0x00000027 0x00000028 0x00000028 0x00000029 + 0x0000002a 0x0000002b 0x0000002c 0x0000002c 0x0000002d 0x0000002e 0x0000002f 0x00000030 + 0x00000031 0x00000032 0x00000032 0x00000033 0x00000034 0x00000035 0x00000036 0x00000037 + 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d 0x0000003e 0x0000003f + 0x00000040 0x00000041 0x00000042 0x00000043 0x00000044 0x00000045 0x00000046 0x00000047 + 0x00000048 0x00000049 0x0000004a 0x0000004b 0x0000004c 0x0000004d 0x0000004f 0x00000050 + 0x00000051 0x00000052 0x00000053 0x00000054 0x00000055 0x00000057 0x00000058 0x00000059 + 0x0000005a 0x0000005b 0x0000005d 0x0000005e 0x0000005f 0x00000060 0x00000061 0x00000063 + 0x00000064 0x00000065 0x00000066 0x00000068 0x00000069 0x0000006a 0x0000006c 0x0000006d + 0x0000006e 0x00000070 0x00000071 0x00000072 0x00000074 0x00000075 0x00000076 0x00000078 + 0x00000079 0x0000007a 0x0000007c 0x0000007d 0x0000007f 0x00000080 0x00000081 0x00000083 + 0x00000084 0x00000086 0x00000087 0x00000089 0x0000008a 0x0000008c 0x0000008d 0x0000008f + 0x00000090 0x00000092 0x00000093 0x00000095 0x00000096 0x00000098 0x00000099 0x0000009b + 0x0000009c 0x0000009e 0x000000a0 0x000000a1 0x000000a3 0x000000a4 0x000000a6 0x000000a8 + 0x000000a9 0x000000ab 0x000000ac 0x000000ae 0x000000b0 0x000000b1 0x000000b3 0x000000b5 + 0x000000b6 0x000000b8 0x000000ba 0x000000bc 0x000000bd 0x000000bf 0x000000c1 0x000000c3 + 0x000000c4 0x000000c6 0x000000c8 0x000000ca 0x000000cb 0x000000cd 0x000000cf 0x000000d1 + 0x000000d3 0x000000d4 0x000000d6 0x000000d8 0x000000da 0x000000dc 0x000000de 0x000000e0 + 0x000000e1 0x000000e3 0x000000e5 0x000000e7 0x000000e9 0x000000eb 0x000000ed 0x000000ef + 0x000000f1 0x000000f3 0x000000f5 0x000000f7 0x000000f9 0x000000fb 0x000000fd 0x000000ff>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-h381dln01-1080x1200-double.dtsi b/include/dt-bindings/display/screen-timing/lcd-h381dln01-1080x1200-double.dtsi new file mode 100644 index 000000000000..6fe841cdf720 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-h381dln01-1080x1200-double.dtsi @@ -0,0 +1,317 @@ +/* + * + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * author: xubilv <xbl@rock-chips.com> + * create date: 2016-08-11 + * resolution: 1080 X 1200 + * mipi channel: double + */ + +/* about mipi */ +disp_mipi_init: mipi_dsi_init { + compatible = "rockchip,mipi_dsi_init"; + rockchip,screen_init = <1>; + rockchip,dsi_lane = <4>; + rockchip,dsi_hs_clk = <970>; + rockchip,mipi_dsi_num = <2>; +}; + +disp_mipi_power_ctr: mipi_power_ctr { + compatible = "rockchip,mipi_power_ctr"; + + /*mipi_lcd_rst:mipi_lcd_rst { + compatible = "rockchip,lcd_rst"; + rockchip,gpios = <&gpio7 GPIO_A1 GPIO_ACTIVE_LOW>; + rockchip,delay = <0>; + }; + + mipi_lcd_avdd:mipi_lcd_avdd { + compatible = "rockchip,lcd_avdd"; + rockchip,gpios = <&gpio7 GPIO_A2 GPIO_ACTIVE_HIGH>; + rockchip,delay = <0>; + }; + + mipi_lcd_ovdd:mipi_lcd_ovdd { + compatible = "rockchip,lcd_ovdd"; + rockchip,gpios = <&gpio7 GPIO_A3 GPIO_ACTIVE_HIGH>; + rockchip,delay = <0>; + }; + + mipi_lcd_ovss:mipi_lcd_ovss { + compatible = "rockchip,lcd_ovss"; + rockchip,gpios = <&gpio7 GPIO_B0 GPIO_ACTIVE_HIGH>; + rockchip,delay = <0>; + }; + mipi_lcd_rst:mipi_lcd_rst{ + compatible = "rockchip,lcd_rst"; + rockchip,gpios = <&gpio7 GPIO_A1 GPIO_ACTIVE_LOW>; + rockchip,delay = <100>; + }; + mipi_lcd_en:mipi_lcd_en { + compatible = "rockchip,lcd_en"; + rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>; + rockchip,delay = <100>; + };*/ +}; + +disp_mipi_init_cmds: screen-on-cmds { + compatible = "rockchip,screen-on-cmds"; + rockchip,cmd_debug = <0>; + rockchip,on-cmds1 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xFE 0x07>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds2 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x00 0xEC>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds3 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x0B 0xEC>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds4 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x16 0xEC>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds5 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x21 0xEC>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds6 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x2D 0xEC>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds7 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xA9 0xBA>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds8 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xAB 0x06>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds9 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xBB 0x84>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds10 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xBC 0x1C>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds11 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xFE 0x08>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds12 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x07 0x1A>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds13 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xFE 0x0A>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds14 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x2A 0x1B>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds15 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xFE 0x0D>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds16 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x02 0x65>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds17 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x4D 0x41>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds18 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x4B 0x0F>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds19 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x53 0xFE>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds20 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xFE 0x00>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds21 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xC2 0x03>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds22 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x51 0xFF>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds23 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x05 0x11>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds24 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x05 0x29>; + rockchip,cmd_delay = <10>; + }; +}; + +disp_timings: display-timings { + native-mode = <&timing0>; + compatible = "rockchip,display-timings"; + timing0: timing0 { + screen-type = <SCREEN_DUAL_MIPI>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_P888>; + clock-frequency = <231795000>; /* 185436000 60fps, 231795000 75fps, 278154000 90fps */ + hactive = <2160>; //1080 + vactive = <1200>; + hback-porch = <180>; + hfront-porch = <200>; + vback-porch = <3>; + vfront-porch = <6>; + hsync-len = <10>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + screen-width = <130>; + screen-hight = <72>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-h381dln01-1080x1200.dtsi b/include/dt-bindings/display/screen-timing/lcd-h381dln01-1080x1200.dtsi new file mode 100644 index 000000000000..994809469890 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-h381dln01-1080x1200.dtsi @@ -0,0 +1,314 @@ +/* + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * author: xubilv <xbl@rock-chips.com> + * create date: 2016-08-11 + * resolution: 1080 X 1200 + * mipi channel: single + */ + +disp_mipi_init: mipi_dsi_init { + compatible = "rockchip,mipi_dsi_init"; + rockchip,screen_init = <1>; + rockchip,dsi_lane = <4>; + rockchip,dsi_hs_clk = <970>; + rockchip,mipi_dsi_num = <1>; +}; + +disp_mipi_power_ctr: mipi_power_ctr { + compatible = "rockchip,mipi_power_ctr"; + + /*mipi_lcd_rst:mipi_lcd_rst { + compatible = "rockchip,lcd_rst"; + rockchip,gpios = <&gpio7 GPIO_A1 GPIO_ACTIVE_LOW>; + rockchip,delay = <0>; + }; + + mipi_lcd_avdd:mipi_lcd_avdd { + compatible = "rockchip,lcd_avdd"; + rockchip,gpios = <&gpio7 GPIO_A2 GPIO_ACTIVE_HIGH>; + rockchip,delay = <0>; + }; + + mipi_lcd_ovdd:mipi_lcd_ovdd { + compatible = "rockchip,lcd_ovdd"; + rockchip,gpios = <&gpio7 GPIO_A3 GPIO_ACTIVE_HIGH>; + rockchip,delay = <0>; + }; + + mipi_lcd_ovss:mipi_lcd_ovss { + compatible = "rockchip,lcd_ovss"; + rockchip,gpios = <&gpio7 GPIO_B0 GPIO_ACTIVE_HIGH>; + rockchip,delay = <0>; + }; + + mipi_lcd_rst:mipi_lcd_rst { + compatible = "rockchip,lcd_rst"; + rockchip,gpios = <&gpio7 GPIO_A1 GPIO_ACTIVE_LOW>; + rockchip,delay = <100>; + }; + + mipi_lcd_en:mipi_lcd_en { + compatible = "rockchip,lcd_en"; + rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>; + rockchip,delay = <100>; + };*/ +}; + +disp_mipi_init_cmds: screen-on-cmds { + compatible = "rockchip,screen-on-cmds"; + rockchip,cmd_debug = <0>; + rockchip,on-cmds1 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0xFE 0x07>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds2 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x00 0xEC>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds3 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x0B 0xEC>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds4 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x16 0xEC>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds5 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x21 0xEC>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds6 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x2D 0xEC>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds7 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0xA9 0xBA>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds8 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0xAB 0x06>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds9 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0xBB 0x84>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds10 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0xBC 0x1C>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds11 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0xFE 0x08>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds12 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x07 0x1A>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds13 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0xFE 0x0A>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds14 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x2A 0x1B>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds15 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0xFE 0x0D>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds16 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x02 0x65>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds17 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x4D 0x41>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds18 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x4B 0x0F>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds19 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x53 0xFE>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds20 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0xFE 0x00>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds21 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0xC2 0x03>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds22 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x51 0xFF>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds23 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x05 0x11>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds24 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x05 0x29>; + rockchip,cmd_delay = <10>; + }; +}; + +disp_timings: display-timings { + native-mode = <&timing0>; + compatible = "rockchip,display-timings"; + timing0: timing0 { + screen-type = <SCREEN_MIPI>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_P888>; + clock-frequency = <139000000>;//139 + hactive = <1080>; + vactive = <1200>; + hback-porch = <90>; + hfront-porch = <100>; + vback-porch = <3>; + vfront-porch = <6>; + hsync-len = <5>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-h546dlb01-mipi.dtsi b/include/dt-bindings/display/screen-timing/lcd-h546dlb01-mipi.dtsi new file mode 100644 index 000000000000..19d427c71e5f --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-h546dlb01-mipi.dtsi @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * include/dt-bindings/display/screen-timing/lcd-h546dlb01-mipi.dtsi + * author: bivvy.bi@rock-chips.com + * create date: 2016-09-02 + * lcd Model: AUO h546dlb01 + * resolution: 1080 X 1920 + * mipi channel: single + */ + +disp_mipi_init: mipi_dsi_init { + compatible = "rockchip,mipi_dsi_init"; + rockchip,screen_init = <1>; + rockchip,dsi_lane = <4>; + rockchip,dsi_hs_clk = <1050>; + rockchip,mipi_dsi_num = <1>; +}; + +disp_mipi_power_ctr: mipi_power_ctr { + compatible = "rockchip,mipi_power_ctr"; +}; + +disp_mipi_init_cmds: screen-on-cmds { + compatible = "rockchip,screen-on-cmds"; + rockchip,cmd_debug = <1>; + + rockchip,on-cmds1 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x23 0xFE 0x08>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds2 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x23 0x03 0x40>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds3 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x23 0x07 0x1a>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds4 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x23 0xfe 0x0d>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds5 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x23 0x53 0xfe>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds6 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x23 0xfe 0x00>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds7 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x23 0x51 0xff>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds8 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x23 0xc2 0x03>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds9 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x05 dcs_exit_sleep_mode>; + rockchip,cmd_delay = <120>; + }; + + rockchip,on-cmds10 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x05 dcs_set_display_on>; + rockchip,cmd_delay = <0>; + }; +}; + +disp_timings: display-timings { + native-mode = <&timing0>; + compatible = "rockchip,display-timings"; + + timing0: timing0 { + screen-type = <SCREEN_MIPI>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_P888>; + clock-frequency = <153000000>; + hactive = <1080>; + vactive = <1920>; + hback-porch = <24>; + hfront-porch = <8>; + vback-porch = <7>; + vfront-porch = <12>; + hsync-len = <5>; + vsync-len = <5>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + screen-width = <68>; + screen-hight = <120>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-ld089wu1-mipi.dtsi b/include/dt-bindings/display/screen-timing/lcd-ld089wu1-mipi.dtsi new file mode 100644 index 000000000000..a20e51a37d69 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-ld089wu1-mipi.dtsi @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2014 ROCKCHIP, Inc. + * arch/arm/boot/dts/lcd-lq070m1sx01-mipi.dtsi + * author: libing@rock-chips.com + * create date: 2014-04-15 + * lcd model: ld089wu1 + * resolution: 1920 X 1200 + * mipi channel: single + */ + +/* about mipi */ +disp_mipi_init: mipi_dsi_init{ + compatible = "rockchip,mipi_dsi_init"; + rockchip,screen_init = <0>; + rockchip,dsi_lane = <4>; + rockchip,dsi_hs_clk = <1000>; + rockchip,mipi_dsi_num = <1>; +}; +disp_mipi_power_ctr: mipi_power_ctr { + compatible = "rockchip,mipi_power_ctr"; + /*mipi_lcd_rst:mipi_lcd_rst{ + compatible = "rockchip,lcd_rst"; + rockchip,gpios = <&gpio2 GPIO_B7 GPIO_ACTIVE_LOW>; + rockchip,delay = <100>; + }; + mipi_lcd_en:mipi_lcd_en { + compatible = "rockchip,lcd_en"; + rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>; + rockchip,delay = <100>; + };*/ +}; +disp_mipi_init_cmds: screen-on-cmds { + compatible = "rockchip,screen-on-cmds"; + /*rockchip,cmd_debug = <1>; + rockchip,on-cmds1 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <HSDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0xb0 0x02>; + rockchip,cmd_delay = <0>; + }; + */ +}; + + +disp_timings: display-timings { + native-mode = <&timing0>; + compatible = "rockchip,display-timings"; + timing0: timing0 { + screen-type = <SCREEN_MIPI>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_P888>; + clock-frequency = <145000000>; + hactive = <1920>; + vactive = <1200>; + hback-porch = <16>; + hfront-porch = <24>; + vback-porch = <10>; + vfront-porch = <16>; + hsync-len = <10>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + cabc-lut = < + /*gamma = 2.2*/ + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000001 + 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 + 0x00000001 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 + 0x00000003 0x00000003 0x00000003 0x00000003 0x00000003 0x00000004 0x00000004 0x00000004 + 0x00000004 0x00000005 0x00000005 0x00000005 0x00000005 0x00000006 0x00000006 0x00000006 + 0x00000006 0x00000007 0x00000007 0x00000007 0x00000008 0x00000008 0x00000008 0x00000009 + 0x00000009 0x00000009 0x0000000a 0x0000000a 0x0000000b 0x0000000b 0x0000000b 0x0000000c + 0x0000000c 0x0000000d 0x0000000d 0x0000000d 0x0000000e 0x0000000e 0x0000000f 0x0000000f + 0x00000010 0x00000010 0x00000011 0x00000011 0x00000012 0x00000012 0x00000013 0x00000013 + 0x00000014 0x00000014 0x00000015 0x00000016 0x00000016 0x00000017 0x00000017 0x00000018 + 0x00000019 0x00000019 0x0000001a 0x0000001a 0x0000001b 0x0000001c 0x0000001c 0x0000001d + 0x0000001e 0x0000001e 0x0000001f 0x00000020 0x00000021 0x00000021 0x00000022 0x00000023 + 0x00000023 0x00000024 0x00000025 0x00000026 0x00000027 0x00000027 0x00000028 0x00000029 + 0x0000002a 0x0000002b 0x0000002b 0x0000002c 0x0000002d 0x0000002e 0x0000002f 0x00000030 + 0x00000031 0x00000031 0x00000032 0x00000033 0x00000034 0x00000035 0x00000036 0x00000037 + 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d 0x0000003e 0x0000003f + 0x00000040 0x00000041 0x00000042 0x00000043 0x00000044 0x00000045 0x00000046 0x00000047 + 0x00000049 0x0000004a 0x0000004b 0x0000004c 0x0000004d 0x0000004e 0x0000004f 0x00000051 + 0x00000052 0x00000053 0x00000054 0x00000055 0x00000057 0x00000058 0x00000059 0x0000005a + 0x0000005b 0x0000005d 0x0000005e 0x0000005f 0x00000061 0x00000062 0x00000063 0x00000064 + 0x00000066 0x00000067 0x00000069 0x0000006a 0x0000006b 0x0000006d 0x0000006e 0x0000006f + 0x00000071 0x00000072 0x00000074 0x00000075 0x00000077 0x00000078 0x00000079 0x0000007b + 0x0000007c 0x0000007e 0x0000007f 0x00000081 0x00000082 0x00000084 0x00000085 0x00000087 + 0x00000089 0x0000008a 0x0000008c 0x0000008d 0x0000008f 0x00000091 0x00000092 0x00000094 + 0x00000095 0x00000097 0x00000099 0x0000009a 0x0000009c 0x0000009e 0x0000009f 0x000000a1 + 0x000000a3 0x000000a5 0x000000a6 0x000000a8 0x000000aa 0x000000ac 0x000000ad 0x000000af + 0x000000b1 0x000000b3 0x000000b5 0x000000b6 0x000000b8 0x000000ba 0x000000bc 0x000000be + 0x000000c0 0x000000c2 0x000000c4 0x000000c5 0x000000c7 0x000000c9 0x000000cb 0x000000cd + 0x000000cf 0x000000d1 0x000000d3 0x000000d5 0x000000d7 0x000000d9 0x000000db 0x000000dd + 0x000000df 0x000000e1 0x000000e3 0x000000e5 0x000000e7 0x000000ea 0x000000ec 0x000000ee + 0x000000f0 0x000000f2 0x000000f4 0x000000f6 0x000000f8 0x000000fb 0x000000fd 0x000000ff>; + cabc-gamma-base = < + /*gamma = 2.2*/ + 0x00010000 0x0000fdd0 0x0000fba8 0x0000f986 0x0000f76a 0x0000f556 0x0000f347 0x0000f140 + 0x0000ef3e 0x0000ed43 0x0000eb4e 0x0000e95e 0x0000e775 0x0000e592 0x0000e3b4 0x0000e1dc + 0x0000e009 0x0000de3c 0x0000dc74 0x0000dab2 0x0000d8f4 0x0000d73c 0x0000d589 0x0000d3db + 0x0000d232 0x0000d08d 0x0000ceee 0x0000cd53 0x0000cbbc 0x0000ca2b 0x0000c89d 0x0000c714 + 0x0000c590 0x0000c410 0x0000c294 0x0000c11c 0x0000bfa8 0x0000be39 0x0000bccd 0x0000bb65 + 0x0000ba01 0x0000b8a1 0x0000b745 0x0000b5ed 0x0000b498 0x0000b347 0x0000b1f9 0x0000b0af + 0x0000af68 0x0000ae25 0x0000ace5 0x0000aba8 0x0000aa6f 0x0000a939 0x0000a806 0x0000a6d7 + 0x0000a5aa 0x0000a480 0x0000a35a 0x0000a236 0x0000a116 0x00009ff8 0x00009edd 0x00009dc5 + 0x00009cb0 0x00009b9e 0x00009a8e 0x00009981 0x00009877 0x0000976f 0x0000966a 0x00009567 + 0x00009467 0x0000936a 0x0000926f 0x00009176 0x00009080 0x00008f8c 0x00008e9a 0x00008dab + 0x00008cbe 0x00008bd3 0x00008aea 0x00008a04 0x00008920 0x0000883e 0x0000875e 0x00008680 + 0x000085a4 0x000084ca 0x000083f3 0x0000831d 0x00008249 0x00008177 0x000080a7 0x00007fd9 + 0x00007f0d 0x00007e42 0x00007d7a 0x00007cb3 0x00007bee 0x00007b2b 0x00007a6a 0x000079aa + 0x000078ec 0x0000782f 0x00007775 0x000076bc 0x00007604 0x0000754f 0x0000749a 0x000073e8 + 0x00007337 0x00007287 0x000071d9 0x0000712c 0x00007081 0x00006fd8 0x00006f30 0x00006e89 + 0x00006de4 0x00006d40 0x00006c9d 0x00006bfc 0x00006b5c 0x00006abe 0x00006a21 0x00006985 + 0x000068ea 0x00006851 0x000067b9 0x00006722 0x0000668d 0x000065f9 0x00006566 0x000064d4 + 0x00006443 0x000063b4 0x00006325 0x00006298 0x0000620c 0x00006181 0x000060f8 0x0000606f + 0x00005fe7 0x00005f61 0x00005edb 0x00005e57 0x00005dd4 0x00005d51 0x00005cd0 0x00005c50 + 0x00005bd1 0x00005b52 0x00005ad5 0x00005a59 0x000059de 0x00005963 0x000058ea 0x00005871 + 0x000057fa 0x00005783 0x0000570d 0x00005699 0x00005625 0x000055b2 0x0000553f 0x000054ce + 0x0000545d 0x000053ee 0x0000537f 0x00005311 0x000052a4 0x00005238 0x000051cc 0x00005161 + 0x000050f7 0x0000508e 0x00005026 0x00004fbe 0x00004f57 0x00004ef1 0x00004e8c 0x00004e27 + 0x00004dc3 0x00004d60 0x00004cfe 0x00004c9c 0x00004c3b 0x00004bdb 0x00004b7b 0x00004b1c + 0x00004abe 0x00004a60 0x00004a03 0x000049a7 0x0000494b 0x000048f0 0x00004896 0x0000483c + 0x000047e3 0x0000478a 0x00004733 0x000046db 0x00004685 0x0000462f 0x000045d9 0x00004584 + 0x00004530 0x000044dc 0x00004489 0x00004437 0x000043e5 0x00004393 0x00004342 0x000042f2 + 0x000042a2 0x00004253 0x00004204 0x000041b6 0x00004169 0x0000411b 0x000040cf 0x00004083 + 0x00004037 0x00003fec 0x00003fa1 0x00003f57 0x00003f0e 0x00003ec5 0x00003e7c 0x00003e34 + 0x00003dec 0x00003da5 0x00003d5e 0x00003d18 0x00003cd2 0x00003c8c 0x00003c48 0x00003c03 + 0x00003bbf 0x00003b7b 0x00003b38 0x00003af5 0x00003ab3 0x00003a71 0x00003a30 0x000039ef + 0x000039ae 0x0000396e 0x0000392e 0x000038ee 0x000038af 0x00003871 0x00003832 0x000037f5>; + }; + }; diff --git a/include/dt-bindings/display/screen-timing/lcd-lq070m1sx01-mipi.dtsi b/include/dt-bindings/display/screen-timing/lcd-lq070m1sx01-mipi.dtsi new file mode 100644 index 000000000000..5f83e3b0d407 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-lq070m1sx01-mipi.dtsi @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2014 ROCKCHIP, Inc. + * arch/arm/boot/dts/lcd-lq070m1sx01-mipi.dtsi + * author: libing@rock-chips.com + * create date: 2014-04-15 + * lcd model: lq070m1sx01 + * resolution: 1920 X 1200 + * mipi channel: dual + */ + +/* about mipi */ +disp_mipi_init: mipi_dsi_init{ + compatible = "rockchip,mipi_dsi_init"; + rockchip,screen_init = <1>; + rockchip,dsi_lane = <2>; + rockchip,dsi_hs_clk = <1000>; + rockchip,mipi_dsi_num = <2>; +}; +disp_mipi_power_ctr: mipi_power_ctr { + compatible = "rockchip,mipi_power_ctr"; + mipi_lcd_rst:mipi_lcd_rst{ + compatible = "rockchip,lcd_rst"; + rockchip,gpios = <&gpio2 GPIO_B7 GPIO_ACTIVE_HIGH>; + rockchip,delay = <10>; + }; + mipi_lcd_en:mipi_lcd_en { + compatible = "rockchip,lcd_en"; + rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>; + rockchip,delay = <10>; + }; +}; +disp_mipi_init_cmds: screen-on-cmds { + rockchip,cmd_debug = <0>; + compatible = "rockchip,screen-on-cmds"; + rockchip,on-cmds1 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xb0 0x02>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds2 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xb1 0x21>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds3 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xb0 0x06>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds4 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xb1 0x21>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds5 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xb4 0x15>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds6 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xb9 0x40>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds7 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0xb0 0x00>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds8 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x05 dcs_set_display_on>; + rockchip,cmd_delay = <10>; + }; + rockchip,on-cmds9 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,data_type = <DATA_TYPE_DCS>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x05 dcs_exit_sleep_mode>; + rockchip,cmd_delay = <10>; + }; +}; + +disp_timings: display-timings { + native-mode = <&timing0>; + compatible = "rockchip,display-timings"; + timing0: timing0 { + screen-type = <SCREEN_DUAL_MIPI>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_P888>; + clock-frequency = <150000000>; + hactive = <1200>; + vactive = <1920>; + hsync-len = <8>; + hback-porch = <32>; + hfront-porch = <156>; + + vsync-len = <2>; + vback-porch = <6>; + vfront-porch = <12>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-ls055r1sx04-mipi.dtsi b/include/dt-bindings/display/screen-timing/lcd-ls055r1sx04-mipi.dtsi new file mode 100644 index 000000000000..7e93e7e1c300 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-ls055r1sx04-mipi.dtsi @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * include/dt-bindings/display/screen-timing/lcd-ls055r1sx04-mipi.dtsi + * author: xbl@rock-chips.com + * create date: 2016-05-16 + * lcd model: sharp ls055r1sx04 + * resolution: 1440 * 2560 + * mipi channel: double + */ + +/* about mipi */ +disp_mipi_init: mipi_dsi_init{ + compatible = "rockchip,mipi_dsi_init"; + rockchip,screen_init = <1>; + rockchip,dsi_lane = <4>; + rockchip,dsi_hs_clk = <850>; + rockchip,mipi_dsi_num = <2>; +}; + +disp_mipi_power_ctr: mipi_power_ctr { + compatible = "rockchip,mipi_power_ctr"; + /* mipi_lcd_rst:mipi_lcd_rst{ + compatible = "rockchip,lcd_rst"; + rockchip,gpios = <&gpio2 GPIO_B7 GPIO_ACTIVE_LOW>; + rockchip,delay = <100>; + }; + mipi_lcd_en:mipi_lcd_en { + compatible = "rockchip,lcd_en"; + rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>; + rockchip,delay = <100>; + }; + */ +}; + +disp_mipi_init_cmds: screen-on-cmds { + compatible = "rockchip,screen-on-cmds"; + rockchip,cmd_debug = <1>; + rockchip,on-cmds1 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xb0 0x00>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds2 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xd6 0x01>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds3 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xb3 0x18>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds4 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x39 0x51 0xff>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds5 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x39 0x53 0x0c>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds6 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x39 0x35 0x00>; + rockchip,cmd_delay = <0>; + }; +/* + rockchip,on-cmds7 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xb0 0x03>; + rockchip,cmd_delay = <0>; + }; +*/ + rockchip,on-cmds7 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x05 dcs_set_display_on>; + rockchip,cmd_delay = <10>; + }; + rockchip,on-cmds8 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x05 dcs_exit_sleep_mode>; + rockchip,cmd_delay = <10>; + }; +}; + +disp_timings: display-timings { + native-mode = <&timing0>; + compatible = "rockchip,display-timings"; + timing0: timing0 { + screen-type = <SCREEN_DUAL_MIPI>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_P888>; + clock-frequency = <245000000>; + hactive = <1440>; + vactive = <2560>; + hback-porch = <40>; + hfront-porch = <100>; + vback-porch = <3>; + vfront-porch = <4>; + hsync-len = <6>; + vsync-len = <1>; + screen-width = <68>; + screen-hight = <120>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-mipi-RK055AUWI5003-1440X2560.dtsi b/include/dt-bindings/display/screen-timing/lcd-mipi-RK055AUWI5003-1440X2560.dtsi new file mode 100644 index 000000000000..5d021df56366 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-mipi-RK055AUWI5003-1440X2560.dtsi @@ -0,0 +1,288 @@ +/* + * + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * author: lyx@rock-chips.com + * create date: 2016-04-05 + * resolution: 1440 X 2560 + * mipi channel: single + */ + +/* about mipi */ +disp_mipi_init: mipi_dsi_init{ + compatible = "rockchip,mipi_dsi_init"; + rockchip,screen_init = <1>; + rockchip,dsi_lane = <4>; + rockchip,dsi_hs_clk = <1000>; + rockchip,mipi_dsi_num = <2>; +}; + +disp_mipi_power_ctr: mipi_power_ctr { + compatible = "rockchip,mipi_power_ctr"; + /* + mipi_lcd_rst:mipi_lcd_rst { + compatible = "rockchip,lcd_rst"; + rockchip,gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; + rockchip,delay = <100>; + }; + + mipi_lcd_en:mipi_lcd_en { + compatible = "rockchip,lcd_en"; + rockchip,gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + rockchip,delay = <20>; + }; + */ +}; + +disp_mipi_init_cmds: screen-on-cmds { + rockchip,cmd_debug = <0>; + compatible = "rockchip,screen-on-cmds"; + rockchip,on-cmds1 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x23 0xb0 0x00>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds2 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x23 0xd6 0x01>; + rockchip,cmd_delay = <120>; + }; + + rockchip,on-cmds3 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xb3 0x18 0x00 0x00>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds4 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x23 0xb4 0x00>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds5 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xb6 0x3a 0xd3>; + rockchip,cmd_delay = <20>; + }; + + rockchip,on-cmds6 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x23 0xbe 0x04>; + rockchip,cmd_delay = <120>; + }; + + rockchip,on-cmds7 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xc3 0x00 0x00 0x00>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds8 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x23 0xc5 0x00>; + rockchip,cmd_delay = <20>; + }; + + rockchip,on-cmds9 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xc0 0x00 0x00 0x00 0x00>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds10 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xc1 0x00 0x61 0x00 0x30 0x29 0x10 0x19 0x63 0x61 0xb4 0xe6 0xdc 0x7b 0xef 0x39 0xd7 0xda 0x08 0x8c 0xb1 0x08 0x54 0x82 0x00 0x00 0x00 0x00 0x00 0x02 0x63 0x27 0x03 0x00 0xff 0x11>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds11 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xc2 0x08 0x0a 0x00 0x04 0x04 0xf0 0x00 0x04>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds12 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xc4 0x70 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x05 0x01>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds13 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xc6 0x5a 0x00 0x2d 0x03 0x01 0x02 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x06 0x15 0x08 0x5a>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds14 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xcb 0xff 0xff 0xff 0xff 0x00 0x00 0x00 0x00 0x54 0xe0 0x07 0x2a 0xe0 0x00 0x00>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds15 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x23 0xcc 0x32>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds16 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xd7 0x82 0xff 0x21 0x8e 0x8c 0xf1 0x87 0x3f 0x7e 0x10 0x00 0x00 0x8f>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds17 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xd9 0x00 0x00>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds18 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xd0 0x11 0x17 0x14 0xfd>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds19 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xd2 0xcd 0x2b 0x2b 0x33 0x12 0x33 0x33 0x33 0x77 0x77 0x33 0x33 0x33 0x00 0x00 0x00>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds20 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xd5 0x06 0x00 0x00 0x01 0x40 0x01 0x40>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds21 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xc7 0x00 0x10 0x17 0x21 0x2f 0x3d 0x48 0x58 0x3c 0x44 0x50 0x5d 0x66 0x6c 0x75 0x00 0x10 0x17 0x21 0x2f 0x3d 0x48 0x58 0x3c 0x44 0x50 0x5d 0x66 0x6c 0x75>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds22 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x05 0x29>; + rockchip,cmd_delay = <120>; + }; + + rockchip,on-cmds23 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x05 0x11>; + rockchip,cmd_delay = <100>; + }; +}; + +disp_timings: display-timings { + native-mode = <&timing0>; + compatible = "rockchip,display-timings"; + timing0: timing0 { + screen-type = <SCREEN_DUAL_MIPI>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_P888>; + clock-frequency = <245000000>; + hactive = <1440>; + vactive = <2560>; + hback-porch = <16>; + hfront-porch = <50>; + vback-porch = <20>; + vfront-porch = <20>; + hsync-len = <20>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + screen-width = <68>; + screen-hight = <120>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-rk3128-86v-LVDS1024x600.dtsi b/include/dt-bindings/display/screen-timing/lcd-rk3128-86v-LVDS1024x600.dtsi new file mode 100644 index 000000000000..c4cbc6d9c058 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-rk3128-86v-LVDS1024x600.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RockChip. LCD_LVDS1024x600 FOR rk3128-86V + * + */ + + +disp_timings: display-timings { + native-mode = <&timing0>; + timing0: timing0 { + screen-type = <SCREEN_LVDS>; + lvds-format = <LVDS_8BIT_1>; + out-face = <OUT_P888>; + /* Min Typ Max Unit + * Clock Frequency fclk 44.9 51.2 63 MHz + */ + clock-frequency = <60000000>; + hactive = <1024>; /* Horizontal display area thd 1024 DCLK */ + vactive = <600>; /* Vertical display area tvd 600 H */ + hback-porch = <90>; /* HS Width +Back Porch 160 160 160 DCLK (Thw+ thbp)*/ + hfront-porch = <160>; /* HS front porch thfp 16 160 216 DCLK */ + vback-porch = <13>; /* VS front porch tvfp 1 12 127 H */ + vfront-porch = <12>; /* VS Width+Back Porch 23 23 23 H (Tvw+ tvbp) */ + hsync-len = <70>; /* HS Pulse Width thw 1 - 140 DCLK */ + vsync-len = <10>; /* VS Pulse Width tvw 1 - 20 H */ + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-td043mgeal.dtsi b/include/dt-bindings/display/screen-timing/lcd-td043mgeal.dtsi new file mode 100644 index 000000000000..32583775b084 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-td043mgeal.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RockChip. LCD_TD043MGEA1 FOR FPGA + * + */ + + +disp_timings: display-timings { + native-mode = <&timing0>; + timing0: timing0 { + screen-type = <SCREEN_RGB>; + out-face = <OUT_P888>; + clock-frequency = <27000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <206>; + hfront-porch = <40>; + vback-porch = <25>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-tv080wum-mipi.dtsi b/include/dt-bindings/display/screen-timing/lcd-tv080wum-mipi.dtsi new file mode 100644 index 000000000000..2bf4ef99b506 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-tv080wum-mipi.dtsi @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2014 ROCKCHIP, Inc. + * arch/arm/boot/dts/lcd-lq070m1sx01-mipi.dtsi + * author: libing@rock-chips.com + * create date: 2014-04-15 + * lcd model: ld089wu1 + * resolution: 1920 X 1200 + * mipi channel: single + */ + +/* about mipi */ +disp_mipi_init: mipi_dsi_init{ + compatible = "rockchip,mipi_dsi_init"; + rockchip,screen_init = <0>; + rockchip,dsi_lane = <4>; + rockchip,dsi_hs_clk = <1000>; + rockchip,mipi_dsi_num = <1>; +}; +disp_mipi_power_ctr: mipi_power_ctr { + compatible = "rockchip,mipi_power_ctr"; + /*mipi_lcd_rst:mipi_lcd_rst{ + compatible = "rockchip,lcd_rst"; + rockchip,gpios = <&gpio2 GPIO_B7 GPIO_ACTIVE_LOW>; + rockchip,delay = <100>; + }; + mipi_lcd_en:mipi_lcd_en { + compatible = "rockchip,lcd_en"; + rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>; + rockchip,delay = <100>; + };*/ +}; +disp_mipi_init_cmds: screen-on-cmds { + compatible = "rockchip,screen-on-cmds"; + /*rockchip,cmd_debug = <1>; + rockchip,on-cmds1 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <HSDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0xb0 0x02>; + rockchip,cmd_delay = <0>; + }; + */ +}; + + +disp_timings: display-timings { + native-mode = <&timing0>; + compatible = "rockchip,display-timings"; + timing0: timing0 { + screen-type = <SCREEN_MIPI>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_P888>; + clock-frequency = <150000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <80>; + hfront-porch = <81>; + vback-porch = <21>; + vfront-porch = <21>; + hsync-len = <10>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + cabc-lut = < + /*gamma = 2.2*/ + 0x00000383 0x00000392 0x000003a2 0x000003b2 0x000003c2 0x000003d2 0x000003e2 0x000003f3 + 0x00000403 0x00000414 0x00000425 0x00000436 0x00000447 0x00000458 0x0000046a 0x0000047b + 0x0000048d 0x0000049f 0x000004b1 0x000004c3 0x000004d5 0x000004e8 0x000004fa 0x0000050d + 0x00000520 0x00000533 0x00000546 0x0000055a 0x0000056d 0x00000581 0x00000595 0x000005a9 + 0x000005bd 0x000005d1 0x000005e5 0x000005fa 0x0000060f 0x00000624 0x00000639 0x0000064e + 0x00000663 0x00000679 0x0000068e 0x000006a4 0x000006ba 0x000006d0 0x000006e6 0x000006fd + 0x00000713 0x0000072a 0x00000741 0x00000758 0x0000076f 0x00000786 0x0000079e 0x000007b6 + 0x000007cd 0x000007e5 0x000007fd 0x00000816 0x0000082e 0x00000847 0x0000085f 0x00000878 + 0x00000891 0x000008ab 0x000008c4 0x000008de 0x000008f7 0x00000911 0x0000092b 0x00000945 + 0x00000960 0x0000097a 0x00000995 0x000009af 0x000009ca 0x000009e6 0x00000a01 0x00000a1c + 0x00000a38 0x00000a54 0x00000a6f 0x00000a8c 0x00000aa8 0x00000ac4 0x00000ae1 0x00000afd + 0x00000b1a 0x00000b37 0x00000b54 0x00000b72 0x00000b8f 0x00000bad 0x00000bcb 0x00000be9 + 0x00000c07 0x00000c25 0x00000c44 0x00000c62 0x00000c81 0x00000ca0 0x00000cbf 0x00000cdf + 0x00000cfe 0x00000d1e 0x00000d3e 0x00000d5d 0x00000d7e 0x00000d9e 0x00000dbe 0x00000ddf + 0x00000e00 0x00000e21 0x00000e42 0x00000e63 0x00000e84 0x00000ea6 0x00000ec8 0x00000eea + 0x00000f0c 0x00000f2e 0x00000f50 0x00000f73 0x00000f96 0x00000fb9 0x00000fdc 0x00000fff + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; + cabc-gamma-base = < + /*gamma = 2.2*/ + 0x00010000 0x0000fdd0 0x0000fba8 0x0000f986 0x0000f76a 0x0000f556 0x0000f347 0x0000f140 + 0x0000ef3e 0x0000ed43 0x0000eb4e 0x0000e95e 0x0000e775 0x0000e592 0x0000e3b4 0x0000e1dc + 0x0000e009 0x0000de3c 0x0000dc74 0x0000dab2 0x0000d8f4 0x0000d73c 0x0000d589 0x0000d3db + 0x0000d232 0x0000d08d 0x0000ceee 0x0000cd53 0x0000cbbc 0x0000ca2b 0x0000c89d 0x0000c714 + 0x0000c590 0x0000c410 0x0000c294 0x0000c11c 0x0000bfa8 0x0000be39 0x0000bccd 0x0000bb65 + 0x0000ba01 0x0000b8a1 0x0000b745 0x0000b5ed 0x0000b498 0x0000b347 0x0000b1f9 0x0000b0af + 0x0000af68 0x0000ae25 0x0000ace5 0x0000aba8 0x0000aa6f 0x0000a939 0x0000a806 0x0000a6d7 + 0x0000a5aa 0x0000a480 0x0000a35a 0x0000a236 0x0000a116 0x00009ff8 0x00009edd 0x00009dc5 + 0x00009cb0 0x00009b9e 0x00009a8e 0x00009981 0x00009877 0x0000976f 0x0000966a 0x00009567 + 0x00009467 0x0000936a 0x0000926f 0x00009176 0x00009080 0x00008f8c 0x00008e9a 0x00008dab + 0x00008cbe 0x00008bd3 0x00008aea 0x00008a04 0x00008920 0x0000883e 0x0000875e 0x00008680 + 0x000085a4 0x000084ca 0x000083f3 0x0000831d 0x00008249 0x00008177 0x000080a7 0x00007fd9 + 0x00007f0d 0x00007e42 0x00007d7a 0x00007cb3 0x00007bee 0x00007b2b 0x00007a6a 0x000079aa + 0x000078ec 0x0000782f 0x00007775 0x000076bc 0x00007604 0x0000754f 0x0000749a 0x000073e8 + 0x00007337 0x00007287 0x000071d9 0x0000712c 0x00007081 0x00006fd8 0x00006f30 0x00006e89 + 0x00006de4 0x00006d40 0x00006c9d 0x00006bfc 0x00006b5c 0x00006abe 0x00006a21 0x00006985 + 0x000068ea 0x00006851 0x000067b9 0x00006722 0x0000668d 0x000065f9 0x00006566 0x000064d4 + 0x00006443 0x000063b4 0x00006325 0x00006298 0x0000620c 0x00006181 0x000060f8 0x0000606f + 0x00005fe7 0x00005f61 0x00005edb 0x00005e57 0x00005dd4 0x00005d51 0x00005cd0 0x00005c50 + 0x00005bd1 0x00005b52 0x00005ad5 0x00005a59 0x000059de 0x00005963 0x000058ea 0x00005871 + 0x000057fa 0x00005783 0x0000570d 0x00005699 0x00005625 0x000055b2 0x0000553f 0x000054ce + 0x0000545d 0x000053ee 0x0000537f 0x00005311 0x000052a4 0x00005238 0x000051cc 0x00005161 + 0x000050f7 0x0000508e 0x00005026 0x00004fbe 0x00004f57 0x00004ef1 0x00004e8c 0x00004e27 + 0x00004dc3 0x00004d60 0x00004cfe 0x00004c9c 0x00004c3b 0x00004bdb 0x00004b7b 0x00004b1c + 0x00004abe 0x00004a60 0x00004a03 0x000049a7 0x0000494b 0x000048f0 0x00004896 0x0000483c + 0x000047e3 0x0000478a 0x00004733 0x000046db 0x00004685 0x0000462f 0x000045d9 0x00004584 + 0x00004530 0x000044dc 0x00004489 0x00004437 0x000043e5 0x00004393 0x00004342 0x000042f2 + 0x000042a2 0x00004253 0x00004204 0x000041b6 0x00004169 0x0000411b 0x000040cf 0x00004083 + 0x00004037 0x00003fec 0x00003fa1 0x00003f57 0x00003f0e 0x00003ec5 0x00003e7c 0x00003e34 + 0x00003dec 0x00003da5 0x00003d5e 0x00003d18 0x00003cd2 0x00003c8c 0x00003c48 0x00003c03 + 0x00003bbf 0x00003b7b 0x00003b38 0x00003af5 0x00003ab3 0x00003a71 0x00003a30 0x000039ef + 0x000039ae 0x0000396e 0x0000392e 0x000038ee 0x000038af 0x00003871 0x00003832 0x000037f5>; + }; + }; diff --git a/include/dt-bindings/display/screen-timing/lcd-tv080wum-nl0-mipi.dtsi b/include/dt-bindings/display/screen-timing/lcd-tv080wum-nl0-mipi.dtsi new file mode 100644 index 000000000000..b408d6555de8 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-tv080wum-nl0-mipi.dtsi @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * include/dt-bindings/display/screen-timing/lcd-tv080wum-nl0-mipi.dtsi + * author: hjc@rock-chips.com + * create date: 2016-03-28 + * lcd model: tv080wum-n10 + * resolution: 1200 * 1920 + * mipi channel: single + */ + +/* about mipi */ +disp_mipi_init: mipi_dsi_init{ + compatible = "rockchip,mipi_dsi_init"; + rockchip,screen_init = <0>; + rockchip,dsi_lane = <4>; + rockchip,dsi_hs_clk = <1200>; + rockchip,mipi_dsi_num = <1>; +}; + +disp_mipi_power_ctr: mipi_power_ctr { + compatible = "rockchip,mipi_power_ctr"; + /* mipi_lcd_rst:mipi_lcd_rst{ + compatible = "rockchip,lcd_rst"; + rockchip,gpios = <&gpio2 GPIO_B7 GPIO_ACTIVE_LOW>; + rockchip,delay = <100>; + }; + mipi_lcd_en:mipi_lcd_en { + compatible = "rockchip,lcd_en"; + rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>; + rockchip,delay = <100>; + }; + */ +}; + +disp_mipi_init_cmds: screen-on-cmds { + compatible = "rockchip,screen-on-cmds"; + /* rockchip,cmd_debug = <1>; + rockchip,on-cmds1 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <HSDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0xb0 0x02>; + rockchip,cmd_delay = <0>; + }; + */ +}; + +disp_timings: display-timings { + native-mode = <&timing0>; + compatible = "rockchip,display-timings"; + timing0: timing0 { + screen-type = <SCREEN_MIPI>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_P888>; + clock-frequency = <160000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <21>; + hfront-porch = <120>; + vback-porch = <18>; + vfront-porch = <21>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + cabc-lut = < + /*gamma = 2.2*/ + 0x00000383 0x00000392 0x000003a2 0x000003b2 0x000003c2 0x000003d2 0x000003e2 0x000003f3 + 0x00000403 0x00000414 0x00000425 0x00000436 0x00000447 0x00000458 0x0000046a 0x0000047b + 0x0000048d 0x0000049f 0x000004b1 0x000004c3 0x000004d5 0x000004e8 0x000004fa 0x0000050d + 0x00000520 0x00000533 0x00000546 0x0000055a 0x0000056d 0x00000581 0x00000595 0x000005a9 + 0x000005bd 0x000005d1 0x000005e5 0x000005fa 0x0000060f 0x00000624 0x00000639 0x0000064e + 0x00000663 0x00000679 0x0000068e 0x000006a4 0x000006ba 0x000006d0 0x000006e6 0x000006fd + 0x00000713 0x0000072a 0x00000741 0x00000758 0x0000076f 0x00000786 0x0000079e 0x000007b6 + 0x000007cd 0x000007e5 0x000007fd 0x00000816 0x0000082e 0x00000847 0x0000085f 0x00000878 + 0x00000891 0x000008ab 0x000008c4 0x000008de 0x000008f7 0x00000911 0x0000092b 0x00000945 + 0x00000960 0x0000097a 0x00000995 0x000009af 0x000009ca 0x000009e6 0x00000a01 0x00000a1c + 0x00000a38 0x00000a54 0x00000a6f 0x00000a8c 0x00000aa8 0x00000ac4 0x00000ae1 0x00000afd + 0x00000b1a 0x00000b37 0x00000b54 0x00000b72 0x00000b8f 0x00000bad 0x00000bcb 0x00000be9 + 0x00000c07 0x00000c25 0x00000c44 0x00000c62 0x00000c81 0x00000ca0 0x00000cbf 0x00000cdf + 0x00000cfe 0x00000d1e 0x00000d3e 0x00000d5d 0x00000d7e 0x00000d9e 0x00000dbe 0x00000ddf + 0x00000e00 0x00000e21 0x00000e42 0x00000e63 0x00000e84 0x00000ea6 0x00000ec8 0x00000eea + 0x00000f0c 0x00000f2e 0x00000f50 0x00000f73 0x00000f96 0x00000fb9 0x00000fdc 0x00000fff + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; + cabc-gamma-base = < + /*gamma = 2.2*/ + 0x00010000 0x0000fdd0 0x0000fba8 0x0000f986 0x0000f76a 0x0000f556 0x0000f347 0x0000f140 + 0x0000ef3e 0x0000ed43 0x0000eb4e 0x0000e95e 0x0000e775 0x0000e592 0x0000e3b4 0x0000e1dc + 0x0000e009 0x0000de3c 0x0000dc74 0x0000dab2 0x0000d8f4 0x0000d73c 0x0000d589 0x0000d3db + 0x0000d232 0x0000d08d 0x0000ceee 0x0000cd53 0x0000cbbc 0x0000ca2b 0x0000c89d 0x0000c714 + 0x0000c590 0x0000c410 0x0000c294 0x0000c11c 0x0000bfa8 0x0000be39 0x0000bccd 0x0000bb65 + 0x0000ba01 0x0000b8a1 0x0000b745 0x0000b5ed 0x0000b498 0x0000b347 0x0000b1f9 0x0000b0af + 0x0000af68 0x0000ae25 0x0000ace5 0x0000aba8 0x0000aa6f 0x0000a939 0x0000a806 0x0000a6d7 + 0x0000a5aa 0x0000a480 0x0000a35a 0x0000a236 0x0000a116 0x00009ff8 0x00009edd 0x00009dc5 + 0x00009cb0 0x00009b9e 0x00009a8e 0x00009981 0x00009877 0x0000976f 0x0000966a 0x00009567 + 0x00009467 0x0000936a 0x0000926f 0x00009176 0x00009080 0x00008f8c 0x00008e9a 0x00008dab + 0x00008cbe 0x00008bd3 0x00008aea 0x00008a04 0x00008920 0x0000883e 0x0000875e 0x00008680 + 0x000085a4 0x000084ca 0x000083f3 0x0000831d 0x00008249 0x00008177 0x000080a7 0x00007fd9 + 0x00007f0d 0x00007e42 0x00007d7a 0x00007cb3 0x00007bee 0x00007b2b 0x00007a6a 0x000079aa + 0x000078ec 0x0000782f 0x00007775 0x000076bc 0x00007604 0x0000754f 0x0000749a 0x000073e8 + 0x00007337 0x00007287 0x000071d9 0x0000712c 0x00007081 0x00006fd8 0x00006f30 0x00006e89 + 0x00006de4 0x00006d40 0x00006c9d 0x00006bfc 0x00006b5c 0x00006abe 0x00006a21 0x00006985 + 0x000068ea 0x00006851 0x000067b9 0x00006722 0x0000668d 0x000065f9 0x00006566 0x000064d4 + 0x00006443 0x000063b4 0x00006325 0x00006298 0x0000620c 0x00006181 0x000060f8 0x0000606f + 0x00005fe7 0x00005f61 0x00005edb 0x00005e57 0x00005dd4 0x00005d51 0x00005cd0 0x00005c50 + 0x00005bd1 0x00005b52 0x00005ad5 0x00005a59 0x000059de 0x00005963 0x000058ea 0x00005871 + 0x000057fa 0x00005783 0x0000570d 0x00005699 0x00005625 0x000055b2 0x0000553f 0x000054ce + 0x0000545d 0x000053ee 0x0000537f 0x00005311 0x000052a4 0x00005238 0x000051cc 0x00005161 + 0x000050f7 0x0000508e 0x00005026 0x00004fbe 0x00004f57 0x00004ef1 0x00004e8c 0x00004e27 + 0x00004dc3 0x00004d60 0x00004cfe 0x00004c9c 0x00004c3b 0x00004bdb 0x00004b7b 0x00004b1c + 0x00004abe 0x00004a60 0x00004a03 0x000049a7 0x0000494b 0x000048f0 0x00004896 0x0000483c + 0x000047e3 0x0000478a 0x00004733 0x000046db 0x00004685 0x0000462f 0x000045d9 0x00004584 + 0x00004530 0x000044dc 0x00004489 0x00004437 0x000043e5 0x00004393 0x00004342 0x000042f2 + 0x000042a2 0x00004253 0x00004204 0x000041b6 0x00004169 0x0000411b 0x000040cf 0x00004083 + 0x00004037 0x00003fec 0x00003fa1 0x00003f57 0x00003f0e 0x00003ec5 0x00003e7c 0x00003e34 + 0x00003dec 0x00003da5 0x00003d5e 0x00003d18 0x00003cd2 0x00003c8c 0x00003c48 0x00003c03 + 0x00003bbf 0x00003b7b 0x00003b38 0x00003af5 0x00003ab3 0x00003a71 0x00003a30 0x000039ef + 0x000039ae 0x0000396e 0x0000392e 0x000038ee 0x000038af 0x00003871 0x00003832 0x000037f5>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-vga.dtsi b/include/dt-bindings/display/screen-timing/lcd-vga.dtsi new file mode 100644 index 000000000000..13d214b2e8c8 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-vga.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RockChip. VGA timing + * + */ + +disp_timings: display-timings { + native-mode = <&timing1>; + timing0: timing0 { + screen-type = <SCREEN_RGB>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_D888_P666>; + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <160>; + hfront-porch = <24>; + vback-porch = <29>; + vfront-porch = <3>; + hsync-len = <136>; + vsync-len = <6>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; + + timing1: timing1 { + screen-type = <SCREEN_RGB>; + out-face = <OUT_D888_P666>; + lvds-format = <LVDS_8BIT_2>; + clock-frequency = <88750000>; + hactive = <1440>; + vactive = <900>; + hback-porch = <80>; + hfront-porch = <48>; + vback-porch = <17>; + vfront-porch = <3>; + hsync-len = <32>; + vsync-len = <6>; + hsync-active = <1>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; + + timing2: timing2 { + screen-type = <SCREEN_RGB>; + out-face = <OUT_D888_P666>; + lvds-format = <LVDS_8BIT_2>; + clock-frequency = <106500000>; + hactive = <1440>; + vactive = <900>; + hback-porch = <232>; + hfront-porch = <80>; + vback-porch = <25>; + vfront-porch = <3>; + hsync-len = <152>; + vsync-len = <6>; + hsync-active = <0>; + vsync-active = <1>; + de-active = <0>; + pixelclk-active = <1>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-wqxga-mipi.dtsi b/include/dt-bindings/display/screen-timing/lcd-wqxga-mipi.dtsi new file mode 100644 index 000000000000..e41c7d147747 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-wqxga-mipi.dtsi @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2014 ROCKCHIP, Inc. + * arch/arm/boot/dts/lcd-lq070m1sx01-mipi.dtsi + * author: libing@rock-chips.com + * create date: 2014-04-15 + * lcd model: wqxga + * resolution: 2560 X 1600 + * mipi channel: dual + */ + +/* about mipi */ +disp_mipi_init: mipi_dsi_init{ + compatible = "rockchip,mipi_dsi_init"; + rockchip,screen_init = <1>; + rockchip,dsi_lane = <4>; + rockchip,dsi_hs_clk = <940>; + rockchip,mipi_dsi_num = <2>; +}; +disp_mipi_power_ctr: mipi_power_ctr { + compatible = "rockchip,mipi_power_ctr"; + mipi_lcd_rst:mipi_lcd_rst{ + compatible = "rockchip,lcd_rst"; + rockchip,gpios = <&gpio7 GPIO_B2 GPIO_ACTIVE_HIGH>; + rockchip,delay = <10>; + }; + mipi_lcd_en:mipi_lcd_en { + compatible = "rockchip,lcd_en"; + rockchip,gpios = <&gpio6 GPIO_A7 GPIO_ACTIVE_HIGH>; + rockchip,delay = <10>; + }; +}; +disp_mipi_init_cmds: screen-on-cmds { + rockchip,cmd_debug = <0>; + compatible = "rockchip,screen-on-cmds"; + rockchip,on-cmds1 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x05 0x01>; //set soft reset + rockchip,cmd_delay = <10>; + }; + + rockchip,on-cmds2 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x05 0x01>; //set soft reset + rockchip,cmd_delay = <10>; + }; + rockchip,on-cmds3 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x3a 0x77>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds4 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x39 0x2a 0x00 0x00 0x04 0xff>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds5 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x39 0x2b 0x00 0x00 0x06 0x3f>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds6 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x15 0x35 0x00>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds7 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <0>; + rockchip,cmd = <0x39 0x44 0x00 0x00>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds8 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x51 0xff>; //0xff + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds9 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x53 0x04>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds10 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x51 0xff>; //0xff + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds11 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x53 0x04>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds12 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x15 0x55 0x00>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds13 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x05 dcs_exit_sleep_mode>; + rockchip,cmd_delay = <120>; + }; + + rockchip,on-cmds14 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x23 0xb0 0x00>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds15 { //video + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xb3 0x1c>; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds16 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x29 0xce 0x7d 0x40 0x48 0x56 0x67 0x78 0x88 0x98 0xa7 0xb5 0xc3 0xd1 0xde 0xe9 0xf2 0xfa 0xff 0x04 0x00>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds17 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x23 0xb0 0x03>; + rockchip,cmd_delay = <0>; + }; + rockchip,on-cmds18 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x39 0x2c >; + rockchip,cmd_delay = <0>; + }; + + rockchip,on-cmds19 { + compatible = "rockchip,on-cmds"; + rockchip,cmd_type = <LPDT>; + rockchip,dsi_id = <2>; + rockchip,cmd = <0x05 dcs_set_display_on>; + rockchip,cmd_delay = <10>; + }; + +}; + +disp_timings: display-timings { + native-mode = <&timing0>; + compatible = "rockchip,display-timings"; + timing0: timing0 { + screen-type = <SCREEN_DUAL_MIPI>; + lvds-format = <LVDS_8BIT_2>; + out-face = <OUT_P888>; + clock-frequency = <265000000>; + hactive = <2560>; + vactive = <1600>; + + hsync-len = <38>;//19 + hback-porch = <40>;//40 + hfront-porch = <108>;//123 + + vsync-len = <4>; + vback-porch = <4>; + vfront-porch = <12>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; +}; diff --git a/include/dt-bindings/display/screen-timing/lcd-y81349.dtsi b/include/dt-bindings/display/screen-timing/lcd-y81349.dtsi new file mode 100644 index 000000000000..f0db3a36b142 --- /dev/null +++ b/include/dt-bindings/display/screen-timing/lcd-y81349.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RockChip. LCD_Y81349 FOR 86V + * + */ + + +disp_timings: display-timings { + native-mode = <&timing0>; + timing0: timing0 { + screen-type = <SCREEN_RGB>; + out-face = <OUT_P666>; + clock-frequency = <33000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <10>; + hfront-porch = <210>; + vback-porch = <10>; + vfront-porch = <22>; + hsync-len = <30>; + vsync-len = <13>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; +}; diff --git a/include/dt-bindings/dram/rockchip,rk322x.h b/include/dt-bindings/dram/rockchip,rk322x.h new file mode 100644 index 000000000000..1ab3317d700e --- /dev/null +++ b/include/dt-bindings/dram/rockchip,rk322x.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H +#define _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H + +#define DDR3_DS_34ohm (1 << 1) +#define DDR3_DS_40ohm (0x0) + +#define LP2_DS_34ohm (0x1) +#define LP2_DS_40ohm (0x2) +#define LP2_DS_48ohm (0x3) +#define LP2_DS_60ohm (0x4) +#define LP2_DS_68_6ohm (0x5)/* optional */ +#define LP2_DS_80ohm (0x6) +#define LP2_DS_120ohm (0x7)/* optional */ + +#define LP3_DS_34ohm (0x1) +#define LP3_DS_40ohm (0x2) +#define LP3_DS_48ohm (0x3) +#define LP3_DS_60ohm (0x4) +#define LP3_DS_80ohm (0x6) +#define LP3_DS_34D_40U (0x9) +#define LP3_DS_40D_48U (0xa) +#define LP3_DS_34D_48U (0xb) + +#define DDR3_ODT_DIS (0) +#define DDR3_ODT_40ohm ((1 << 2) | (1 << 6)) +#define DDR3_ODT_60ohm (1 << 2) +#define DDR3_ODT_120ohm (1 << 6) + +#define LP3_ODT_DIS (0) +#define LP3_ODT_60ohm (1) +#define LP3_ODT_120ohm (2) +#define LP3_ODT_240ohm (3) + +#define PHY_DDR3_RON_RTT_DISABLE (0) +#define PHY_DDR3_RON_RTT_451ohm (1) +#define PHY_DDR3_RON_RTT_225ohm (2) +#define PHY_DDR3_RON_RTT_150ohm (3) +#define PHY_DDR3_RON_RTT_112ohm (4) +#define PHY_DDR3_RON_RTT_90ohm (5) +#define PHY_DDR3_RON_RTT_75ohm (6) +#define PHY_DDR3_RON_RTT_64ohm (7) +#define PHY_DDR3_RON_RTT_56ohm (16) +#define PHY_DDR3_RON_RTT_50ohm (17) +#define PHY_DDR3_RON_RTT_45ohm (18) +#define PHY_DDR3_RON_RTT_41ohm (19) +#define PHY_DDR3_RON_RTT_37ohm (20) +#define PHY_DDR3_RON_RTT_34ohm (21) +#define PHY_DDR3_RON_RTT_33ohm (22) +#define PHY_DDR3_RON_RTT_30ohm (23) +#define PHY_DDR3_RON_RTT_28ohm (24) +#define PHY_DDR3_RON_RTT_26ohm (25) +#define PHY_DDR3_RON_RTT_25ohm (26) +#define PHY_DDR3_RON_RTT_23ohm (27) +#define PHY_DDR3_RON_RTT_22ohm (28) +#define PHY_DDR3_RON_RTT_21ohm (29) +#define PHY_DDR3_RON_RTT_20ohm (30) +#define PHY_DDR3_RON_RTT_19ohm (31) + +#define PHY_LP23_RON_RTT_DISABLE (0) +#define PHY_LP23_RON_RTT_480ohm (1) +#define PHY_LP23_RON_RTT_240ohm (2) +#define PHY_LP23_RON_RTT_160ohm (3) +#define PHY_LP23_RON_RTT_120ohm (4) +#define PHY_LP23_RON_RTT_96ohm (5) +#define PHY_LP23_RON_RTT_80ohm (6) +#define PHY_LP23_RON_RTT_68ohm (7) +#define PHY_LP23_RON_RTT_60ohm (16) +#define PHY_LP23_RON_RTT_53ohm (17) +#define PHY_LP23_RON_RTT_48ohm (18) +#define PHY_LP23_RON_RTT_43ohm (19) +#define PHY_LP23_RON_RTT_40ohm (20) +#define PHY_LP23_RON_RTT_37ohm (21) +#define PHY_LP23_RON_RTT_34ohm (22) +#define PHY_LP23_RON_RTT_32ohm (23) +#define PHY_LP23_RON_RTT_30ohm (24) +#define PHY_LP23_RON_RTT_28ohm (25) +#define PHY_LP23_RON_RTT_26ohm (26) +#define PHY_LP23_RON_RTT_25ohm (27) +#define PHY_LP23_RON_RTT_24ohm (28) +#define PHY_LP23_RON_RTT_22ohm (29) +#define PHY_LP23_RON_RTT_21ohm (30) +#define PHY_LP23_RON_RTT_20ohm (31) + +#endif /* _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H */ diff --git a/include/dt-bindings/dram/rockchip,rk3368.h b/include/dt-bindings/dram/rockchip,rk3368.h new file mode 100644 index 000000000000..993f1eed9816 --- /dev/null +++ b/include/dt-bindings/dram/rockchip,rk3368.h @@ -0,0 +1,80 @@ +/* + * + * Copyright (C) 2011-2014 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3368_H +#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3368_H + +#define DDR3_DS_34ohm (1<<1) +#define DDR3_DS_40ohm (0x0) + +#define LP2_DS_34ohm (0x1) +#define LP2_DS_40ohm (0x2) +#define LP2_DS_48ohm (0x3) +#define LP2_DS_60ohm (0x4) +#define LP2_DS_68_6ohm (0x5)/*optional*/ +#define LP2_DS_80ohm (0x6) +#define LP2_DS_120ohm (0x7)/*optional*/ + +#define LP3_DS_34ohm (0x1) +#define LP3_DS_40ohm (0x2) +#define LP3_DS_48ohm (0x3) +#define LP3_DS_60ohm (0x4) +#define LP3_DS_80ohm (0x6) +#define LP3_DS_34D_40U (0x9) +#define LP3_DS_40D_48U (0xa) +#define LP3_DS_34D_48U (0xb) + +#define DDR3_ODT_DIS (0) +#define DDR3_ODT_40ohm ((1<<2)|(1<<6)) +#define DDR3_ODT_60ohm (1<<2) +#define DDR3_ODT_120ohm (1<<6) + +#define LP3_ODT_DIS (0) +#define LP3_ODT_60ohm (1) +#define LP3_ODT_120ohm (2) +#define LP3_ODT_240ohm (3) + +#define PHY_RON_DISABLE (0) +#define PHY_RON_272ohm (1) +#define PHY_RON_135ohm (2) +#define PHY_RON_91ohm (3) +#define PHY_RON_38ohm (7) +#define PHY_RON_68ohm (8) +#define PHY_RON_54ohm (9) +#define PHY_RON_45ohm (10) +#define PHY_RON_39ohm (11) +#define PHY_RON_34ohm (12) +#define PHY_RON_30ohm (13) +#define PHY_RON_27ohm (14) +#define PHY_RON_25ohm (15) + +#define PHY_RTT_DISABLE (0) +#define PHY_RTT_1116ohm (1) +#define PHY_RTT_558ohm (2) +#define PHY_RTT_372ohm (3) +#define PHY_RTT_279ohm (4) +#define PHY_RTT_223ohm (5) +#define PHY_RTT_186ohm (6) +#define PHY_RTT_159ohm (7) +#define PHY_RTT_139ohm (8) +#define PHY_RTT_124ohm (9) +#define PHY_RTT_112ohm (10) +#define PHY_RTT_101ohm (11) +#define PHY_RTT_93ohm (12) +#define PHY_RTT_86ohm (13) +#define PHY_RTT_80ohm (14) +#define PHY_RTT_74ohm (15) + +#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3368_H*/ diff --git a/include/dt-bindings/input/rk-input.h b/include/dt-bindings/input/rk-input.h new file mode 100644 index 000000000000..00b412927890 --- /dev/null +++ b/include/dt-bindings/input/rk-input.h @@ -0,0 +1,814 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Device properties and quirks + */ + +#define INPUT_PROP_POINTER 0x00 /* needs a pointer */ +#define INPUT_PROP_DIRECT 0x01 /* direct input devices */ +#define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */ +#define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */ + +#define INPUT_PROP_MAX 0x1f +#define INPUT_PROP_CNT (INPUT_PROP_MAX + 1) + +/* + * Event types + */ + +#define EV_SYN 0x00 +#define EV_KEY 0x01 +#define EV_REL 0x02 +#define EV_ABS 0x03 +#define EV_MSC 0x04 +#define EV_SW 0x05 +#define EV_LED 0x11 +#define EV_SND 0x12 +#define EV_REP 0x14 +#define EV_FF 0x15 +#define EV_PWR 0x16 +#define EV_FF_STATUS 0x17 +#define EV_MAX 0x1f +#define EV_CNT (EV_MAX+1) + +/* + * Synchronization events. + */ + +#define SYN_REPORT 0 +#define SYN_CONFIG 1 +#define SYN_MT_REPORT 2 +#define SYN_DROPPED 3 + +/* + * Keys and buttons + * + * Most of the keys/buttons are modeled after USB HUT 1.12 + * (see http://www.usb.org/developers/hidpage). + * Abbreviations in the comments: + * AC - Application Control + * AL - Application Launch Button + * SC - System Control + */ + +#define KEY_RESERVED 0 +#define KEY_ESC 1 +#define KEY_1 2 +#define KEY_2 3 +#define KEY_3 4 +#define KEY_4 5 +#define KEY_5 6 +#define KEY_6 7 +#define KEY_7 8 +#define KEY_8 9 +#define KEY_9 10 +#define KEY_0 11 +#define KEY_MINUS 12 +#define KEY_EQUAL 13 +#define KEY_BACKSPACE 14 +#define KEY_TAB 15 +#define KEY_Q 16 +#define KEY_W 17 +#define KEY_E 18 +#define KEY_R 19 +#define KEY_T 20 +#define KEY_Y 21 +#define KEY_U 22 +#define KEY_I 23 +#define KEY_O 24 +#define KEY_P 25 +#define KEY_LEFTBRACE 26 +#define KEY_RIGHTBRACE 27 +#define KEY_ENTER 28 +#define KEY_LEFTCTRL 29 +#define KEY_A 30 +#define KEY_S 31 +#define KEY_D 32 +#define KEY_F 33 +#define KEY_G 34 +#define KEY_H 35 +#define KEY_J 36 +#define KEY_K 37 +#define KEY_L 38 +#define KEY_SEMICOLON 39 +#define KEY_APOSTROPHE 40 +#define KEY_GRAVE 41 +#define KEY_LEFTSHIFT 42 +#define KEY_BACKSLASH 43 +#define KEY_Z 44 +#define KEY_X 45 +#define KEY_C 46 +#define KEY_V 47 +#define KEY_B 48 +#define KEY_N 49 +#define KEY_M 50 +#define KEY_COMMA 51 +#define KEY_DOT 52 +#define KEY_SLASH 53 +#define KEY_RIGHTSHIFT 54 +#define KEY_KPASTERISK 55 +#define KEY_LEFTALT 56 +#define KEY_SPACE 57 +#define KEY_CAPSLOCK 58 +#define KEY_F1 59 +#define KEY_F2 60 +#define KEY_F3 61 +#define KEY_F4 62 +#define KEY_F5 63 +#define KEY_F6 64 +#define KEY_F7 65 +#define KEY_F8 66 +#define KEY_F9 67 +#define KEY_F10 68 +#define KEY_NUMLOCK 69 +#define KEY_SCROLLLOCK 70 +#define KEY_KP7 71 +#define KEY_KP8 72 +#define KEY_KP9 73 +#define KEY_KPMINUS 74 +#define KEY_KP4 75 +#define KEY_KP5 76 +#define KEY_KP6 77 +#define KEY_KPPLUS 78 +#define KEY_KP1 79 +#define KEY_KP2 80 +#define KEY_KP3 81 +#define KEY_KP0 82 +#define KEY_KPDOT 83 + +#define KEY_ZENKAKUHANKAKU 85 +#define KEY_102ND 86 +#define KEY_F11 87 +#define KEY_F12 88 +#define KEY_RO 89 +#define KEY_KATAKANA 90 +#define KEY_HIRAGANA 91 +#define KEY_HENKAN 92 +#define KEY_KATAKANAHIRAGANA 93 +#define KEY_MUHENKAN 94 +#define KEY_KPJPCOMMA 95 +#define KEY_KPENTER 96 +#define KEY_RIGHTCTRL 97 +#define KEY_KPSLASH 98 +#define KEY_SYSRQ 99 +#define KEY_RIGHTALT 100 +#define KEY_LINEFEED 101 +#define KEY_HOME 102 +#define KEY_UP 103 +#define KEY_PAGEUP 104 +#define KEY_LEFT 105 +#define KEY_RIGHT 106 +#define KEY_END 107 +#define KEY_DOWN 108 +#define KEY_PAGEDOWN 109 +#define KEY_INSERT 110 +#define KEY_DELETE 111 +#define KEY_MACRO 112 +#define KEY_MUTE 113 +#define KEY_VOLUMEDOWN 114 +#define KEY_VOLUMEUP 115 +#define KEY_POWER 116 /* SC System Power Down */ +#define KEY_KPEQUAL 117 +#define KEY_KPPLUSMINUS 118 +#define KEY_PAUSE 119 +#define KEY_SCALE 120 /* AL Compiz Scale (Expose) */ + +#define KEY_KPCOMMA 121 +#define KEY_HANGEUL 122 +#define KEY_HANGUEL KEY_HANGEUL +#define KEY_HANJA 123 +#define KEY_YEN 124 +#define KEY_LEFTMETA 125 +#define KEY_RIGHTMETA 126 +#define KEY_COMPOSE 127 + +#define KEY_STOP 128 /* AC Stop */ +#define KEY_AGAIN 129 +#define KEY_PROPS 130 /* AC Properties */ +#define KEY_UNDO 131 /* AC Undo */ +#define KEY_FRONT 132 +#define KEY_COPY 133 /* AC Copy */ +#define KEY_OPEN 134 /* AC Open */ +#define KEY_PASTE 135 /* AC Paste */ +#define KEY_FIND 136 /* AC Search */ +#define KEY_CUT 137 /* AC Cut */ +#define KEY_HELP 138 /* AL Integrated Help Center */ +#define KEY_MENU 139 /* Menu (show menu) */ +#define KEY_CALC 140 /* AL Calculator */ +#define KEY_SETUP 141 +#define KEY_SLEEP 142 /* SC System Sleep */ +#define KEY_WAKEUP 143 /* System Wake Up */ +#define KEY_FILE 144 /* AL Local Machine Browser */ +#define KEY_SENDFILE 145 +#define KEY_DELETEFILE 146 +#define KEY_XFER 147 +#define KEY_PROG1 148 +#define KEY_PROG2 149 +#define KEY_WWW 150 /* AL Internet Browser */ +#define KEY_MSDOS 151 +#define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */ +#define KEY_SCREENLOCK KEY_COFFEE +#define KEY_DIRECTION 153 +#define KEY_CYCLEWINDOWS 154 +#define KEY_MAIL 155 +#define KEY_BOOKMARKS 156 /* AC Bookmarks */ +#define KEY_COMPUTER 157 +#define KEY_BACK 158 /* AC Back */ +#define KEY_FORWARD 159 /* AC Forward */ +#define KEY_CLOSECD 160 +#define KEY_EJECTCD 161 +#define KEY_EJECTCLOSECD 162 +#define KEY_NEXTSONG 163 +#define KEY_PLAYPAUSE 164 +#define KEY_PREVIOUSSONG 165 +#define KEY_STOPCD 166 +#define KEY_RECORD 167 +#define KEY_REWIND 168 +#define KEY_PHONE 169 /* Media Select Telephone */ +#define KEY_ISO 170 +#define KEY_CONFIG 171 /* AL Consumer Control Configuration */ +#define KEY_HOMEPAGE 172 /* AC Home */ +#define KEY_REFRESH 173 /* AC Refresh */ +#define KEY_EXIT 174 /* AC Exit */ +#define KEY_MOVE 175 +#define KEY_EDIT 176 +#define KEY_SCROLLUP 177 +#define KEY_SCROLLDOWN 178 +#define KEY_KPLEFTPAREN 179 +#define KEY_KPRIGHTPAREN 180 +#define KEY_NEW 181 /* AC New */ +#define KEY_REDO 182 /* AC Redo/Repeat */ + +#define KEY_F13 183 +#define KEY_F14 184 +#define KEY_F15 185 +#define KEY_F16 186 +#define KEY_F17 187 +#define KEY_F18 188 +#define KEY_F19 189 +#define KEY_F20 190 +#define KEY_F21 191 +#define KEY_F22 192 +#define KEY_F23 193 +#define KEY_F24 194 + +#define KEY_PLAYCD 200 +#define KEY_PAUSECD 201 +#define KEY_PROG3 202 +#define KEY_PROG4 203 +#define KEY_DASHBOARD 204 /* AL Dashboard */ +#define KEY_SUSPEND 205 +#define KEY_CLOSE 206 /* AC Close */ +#define KEY_PLAY 207 +#define KEY_FASTFORWARD 208 +#define KEY_BASSBOOST 209 +#define KEY_PRINT 210 /* AC Print */ +#define KEY_HP 211 +#define KEY_CAMERA 212 +#define KEY_SOUND 213 +#define KEY_QUESTION 214 +#define KEY_EMAIL 215 +#define KEY_CHAT 216 +#define KEY_SEARCH 217 +#define KEY_CONNECT 218 +#define KEY_FINANCE 219 /* AL Checkbook/Finance */ +#define KEY_SPORT 220 +#define KEY_SHOP 221 +#define KEY_ALTERASE 222 +#define KEY_CANCEL 223 /* AC Cancel */ +#define KEY_BRIGHTNESSDOWN 224 +#define KEY_BRIGHTNESSUP 225 +#define KEY_MEDIA 226 + +#define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video + outputs (Monitor/LCD/TV-out/etc) */ +#define KEY_KBDILLUMTOGGLE 228 +#define KEY_KBDILLUMDOWN 229 +#define KEY_KBDILLUMUP 230 + +#define KEY_SEND 231 /* AC Send */ +#define KEY_REPLY 232 /* AC Reply */ +#define KEY_FORWARDMAIL 233 /* AC Forward Msg */ +#define KEY_SAVE 234 /* AC Save */ +#define KEY_DOCUMENTS 235 + +#define KEY_BATTERY 236 + +#define KEY_BLUETOOTH 237 +#define KEY_WLAN 238 +#define KEY_UWB 239 + +#define KEY_UNKNOWN 240 + +#define KEY_VIDEO_NEXT 241 /* drive next video source */ +#define KEY_VIDEO_PREV 242 /* drive previous video source */ +#define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */ +#define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual + brightness control is off, + rely on ambient */ +#define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO +#define KEY_DISPLAY_OFF 245 /* display device to off state */ + +#define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */ +#define KEY_WIMAX KEY_WWAN +#define KEY_RFKILL 247 /* Key that controls all radios */ + +#define KEY_MICMUTE 248 /* Mute / unmute the microphone */ + +/* Code 255 is reserved for special needs of AT keyboard driver */ + +#define BTN_MISC 0x100 +#define BTN_0 0x100 +#define BTN_1 0x101 +#define BTN_2 0x102 +#define BTN_3 0x103 +#define BTN_4 0x104 +#define BTN_5 0x105 +#define BTN_6 0x106 +#define BTN_7 0x107 +#define BTN_8 0x108 +#define BTN_9 0x109 + +#define BTN_MOUSE 0x110 +#define BTN_LEFT 0x110 +#define BTN_RIGHT 0x111 +#define BTN_MIDDLE 0x112 +#define BTN_SIDE 0x113 +#define BTN_EXTRA 0x114 +#define BTN_FORWARD 0x115 +#define BTN_BACK 0x116 +#define BTN_TASK 0x117 + +#define BTN_JOYSTICK 0x120 +#define BTN_TRIGGER 0x120 +#define BTN_THUMB 0x121 +#define BTN_THUMB2 0x122 +#define BTN_TOP 0x123 +#define BTN_TOP2 0x124 +#define BTN_PINKIE 0x125 +#define BTN_BASE 0x126 +#define BTN_BASE2 0x127 +#define BTN_BASE3 0x128 +#define BTN_BASE4 0x129 +#define BTN_BASE5 0x12a +#define BTN_BASE6 0x12b +#define BTN_DEAD 0x12f + +#define BTN_GAMEPAD 0x130 +#define BTN_SOUTH 0x130 +#define BTN_A BTN_SOUTH +#define BTN_EAST 0x131 +#define BTN_B BTN_EAST +#define BTN_C 0x132 +#define BTN_NORTH 0x133 +#define BTN_X BTN_NORTH +#define BTN_WEST 0x134 +#define BTN_Y BTN_WEST +#define BTN_Z 0x135 +#define BTN_TL 0x136 +#define BTN_TR 0x137 +#define BTN_TL2 0x138 +#define BTN_TR2 0x139 +#define BTN_SELECT 0x13a +#define BTN_START 0x13b +#define BTN_MODE 0x13c +#define BTN_THUMBL 0x13d +#define BTN_THUMBR 0x13e + +#define BTN_DIGI 0x140 +#define BTN_TOOL_PEN 0x140 +#define BTN_TOOL_RUBBER 0x141 +#define BTN_TOOL_BRUSH 0x142 +#define BTN_TOOL_PENCIL 0x143 +#define BTN_TOOL_AIRBRUSH 0x144 +#define BTN_TOOL_FINGER 0x145 +#define BTN_TOOL_MOUSE 0x146 +#define BTN_TOOL_LENS 0x147 +#define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */ +#define BTN_TOUCH 0x14a +#define BTN_STYLUS 0x14b +#define BTN_STYLUS2 0x14c +#define BTN_TOOL_DOUBLETAP 0x14d +#define BTN_TOOL_TRIPLETAP 0x14e +#define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */ + +#define BTN_WHEEL 0x150 +#define BTN_GEAR_DOWN 0x150 +#define BTN_GEAR_UP 0x151 + +#define KEY_OK 0x160 +#define KEY_SELECT 0x161 +#define KEY_GOTO 0x162 +#define KEY_CLEAR 0x163 +#define KEY_POWER2 0x164 +#define KEY_OPTION 0x165 +#define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */ +#define KEY_TIME 0x167 +#define KEY_VENDOR 0x168 +#define KEY_ARCHIVE 0x169 +#define KEY_PROGRAM 0x16a /* Media Select Program Guide */ +#define KEY_CHANNEL 0x16b +#define KEY_FAVORITES 0x16c +#define KEY_EPG 0x16d +#define KEY_PVR 0x16e /* Media Select Home */ +#define KEY_MHP 0x16f +#define KEY_LANGUAGE 0x170 +#define KEY_TITLE 0x171 +#define KEY_SUBTITLE 0x172 +#define KEY_ANGLE 0x173 +#define KEY_ZOOM 0x174 +#define KEY_MODE 0x175 +#define KEY_KEYBOARD 0x176 +#define KEY_SCREEN 0x177 +#define KEY_PC 0x178 /* Media Select Computer */ +#define KEY_TV 0x179 /* Media Select TV */ +#define KEY_TV2 0x17a /* Media Select Cable */ +#define KEY_VCR 0x17b /* Media Select VCR */ +#define KEY_VCR2 0x17c /* VCR Plus */ +#define KEY_SAT 0x17d /* Media Select Satellite */ +#define KEY_SAT2 0x17e +#define KEY_CD 0x17f /* Media Select CD */ +#define KEY_TAPE 0x180 /* Media Select Tape */ +#define KEY_RADIO 0x181 +#define KEY_TUNER 0x182 /* Media Select Tuner */ +#define KEY_PLAYER 0x183 +#define KEY_TEXT 0x184 +#define KEY_DVD 0x185 /* Media Select DVD */ +#define KEY_AUX 0x186 +#define KEY_MP3 0x187 +#define KEY_AUDIO 0x188 /* AL Audio Browser */ +#define KEY_VIDEO 0x189 /* AL Movie Browser */ +#define KEY_DIRECTORY 0x18a +#define KEY_LIST 0x18b +#define KEY_MEMO 0x18c /* Media Select Messages */ +#define KEY_CALENDAR 0x18d +#define KEY_RED 0x18e +#define KEY_GREEN 0x18f +#define KEY_YELLOW 0x190 +#define KEY_BLUE 0x191 +#define KEY_CHANNELUP 0x192 /* Channel Increment */ +#define KEY_CHANNELDOWN 0x193 /* Channel Decrement */ +#define KEY_FIRST 0x194 +#define KEY_LAST 0x195 /* Recall Last */ +#define KEY_AB 0x196 +#define KEY_NEXT 0x197 +#define KEY_RESTART 0x198 +#define KEY_SLOW 0x199 +#define KEY_SHUFFLE 0x19a +#define KEY_BREAK 0x19b +#define KEY_PREVIOUS 0x19c +#define KEY_DIGITS 0x19d +#define KEY_TEEN 0x19e +#define KEY_TWEN 0x19f +#define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */ +#define KEY_GAMES 0x1a1 /* Media Select Games */ +#define KEY_ZOOMIN 0x1a2 /* AC Zoom In */ +#define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */ +#define KEY_ZOOMRESET 0x1a4 /* AC Zoom */ +#define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */ +#define KEY_EDITOR 0x1a6 /* AL Text Editor */ +#define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */ +#define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */ +#define KEY_PRESENTATION 0x1a9 /* AL Presentation App */ +#define KEY_DATABASE 0x1aa /* AL Database App */ +#define KEY_NEWS 0x1ab /* AL Newsreader */ +#define KEY_VOICEMAIL 0x1ac /* AL Voicemail */ +#define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */ +#define KEY_MESSENGER 0x1ae /* AL Instant Messaging */ +#define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */ +#define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE +#define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */ +#define KEY_LOGOFF 0x1b1 /* AL Logoff */ + +#define KEY_DOLLAR 0x1b2 +#define KEY_EURO 0x1b3 + +#define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */ +#define KEY_FRAMEFORWARD 0x1b5 +#define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */ +#define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */ +#define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */ +#define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */ +#define KEY_IMAGES 0x1ba /* AL Image Browser */ + +#define KEY_DEL_EOL 0x1c0 +#define KEY_DEL_EOS 0x1c1 +#define KEY_INS_LINE 0x1c2 +#define KEY_DEL_LINE 0x1c3 + +#define KEY_FN 0x1d0 +#define KEY_FN_ESC 0x1d1 +#define KEY_FN_F1 0x1d2 +#define KEY_FN_F2 0x1d3 +#define KEY_FN_F3 0x1d4 +#define KEY_FN_F4 0x1d5 +#define KEY_FN_F5 0x1d6 +#define KEY_FN_F6 0x1d7 +#define KEY_FN_F7 0x1d8 +#define KEY_FN_F8 0x1d9 +#define KEY_FN_F9 0x1da +#define KEY_FN_F10 0x1db +#define KEY_FN_F11 0x1dc +#define KEY_FN_F12 0x1dd +#define KEY_FN_1 0x1de +#define KEY_FN_2 0x1df +#define KEY_FN_D 0x1e0 +#define KEY_FN_E 0x1e1 +#define KEY_FN_F 0x1e2 +#define KEY_FN_S 0x1e3 +#define KEY_FN_B 0x1e4 + +#define KEY_BRL_DOT1 0x1f1 +#define KEY_BRL_DOT2 0x1f2 +#define KEY_BRL_DOT3 0x1f3 +#define KEY_BRL_DOT4 0x1f4 +#define KEY_BRL_DOT5 0x1f5 +#define KEY_BRL_DOT6 0x1f6 +#define KEY_BRL_DOT7 0x1f7 +#define KEY_BRL_DOT8 0x1f8 +#define KEY_BRL_DOT9 0x1f9 +#define KEY_BRL_DOT10 0x1fa + +#define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */ +#define KEY_NUMERIC_1 0x201 /* and other keypads */ +#define KEY_NUMERIC_2 0x202 +#define KEY_NUMERIC_3 0x203 +#define KEY_NUMERIC_4 0x204 +#define KEY_NUMERIC_5 0x205 +#define KEY_NUMERIC_6 0x206 +#define KEY_NUMERIC_7 0x207 +#define KEY_NUMERIC_8 0x208 +#define KEY_NUMERIC_9 0x209 +#define KEY_NUMERIC_STAR 0x20a +#define KEY_NUMERIC_POUND 0x20b + +#define KEY_CAMERA_FOCUS 0x210 +#define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */ + +#define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */ +#define KEY_TOUCHPAD_ON 0x213 +#define KEY_TOUCHPAD_OFF 0x214 + +#define KEY_CAMERA_ZOOMIN 0x215 +#define KEY_CAMERA_ZOOMOUT 0x216 +#define KEY_CAMERA_UP 0x217 +#define KEY_CAMERA_DOWN 0x218 +#define KEY_CAMERA_LEFT 0x219 +#define KEY_CAMERA_RIGHT 0x21a + +#define KEY_ATTENDANT_ON 0x21b +#define KEY_ATTENDANT_OFF 0x21c +#define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */ +#define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */ + +#define BTN_DPAD_UP 0x220 +#define BTN_DPAD_DOWN 0x221 +#define BTN_DPAD_LEFT 0x222 +#define BTN_DPAD_RIGHT 0x223 + +#define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */ + +#define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */ +#define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */ +#define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */ +#define KEY_CONTROLPANEL 0x243 /* AL Control Panel */ +#define KEY_APPSELECT 0x244 /* AL Select Task/Application */ +#define KEY_SCREENSAVER 0x245 /* AL Screen Saver */ +#define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */ + +#define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */ +#define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */ + +#define BTN_TRIGGER_HAPPY 0x2c0 +#define BTN_TRIGGER_HAPPY1 0x2c0 +#define BTN_TRIGGER_HAPPY2 0x2c1 +#define BTN_TRIGGER_HAPPY3 0x2c2 +#define BTN_TRIGGER_HAPPY4 0x2c3 +#define BTN_TRIGGER_HAPPY5 0x2c4 +#define BTN_TRIGGER_HAPPY6 0x2c5 +#define BTN_TRIGGER_HAPPY7 0x2c6 +#define BTN_TRIGGER_HAPPY8 0x2c7 +#define BTN_TRIGGER_HAPPY9 0x2c8 +#define BTN_TRIGGER_HAPPY10 0x2c9 +#define BTN_TRIGGER_HAPPY11 0x2ca +#define BTN_TRIGGER_HAPPY12 0x2cb +#define BTN_TRIGGER_HAPPY13 0x2cc +#define BTN_TRIGGER_HAPPY14 0x2cd +#define BTN_TRIGGER_HAPPY15 0x2ce +#define BTN_TRIGGER_HAPPY16 0x2cf +#define BTN_TRIGGER_HAPPY17 0x2d0 +#define BTN_TRIGGER_HAPPY18 0x2d1 +#define BTN_TRIGGER_HAPPY19 0x2d2 +#define BTN_TRIGGER_HAPPY20 0x2d3 +#define BTN_TRIGGER_HAPPY21 0x2d4 +#define BTN_TRIGGER_HAPPY22 0x2d5 +#define BTN_TRIGGER_HAPPY23 0x2d6 +#define BTN_TRIGGER_HAPPY24 0x2d7 +#define BTN_TRIGGER_HAPPY25 0x2d8 +#define BTN_TRIGGER_HAPPY26 0x2d9 +#define BTN_TRIGGER_HAPPY27 0x2da +#define BTN_TRIGGER_HAPPY28 0x2db +#define BTN_TRIGGER_HAPPY29 0x2dc +#define BTN_TRIGGER_HAPPY30 0x2dd +#define BTN_TRIGGER_HAPPY31 0x2de +#define BTN_TRIGGER_HAPPY32 0x2df +#define BTN_TRIGGER_HAPPY33 0x2e0 +#define BTN_TRIGGER_HAPPY34 0x2e1 +#define BTN_TRIGGER_HAPPY35 0x2e2 +#define BTN_TRIGGER_HAPPY36 0x2e3 +#define BTN_TRIGGER_HAPPY37 0x2e4 +#define BTN_TRIGGER_HAPPY38 0x2e5 +#define BTN_TRIGGER_HAPPY39 0x2e6 +#define BTN_TRIGGER_HAPPY40 0x2e7 + +/* We avoid low common keys in module aliases so they don't get huge. */ +#define KEY_MIN_INTERESTING KEY_MUTE +#define KEY_MAX 0x2ff +#define KEY_CNT (KEY_MAX+1) + +/* + * Relative axes + */ + +#define REL_X 0x00 +#define REL_Y 0x01 +#define REL_Z 0x02 +#define REL_RX 0x03 +#define REL_RY 0x04 +#define REL_RZ 0x05 +#define REL_HWHEEL 0x06 +#define REL_DIAL 0x07 +#define REL_WHEEL 0x08 +#define REL_MISC 0x09 +#define REL_MAX 0x0f +#define REL_CNT (REL_MAX+1) + +/* + * Absolute axes + */ + +#define ABS_X 0x00 +#define ABS_Y 0x01 +#define ABS_Z 0x02 +#define ABS_RX 0x03 +#define ABS_RY 0x04 +#define ABS_RZ 0x05 +#define ABS_THROTTLE 0x06 +#define ABS_RUDDER 0x07 +#define ABS_WHEEL 0x08 +#define ABS_GAS 0x09 +#define ABS_BRAKE 0x0a +#define ABS_HAT0X 0x10 +#define ABS_HAT0Y 0x11 +#define ABS_HAT1X 0x12 +#define ABS_HAT1Y 0x13 +#define ABS_HAT2X 0x14 +#define ABS_HAT2Y 0x15 +#define ABS_HAT3X 0x16 +#define ABS_HAT3Y 0x17 +#define ABS_PRESSURE 0x18 +#define ABS_DISTANCE 0x19 +#define ABS_TILT_X 0x1a +#define ABS_TILT_Y 0x1b +#define ABS_TOOL_WIDTH 0x1c + +#define ABS_VOLUME 0x20 + +#define ABS_MISC 0x28 + +#define ABS_MT_SLOT 0x2f /* MT slot being modified */ +#define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */ +#define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */ +#define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */ +#define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */ +#define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */ +#define ABS_MT_POSITION_X 0x35 /* Center X touch position */ +#define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */ +#define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */ +#define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */ +#define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */ +#define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */ +#define ABS_MT_DISTANCE 0x3b /* Contact hover distance */ +#define ABS_MT_TOOL_X 0x3c /* Center X tool position */ +#define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */ + + +#define ABS_MAX 0x3f +#define ABS_CNT (ABS_MAX+1) + +/* + * Switch events + */ + +#define SW_LID 0x00 /* set = lid shut */ +#define SW_TABLET_MODE 0x01 /* set = tablet mode */ +#define SW_HEADPHONE_INSERT 0x02 /* set = inserted */ +#define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any" + set = radio enabled */ +#define SW_RADIO SW_RFKILL_ALL /* deprecated */ +#define SW_MICROPHONE_INSERT 0x04 /* set = inserted */ +#define SW_DOCK 0x05 /* set = plugged into dock */ +#define SW_LINEOUT_INSERT 0x06 /* set = inserted */ +#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */ +#define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */ +#define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */ +#define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */ +#define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */ +#define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ +#define SW_LINEIN_INSERT 0x0d /* set = inserted */ +#define SW_MUTE_DEVICE 0x0e /* set = device disabled */ +#define SW_MAX 0x0f +#define SW_CNT (SW_MAX+1) + +/* + * Misc events + */ + +#define MSC_SERIAL 0x00 +#define MSC_PULSELED 0x01 +#define MSC_GESTURE 0x02 +#define MSC_RAW 0x03 +#define MSC_SCAN 0x04 +#define MSC_TIMESTAMP 0x05 +#define MSC_MAX 0x07 +#define MSC_CNT (MSC_MAX+1) + +/* + * LEDs + */ + +#define LED_NUML 0x00 +#define LED_CAPSL 0x01 +#define LED_SCROLLL 0x02 +#define LED_COMPOSE 0x03 +#define LED_KANA 0x04 +#define LED_SLEEP 0x05 +#define LED_SUSPEND 0x06 +#define LED_MUTE 0x07 +#define LED_MISC 0x08 +#define LED_MAIL 0x09 +#define LED_CHARGING 0x0a +#define LED_MAX 0x0f +#define LED_CNT (LED_MAX+1) + +/* + * Autorepeat values + */ + +#define REP_DELAY 0x00 +#define REP_PERIOD 0x01 +#define REP_MAX 0x01 +#define REP_CNT (REP_MAX+1) + +/* + * Sounds + */ + +#define SND_CLICK 0x00 +#define SND_BELL 0x01 +#define SND_TONE 0x02 +#define SND_MAX 0x07 +#define SND_CNT (SND_MAX+1) + +/* + * IDs. + */ + +#define ID_BUS 0 +#define ID_VENDOR 1 +#define ID_PRODUCT 2 +#define ID_VERSION 3 + +#define BUS_PCI 0x01 +#define BUS_ISAPNP 0x02 +#define BUS_USB 0x03 +#define BUS_HIL 0x04 +#define BUS_BLUETOOTH 0x05 +#define BUS_VIRTUAL 0x06 + +#define BUS_ISA 0x10 +#define BUS_I8042 0x11 +#define BUS_XTKBD 0x12 +#define BUS_RS232 0x13 +#define BUS_GAMEPORT 0x14 +#define BUS_PARPORT 0x15 +#define BUS_AMIGA 0x16 +#define BUS_ADB 0x17 +#define BUS_I2C 0x18 +#define BUS_HOST 0x19 +#define BUS_GSC 0x1A +#define BUS_ATARI 0x1B +#define BUS_SPI 0x1C + +/* + * MT_TOOL types + */ +#define MT_TOOL_FINGER 0 +#define MT_TOOL_PEN 1 +#define MT_TOOL_MAX 1 + +/* + * Values describing the status of a force-feedback effect + */ +#define FF_STATUS_STOPPED 0x00 +#define FF_STATUS_PLAYING 0x01 +#define FF_STATUS_MAX 0x01 diff --git a/include/dt-bindings/leds/leds-pca9532.h b/include/dt-bindings/leds/leds-pca9532.h new file mode 100644 index 000000000000..4d917aab7e1e --- /dev/null +++ b/include/dt-bindings/leds/leds-pca9532.h @@ -0,0 +1,18 @@ +/* + * This header provides constants for pca9532 LED bindings. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef _DT_BINDINGS_LEDS_PCA9532_H +#define _DT_BINDINGS_LEDS_PCA9532_H + +#define PCA9532_TYPE_NONE 0 +#define PCA9532_TYPE_LED 1 +#define PCA9532_TYPE_N2100_BEEP 2 +#define PCA9532_TYPE_GPIO 3 +#define PCA9532_LED_TIMER2 4 + +#endif /* _DT_BINDINGS_LEDS_PCA9532_H */ diff --git a/include/dt-bindings/memory/px30-dram.h b/include/dt-bindings/memory/px30-dram.h new file mode 100644 index 000000000000..17d799d802d9 --- /dev/null +++ b/include/dt-bindings/memory/px30-dram.h @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_PX30_H +#define _DT_BINDINGS_DRAM_ROCKCHIP_PX30_H + +#define DDR2_DS_FULL (0) +#define DDR2_DS_REDUCE (1) + +#define DDR2_ODT_DIS (0) +#define DDR2_ODT_50ohm (50) /* optional */ +#define DDR2_ODT_75ohm (75) +#define DDR2_ODT_150ohm (150) + +#define DDR3_DS_34ohm (34) +#define DDR3_DS_40ohm (40) + +#define DDR3_ODT_DIS (0) +#define DDR3_ODT_40ohm (40) +#define DDR3_ODT_60ohm (60) +#define DDR3_ODT_120ohm (120) + +#define LP2_DS_34ohm (34) +#define LP2_DS_40ohm (40) +#define LP2_DS_48ohm (48) +#define LP2_DS_60ohm (60) +#define LP2_DS_68_6ohm (68) /* optional */ +#define LP2_DS_80ohm (80) +#define LP2_DS_120ohm (120) /* optional */ + +#define LP3_DS_34ohm (34) +#define LP3_DS_40ohm (40) +#define LP3_DS_48ohm (48) +#define LP3_DS_60ohm (60) +#define LP3_DS_80ohm (80) +#define LP3_DS_34D_40U (3440) +#define LP3_DS_40D_48U (4048) +#define LP3_DS_34D_48U (3448) + +#define LP3_ODT_DIS (0) +#define LP3_ODT_60ohm (60) +#define LP3_ODT_120ohm (120) +#define LP3_ODT_240ohm (240) + +#define LP4_PDDS_40ohm (40) +#define LP4_PDDS_48ohm (48) +#define LP4_PDDS_60ohm (60) +#define LP4_PDDS_80ohm (80) +#define LP4_PDDS_120ohm (120) +#define LP4_PDDS_240ohm (240) + +#define LP4_DQ_ODT_40ohm (40) +#define LP4_DQ_ODT_48ohm (48) +#define LP4_DQ_ODT_60ohm (60) +#define LP4_DQ_ODT_80ohm (80) +#define LP4_DQ_ODT_120ohm (120) +#define LP4_DQ_ODT_240ohm (240) +#define LP4_DQ_ODT_DIS (0) + +#define LP4_CA_ODT_40ohm (40) +#define LP4_CA_ODT_48ohm (48) +#define LP4_CA_ODT_60ohm (60) +#define LP4_CA_ODT_80ohm (80) +#define LP4_CA_ODT_120ohm (120) +#define LP4_CA_ODT_240ohm (240) +#define LP4_CA_ODT_DIS (0) + +#define DDR4_DS_34ohm (34) +#define DDR4_DS_48ohm (48) +#define DDR4_RTT_NOM_DIS (0) +#define DDR4_RTT_NOM_60ohm (60) +#define DDR4_RTT_NOM_120ohm (120) +#define DDR4_RTT_NOM_40ohm (40) +#define DDR4_RTT_NOM_240ohm (240) +#define DDR4_RTT_NOM_48ohm (48) +#define DDR4_RTT_NOM_80ohm (80) +#define DDR4_RTT_NOM_34ohm (34) + +#define PHY_DDR3_RON_RTT_DISABLE (0) +#define PHY_DDR3_RON_RTT_451ohm (1) +#define PHY_DDR3_RON_RTT_225ohm (2) +#define PHY_DDR3_RON_RTT_150ohm (3) +#define PHY_DDR3_RON_RTT_112ohm (4) +#define PHY_DDR3_RON_RTT_90ohm (5) +#define PHY_DDR3_RON_RTT_75ohm (6) +#define PHY_DDR3_RON_RTT_64ohm (7) +#define PHY_DDR3_RON_RTT_56ohm (16) +#define PHY_DDR3_RON_RTT_50ohm (17) +#define PHY_DDR3_RON_RTT_45ohm (18) +#define PHY_DDR3_RON_RTT_41ohm (19) +#define PHY_DDR3_RON_RTT_37ohm (20) +#define PHY_DDR3_RON_RTT_34ohm (21) +#define PHY_DDR3_RON_RTT_33ohm (22) +#define PHY_DDR3_RON_RTT_30ohm (23) +#define PHY_DDR3_RON_RTT_28ohm (24) +#define PHY_DDR3_RON_RTT_26ohm (25) +#define PHY_DDR3_RON_RTT_25ohm (26) +#define PHY_DDR3_RON_RTT_23ohm (27) +#define PHY_DDR3_RON_RTT_22ohm (28) +#define PHY_DDR3_RON_RTT_21ohm (29) +#define PHY_DDR3_RON_RTT_20ohm (30) +#define PHY_DDR3_RON_RTT_19ohm (31) + +#define PHY_DDR4_LPDDR3_2_RON_RTT_DISABLE (0) +#define PHY_DDR4_LPDDR3_2_RON_RTT_480ohm (1) +#define PHY_DDR4_LPDDR3_2_RON_RTT_240ohm (2) +#define PHY_DDR4_LPDDR3_2_RON_RTT_160ohm (3) +#define PHY_DDR4_LPDDR3_2_RON_RTT_120ohm (4) +#define PHY_DDR4_LPDDR3_2_RON_RTT_96ohm (5) +#define PHY_DDR4_LPDDR3_2_RON_RTT_80ohm (6) +#define PHY_DDR4_LPDDR3_2_RON_RTT_68ohm (7) +#define PHY_DDR4_LPDDR3_2_RON_RTT_60ohm (16) +#define PHY_DDR4_LPDDR3_2_RON_RTT_53ohm (17) +#define PHY_DDR4_LPDDR3_2_RON_RTT_48ohm (18) +#define PHY_DDR4_LPDDR3_2_RON_RTT_43ohm (19) +#define PHY_DDR4_LPDDR3_2_RON_RTT_40ohm (20) +#define PHY_DDR4_LPDDR3_2_RON_RTT_37ohm (21) +#define PHY_DDR4_LPDDR3_2_RON_RTT_34ohm (22) +#define PHY_DDR4_LPDDR3_2_RON_RTT_32ohm (23) +#define PHY_DDR4_LPDDR3_2_RON_RTT_30ohm (24) +#define PHY_DDR4_LPDDR3_2_RON_RTT_28ohm (25) +#define PHY_DDR4_LPDDR3_2_RON_RTT_26ohm (26) +#define PHY_DDR4_LPDDR3_2_RON_RTT_25ohm (27) +#define PHY_DDR4_LPDDR3_2_RON_RTT_24ohm (28) +#define PHY_DDR4_LPDDR3_2_RON_RTT_22ohm (29) +#define PHY_DDR4_LPDDR3_2_RON_RTT_21ohm (30) +#define PHY_DDR4_LPDDR3_2_RON_RTT_20ohm (31) + +#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_PX30_H*/ diff --git a/include/dt-bindings/memory/rk1808-dram.h b/include/dt-bindings/memory/rk1808-dram.h new file mode 100644 index 000000000000..522bd75a4a55 --- /dev/null +++ b/include/dt-bindings/memory/rk1808-dram.h @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK1808_H +#define _DT_BINDINGS_DRAM_ROCKCHIP_RK1808_H + +#define DDR2_DS_FULL (0) +#define DDR2_DS_REDUCE (1) + +#define DDR2_ODT_DIS (0) +#define DDR2_ODT_50ohm (50) /* optional */ +#define DDR2_ODT_75ohm (75) +#define DDR2_ODT_150ohm (150) + +#define DDR3_DS_34ohm (34) +#define DDR3_DS_40ohm (40) + +#define DDR3_ODT_DIS (0) +#define DDR3_ODT_40ohm (40) +#define DDR3_ODT_60ohm (60) +#define DDR3_ODT_120ohm (120) + +#define LP2_DS_34ohm (34) +#define LP2_DS_40ohm (40) +#define LP2_DS_48ohm (48) +#define LP2_DS_60ohm (60) +#define LP2_DS_68_6ohm (68) /* optional */ +#define LP2_DS_80ohm (80) +#define LP2_DS_120ohm (120) /* optional */ + +#define LP3_DS_34ohm (34) +#define LP3_DS_40ohm (40) +#define LP3_DS_48ohm (48) +#define LP3_DS_60ohm (60) +#define LP3_DS_80ohm (80) +#define LP3_DS_34D_40U (3440) +#define LP3_DS_40D_48U (4048) +#define LP3_DS_34D_48U (3448) + +#define LP3_ODT_DIS (0) +#define LP3_ODT_60ohm (60) +#define LP3_ODT_120ohm (120) +#define LP3_ODT_240ohm (240) + +#define LP4_PDDS_40ohm (40) +#define LP4_PDDS_48ohm (48) +#define LP4_PDDS_60ohm (60) +#define LP4_PDDS_80ohm (80) +#define LP4_PDDS_120ohm (120) +#define LP4_PDDS_240ohm (240) + +#define LP4_DQ_ODT_40ohm (40) +#define LP4_DQ_ODT_48ohm (48) +#define LP4_DQ_ODT_60ohm (60) +#define LP4_DQ_ODT_80ohm (80) +#define LP4_DQ_ODT_120ohm (120) +#define LP4_DQ_ODT_240ohm (240) +#define LP4_DQ_ODT_DIS (0) + +#define LP4_CA_ODT_40ohm (40) +#define LP4_CA_ODT_48ohm (48) +#define LP4_CA_ODT_60ohm (60) +#define LP4_CA_ODT_80ohm (80) +#define LP4_CA_ODT_120ohm (120) +#define LP4_CA_ODT_240ohm (240) +#define LP4_CA_ODT_DIS (0) + +#define DDR4_DS_34ohm (34) +#define DDR4_DS_48ohm (48) +#define DDR4_RTT_NOM_DIS (0) +#define DDR4_RTT_NOM_60ohm (60) +#define DDR4_RTT_NOM_120ohm (120) +#define DDR4_RTT_NOM_40ohm (40) +#define DDR4_RTT_NOM_240ohm (240) +#define DDR4_RTT_NOM_48ohm (48) +#define DDR4_RTT_NOM_80ohm (80) +#define DDR4_RTT_NOM_34ohm (34) + +#define PHY_DDR3_RON_DISABLE (0) +#define PHY_DDR3_RON_340ohm (1) +#define PHY_DDR3_RON_170ohm (2) +#define PHY_DDR3_RON_113ohm (3) +#define PHY_DDR3_RON_85ohm (4) +#define PHY_DDR3_RON_68ohm (5) +#define PHY_DDR3_RON_57ohm (6) +#define PHY_DDR3_RON_49ohm (7) +#define PHY_DDR3_RON_43ohm (16) +#define PHY_DDR3_RON_38ohm (17) +#define PHY_DDR3_RON_34ohm (18) +#define PHY_DDR3_RON_31ohm (19) +#define PHY_DDR3_RON_28ohm (20) +#define PHY_DDR3_RON_26ohm (21) +#define PHY_DDR3_RON_24ohm (22) +#define PHY_DDR3_RON_23ohm (23) +#define PHY_DDR3_RON_21ohm (24) +#define PHY_DDR3_RON_20ohm (25) +#define PHY_DDR3_RON_19ohm (26) +#define PHY_DDR3_RON_18ohm (27) +#define PHY_DDR3_RON_17ohm (28) +#define PHY_DDR3_RON_16ohm (29) +#define PHY_DDR3_RON_15ohm (31) + +#define PHY_DDR3_RTT_DISABLE (0) +#define PHY_DDR3_RTT_852ohm (1) +#define PHY_DDR3_RTT_427ohm (2) +#define PHY_DDR3_RTT_284ohm (3) +#define PHY_DDR3_RTT_213ohm (4) +#define PHY_DDR3_RTT_171ohm (5) +#define PHY_DDR3_RTT_142ohm (6) +#define PHY_DDR3_RTT_122ohm (7) +#define PHY_DDR3_RTT_107ohm (16) +#define PHY_DDR3_RTT_95ohm (17) +#define PHY_DDR3_RTT_85ohm (18) +#define PHY_DDR3_RTT_78ohm (19) +#define PHY_DDR3_RTT_71ohm (20) +#define PHY_DDR3_RTT_66ohm (21) +#define PHY_DDR3_RTT_61ohm (22) +#define PHY_DDR3_RTT_57ohm (23) +#define PHY_DDR3_RTT_53ohm (24) +#define PHY_DDR3_RTT_50ohm (25) +#define PHY_DDR3_RTT_47ohm (26) +#define PHY_DDR3_RTT_45ohm (27) +#define PHY_DDR3_RTT_43ohm (28) +#define PHY_DDR3_RTT_41ohm (29) +#define PHY_DDR3_RTT_39ohm (30) +#define PHY_DDR3_RTT_37ohm (31) + +#define PHY_DDR4_LPDDR2_3_RON_DISABLE (0) +#define PHY_DDR4_LPDDR2_3_RON_376ohm (1) +#define PHY_DDR4_LPDDR2_3_RON_188ohm (2) +#define PHY_DDR4_LPDDR2_3_RON_125ohm (3) +#define PHY_DDR4_LPDDR2_3_RON_94ohm (4) +#define PHY_DDR4_LPDDR2_3_RON_75ohm (5) +#define PHY_DDR4_LPDDR2_3_RON_63ohm (6) +#define PHY_DDR4_LPDDR2_3_RON_54ohm (7) +#define PHY_DDR4_LPDDR2_3_RON_47ohm (16) +#define PHY_DDR4_LPDDR2_3_RON_42ohm (17) +#define PHY_DDR4_LPDDR2_3_RON_38ohm (18) +#define PHY_DDR4_LPDDR2_3_RON_34ohm (19) +#define PHY_DDR4_LPDDR2_3_RON_31ohm (20) +#define PHY_DDR4_LPDDR2_3_RON_29ohm (21) +#define PHY_DDR4_LPDDR2_3_RON_27ohm (22) +#define PHY_DDR4_LPDDR2_3_RON_25ohm (23) +#define PHY_DDR4_LPDDR2_3_RON_23ohm (24) +#define PHY_DDR4_LPDDR2_3_RON_22ohm (25) +#define PHY_DDR4_LPDDR2_3_RON_21ohm (26) +#define PHY_DDR4_LPDDR2_3_RON_20ohm (27) +#define PHY_DDR4_LPDDR2_3_RON_19ohm (28) +#define PHY_DDR4_LPDDR2_3_RON_18ohm (29) +#define PHY_DDR4_LPDDR2_3_RON_17ohm (30) +#define PHY_DDR4_LPDDR2_3_RON_16ohm (31) + +#define PHY_DDR4_LPDDR2_3_RTT_DISABLE (0) +#define PHY_DDR4_LPDDR2_3_RTT_915ohm (1) +#define PHY_DDR4_LPDDR2_3_RTT_458ohm (2) +#define PHY_DDR4_LPDDR2_3_RTT_305ohm (3) +#define PHY_DDR4_LPDDR2_3_RTT_229ohm (4) +#define PHY_DDR4_LPDDR2_3_RTT_183ohm (5) +#define PHY_DDR4_LPDDR2_3_RTT_153ohm (6) +#define PHY_DDR4_LPDDR2_3_RTT_131ohm (7) +#define PHY_DDR4_LPDDR2_3_RTT_115ohm (16) +#define PHY_DDR4_LPDDR2_3_RTT_102ohm (17) +#define PHY_DDR4_LPDDR2_3_RTT_92ohm (18) +#define PHY_DDR4_LPDDR2_3_RTT_83ohm (19) +#define PHY_DDR4_LPDDR2_3_RTT_76ohm (20) +#define PHY_DDR4_LPDDR2_3_RTT_70ohm (21) +#define PHY_DDR4_LPDDR2_3_RTT_65ohm (22) +#define PHY_DDR4_LPDDR2_3_RTT_61ohm (23) +#define PHY_DDR4_LPDDR2_3_RTT_57ohm (24) +#define PHY_DDR4_LPDDR2_3_RTT_54ohm (25) +#define PHY_DDR4_LPDDR2_3_RTT_51ohm (26) +#define PHY_DDR4_LPDDR2_3_RTT_48ohm (27) +#define PHY_DDR4_LPDDR2_3_RTT_46ohm (28) +#define PHY_DDR4_LPDDR2_3_RTT_44ohm (29) +#define PHY_DDR4_LPDDR2_3_RTT_42ohm (30) +#define PHY_DDR4_LPDDR2_3_RTT_40ohm (31) + +#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK1808_H*/ diff --git a/include/dt-bindings/memory/rk3128-dram.h b/include/dt-bindings/memory/rk3128-dram.h new file mode 100644 index 000000000000..2598ac98e525 --- /dev/null +++ b/include/dt-bindings/memory/rk3128-dram.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3128_H +#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3128_H + +#define BIT(nr) (1UL << (nr)) + +#define DDR3_DS_34ohm BIT(1) +#define DDR3_DS_40ohm (0x0) + +#define LP2_DS_34ohm (0x1) +#define LP2_DS_40ohm (0x2) +#define LP2_DS_48ohm (0x3) +#define LP2_DS_60ohm (0x4) +#define LP2_DS_68_6ohm (0x5) /* optional */ +#define LP2_DS_80ohm (0x6) +#define LP2_DS_120ohm (0x7) /* optional */ + +#define DDR3_ODT_DIS (0) +#define DDR3_ODT_40ohm (BIT(2) | BIT(6)) +#define DDR3_ODT_60ohm BIT(2) +#define DDR3_ODT_120ohm BIT(6) + +#define PHY_RON_DISABLE (0) +#define PHY_RON_309ohm (1) +#define PHY_RON_155ohm (2) +#define PHY_RON_103ohm (3) +#define PHY_RON_77ohm (4) +#define PHY_RON_63ohm (5) +#define PHY_RON_52ohm (6) +#define PHY_RON_45ohm (7) +#define PHY_RON_62ohm (9) +#define PHY_RON_44ohm (11) +#define PHY_RON_39ohm (12) +#define PHY_RON_34ohm (13) +#define PHY_RON_31ohm (14) +#define PHY_RON_28ohm (15) + +#define PHY_RTT_DISABLE (0) +#define PHY_RTT_816ohm (1) +#define PHY_RTT_431ohm (2) +#define PHY_RTT_287ohm (3) +#define PHY_RTT_216ohm (4) +#define PHY_RTT_172ohm (5) +#define PHY_RTT_145ohm (6) +#define PHY_RTT_124ohm (7) +#define PHY_RTT_215ohm (8) +#define PHY_RTT_144ohm (10) +#define PHY_RTT_123ohm (11) +#define PHY_RTT_108ohm (12) +#define PHY_RTT_96ohm (13) +#define PHY_RTT_86ohm (14) +#define PHY_RTT_78ohm (15) + +#endif /* _DT_BINDINGS_DRAM_ROCKCHIP_RK3128_H */ diff --git a/include/dt-bindings/memory/rk3288-dram.h b/include/dt-bindings/memory/rk3288-dram.h new file mode 100644 index 000000000000..1c531dca755c --- /dev/null +++ b/include/dt-bindings/memory/rk3288-dram.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3288_H +#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3288_H + +#define DDR3_DS_34ohm (34) +#define DDR3_DS_40ohm (40) + +#define DDR3_ODT_DIS (0) +#define DDR3_ODT_40ohm (40) +#define DDR3_ODT_60ohm (60) +#define DDR3_ODT_120ohm (120) + +#define LP2_DS_34ohm (34) +#define LP2_DS_40ohm (40) +#define LP2_DS_48ohm (48) +#define LP2_DS_60ohm (60) +#define LP2_DS_68_6ohm (68) /* optional */ +#define LP2_DS_80ohm (80) +#define LP2_DS_120ohm (120) /* optional */ + +#define LP3_DS_34ohm (34) +#define LP3_DS_40ohm (40) +#define LP3_DS_48ohm (48) +#define LP3_DS_60ohm (60) +#define LP3_DS_80ohm (80) +#define LP3_DS_34D_40U (3440) +#define LP3_DS_40D_48U (4048) +#define LP3_DS_34D_48U (3448) + +#define LP3_ODT_DIS (0) +#define LP3_ODT_60ohm (60) +#define LP3_ODT_120ohm (120) +#define LP3_ODT_240ohm (240) + +/* PHY DRV ODT strength*/ +#define PHY_DDR3_RON_114ohm (7) +#define PHY_DDR3_RON_95ohm (4) +#define PHY_DDR3_RON_81ohm (5) +#define PHY_DDR3_RON_71ohm (0xc) +#define PHY_DDR3_RON_63ohm (0xd) +#define PHY_DDR3_RON_57ohm (0xe) +#define PHY_DDR3_RON_52ohm (0xf) +#define PHY_DDR3_RON_47ohm (0xa) +#define PHY_DDR3_RON_44ohm (0xb) +#define PHY_DDR3_RON_41ohm (0x8) +#define PHY_DDR3_RON_38ohm (0x9) +#define PHY_DDR3_RON_34ohm (0x19) +#define PHY_DDR3_RON_30ohm (0x1b) +#define PHY_DDR3_RON_26ohm (0x1c) +#define PHY_DDR3_RON_23ohm (0x15) +#define PHY_DDR3_RON_20ohm (0x12) +#define PHY_DDR3_RON_18ohm (0x11) + +#define PHY_DDR3_RTT_368ohm (0x1) +#define PHY_DDR3_RTT_155ohm (0x2) +#define PHY_DDR3_RTT_113ohm (0x3) +#define PHY_DDR3_RTT_80ohm (0x6) +#define PHY_DDR3_RTT_64ohm (0x7) +#define PHY_DDR3_RTT_54ohm (0x4) +#define PHY_DDR3_RTT_40ohm (0xc) +#define PHY_DDR3_RTT_30ohm (0xf) + +#define PHY_LP23_RON_110ohm (4) +#define PHY_LP23_RON_83ohm (0xc) +#define PHY_LP23_RON_73ohm (0xd) +#define PHY_LP23_RON_66ohm (0xe) +#define PHY_LP23_RON_60ohm (0xf) +#define PHY_LP23_RON_55ohm (0xa) +#define PHY_LP23_RON_51ohm (0xb) +#define PHY_LP23_RON_44ohm (0x9) +#define PHY_LP23_RON_39ohm (0x19) +#define PHY_LP23_RON_35ohm (0x1b) +#define PHY_LP23_RON_30ohm (0x1c) +#define PHY_LP23_RON_26ohm (0x16) +#define PHY_LP23_RON_22ohm (0x10) + +#define PHY_LP23_RTT_368ohm (0x1) +#define PHY_LP23_RTT_155ohm (0x2) +#define PHY_LP23_RTT_113ohm (0x3) +#define PHY_LP23_RTT_80ohm (0x6) +#define PHY_LP23_RTT_64ohm (0x7) +#define PHY_LP23_RTT_54ohm (0x4) +#define PHY_LP23_RTT_40ohm (0xc) +#define PHY_LP23_RTT_30ohm (0xf) + +#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3288_H*/ diff --git a/include/dt-bindings/memory/rk3328-dram.h b/include/dt-bindings/memory/rk3328-dram.h new file mode 100644 index 000000000000..171f41c256d3 --- /dev/null +++ b/include/dt-bindings/memory/rk3328-dram.h @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H +#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H + +#define DDR3_DS_34ohm (34) +#define DDR3_DS_40ohm (40) + +#define DDR3_ODT_DIS (0) +#define DDR3_ODT_40ohm (40) +#define DDR3_ODT_60ohm (60) +#define DDR3_ODT_120ohm (120) + +#define LP2_DS_34ohm (34) +#define LP2_DS_40ohm (40) +#define LP2_DS_48ohm (48) +#define LP2_DS_60ohm (60) +#define LP2_DS_68_6ohm (68) /* optional */ +#define LP2_DS_80ohm (80) +#define LP2_DS_120ohm (120) /* optional */ + +#define LP3_DS_34ohm (34) +#define LP3_DS_40ohm (40) +#define LP3_DS_48ohm (48) +#define LP3_DS_60ohm (60) +#define LP3_DS_80ohm (80) +#define LP3_DS_34D_40U (3440) +#define LP3_DS_40D_48U (4048) +#define LP3_DS_34D_48U (3448) + +#define LP3_ODT_DIS (0) +#define LP3_ODT_60ohm (60) +#define LP3_ODT_120ohm (120) +#define LP3_ODT_240ohm (240) + +#define LP4_PDDS_40ohm (40) +#define LP4_PDDS_48ohm (48) +#define LP4_PDDS_60ohm (60) +#define LP4_PDDS_80ohm (80) +#define LP4_PDDS_120ohm (120) +#define LP4_PDDS_240ohm (240) + +#define LP4_DQ_ODT_40ohm (40) +#define LP4_DQ_ODT_48ohm (48) +#define LP4_DQ_ODT_60ohm (60) +#define LP4_DQ_ODT_80ohm (80) +#define LP4_DQ_ODT_120ohm (120) +#define LP4_DQ_ODT_240ohm (240) +#define LP4_DQ_ODT_DIS (0) + +#define LP4_CA_ODT_40ohm (40) +#define LP4_CA_ODT_48ohm (48) +#define LP4_CA_ODT_60ohm (60) +#define LP4_CA_ODT_80ohm (80) +#define LP4_CA_ODT_120ohm (120) +#define LP4_CA_ODT_240ohm (240) +#define LP4_CA_ODT_DIS (0) + +#define DDR4_DS_34ohm (34) +#define DDR4_DS_48ohm (48) +#define DDR4_RTT_NOM_DIS (0) +#define DDR4_RTT_NOM_60ohm (60) +#define DDR4_RTT_NOM_120ohm (120) +#define DDR4_RTT_NOM_40ohm (40) +#define DDR4_RTT_NOM_240ohm (240) +#define DDR4_RTT_NOM_48ohm (48) +#define DDR4_RTT_NOM_80ohm (80) +#define DDR4_RTT_NOM_34ohm (34) + +#define PHY_DDR3_RON_RTT_DISABLE (0) +#define PHY_DDR3_RON_RTT_451ohm (1) +#define PHY_DDR3_RON_RTT_225ohm (2) +#define PHY_DDR3_RON_RTT_150ohm (3) +#define PHY_DDR3_RON_RTT_112ohm (4) +#define PHY_DDR3_RON_RTT_90ohm (5) +#define PHY_DDR3_RON_RTT_75ohm (6) +#define PHY_DDR3_RON_RTT_64ohm (7) +#define PHY_DDR3_RON_RTT_56ohm (16) +#define PHY_DDR3_RON_RTT_50ohm (17) +#define PHY_DDR3_RON_RTT_45ohm (18) +#define PHY_DDR3_RON_RTT_41ohm (19) +#define PHY_DDR3_RON_RTT_37ohm (20) +#define PHY_DDR3_RON_RTT_34ohm (21) +#define PHY_DDR3_RON_RTT_33ohm (22) +#define PHY_DDR3_RON_RTT_30ohm (23) +#define PHY_DDR3_RON_RTT_28ohm (24) +#define PHY_DDR3_RON_RTT_26ohm (25) +#define PHY_DDR3_RON_RTT_25ohm (26) +#define PHY_DDR3_RON_RTT_23ohm (27) +#define PHY_DDR3_RON_RTT_22ohm (28) +#define PHY_DDR3_RON_RTT_21ohm (29) +#define PHY_DDR3_RON_RTT_20ohm (30) +#define PHY_DDR3_RON_RTT_19ohm (31) + +#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0) +#define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1) +#define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2) +#define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3) +#define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4) +#define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5) +#define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6) +#define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7) +#define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16) +#define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17) +#define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18) +#define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19) +#define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20) +#define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21) +#define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22) +#define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23) +#define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24) +#define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25) +#define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26) +#define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27) +#define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28) +#define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29) +#define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30) +#define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31) + +#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H*/ diff --git a/include/dt-bindings/memory/rk3368-dram.h b/include/dt-bindings/memory/rk3368-dram.h new file mode 100644 index 000000000000..400f7b52a59f --- /dev/null +++ b/include/dt-bindings/memory/rk3368-dram.h @@ -0,0 +1,106 @@ +/* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3368_H +#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3368_H + +#define DDR3_DS_34ohm (0x2) +#define DDR3_DS_40ohm (0x0) + +#define LP2_DS_34ohm (0x1) +#define LP2_DS_40ohm (0x2) +#define LP2_DS_48ohm (0x3) +#define LP2_DS_60ohm (0x4) +#define LP2_DS_68_6ohm (0x5)/* optional */ +#define LP2_DS_80ohm (0x6) +#define LP2_DS_120ohm (0x7)/* optional */ + +#define LP3_DS_34ohm (0x1) +#define LP3_DS_40ohm (0x2) +#define LP3_DS_48ohm (0x3) +#define LP3_DS_60ohm (0x4) +#define LP3_DS_80ohm (0x6) +#define LP3_DS_34D_40U (0x9) +#define LP3_DS_40D_48U (0xa) +#define LP3_DS_34D_48U (0xb) + +#define DDR3_ODT_DIS (0) +#define DDR3_ODT_40ohm (0x44) +#define DDR3_ODT_60ohm (0x4) +#define DDR3_ODT_120ohm (0x40) + +#define LP3_ODT_DIS (0) +#define LP3_ODT_60ohm (1) +#define LP3_ODT_120ohm (2) +#define LP3_ODT_240ohm (3) + +#define PHY_RON_DISABLE (0) +#define PHY_RON_272ohm (1) +#define PHY_RON_135ohm (2) +#define PHY_RON_91ohm (3) +#define PHY_RON_38ohm (7) +#define PHY_RON_68ohm (8) +#define PHY_RON_54ohm (9) +#define PHY_RON_45ohm (10) +#define PHY_RON_39ohm (11) +#define PHY_RON_34ohm (12) +#define PHY_RON_30ohm (13) +#define PHY_RON_27ohm (14) +#define PHY_RON_25ohm (15) + +#define PHY_RTT_DISABLE (0) +#define PHY_RTT_1116ohm (1) +#define PHY_RTT_558ohm (2) +#define PHY_RTT_372ohm (3) +#define PHY_RTT_279ohm (4) +#define PHY_RTT_223ohm (5) +#define PHY_RTT_186ohm (6) +#define PHY_RTT_159ohm (7) +#define PHY_RTT_139ohm (8) +#define PHY_RTT_124ohm (9) +#define PHY_RTT_112ohm (10) +#define PHY_RTT_101ohm (11) +#define PHY_RTT_93ohm (12) +#define PHY_RTT_86ohm (13) +#define PHY_RTT_80ohm (14) +#define PHY_RTT_74ohm (15) + +#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3368_H*/ diff --git a/include/dt-bindings/memory/rk3399-dram.h b/include/dt-bindings/memory/rk3399-dram.h new file mode 100644 index 000000000000..44abb0aafb05 --- /dev/null +++ b/include/dt-bindings/memory/rk3399-dram.h @@ -0,0 +1,107 @@ +/* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3399_H +#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3399_H + +#define DDR3_DS_34ohm (34) +#define DDR3_DS_40ohm (40) + +#define DDR3_ODT_DIS (0) +#define DDR3_ODT_40ohm (40) +#define DDR3_ODT_60ohm (60) +#define DDR3_ODT_120ohm (120) + +#define LP2_DS_34ohm (34) +#define LP2_DS_40ohm (40) +#define LP2_DS_48ohm (48) +#define LP2_DS_60ohm (60) +#define LP2_DS_68_6ohm (68) /* optional */ +#define LP2_DS_80ohm (80) +#define LP2_DS_120ohm (120) /* optional */ + +#define LP3_DS_34ohm (34) +#define LP3_DS_40ohm (40) +#define LP3_DS_48ohm (48) +#define LP3_DS_60ohm (60) +#define LP3_DS_80ohm (80) +#define LP3_DS_34D_40U (3440) +#define LP3_DS_40D_48U (4048) +#define LP3_DS_34D_48U (3448) + +#define LP3_ODT_DIS (0) +#define LP3_ODT_60ohm (60) +#define LP3_ODT_120ohm (120) +#define LP3_ODT_240ohm (240) + +#define LP4_PDDS_40ohm (40) +#define LP4_PDDS_48ohm (48) +#define LP4_PDDS_60ohm (60) +#define LP4_PDDS_80ohm (80) +#define LP4_PDDS_120ohm (120) +#define LP4_PDDS_240ohm (240) + +#define LP4_DQ_ODT_40ohm (40) +#define LP4_DQ_ODT_48ohm (48) +#define LP4_DQ_ODT_60ohm (60) +#define LP4_DQ_ODT_80ohm (80) +#define LP4_DQ_ODT_120ohm (120) +#define LP4_DQ_ODT_240ohm (240) +#define LP4_DQ_ODT_DIS (0) + +#define LP4_CA_ODT_40ohm (40) +#define LP4_CA_ODT_48ohm (48) +#define LP4_CA_ODT_60ohm (60) +#define LP4_CA_ODT_80ohm (80) +#define LP4_CA_ODT_120ohm (120) +#define LP4_CA_ODT_240ohm (240) +#define LP4_CA_ODT_DIS (0) + +#define PHY_DRV_ODT_Hi_Z (0) +#define PHY_DRV_ODT_240 (240) +#define PHY_DRV_ODT_120 (120) +#define PHY_DRV_ODT_80 (80) +#define PHY_DRV_ODT_60 (60) +#define PHY_DRV_ODT_48 (48) +#define PHY_DRV_ODT_40 (40) +#define PHY_DRV_ODT_34_3 (34) + +#endif /* _DT_BINDINGS_DRAM_ROCKCHIP_RK3399_H */ diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h index 172744a72eb7..7b1656427cbe 100644 --- a/include/dt-bindings/net/ti-dp83867.h +++ b/include/dt-bindings/net/ti-dp83867.h @@ -42,4 +42,18 @@ #define DP83867_RGMIIDCTL_3_75_NS 0xe #define DP83867_RGMIIDCTL_4_00_NS 0xf +/* IO_MUX_CFG - Clock output selection */ +#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 +#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 +#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 +#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 +#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 +#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 +#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 +#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 +#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 +#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 +#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA +#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB +#define DP83867_CLK_O_SEL_REF_CLK 0xC #endif diff --git a/include/dt-bindings/pinctrl/rockchip-rk3036.h b/include/dt-bindings/pinctrl/rockchip-rk3036.h new file mode 100644 index 000000000000..553c33579065 --- /dev/null +++ b/include/dt-bindings/pinctrl/rockchip-rk3036.h @@ -0,0 +1,267 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_RK3036_H__ +#define __DT_BINDINGS_ROCKCHIP_PINCTRL_RK3036_H__ + + /* GPIO0_A */ + #define GPIO0_A0 0x0a00 + #define I2C0_SCL 0x0a01 + #define PWM1 0x0a02 + + #define GPIO0_A1 0x0a10 + #define I2C0_SDA 0x0a11 + #define PWM2 0x0a12 + + #define GPIO0_A2 0x0a20 + #define I2C1_SCL 0x0a21 + + #define GPIO0_A3 0x0a30 + #define I2C1_SDA 0x0a31 + + + /* GPIO0_B */ + #define GPIO0_B0 0x0b00 + #define MMC1_CMD 0x0b01 + #define I2S1_SDO 0x0b02 + + #define GPIO0_B1 0x0b10 + #define MMC1_CLKOUT 0x0b11 + #define I2S1_MCLK 0x0b12 + + #define GPIO0_B3 0x0b30 + #define MMC1_D0 0x0b31 + #define I2S1_LRCKRX 0x0b32 + + #define GPIO0_B4 0x0b40 + #define MMC1_D1 0x0b41 + #define I2S1_LRCKTX 0x0b42 + + #define GPIO0_B5 0x0b50 + #define MMC1_D2 0x0b51 + #define I2S1_SDI 0x0b52 + + #define GPIO0_B6 0x0b60 + #define MMC1_D3 0x0b61 + #define I2S1_SCLK 0x0b62 + + + /* GPIO0_C */ + #define GPIO0_C0 0x0c00 + #define UART0_SOUT 0x0c01 + + #define GPIO0_C1 0x0c10 + #define UART0_SIN 0x0c11 + + #define GPIO0_C2 0x0c20 + #define UART0_RTSN 0x0c21 + + #define GPIO0_C3 0x0c30 + #define UART0_CTSN 0x0c31 + + #define GPIO0_C4 0x0c40 + #define DRIVE_VBUS 0x0c41 + + + /* GPIO0_D */ + #define GPIO0_D2 0x0d20 + #define PWM0 0x0d21 + + #define GPIO0_D3 0x0d30 + #define PWM3(IR) 0x0d31 + + #define GPIO0_D4 0x0d40 + #define SPDIF_TX 0x0d41 + + + /* GPIO1_A */ + #define GPIO1_A0 0x1a00 + #define I2S0_MCLK 0x1a01 + + #define GPIO1_A1 0x1a10 + #define I2S0_SCLK 0x1a11 + + #define GPIO1_A2 0x1a20 + #define I2S0_LRCKRX 0x1a21 + #define PWM1_0 0x1a22 + + #define GPIO1_A3 0x1a30 + #define I2S0_LRCKTX 0x1a31 + + #define GPIO1_A4 0x1a40 + #define I2S0_SDO 0x1a41 + + #define GPIO1_A5 0x1a50 + #define I2S0_SDI 0x1a51 + + + /* GPIO1_B */ + #define GPIO1_B0 0x1b00 + #define HDMI_CEC 0x1b01 + + #define GPIO1_B1 0x1b10 + #define HDMI_SDA 0x1b11 + + #define GPIO1_B2 0x1b20 + #define HDMI_SCL 0x1b21 + + #define GPIO1_B3 0x1b30 + #define HDMI_HPD 0x1b31 + + #define GPIO1_B7 0x1b70 + #define MMC0_CMD 0x1b71 + + + /* GPIO1_C */ + #define GPIO1_C0 0x1c00 + #define MMC0_CLKOUT 0x1c01 + + #define GPIO1_C1 0x1c10 + #define MMC0_DETN 0x1c11 + + #define GPIO1_C2 0x1c20 + #define MMC0_D0 0x1c21 + #define UART2_SIN 0x1c22 + + #define GPIO1_C3 0x1c30 + #define MMC0_D1 0x1c31 + #define UART2_SOUT 0x1c32 + + #define GPIO1_C4 0x1c40 + #define MMC0_D2 0x1c41 + #define JTAG_TCK 0x1c42 + + #define GPIO1_C5 0x1c50 + #define MMC0_D3 0x1c51 + #define JTAG_TMS 0x1c52 + + + /* GPIO1_D */ + #define GPIO1_D0 0x1d00 + #define NAND_D0 0x1d01 + #define EMMC_D0 0x1d02 + #define SFC_SIO0 0x1d03 + + #define GPIO1_D1 0x1d10 + #define NAND_D1 0x1d11 + #define EMMC_D1 0x1d12 + #define SFC_SIO1 0x1d13 + + #define GPIO1_D2 0x1d20 + #define NAND_D2 0x1d21 + #define EMMC_D2 0x1d22 + #define SFC_SIO2 0x1d23 + + #define GPIO1_D3 0x1d30 + #define NAND_D3 0x1d31 + #define EMMC_D3 0x1d32 + #define SFC_SIO3 0x1d33 + + #define GPIO1_D4 0x1d40 + #define NAND_D4 0x1d41 + #define EMMC_D4 0x1d42 + #define SPI0_RXD 0x1d43 + + #define GPIO1_D5 0x1d50 + #define NAND_D5 0x1d51 + #define EMMC_D5 0x1d52 + #define SPI0_TXD 0x1d53 + + #define GPIO1_D6 0x1d60 + #define NAND_D6 0x1d61 + #define EMMC_D6 0x1d62 + #define SPI0_CS0 0x1d63 + + #define GPIO1_D7 0x1d70 + #define NAND_D7 0x1d71 + #define EMMC_D7 0x1d72 + #define SPI0_CS1 0x1d73 + + + /* GPIO2_A */ + #define GPIO2_A0 0x2a00 + #define NAND_ALE 0x2a01 + #define SPI0_CLK 0x2a02 + + #define GPIO2_A1 0x2a10 + #define NAND_CLE 0x2a11 + #define EMMC_CLKOUT 0x2a12 + + #define GPIO2_A2 0x2a20 + #define NAND_WRN 0x2a21 + #define SFC_CSN0 0x2a22 + + #define GPIO2_A3 0x2a30 + #define NAND_RDN 0x2a31 + #define SFC_CSN1 0x2a32 + + #define GPIO2_A4 0x2a40 + #define NAND_RDY 0x2a41 + #define EMMC_CMD 0x2a42 + #define SFC_CLK 0x2a43 + + #define GPIO2_A6 0x2a60 + #define NAND_CS0 0x2a61 + + #define GPIO2_A7 0x2a70 + #define TESTCLK_OUT 0x2a71 + + + /* GPIO2_B */ + #define GPIO2_B2 0x2b20 + #define MAC_CRS 0x2b21 + + #define GPIO2_B4 0x2b40 + #define MAC_MDIO 0x2b41 + + #define GPIO2_B5 0x2b50 + #define MAC_TXEN 0x2b51 + + #define GPIO2_B6 0x2b60 + #define MAC_CLKOUT 0x2b61 + #define MAC_CLKIN 0x2b62 + + #define GPIO2_B7 0x2b70 + #define MAC_RXER 0x2b71 + + + /* GPIO2_C */ + #define GPIO2_C0 0x2c00 + #define MAC_RXD1 0x2c01 + + #define GPIO2_C1 0x2c10 + #define MAC_RXD0 0x2c11 + + #define GPIO2_C2 0x2c20 + #define MAC_TXD1 0x2c21 + + #define GPIO2_C3 0x2c30 + #define MAC_TXD0 0x2c31 + + #define GPIO2_C4 0x2c40 + #define I2C2_SDA 0x2c41 + + #define GPIO2_C5 0x2c50 + #define I2C2_SCL 0x2c51 + + #define GPIO2_C6 0x2c60 + #define UART1_SIN 0x2c61 + + #define GPIO2_C7 0x2c70 + #define UART1_SOUT 0x2c71 + #define TESTCLK_OUT1 0x2c72 + + + /* GPIO2_D */ + #define GPIO2_D1 0x2d10 + #define MAC_MDC 0x2d11 + + #define GPIO2_D4 0x2d40 + #define I2S0_SDO3 0x2d41 + + #define GPIO2_D5 0x2d50 + #define I2S0_SDO2 0x2d51 + + #define GPIO2_D6 0x2d60 + #define I2S0_SDO1 0x2d61 + + +#endif diff --git a/include/dt-bindings/pinctrl/rockchip-rk312x.h b/include/dt-bindings/pinctrl/rockchip-rk312x.h new file mode 100644 index 000000000000..e0fa5976c18f --- /dev/null +++ b/include/dt-bindings/pinctrl/rockchip-rk312x.h @@ -0,0 +1,384 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_RK312X_H__ +#define __DT_BINDINGS_ROCKCHIP_PINCTRL_RK312X_H__ + +/* GPIO0_A */ +#define GPIO0_A0 0x0a00 +#define I2C0_SCL 0x0a01 + +#define GPIO0_A1 0x0a10 +#define I2C0_SDA 0x0a11 + +#define GPIO0_A2 0x0a20 +#define I2C1_SCL 0x0a21 + +#define GPIO0_A3 0x0a30 +#define I2C1_SDA 0x0a31 +#define MMC1_CMD 0x0a32 + +#define GPIO0_A6 0x0a60 +#define I2C3_SCL 0x0a61 +#define HDMI_DSCL 0x0a62 + +#define GPIO0_A7 0x0a70 +#define I2C3_SDA 0x0a71 +#define HDMI_DSDA 0x0a72 + + +/* GPIO0_B */ +#define GPIO0_B0 0x0b00 +#define I2S0_MCLK_MUX0 0x0b01 + +#define GPIO0_B1 0x0b10 +#define I2S0_SCLK_MUX0 0x0b11 +#define SPI0_CLK_MUX2 0x0b12 + +#define GPIO0_B3 0x0b30 +#define I2S0_LRCKRX_MUX0 0x0b31 +#define SPI0_TXD_MUX2 0x0b32 + +#define GPIO0_B4 0x0b40 +#define I2S0_LRCKTX_MUX0 0x0b41 + +#define GPIO0_B5 0x0b50 +#define I2S0_SDO_MUX0 0x0b51 +#define SPI0_RXD_MUX2 0x0b52 + +#define GPIO0_B6 0x0b60 +#define I2S0_SDI_MUX0 0x0b61 +#define SPI0_CS0_MUX2 0x0b62 + +#define GPIO0_B7 0x0b70 +#define HDMI_HPD 0x0b71 + + +/* GPIO0_C */ +#define GPIO0_C1 0x0c10 +#define SC_IO 0x0c11 +#define UART0_RTSN 0x0c12 + +#define GPIO0_C4 0x0c40 +#define HDMI_CEC 0x0c41 + +#define GPIO0_C7 0x0c70 +#define NAND_CS1 0x0c71 + + +/* GPIO0_D */ +#define GPIO0_D0 0x0d00 +#define UART2_RTSN 0x0d01 +#define PMIC_SLEEP_MUX0 0x0d02 + +#define GPIO0_D1 0x0d10 +#define UART2_CTSN 0x0d11 + +#define GPIO0_D2 0x0d20 +#define PWM0 0x0d21 + +#define GPIO0_D3 0x0d30 +#define PWM1 0x0d31 + +#define GPIO0_D4 0x0d40 +#define PWM2 0x0d41 + +#define GPIO0_D6 0x0d60 +#define MMC1_PWREN 0x0d61 + + +/* GPIO1_A */ +#define GPIO1_A0 0x1a00 +#define I2S0_MCLK_MUX1 0x1a01 +#define SDMMC_CLKOUT 0x1a02 +#define XIN32K 0x1a03 + +#define GPIO1_A1 0x1a10 +#define I2S0_SCLK_MUX1 0x1a11 +#define SDMMC_DATA0 0x1a12 +#define PMIC_SLEEP_MUX1 0x1a13 + +#define GPIO1_A2 0x1a20 +#define I2S0_LRCKRX_MUX1 0x1a21 +#define SDMMC_DATA1 0x1a22 + +#define GPIO1_A3 0x1a30 +#define I2S0_LRCKTX_MUX1 0x1a31 + +#define GPIO1_A4 0x1a40 +#define I2S0_SDO_MUX1 0x1a41 +#define SDMMC_DATA2 0x1a42 + +#define GPIO1_A5 0x1a50 +#define I2S0_SDI_MUX1 0x1a51 +#define SDMMC_DATA3 0x1a52 + +#define GPIO1_A7 0x1a70 +#define MMC0_WRPRT 0x1a71 + + +/* GPIO1_B */ +#define GPIO1_B0 0x1b00 +#define SPI0_CLK_MUX0 0x1b01 +#define UART1_CTSN 0x1b02 + +#define GPIO1_B1 0x1b10 +#define SPI0_TXD_MUX0 0x1b11 +#define UART1_SOUT 0x1b12 + +#define GPIO1_B2 0x1b20 +#define SPI0_RXD_MUX0 0x1b21 +#define UART1_SIN 0x1b22 + +#define GPIO1_B3 0x1b30 +#define SPI0_CS0_MUX0 0x1b31 +#define UART1_RTSN 0x1b32 + +#define GPIO1_B4 0x1b40 +#define SPI0_CS1_MUX0 0x1b41 + +#define GPIO1_B6 0x1b60 +#define MMC0_PWREN 0x1b61 + +#define GPIO1_B7 0x1b70 +#define MMC0_CMD 0x1b71 + + +/* GPIO1_C */ +#define GPIO1_C0 0x1c00 +#define MMC0_CLKOUT 0x1c01 + +#define GPIO1_C1 0x1c10 +#define MMC0_DETN 0x1c11 + +#define GPIO1_C2 0x1c20 +#define MMC0_D0 0x1c21 +#define UART2_SOUT 0x1c22 + +#define GPIO1_C3 0x1c30 +#define MMC0_D1 0x1c31 +#define UART2_SIN 0x1c32 + +#define GPIO1_C4 0x1c40 +#define MMC0_D2 0x1c41 +#define JTAG_TCK 0x1c42 + +#define GPIO1_C5 0x1c50 +#define MMC0_D3 0x1c51 +#define JTAG_TMS 0x1c52 + +#define GPIO1_C6 0x1c60 +#define NAND_CS2 0x1c61 +#define EMMC_CMD_MUX0 0x1c62 + +#define GPIO1_C7 0x1c70 +#define NAND_CS3 0x1c71 +#define EMMC_RSTNOUT 0x1c72 + + +/* GPIO1_D */ +#define GPIO1_D0 0x1d00 +#define NAND_D0 0x1d01 +#define EMMC_D0 0x1d02 +#define SFC_D0 0x1d03 + +#define GPIO1_D1 0x1d10 +#define NAND_D1 0x1d11 +#define EMMC_D1 0x1d12 +#define SFC_D1 0x1d13 + +#define GPIO1_D2 0x1d20 +#define NAND_D2 0x1d21 +#define EMMC_D2 0x1d22 +#define SFC_D2 0x1d23 + +#define GPIO1_D3 0x1d30 +#define NAND_D3 0x1d31 +#define EMMC_D3 0x1d32 +#define SFC_D3 0x1d33 + +#define GPIO1_D4 0x1d40 +#define NAND_D4 0x1d41 +#define EMMC_D4 0x1d42 +#define SPI0_RXD_MUX1 0x1d43 + +#define GPIO1_D5 0x1d50 +#define NAND_D5 0x1d51 +#define EMMC_D5 0x1d52 +#define SPI0_TXD_MUX1 0x1d53 + +#define GPIO1_D6 0x1d60 +#define NAND_D6 0x1d61 +#define EMMC_D6 0x1d62 +#define SPI0_CS0_MUX1 0x1d63 + +#define GPIO1_D7 0x1d70 +#define NAND_D7 0x1d71 +#define EMMC_D7 0x1d72 +#define SPI0_CS1_MUX1 0x1d73 + + +/* GPIO2_A */ +#define GPIO2_A0 0x2a00 +#define NAND_ALE 0x2a01 +#define SPI0_CLK_MUX1 0x2a02 + +#define GPIO2_A1 0x2a10 +#define NAND_CLE 0x2a11 + +#define GPIO2_A2 0x2a20 +#define NAND_WRN 0x2a21 +#define SFC_CSN0 0x2a22 + +#define GPIO2_A3 0x2a30 +#define NAND_RDN 0x2a31 +#define SFC_CSN1 0x2a32 + +#define GPIO2_A4 0x2a40 +#define NAND_RDY 0x2a41 +#define EMMC_CMD_MUX1 0x2a42 +#define SFC_CLK 0x2a43 + +#define GPIO2_A5 0x2a50 +#define NAND_WP 0x2a51 +#define EMMC_PWREN 0x2a52 + +#define GPIO2_A6 0x2a60 +#define NAND_CS0 0x2a61 + +#define GPIO2_A7 0x2a70 +#define NAND_DQS 0x2a71 +#define EMMC_CLKOUT 0x2a72 + + +/* GPIO2_B */ +#define GPIO2_B0 0x2b00 +#define LCDC0_DCLK 0x2b01 +#define EBC_SDCLK 0x2b02 +#define GMAC_RXDV 0x2b03 + +#define GPIO2_B1 0x2b10 +#define LCDC0_HSYNC 0x2b11 +#define EBC_SDLE 0x2b12 +#define GMAC_TXCLK 0x2b13 + +#define GPIO2_B2 0x2b20 +#define LCDC0_VSYNC 0x2b21 +#define EBC_SDOE 0x2b22 +#define GMAC_CRS 0x2b23 + +#define GPIO2_B3 0x2b30 +#define LCDC0_DEN 0x2b31 +#define EBC_GDCLK 0x2b32 +#define GMAC_RXCLK 0x2b33 + +#define GPIO2_B4 0x2b40 +#define LCDC0_D10 0x2b41 +#define EBC_SDCE2 0x2b42 +#define GMAC_MDIO 0x2b43 + +#define GPIO2_B5 0x2b50 +#define LCDC0_D11 0x2b51 +#define EBC_SDCE3 0x2b52 +#define GMAC_TXEN 0x2b53 + +#define GPIO2_B6 0x2b60 +#define LCDC0_D12 0x2b61 +#define EBC_SDCE4 0x2b62 +#define GMAC_CLK 0x2b63 + +#define GPIO2_B7 0x2b70 +#define LCDC0_D13 0x2b71 +#define EBC_SDCE5 0x2b72 +#define GMAC_RXER 0x2b73 + + +/* GPIO2_C */ +#define GPIO2_C0 0x2c00 +#define LCDC0_D14 0x2c01 +#define EBC_VCOM 0x2c02 +#define GMAC_RXD1 0x2c03 + +#define GPIO2_C1 0x2c10 +#define LCDC0_D15 0x2c11 +#define EBC_GDOE 0x2c12 +#define GMAC_RXD0 0x2c13 + +#define GPIO2_C2 0x2c20 +#define LCDC0_D16 0x2c21 +#define EBC_GDSP 0x2c22 +#define GMAC_TXD1 0x2c23 + +#define GPIO2_C3 0x2c30 +#define LCDC0_D17 0x2c31 +#define EBC_GDPWR0 0x2c32 +#define GMAC_TXD0 0x2c33 + +#define GPIO2_C4 0x2c40 +#define LCDC0_D18 0x2c41 +#define EBC_GDRL 0x2c42 +#define I2C2_SDA 0x2c43 +#define GMAC_RXD3 0x2c44 + +#define GPIO2_C5 0x2c50 +#define LCDC0_D19 0x2c51 +#define EBC_SDSHR 0x2c52 +#define I2C2_SCL 0x2c53 +#define GMAC_RXD2 0x2c54 + +#define GPIO2_C6 0x2c60 +#define LCDC0_D20 0x2c61 +#define EBC_BORDER0 0x2c62 +#define GPS_SIGN 0x2c63 +#define GMAC_TXD2 0x2c64 + +#define GPIO2_C7 0x2c70 +#define LCDC0_D21 0x2c71 +#define EBC_BORDER1 0x2c72 +#define GPS_MAG 0x2c73 +#define GMAC_TXD3 0x2c74 + + +/* GPIO2_D */ +#define GPIO2_D0 0x2d00 +#define LCDC0_D22 0x2d01 +#define EBC_GDPWR1 0x2d02 +#define GPS_CLK 0x2d03 +#define GMAC_COL 0x2d04 + +#define GPIO2_D1 0x2d10 +#define LCDC0_D23 0x2d11 +#define EBC_GDPWR2 0x2d12 +#define GMAC_MDC 0x2d13 + +#define GPIO2_D2 0x2d20 +#define SC_RST 0x2d21 +#define UART0_SOUT 0x2d22 + +#define GPIO2_D3 0x2d30 +#define SC_CLK 0x2d31 +#define UART0_SIN 0x2d32 + +#define GPIO2_D5 0x2d50 +#define SC_DET 0x2d51 +#define UART0_CTSN 0x2d52 + + +/* GPIO3_A */ +/* GPIO3_B */ +#define GPIO3_B3 0x3b30 +#define TESTCLK_OUT 0x3b31 + + +/* GPIO3_C */ +#define GPIO3_C1 0x3c10 +#define OTG_DRVVBUS 0x3c11 + + +/* GPIO3_D */ +#define GPIO3_D2 0x3d20 +#define PWM_IRIN 0x3d21 + +#define GPIO3_D3 0x3d30 +#define SPDIF_TX 0x3d31 + + +#endif diff --git a/include/dt-bindings/pinctrl/rockchip-rk3188.h b/include/dt-bindings/pinctrl/rockchip-rk3188.h new file mode 100755 index 000000000000..58bba225d1de --- /dev/null +++ b/include/dt-bindings/pinctrl/rockchip-rk3188.h @@ -0,0 +1,457 @@ +/* + * Header providing constants for Rockchip pinctrl bindings. + * + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_RK3188_H__ +#define __DT_BINDINGS_ROCKCHIP_PINCTRL_RK3188_H__ + + +/* GPIO0_A */ +#define GPIO0_A0 0x0A00 +#define GPIO0_A1 0x0A10 + +/* GPIO0_B */ +/* GPIO0_C */ +#define GPIO0_C0 0x0c00 +#define NAND_D8 0x0c01 + +#define GPIO0_C1 0x0c10 +#define NAND_D9 0x0c11 + +#define GPIO0_C2 0x0c20 +#define NAND_D10 0x0c21 + +#define GPIO0_C3 0x0c30 +#define NAND_D11 0x0c31 + +#define GPIO0_C4 0x0c40 +#define NAND_D12 0x0c41 + +#define GPIO0_C5 0x0c50 +#define NAND_D13 0x0c51 + +#define GPIO0_C6 0x0c60 +#define NAND_D14 0x0c61 + +#define GPIO0_C7 0x0c70 +#define NAND_D15 0x0c71 + + +/* GPIO0_D */ +#define GPIO0_D0 0x0d00 +#define NAND_DQS 0x0d01 +#define EMMC_CLKOUT 0x0d02 + +#define GPIO0_D1 0x0d10 +#define NAND_CS1 0x0d11 + +#define GPIO0_D2 0x0d20 +#define NAND_CS2 0x0d21 +#define EMMC_CMD 0x0d22 + +#define GPIO0_D3 0x0d30 +#define NAND_CS3 0x0d31 +#define EMMC_RSTNOUT 0x0d32 + +#define GPIO0_D4 0x0d40 +#define SPI1_RXD 0x0d41 + +#define GPIO0_D5 0x0d50 +#define SPI1_TXD 0x0d51 + +#define GPIO0_D6 0x0d60 +#define SPI1_CLK 0x0d61 + +#define GPIO0_D7 0x0d70 +#define SPI1_CS0 0x0d71 + + +/* GPIO1_A */ +#define GPIO1_A0 0x1a00 +#define UART0_SIN 0x1a01 + +#define GPIO1_A1 0x1a10 +#define UART0_SOUT 0x1a11 + +#define GPIO1_A2 0x1a20 +#define UART0_CTSN 0x1a21 + +#define GPIO1_A3 0x1a30 +#define UART0_RTSN 0x1a31 + +#define GPIO1_A4 0x1a40 +#define UART1_SIN 0x1a41 +#define SPI0_RXD 0x1a42 + +#define GPIO1_A5 0x1a50 +#define UART1_SOUT 0x1a51 +#define SPI0_TXD 0x1a52 + +#define GPIO1_A6 0x1a60 +#define UART1_CTSN 0x1a61 +#define SPI0_CLK 0x1a62 + +#define GPIO1_A7 0x1a70 +#define UART1_RTSN 0x1a71 +#define SPI0_CS0 0x1a72 + +/* GPIO1_B */ +#define GPIO1_B0 0x1b00 +#define UART2_SIN 0x1b01 +#define JTAG_TDI 0x1b02 + +#define GPIO1_B1 0x1b10 +#define UART2_SOUT 0x1b11 +#define JTAG_TDO 0x1b12 + +#define GPIO1_B2 0x1b20 +#define UART3_SIN 0x1b21 +#define GPS_MAG 0x1b22 + +#define GPIO1_B3 0x1b30 +#define UART3_SOUT 0x1b31 +#define GPS_SIG 0x1b32 + +#define GPIO1_B4 0x1b40 +#define UART3_CTSN 0x1b41 +#define GPS_RFCLK 0x1b42 + +#define GPIO1_B5 0x1b50 +#define UART3_RTSN 0x1b51 + +#define GPIO1_B6 0x1b60 +#define SPDIF_TX 0x1b61 +#define SPI1_CS1 0x1b62 + +#define GPIO1_B7 0x1b70 +#define SPI0_CS1 0x1b71 + + +/* GPIO1_C */ +#define GPIO1_C0 0x1c00 +#define I2S0_MCLK 0x1c01 + +#define GPIO1_C1 0x1c10 +#define I2S0_SCLK 0x1c11 + +#define GPIO1_C2 0x1c20 +#define I2S0_LRCKRX 0x1c21 + +#define GPIO1_C3 0x1c30 +#define I2S0_LRCKTX 0x1c31 + +#define GPIO1_C4 0x1c40 +#define I2S0_SDI 0x1c41 + +#define GPIO1_C5 0x1c50 +#define I2S0_SDO 0x1c51 + + +/* GPIO1_D */ +#define GPIO1_D0 0x1d00 +#define I2C0_SDA 0x1d01 + +#define GPIO1_D1 0x1d10 +#define I2C0_SCL 0x1d11 + +#define GPIO1_D2 0x1d20 +#define I2C1_SDA 0x1d21 + +#define GPIO1_D3 0x1d30 +#define I2C1_SCL 0x1d31 + +#define GPIO1_D4 0x1d40 +#define I2C2_SDA 0x1d41 + +#define GPIO1_D5 0x1d50 +#define I2C2_SCL 0x1d51 + +#define GPIO1_D6 0x1d60 +#define I2C4_SDA 0x1d61 + +#define GPIO1_D7 0x1d70 +#define I2C4_SCL 0x1d71 + + +/* GPIO2_A */ +#define GPIO2_A0 0x2a00 +#define LCDC1_D0 0x2a01 +#define SMC_D0 0x2a02 +#define TRACE_D0 0x2a03 + +#define GPIO2_A1 0x2a10 +#define LCDC1_D1 0x2a11 +#define SMC_D1 0x2a12 +#define TRACE_D1 0x2a13 + +#define GPIO2_A2 0x2a20 +#define LCDC1_D2 0x2a21 +#define SMC_D2 0x2a22 +#define TRACE_D2 0x2a23 + +#define GPIO2_A3 0x2a30 +#define LCDC1_D3 0x2a31 +#define SMC_D3 0x2a32 +#define TRACE_D3 0x2a33 + +#define GPIO2_A4 0x2a40 +#define LCDC1_D4 0x2a41 +#define SMC_D4 0x2a42 +#define TRACE_D4 0x2a43 + +#define GPIO2_A5 0x2a50 +#define LCDC1_D5 0x2a51 +#define SMC_D5 0x2a52 +#define TRACE_D5 0x2a53 + +#define GPIO2_A6 0x2a60 +#define LCDC1_D6 0x2a61 +#define SMC_D6 0x2a62 +#define TRACE_D6 0x2a63 + +#define GPIO2_A7 0x2a70 +#define LCDC1_D7 0x2a71 +#define SMC_D7 0x2a72 +#define TRACE_D7 0x2a73 + + +/* GPIO2_B */ +#define GPIO2_B0 0x2b00 +#define LCDC1_D8 0x2b01 +#define SMC_D8 0x2b02 +#define TRACE_D8 0x2b03 + +#define GPIO2_B1 0x2b10 +#define LCDC1_D9 0x2b11 +#define SMC_D9 0x2b11 +#define TRACE_D9 0x2b12 + +#define GPIO2_B2 0x2b20 +#define LCDC1_D10 0x2b21 +#define SMC_D10 0x2b22 +#define TRACE_D10 0x2b23 + +#define GPIO2_B3 0x2b30 +#define LCDC1_D11 0x2b31 +#define SMC_D11 0x2b32 +#define TRACE_D11 0x2b33 + +#define GPIO2_B4 0x2b40 +#define LCDC1_D12 0x2b41 +#define SMC_D12 0x2b42 +#define TRACE_D12 0x2b43 + +#define GPIO2_B5 0x2b50 +#define LCDC1_D13 0x2b51 +#define SMC_D13 0x2b52 +#define TRACE_D13 0x2b53 + +#define GPIO2_B6 0x2b60 +#define LCDC1_D14 0x2b61 +#define SMC_D14 0x2b62 +#define TRACE_D14 0x2b63 + + +#define GPIO2_B7 0x2b70 +#define LCDC1_D15 0x2b71 +#define SMC_D15 0x2b72 +#define TRACE_D15 0x2b73 + + +/* GPIO2_C */ +#define GPIO2_C0 0x2c00 +#define LCDC1_D16 0x2c01 +#define SMC_R0 0x2c02 +#define TRACE_CLK 0x2c03 + +#define GPIO2_C1 0x2c10 +#define LCDC1_D17 0x2c11 +#define SMC_R1 0x2c12 +#define TRACE_CTL 0x2c13 + +#define GPIO2_C2 0x2c20 +#define LCDC1_D18 0x2c21 +#define SMC_R2 0x2c22 + +#define GPIO2_C3 0x2c30 +#define LCDC1_D19 0x2c31 +#define SMC_R3 0x2c32 + +#define GPIO2_C4 0x2c40 +#define LCDC1_D20 0x2c41 +#define SMC_R4 0x2c42 + +#define GPIO2_C5 0x2c50 +#define LCDC1_D21 0x2c51 +#define SMC_R5 0x2c52 + +#define GPIO2_C6 0x2c60 +#define LCDC1_D22 0x2c61 +#define SMC_R6 0x2c62 + +#define GPIO2_C7 0x2c70 +#define LCDC1_D23 0x2c71 +#define SMC_R7 0x2c72 + + +/* GPIO2_D */ +#define GPIO2_D0 0x2d00 +#define LCDC1_DCLK 0x2d01 +#define SMC_CS0 0x2d02 + +#define GPIO2_D1 0x2d10 +#define LCDC1_DEN 0x2d11 +#define SMC_WEN 0x2d12 + +#define GPIO2_D2 0x2d20 +#define LCDC1_HSYNC 0x2d21 +#define SMC_OEN 0x2d22 + +#define GPIO2_D3 0x2d30 +#define LCDC1_VSYNC 0x2d31 +#define SMC_ADVN 0x2d32 + +#define GPIO2_D4 0x2d40 +#define SMC_BLSN0 0x2d41 + +#define GPIO2_D5 0x2d50 +#define SMC_BLSN1 0x2d51 + +#define GPIO2_D6 0x2d60 +#define SMC_CS1 0x2d61 + +#define GPIO2_D7 0x2d70 +#define TEST_CLK_OUT 0x2d71 + + +/* GPIO3_A */ +#define GPIO3_A0 0x3a00 +#define MMC0_RSTNOUT 0x3a01 + +#define GPIO3_A1 0x3a10 +#define MMC0_PWREN 0x3a11 + +#define GPIO3_A2 0x3a20 +#define MMC0_CLKOUT 0x3a21 + +#define GPIO3_A3 0x3a30 +#define MMC0_CMD 0x3a31 + +#define GPIO3_A4 0x3a40 +#define MMC0_D0 0x3a41 + +#define GPIO3_A5 0x3a50 +#define MMC0_D1 0x3a51 + +#define GPIO3_A6 0x3a60 +#define MMC0_D2 0x3a61 + +#define GPIO3_A7 0x3a70 +#define MMC0_D3 0x3a71 + + +/* GPIO3_B */ +#define GPIO3_B0 0x3b00 +#define MMC0_DETN 0x3b01 + +#define GPIO3_B1 0x3b10 +#define MMC0_WRPRT 0x3b11 + +#define GPIO3_B3 0x3b30 +#define CIF0_CLKOUT 0x3b31 + +#define GPIO3_B4 0x3b40 +#define CIF0_D0 0x3b41 +#define HSADC_D8 0x3b42 + +#define GPIO3_B5 0x3b50 +#define CIF0_D1 0x3b51 +#define HSADC_D9 0x3b52 + +#define GPIO3_B6 0x3b60 +#define CIF0_D10 0x3b61 +#define I2C3_SDA 0x3b62 + +#define GPIO3_B7 0x3b70 +#define CIF0_D11 0x3b71 +#define I2C3_SCL 0x3b72 + + +/* GPIO3_C */ +#define GPIO3_C0 0x3c00 +#define MMC1_CMD 0x3c01 +#define RMII_TXEN 0x3c02 + +#define GPIO3_C1 0x3c10 +#define MMC1_D0 0x3c11 +#define RMII_TXD1 0x3c12 + +#define GPIO3_C2 0x3c20 +#define MMC1_D1 0x3c21 +#define RMII_TXD0 0x3c22 + +#define GPIO3_C3 0x3c30 +#define MMC1_D2 0x3c31 +#define RMII_RXD0 0x3c32 + +#define GPIO3_C4 0x3c40 +#define MMC1_D3 0x3c41 +#define RMII_RXD1 0x3c42 + +#define GPIO3_C5 0x3c50 +#define MMC1_CLKOUT 0x3c51 +#define RMII_CLKOUT 0x3c52 +#define RMII_CLKIN 0x3c52 + +#define GPIO3_C6 0x3c60 +#define MMC1_DETN 0x3c61 +#define RMII_RXERR 0x3c62 + +#define GPIO3_C7 0x3c70 +#define MMC1_WRPRT 0x3c71 +#define RMII_CRS 0x3c72 + + +/* GPIO3_D */ +#define GPIO3_D0 0x3d00 +#define MMC1_PWREN 0x3d01 +#define RMII_MD 0x3d02 + +#define GPIO3_D1 0x3d10 +#define MMC1_BKEPWR 0x3d11 +#define RMII_MDCLK 0x3d12 + +#define GPIO3_D2 0x3d20 +#define MMC1_INTN 0x3d21 + +#define GPIO3_D3 0x3d30 +#define PWM0 0x3d31 + +#define GPIO3_D4 0x3d40 +#define PWM1 0x3d41 +#define JTAG_TRSTN 0x3d42 + +#define GPIO3_D5 0x3d50 +#define PWM2 0x3d51 +#define JTAG_TCK 0x3d52 +#define OTG_DRV_VBUS 0x3d53 + +#define GPIO3_D6 0x3d60 +#define PWM3 0x3d61 +#define JTAG_TMS 0x3d62 +#define HOST_DRV_VBUS 0x3d63 + +#endif diff --git a/include/dt-bindings/pinctrl/rockchip-rk3288.h b/include/dt-bindings/pinctrl/rockchip-rk3288.h new file mode 100755 index 000000000000..97aa66e2b329 --- /dev/null +++ b/include/dt-bindings/pinctrl/rockchip-rk3288.h @@ -0,0 +1,666 @@ +/* + * Header providing constants for Rockchip pinctrl bindings. + * + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_RK3288_H__ +#define __DT_BINDINGS_ROCKCHIP_PINCTRL_RK3288_H__ + +/* GPIO0_A */ +#define GPIO0_A0 0x0a00 +#define GLOBAL_PWROFF 0x0a01 + +#define GPIO0_A1 0x0a10 +#define DDRIO_PWROFF 0x0a11 + +#define GPIO0_A2 0x0a20 +#define DDR0_RETENTION 0x0a21 + +#define GPIO0_A3 0x0a30 +#define DDR1_RETENTION 0x0a31 + +#define GPIO0_A4 0x0a40 + +#define GPIO0_A5 0x0a50 + +#define GPIO0_A6 0x0a60 + +#define GPIO0_A7 0x0a70 + +/* GPIO0_B */ +#define GPIO0_B0 0x0b00 + +#define GPIO0_B1 0x0b10 + +#define GPIO0_B2 0x0b20 +#define TSADC_INT 0x0b21 + +#define GPIO0_B3 0x0b30 + +#define GPIO0_B4 0x0b40 + +#define GPIO0_B5 0x0b50 +#define CLK_27M 0x0b51 + +#define GPIO0_B6 0x0b60 + +#define GPIO0_B7 0x0b70 +#define I2C0PMU_SDA 0x0b71 + + +/* GPIO0_C */ +#define GPIO0_C0 0x0c00 +#define I2C0PMU_SCL 0x0c01 + +#define GPIO0_C1 0x0c10 +#define TEST_CLKOUT 0x0c11 +#define CLKT1_27M 0x0c12 + +#define GPIO0_C2 0x0c20 + + +/* GPIO1_A */ +/* GPIO1_B */ +/* GPIO1_C */ +/* GPIO1_D */ +#define GPIO1_D0 0x1d00 +#define LCDC0_HSYNC_GPIO1D 0x1d01 + +#define GPIO1_D1 0x1d10 +#define LCDC0_VSYNC_GPIO1D 0x1d11 + +#define GPIO1_D2 0x1d20 +#define LCDC0_DEN_GPIO1D 0x1d21 + +#define GPIO1_D3 0x1d30 +#define LCDC0_DCLK_GPIO1D 0x1d31 + + +/* GPIO2_A */ +#define GPIO2_A0 0x2a00 +#define CIF_DATA2 0x2a01 +#define HOST_DIN0 0x2a02 +#define HSADC_DATA0 0x2a03 + +#define GPIO2_A1 0x2a10 +#define CIF_DATA3 0x2a11 +#define HOST_DIN1 0x2a12 +#define HSADC_DATA1 0x2a13 + +#define GPIO2_A2 0x2a20 +#define CIF_DATA4 0x2a21 +#define HOST_DIN2 0x2a22 +#define HSADC_DATA2 0x2a23 + +#define GPIO2_A3 0x2a30 +#define CIF_DATA5 0x2a31 +#define HOST_DIN3 0x2a32 +#define HSADC_DATA3 0x2a33 + +#define GPIO2_A4 0x2a40 +#define CIF_DATA6 0x2a41 +#define HOST_CKINP 0x2a42 +#define HSADC_DATA4 0x2a43 + +#define GPIO2_A5 0x2a50 +#define CIF_DATA7 0x2a51 +#define HOST_CKINN 0x2a52 +#define HSADC_DATA5 0x2a53 + +#define GPIO2_A6 0x2a60 +#define CIF_DATA8 0x2a61 +#define HOST_DIN4 0x2a62 +#define HSADC_DATA6 0x2a63 + +#define GPIO2_A7 0x2a70 +#define CIF_DATA9 0x2a71 +#define HOST_DIN5 0x2a72 +#define HSADC_DATA7 0x2a73 + + +/* GPIO2_B */ +#define GPIO2_B0 0x2b00 +#define CIF_VSYNC 0x2b01 +#define HOST_DIN6 0x2b02 +#define HSADCTS_SYNC 0x2b03 + +#define GPIO2_B1 0x2b10 +#define CIF_HREF 0x2b11 +#define HOST_DIN7 0x2b12 +#define HSADCTS_VALID 0x2b13 + +#define GPIO2_B2 0x2b20 +#define CIF_CLKIN 0x2b21 +#define HOST_WKACK 0x2b22 +#define GPS_CLK 0x2b23 + +#define GPIO2_B3 0x2b30 +#define CIF_CLKOUT 0x2b31 +#define HOST_WKREQ 0x2b32 +#define HSADCTS_FAIL 0x2b33 + +#define GPIO2_B4 0x2b40 +#define CIF_DATA0 0x2b41 + +#define GPIO2_B5 0x2b50 +#define CIF_DATA1 0x2b51 + +#define GPIO2_B6 0x2b60 +#define CIF_DATA10 0x2b61 + +#define GPIO2_B7 0x2b70 +#define CIF_DATA11 0x2b71 + + +/* GPIO2_C */ +#define GPIO2_C0 0x2c00 +#define I2C3CAM_SCL 0x2c01 + +#define GPIO2_C1 0x2c10 +#define I2C3CAM_SDA 0x2c11 + + +/* GPIO2_D */ +/* GPIO3_A */ +#define GPIO3_A0 0x3a00 +#define FLASH0_DATA0 0x3a01 +#define EMMC_DATA0 0x3a02 + +#define GPIO3_A1 0x3a10 +#define FLASH0_DATA1 0x3a11 +#define EMMC_DATA1 0x3a12 + +#define GPIO3_A2 0x3a20 +#define FLASH0_DATA2 0x3a21 +#define EMMC_DATA2 0x3a22 + +#define GPIO3_A3 0x3a30 +#define FLASH0_DATA3 0x3a31 +#define EMMC_DATA3 0x3a32 + +#define GPIO3_A4 0x3a40 +#define FLASH0_DATA4 0x3a41 +#define EMMC_DATA4 0x3a42 + +#define GPIO3_A5 0x3a50 +#define FLASH0_DATA5 0x3a51 +#define EMMC_DATA5 0x3a52 + +#define GPIO3_A6 0x3a60 +#define FLASH0_DATA6 0x3a61 +#define EMMC_DATA6 0x3a62 + +#define GPIO3_A7 0x3a70 +#define FLASH0_DATA7 0x3a71 +#define EMMC_DATA7 0x3a72 + + +/* GPIO3_B */ +#define GPIO3_B0 0x3b00 +#define FLASH0_RDY 0x3b01 + +#define GPIO3_B1 0x3b10 +#define FLASH0_WP 0x3b11 +#define EMMC_PWREN 0x3b12 + +#define GPIO3_B2 0x3b20 +#define FLASH0_RDN 0x3b21 + +#define GPIO3_B3 0x3b30 +#define FLASH0_ALE 0x3b31 + +#define GPIO3_B4 0x3b40 +#define FLASH0_CLE 0x3b41 + +#define GPIO3_B5 0x3b50 +#define FLASH0_WRN 0x3b51 + +#define GPIO3_B6 0x3b60 +#define FLASH0_CSN0 0x3b61 + +#define GPIO3_B7 0x3b70 +#define FLASH0_CSN1 0x3b71 + + +/* GPIO3_C */ +#define GPIO3_C0 0x3c00 +#define FLASH0_CSN2 0x3c01 +#define EMMC_CMD 0x3c02 + +#define GPIO3_C1 0x3c10 +#define FLASH0_CSN3 0x3c11 +#define EMMC_RSTNOUT 0x3c12 + +#define GPIO3_C2 0x3c20 +#define FLASH0_DQS 0x3c21 +#define EMMC_CLKOUT 0x3c22 + + +/* GPIO3_D */ +#define GPIO3_D0 0x3d00 +#define FLASH1_DATA0 0x3d01 +#define HOST_DOUT0 0x3d02 +#define MAC_TXD2 0x3d03 +#define SDIO1_DATA0 0x3d04 + +#define GPIO3_D1 0x3d10 +#define FLASH1_DATA1 0x3d11 +#define HOST_DOUT1 0x3d12 +#define MAC_TXD3 0x3d13 +#define SDIO1_DATA1 0x3d14 + +#define GPIO3_D2 0x3d20 +#define FLASH1_DATA2 0x3d21 +#define HOST_DOUT2 0x3d22 +#define MAC_RXD2 0x3d23 +#define SDIO1_DATA2 0x3d24 + +#define GPIO3_D3 0x3d30 +#define FLASH1_DATA3 0x3d31 +#define HOST_DOUT3 0x3d32 +#define MAC_RXD3 0x3d33 +#define SDIO1_DATA3 0x3d34 + +#define GPIO3_D4 0x3d40 +#define FLASH1_DATA4 0x3d41 +#define HOST_DOUT4 0x3d42 +#define MAC_TXD0 0x3d43 +#define SDIO1_DETECTN 0x3d44 + +#define GPIO3_D5 0x3d50 +#define FLASH1_DATA5 0x3d51 +#define HOST_DOUT5 0x3d52 +#define MAC_TXD1 0x3d53 +#define SDIO1_WRPRT 0x3d54 + +#define GPIO3_D6 0x3d60 +#define FLASH1_DATA6 0x3d61 +#define HOST_DOUT6 0x3d62 +#define MAC_RXD0 0x3d63 +#define SDIO1_BKPWR 0x3d64 + +#define GPIO3_D7 0x3d70 +#define FLASH1_DATA7 0x3d71 +#define HOST_DOUT7 0x3d72 +#define MAC_RXD1 0x3d73 +#define SDIO1_INTN 0x3d74 + + +/* GPIO4_A */ +#define GPIO4_A0 0x4a00 +#define FLASH1_RDY 0x4a01 +#define HOST_CKOUTP 0x4a02 +#define MAC_MDC 0x4a03 + +#define GPIO4_A1 0x4a10 +#define FLASH1_WP 0x4a11 +#define HOST_CKOUTN 0x4a12 +#define MAC_RXDV 0x4a13 +#define FLASH0_CSN4 0x4a14 + +#define GPIO4_A2 0x4a20 +#define FLASH1_RDN 0x4a21 +#define HOST_DOUT8 0x4a22 +#define MAC_RXER 0x4a23 +#define FLASH0_CSN5 0x4a24 + +#define GPIO4_A3 0x4a30 +#define FLASH1_ALE 0x4a31 +#define HOST_DOUT9 0x4a32 +#define MAC_CLK 0x4a33 +#define FLASH0_CSN6 0x4a34 + +#define GPIO4_A4 0x4a40 +#define FLASH1_CLE 0x4a41 +#define HOST_DOUT10 0x4a42 +#define MAC_TXEN 0x4a43 +#define FLASH0_CSN7 0x4a44 + +#define GPIO4_A5 0x4a50 +#define FLASH1_WRN 0x4a51 +#define HOST_DOUT11 0x4a52 +#define MAC_MDIO 0x4a53 + +#define GPIO4_A6 0x4a60 +#define FLASH1_CSN0 0x4a61 +#define HOST_DOUT12 0x4a62 +#define MAC_RXCLK 0x4a63 +#define SDIO1_CMD 0x4a64 + +#define GPIO4_A7 0x4a70 +#define FLASH1_CSN1 0x4a71 +#define HOST_DOUT13 0x4a72 +#define MAC_CRS 0x4a73 +#define SDIO1_CLKOUT 0x4a74 + + +/* GPIO4_B */ +#define GPIO4_B0 0x4b00 +#define FLASH1_DQS 0x4b01 +#define HOST_DOUT14 0x4b02 +#define MAC_COL 0x4b03 +#define FLASH1_CSN3 0x4b04 + +#define GPIO4_B1 0x4b10 +#define FLASH1_CSN2 0x4b11 +#define HOST_DOUT15 0x4b12 +#define MAC_TXCLK 0x4b13 +#define SDIO1_PWREN 0x4b14 + + +/* GPIO4_C */ +#define GPIO4_C0 0x4c00 +#define UART0BT_SIN 0x4c01 + +#define GPIO4_C1 0x4c10 +#define UART0BT_SOUT 0x4c11 + +#define GPIO4_C2 0x4c20 +#define UART0BT_CTSN 0x4c21 + +#define GPIO4_C3 0x4c30 +#define UART0BT_RTSN 0x4c31 + +#define GPIO4_C4 0x4c40 +#define SDIO0_DATA0 0x4c41 + +#define GPIO4_C5 0x4c50 +#define SDIO0_DATA1 0x4c51 + +#define GPIO4_C6 0x4c60 +#define SDIO0_DATA2 0x4c61 + +#define GPIO4_C7 0x4c70 +#define SDIO0_DATA3 0x4c71 + + +/* GPIO4_D */ +#define GPIO4_D0 0x4d00 +#define SDIO0_CMD 0x4d01 + +#define GPIO4_D1 0x4d10 +#define SDIO0_CLKOUT 0x4d11 + +#define GPIO4_D2 0x4d20 +#define SDIO0_DETECTN 0x4d21 + +#define GPIO4_D3 0x4d30 +#define SDIO0_WRPRT 0x4d31 + +#define GPIO4_D4 0x4d40 +#define SDIO0_PWREN 0x4d41 + +#define GPIO4_D5 0x4d50 +#define SDIO0_BKPWR 0x4d51 + +#define GPIO4_D6 0x4d60 +#define SDIO0_INTN 0x4d61 + + +/* GPIO5_A */ +/* GPIO5_B */ +#define GPIO5_B0 0x5b00 +#define UART1BB_SIN 0x5b01 +#define TS0_DATA0 0x5b02 + +#define GPIO5_B1 0x5b10 +#define UART1BB_SOUT 0x5b11 +#define TS0_DATA1 0x5b12 + +#define GPIO5_B2 0x5b20 +#define UART1BB_CTSN 0x5b21 +#define TS0_DATA2 0x5b22 + +#define GPIO5_B3 0x5b30 +#define UART1BB_RTSN 0x5b31 +#define TS0_DATA3 0x5b32 + +#define GPIO5_B4 0x5b40 +#define SPI0_CLK 0x5b41 +#define TS0_DATA4 0x5b42 +#define UART4EXP_CTSN 0x5b43 + +#define GPIO5_B5 0x5b50 +#define SPI0_CS0 0x5b51 +#define TS0_DATA5 0x5b52 +#define UART4EXP_RTSN 0x5b53 + +#define GPIO5_B6 0x5b60 +#define SPI0_TXD 0x5b61 +#define TS0_DATA6 0x5b62 +#define UART4EXP_SOUT 0x5b63 + +#define GPIO5_B7 0x5b70 +#define SPI0_RXD 0x5b71 +#define TS0_DATA7 0x5b72 +#define UART4EXP_SIN 0x5b73 + + +/* GPIO5_C */ +#define GPIO5_C0 0x5c00 +#define SPI0_CS1 0x5c01 +#define TS0_SYNC 0x5c02 + +#define GPIO5_C1 0x5c10 +#define TS0_VALID 0x5c11 + +#define GPIO5_C2 0x5c20 +#define TS0_CLK 0x5c21 + +#define GPIO5_C3 0x5c30 +#define TS0_ERR 0x5c31 + + +/* GPIO5_D */ +/* GPIO6_A */ +#define GPIO6_A0 0x6a00 +#define I2S_SCLK 0x6a01 + +#define GPIO6_A1 0x6a10 +#define I2S_LRCKRX 0x6a11 + +#define GPIO6_A2 0x6a20 +#define I2S_LRCKTX 0x6a21 + +#define GPIO6_A3 0x6a30 +#define I2S_SDI 0x6a31 + +#define GPIO6_A4 0x6a40 +#define I2S_SDO0 0x6a41 + +#define GPIO6_A5 0x6a50 +#define I2S_SDO1 0x6a51 + +#define GPIO6_A6 0x6a60 +#define I2S_SDO2 0x6a61 + +#define GPIO6_A7 0x6a70 +#define I2S_SDO3 0x6a71 + + +/* GPIO6_B */ +#define GPIO6_B0 0x6b00 +#define I2S_CLK 0x6b01 + +#define GPIO6_B1 0x6b10 +#define I2C2AUDIO_SDA 0x6b11 + +#define GPIO6_B2 0x6b20 +#define I2C2AUDIO_SCL 0x6b21 + +#define GPIO6_B3 0x6b30 +#define SPDIF_TX 0x6b31 + + +/* GPIO6_C */ +#define GPIO6_C0 0x6c00 +#define SDMMC0_DATA0 0x6c01 +#define JTAG_TMS 0x6c02 + +#define GPIO6_C1 0x6c10 +#define SDMMC0_DATA1 0x6c11 +#define JTAG_TRSTN 0x6c12 + +#define GPIO6_C2 0x6c20 +#define SDMMC0_DATA2 0x6c21 +#define JTAG_TDI 0x6c22 + +#define GPIO6_C3 0x6c30 +#define SDMMC0_DATA3 0x6c31 +#define JTAG_TCK 0x6c32 + +#define GPIO6_C4 0x6c40 +#define SDMMC0_CLKOUT 0x6c41 +#define JTAG_TDO 0x6c42 + +#define GPIO6_C5 0x6c50 +#define SDMMC0_CMD 0x6c51 + +#define GPIO6_C6 0x6c60 +#define SDMMC0_DECTN 0x6c61 + + +/* GPIO6_D */ +/* GPIO7_A */ +#define GPIO7_A0 0x7a00 +#define PWM0 0x7a01 +#define VOP0_PWM 0x7a02 +#define VOP1_PWM 0x7a03 + +#define GPIO7_A1 0x7a10 +#define PWM1 0x7a11 + +#define GPIO7_A7 0x7a70 +#define UART3GPS_SIN 0x7a71 +#define GPS_MAG 0x7a72 +#define HSADCT1_DATA0 0x7a73 + + +/* GPIO7_B */ +#define GPIO7_B0 0x7b00 +#define UART3GPS_SOUT 0x7b01 +#define GPS_SIG 0x7b02 +#define HSADCT1_DATA1 0x7b03 + +#define GPIO7_B1 0x7b10 +#define UART3GPS_CTSN 0x7b11 +#define GPS_RFCLK 0x7b12 +#define GPST1_CLK 0x7b13 + +#define GPIO7_B2 0x7b20 +#define UART3GPS_RTSN 0x7b21 +#define USB_DRVVBUS0 0x7b22 + +#define GPIO7_B3 0x7b30 +#define USB_DRVVBUS1 0x7b31 +#define EDP_HOTPLUG 0x7b32 + +#define GPIO7_B4 0x7b40 +#define ISP_SHUTTEREN 0x7b41 +#define SPI1_CLK 0x7b42 + +#define GPIO7_B5 0x7b50 +#define ISP_FLASHTRIGOUTSPI1_CS0 0x7b51 +#define SPI1_CS0 0x7b52 + +#define GPIO7_B6 0x7b60 +#define ISP_PRELIGHTTRIGSPI1_RXD 0x7b61 +#define SPI1_RXD 0x7b62 + +#define GPIO7_B7 0x7b70 +#define ISP_SHUTTERTRIG 0x7b71 +#define SPI1_TXD 0x7b72 + + +/* GPIO7_C */ +#define GPIO7_C0 0x7c00 +#define ISP_FLASHTRIGIN 0x7c01 +#define EDPHDMI_CECINOUTRESERVED 0x7c02 + +#define GPIO7_C1 0x7c10 +#define I2C4TP_SDA 0x7c11 + +#define GPIO7_C2 0x7c20 +#define I2C4TP_SCL 0x7c21 + +#define GPIO7_C3 0x7c30 +#define I2C5HDMI_SDA 0x7c31 +#define EDPHDMII2C_SDA 0x7c32 + +#define GPIO7_C4 0x7c40 +#define I2C5HDMI_SCL 0x7c41 +#define EDPHDMII2C_SCL 0x7c42 + +#define GPIO7_C6 0x7c60 +#define UART2DBG_SIN 0x7c61 +#define UART2DBG_SIRIN 0x7c62 +#define PWM2 0x7c63 + +#define GPIO7_C7 0x7c70 +#define UART2DBG_SOUT 0x7c71 +#define UART2DBG_SIROUT 0x7c72 +#define PWM3 0x7c73 +#define EDPHDMI_CECINOUT 0x7c74 + + +/* GPIO7_D */ +/* GPIO8_A */ +#define GPIO8_A0 0x8a00 +#define PS2_CLK 0x8a01 +#define SC_VCC18V 0x8a02 + +#define GPIO8_A1 0x8a10 +#define PS2_DATA 0x8a11 +#define SC_VCC33V 0x8a12 + +#define GPIO8_A2 0x8a20 +#define SC_DETECTT1 0x8a21 + +#define GPIO8_A3 0x8a30 +#define SPI2_CS1 0x8a31 +#define SC_IOT1 0x8a32 + +#define GPIO8_A4 0x8a40 +#define I2C1SENSOR_SDA 0x8a41 +#define SC_RST_GPIO8A 0x8a42 + +#define GPIO8_A5 0x8a50 +#define I2C1SENSOR_SCL 0x8a51 +#define SC_CLK_GPIO8A 0x8a52 + +#define GPIO8_A6 0x8a60 +#define SPI2_CLK 0x8a61 +#define SC_IO 0x8a62 + +#define GPIO8_A7 0x8a70 +#define SPI2_CS0 0x8a71 +#define SC_DETECT 0x8a72 + + +/* GPIO8_B */ +#define GPIO8_B0 0x8b00 +#define SPI2_RXD 0x8b01 +#define SC_RST_GPIO8B 0x8b02 + +#define GPIO8_B1 0x8b10 +#define SPI2_TXD 0x8b11 +#define SC_CLK_GPIO8B 0x8b12 + + +/* GPIO8_C */ +/* GPIO8_D */ + + +#endif diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h index 743e66a95e13..bc2b6af99444 100644 --- a/include/dt-bindings/pinctrl/rockchip.h +++ b/include/dt-bindings/pinctrl/rockchip.h @@ -25,10 +25,46 @@ #define RK_GPIO4 4 #define RK_GPIO6 6 +#define RK_PA0 0 +#define RK_PA1 1 +#define RK_PA2 2 +#define RK_PA3 3 +#define RK_PA4 4 +#define RK_PA5 5 +#define RK_PA6 6 +#define RK_PA7 7 +#define RK_PB0 8 +#define RK_PB1 9 +#define RK_PB2 10 +#define RK_PB3 11 +#define RK_PB4 12 +#define RK_PB5 13 +#define RK_PB6 14 +#define RK_PB7 15 +#define RK_PC0 16 +#define RK_PC1 17 +#define RK_PC2 18 +#define RK_PC3 19 +#define RK_PC4 20 +#define RK_PC5 21 +#define RK_PC6 22 +#define RK_PC7 23 +#define RK_PD0 24 +#define RK_PD1 25 +#define RK_PD2 26 +#define RK_PD3 27 +#define RK_PD4 28 +#define RK_PD5 29 +#define RK_PD6 30 +#define RK_PD7 31 + #define RK_FUNC_GPIO 0 #define RK_FUNC_1 1 #define RK_FUNC_2 2 #define RK_FUNC_3 3 #define RK_FUNC_4 4 +#define RK_FUNC_5 5 +#define RK_FUNC_6 6 +#define RK_FUNC_7 7 #endif diff --git a/include/dt-bindings/power/px30-power.h b/include/dt-bindings/power/px30-power.h new file mode 100644 index 000000000000..4ed482e80950 --- /dev/null +++ b/include/dt-bindings/power/px30-power.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +#ifndef __DT_BINDINGS_POWER_PX30_POWER_H__ +#define __DT_BINDINGS_POWER_PX30_POWER_H__ + +/* VD_CORE */ +#define PX30_PD_A35_0 0 +#define PX30_PD_A35_1 1 +#define PX30_PD_A35_2 2 +#define PX30_PD_A35_3 3 +#define PX30_PD_SCU 4 + +/* VD_LOGIC */ +#define PX30_PD_USB 5 +#define PX30_PD_DDR 6 +#define PX30_PD_SDCARD 7 +#define PX30_PD_CRYPTO 8 +#define PX30_PD_GMAC 9 +#define PX30_PD_MMC_NAND 10 +#define PX30_PD_VPU 11 +#define PX30_PD_VO 12 +#define PX30_PD_VI 13 +#define PX30_PD_GPU 14 + +/* VD_PMU */ +#define PX30_PD_PMU 15 + +#endif diff --git a/include/dt-bindings/power/rk1808-power.h b/include/dt-bindings/power/rk1808-power.h new file mode 100644 index 000000000000..32342c1e7ded --- /dev/null +++ b/include/dt-bindings/power/rk1808-power.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK1808_POWER_H__ +#define __DT_BINDINGS_POWER_RK1808_POWER_H__ + +/* VD_CORE */ +#define RK1808_PD_A35_0 0 +#define RK1808_PD_A35_1 1 +#define RK1808_PD_SCU 2 +#define RK1808_VD_CORE 3 + +/* VD_NPU */ +#define RK1808_VD_NPU 4 + +/* VD_LOGIC */ +#define RK1808_PD_DDR 5 +#define RK1808_PD_PCIE 6 +#define RK1808_PD_VPU 7 +#define RK1808_PD_VIO 8 + +#endif diff --git a/include/dt-bindings/power/rk3036-power.h b/include/dt-bindings/power/rk3036-power.h new file mode 100644 index 000000000000..59e09f1c5af7 --- /dev/null +++ b/include/dt-bindings/power/rk3036-power.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Author: Caesar Wang <wxt@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_POWER_RK3036_POWER_H__ +#define __DT_BINDINGS_POWER_RK3036_POWER_H__ + +#define RK3036_PD_MSCH 0 +#define RK3036_PD_CORE 1 +#define RK3036_PD_PERI 2 +#define RK3036_PD_VIO 3 +#define RK3036_PD_VPU 4 +#define RK3036_PD_GPU 5 +#define RK3036_PD_SYS 6 + +#endif diff --git a/include/dt-bindings/power/rk3128-power.h b/include/dt-bindings/power/rk3128-power.h new file mode 100644 index 000000000000..26aef519cd94 --- /dev/null +++ b/include/dt-bindings/power/rk3128-power.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang <zhangqing@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_POWER_RK3128_POWER_H__ +#define __DT_BINDINGS_POWER_RK3128_POWER_H__ + +/* VD_CORE */ +#define RK3128_PD_CORE 0 + +/* VD_LOGIC */ +#define RK3128_PD_VIO 1 +#define RK3128_PD_VIDEO 2 +#define RK3128_PD_GPU 3 +#define RK3128_PD_MSCH 4 + +#endif diff --git a/include/dt-bindings/power/rk3228-power.h b/include/dt-bindings/power/rk3228-power.h new file mode 100644 index 000000000000..fa1264d5a995 --- /dev/null +++ b/include/dt-bindings/power/rk3228-power.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +#ifndef __DT_BINDINGS_POWER_RK3228_POWER_H__ +#define __DT_BINDINGS_POWER_RK3228_POWER_H__ + +/** + * RK3228 idle id Summary. + */ + +#define RK3228_PD_CORE 0 +#define RK3228_PD_MSCH 1 +#define RK3228_PD_BUS 2 +#define RK3228_PD_SYS 3 +#define RK3228_PD_VIO 4 +#define RK3228_PD_VOP 5 +#define RK3228_PD_VPU 6 +#define RK3228_PD_RKVDEC 7 +#define RK3228_PD_GPU 8 +#define RK3228_PD_PERI 9 +#define RK3228_PD_GMAC 10 + +#endif diff --git a/include/dt-bindings/power/rk3328-power.h b/include/dt-bindings/power/rk3328-power.h new file mode 100644 index 000000000000..02e3d7fc1cce --- /dev/null +++ b/include/dt-bindings/power/rk3328-power.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3328_POWER_H__ +#define __DT_BINDINGS_POWER_RK3328_POWER_H__ + +/** + * RK3328 idle id Summary. + */ +#define RK3328_PD_CORE 0 +#define RK3328_PD_GPU 1 +#define RK3328_PD_BUS 2 +#define RK3328_PD_MSCH 3 +#define RK3328_PD_PERI 4 +#define RK3328_PD_VIDEO 5 +#define RK3328_PD_HEVC 6 +#define RK3328_PD_SYS 7 +#define RK3328_PD_VPU 8 +#define RK3328_PD_VIO 9 + +#endif diff --git a/include/dt-bindings/power/rk3366-power.h b/include/dt-bindings/power/rk3366-power.h new file mode 100644 index 000000000000..af912a40b410 --- /dev/null +++ b/include/dt-bindings/power/rk3366-power.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3366_POWER_H__ +#define __DT_BINDINGS_POWER_RK3366_POWER_H__ + +/* VD_CORE */ +#define RK3366_PD_A53_0 0 +#define RK3366_PD_A53_1 1 +#define RK3366_PD_A53_2 2 +#define RK3366_PD_A53_3 3 + +/* VD_LOGIC */ +#define RK3366_PD_BUS 4 +#define RK3366_PD_PERI 5 +#define RK3366_PD_VIO 6 +#define RK3366_PD_VIDEO 7 +#define RK3366_PD_RKVDEC 8 +#define RK3366_PD_WIFIBT 9 +#define RK3366_PD_VPU 10 +#define RK3366_PD_GPU 11 +#define RK3366_PD_ALIVE 12 + +/* VD_PMU */ +#define RK3366_PD_PMU 13 + +#endif diff --git a/include/dt-bindings/power/rk3368-power.h b/include/dt-bindings/power/rk3368-power.h new file mode 100644 index 000000000000..5e602dbd64ec --- /dev/null +++ b/include/dt-bindings/power/rk3368-power.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3368_POWER_H__ +#define __DT_BINDINGS_POWER_RK3368_POWER_H__ + +/* VD_CORE */ +#define RK3368_PD_A53_L0 0 +#define RK3368_PD_A53_L1 1 +#define RK3368_PD_A53_L2 2 +#define RK3368_PD_A53_L3 3 +#define RK3368_PD_SCU_L 4 +#define RK3368_PD_A53_B0 5 +#define RK3368_PD_A53_B1 6 +#define RK3368_PD_A53_B2 7 +#define RK3368_PD_A53_B3 8 +#define RK3368_PD_SCU_B 9 + +/* VD_LOGIC */ +#define RK3368_PD_BUS 10 +#define RK3368_PD_PERI 11 +#define RK3368_PD_VIO 12 +#define RK3368_PD_ALIVE 13 +#define RK3368_PD_VIDEO 14 +#define RK3368_PD_GPU_0 15 +#define RK3368_PD_GPU_1 16 + +/* VD_PMU */ +#define RK3368_PD_PMU 17 + +#endif diff --git a/include/dt-bindings/power/rk3399-power.h b/include/dt-bindings/power/rk3399-power.h new file mode 100644 index 000000000000..aedd8b180fe4 --- /dev/null +++ b/include/dt-bindings/power/rk3399-power.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3399_POWER_H__ +#define __DT_BINDINGS_POWER_RK3399_POWER_H__ + +/* VD_CORE_L */ +#define RK3399_PD_A53_L0 0 +#define RK3399_PD_A53_L1 1 +#define RK3399_PD_A53_L2 2 +#define RK3399_PD_A53_L3 3 +#define RK3399_PD_SCU_L 4 + +/* VD_CORE_B */ +#define RK3399_PD_A72_B0 5 +#define RK3399_PD_A72_B1 6 +#define RK3399_PD_SCU_B 7 + +/* VD_LOGIC */ +#define RK3399_PD_TCPD0 8 +#define RK3399_PD_TCPD1 9 +#define RK3399_PD_CCI 10 +#define RK3399_PD_CCI0 11 +#define RK3399_PD_CCI1 12 +#define RK3399_PD_PERILP 13 +#define RK3399_PD_PERIHP 14 +#define RK3399_PD_VIO 15 +#define RK3399_PD_VO 16 +#define RK3399_PD_VOPB 17 +#define RK3399_PD_VOPL 18 +#define RK3399_PD_ISP0 19 +#define RK3399_PD_ISP1 20 +#define RK3399_PD_HDCP 21 +#define RK3399_PD_GMAC 22 +#define RK3399_PD_EMMC 23 +#define RK3399_PD_USB3 24 +#define RK3399_PD_EDP 25 +#define RK3399_PD_GIC 26 +#define RK3399_PD_SD 27 +#define RK3399_PD_SDIOAUDIO 28 +#define RK3399_PD_ALIVE 29 + +/* VD_CENTER */ +#define RK3399_PD_CENTER 30 +#define RK3399_PD_VCODEC 31 +#define RK3399_PD_VDU 32 +#define RK3399_PD_RGA 33 +#define RK3399_PD_IEP 34 + +/* VD_GPU */ +#define RK3399_PD_GPU 35 + +/* VD_PMU */ +#define RK3399_PD_PMU 36 + +#endif diff --git a/include/dt-bindings/sensor-dev.h b/include/dt-bindings/sensor-dev.h new file mode 100644 index 000000000000..e03f0027d325 --- /dev/null +++ b/include/dt-bindings/sensor-dev.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __DT_BINDINGS_ROCKCHIP_SENSORDEV_H__ +#define __DT_BINDINGS_ROCKCHIP_SENSORDEV_H__ + +#define SENSOR_TYPE_NULL 0 +#define SENSOR_TYPE_ANGLE 1 +#define SENSOR_TYPE_ACCEL 2 +#define SENSOR_TYPE_COMPASS 3 +#define SENSOR_TYPE_GYROSCOPE 4 +#define SENSOR_TYPE_LIGHT 5 +#define SENSOR_TYPE_PROXIMITY 6 +#define SENSOR_TYPE_TEMPERATURE 7 +#define SENSOR_TYPE_PRESSURE 8 +#define SENSOR_TYPE_HALL 9 +#define SENSOR_NUM_TYPES 10 + +#endif diff --git a/include/dt-bindings/soc/rockchip,boot-mode.h b/include/dt-bindings/soc/rockchip,boot-mode.h new file mode 100644 index 000000000000..01e934fbec40 --- /dev/null +++ b/include/dt-bindings/soc/rockchip,boot-mode.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ROCKCHIP_BOOT_MODE_H +#define __ROCKCHIP_BOOT_MODE_H + +/* high 24 bits is tag, low 8 bits is type */ +#define REBOOT_FLAG 0x5242C300 +/* normal boot */ +#define BOOT_NORMAL (REBOOT_FLAG + 0) +/* enter bootloader rockusb mode */ +#define BOOT_BL_DOWNLOAD (REBOOT_FLAG + 1) +/* enter recovery */ +#define BOOT_RECOVERY (REBOOT_FLAG + 3) +/* enter fastboot mode */ +#define BOOT_FASTBOOT (REBOOT_FLAG + 9) +/* enter charging mode */ +#define BOOT_CHARGING (REBOOT_FLAG + 11) +/* enter usb mass storage mode */ +#define BOOT_UMS (REBOOT_FLAG + 12) + +#endif diff --git a/include/dt-bindings/soc/rockchip-system-status.h b/include/dt-bindings/soc/rockchip-system-status.h new file mode 100644 index 000000000000..fe103a55f222 --- /dev/null +++ b/include/dt-bindings/soc/rockchip-system-status.h @@ -0,0 +1,43 @@ +/* + * + * Copyright (C) 2017 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _DT_BINDINGS_SOC_ROCKCHIP_SYSTEM_STATUS_H +#define _DT_BINDINGS_SOC_ROCKCHIP_SYSTEM_STATUS_H + +#define SYS_STATUS_NORMAL (1 << 0) +#define SYS_STATUS_SUSPEND (1 << 1) +#define SYS_STATUS_IDLE (1 << 2) +#define SYS_STATUS_REBOOT (1 << 3) +#define SYS_STATUS_VIDEO_4K (1 << 4) +#define SYS_STATUS_VIDEO_1080P (1 << 5) +#define SYS_STATUS_GPU (1 << 6) +#define SYS_STATUS_RGA (1 << 7) +#define SYS_STATUS_CIF0 (1 << 8) +#define SYS_STATUS_CIF1 (1 << 9) +#define SYS_STATUS_LCDC0 (1 << 10) +#define SYS_STATUS_LCDC1 (1 << 11) +#define SYS_STATUS_BOOST (1 << 12) +#define SYS_STATUS_PERFORMANCE (1 << 13) +#define SYS_STATUS_ISP (1 << 14) +#define SYS_STATUS_HDMI (1 << 15) +#define SYS_STATUS_VIDEO_4K_10B (1 << 16) +#define SYS_STATUS_LOW_POWER (1 << 17) + +#define SYS_STATUS_VIDEO (SYS_STATUS_VIDEO_4K | \ + SYS_STATUS_VIDEO_1080P | \ + SYS_STATUS_VIDEO_4K_10B) +#define SYS_STATUS_DUALVIEW (SYS_STATUS_LCDC0 | SYS_STATUS_LCDC1) + +#endif diff --git a/include/dt-bindings/suspend/rockchip-px30.h b/include/dt-bindings/suspend/rockchip-px30.h new file mode 100644 index 000000000000..4362028f677c --- /dev/null +++ b/include/dt-bindings/suspend/rockchip-px30.h @@ -0,0 +1,53 @@ +/* + * Header providing constants for Rockchip suspend bindings. + * + * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd + * Author: XiaoDong.Huang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __DT_BINDINGS_ROCKCHIP_PM_H__ +#define __DT_BINDINGS_ROCKCHIP_PM_H__ +/******************************bits ops************************************/ + +#ifndef BIT +#define BIT(nr) (1 << (nr)) +#endif + +#define RKPM_SLP_ARMPD BIT(0) +#define RKPM_SLP_ARMOFF BIT(1) +#define RKPM_SLP_ARMOFF_DDRPD BIT(2) +#define RKPM_SLP_ARMOFF_LOGOFF BIT(3) + +/* all plls except ddr's pll*/ +#define RKPM_SLP_PMU_HW_PLLS_PD BIT(8) +#define RKPM_SLP_PMU_PMUALIVE_32K BIT(9) +#define RKPM_SLP_PMU_DIS_OSC BIT(10) + +#define RKPM_SLP_CLK_GT BIT(16) +#define RKPM_SLP_PMIC_LP BIT(17) + +#define RKPM_SLP_32K_EXT BIT(24) +#define RKPM_SLP_TIME_OUT_WKUP BIT(25) +#define RKPM_SLP_PMU_DBG BIT(26) + +/* the wake up source */ +#define RKPM_CLUSTER_WKUP_EN BIT(0) +#define RKPM_GPIO_WKUP_EN BIT(2) +#define RKPM_SDIO_WKUP_EN BIT(3) +#define RKPM_SDMMC_WKUP_EN BIT(4) +#define RKPM_UART0_WKUP_EN BIT(5) +#define RKPM_TIMER_WKUP_EN BIT(6) +#define RKPM_USB_WKUP_EN BIT(7) +#define RKPM_SFT_WKUP_EN BIT(8) +#define RKPM_TIME_OUT_WKUP_EN BIT(10) + +#endif diff --git a/include/dt-bindings/suspend/rockchip-rk1808.h b/include/dt-bindings/suspend/rockchip-rk1808.h new file mode 100644 index 000000000000..3d565faabf4d --- /dev/null +++ b/include/dt-bindings/suspend/rockchip-rk1808.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Header providing constants for Rockchip suspend bindings. + * + * Copyright (C) 2018, Fuzhou Rockchip Electronics Co., Ltd + * Author: XiaoDong.Huang + */ + +#ifndef __DT_BINDINGS_RK1808_PM_H__ +#define __DT_BINDINGS_RK1808_PM_H__ +/******************************bits ops************************************/ + +#ifndef BIT +#define BIT(nr) (1 << (nr)) +#endif + +#define RKPM_SLP_ARMPD BIT(0) +#define RKPM_SLP_ARMOFF BIT(1) +#define RKPM_SLP_ARMOFF_DDRPD BIT(2) +#define RKPM_SLP_ARMOFF_LOGOFF BIT(3) + +/* all plls except ddr's pll*/ +#define RKPM_SLP_PMU_HW_PLLS_PD BIT(8) +#define RKPM_SLP_PMU_PMUALIVE_32K BIT(9) +#define RKPM_SLP_PMU_DIS_OSC BIT(10) + +#define RKPM_SLP_CLK_GT BIT(16) +#define RKPM_SLP_PMIC_LP BIT(17) + +#define RKPM_SLP_32K_EXT BIT(24) +#define RKPM_SLP_TIME_OUT_WKUP BIT(25) +#define RKPM_SLP_PMU_DBG BIT(26) + +/* the wake up source */ +#define RKPM_CLUSTER_WKUP_EN BIT(0) +#define RKPM_GPIO_WKUP_EN BIT(2) +#define RKPM_SDIO_WKUP_EN BIT(3) +#define RKPM_SDMMC_WKUP_EN BIT(4) +#define RKPM_UART0_WKUP_EN BIT(5) +#define RKPM_TIMER_WKUP_EN BIT(6) +#define RKPM_USB_WKUP_EN BIT(7) +#define RKPM_SFT_WKUP_EN BIT(8) +#define RKPM_VAD_WKUP_EN BIT(9) +#define RKPM_TIME_OUT_WKUP_EN BIT(10) + +#endif diff --git a/include/dt-bindings/suspend/rockchip-rk322x.h b/include/dt-bindings/suspend/rockchip-rk322x.h new file mode 100644 index 000000000000..882ae053fa22 --- /dev/null +++ b/include/dt-bindings/suspend/rockchip-rk322x.h @@ -0,0 +1,57 @@ +/* + * Header providing constants for Rockchip suspend bindings. + * + * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd + * Author: XiaoDong.Huang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_SUSPEND_ROCKCHIP_RK322X_H__ +#define __DT_BINDINGS_SUSPEND_ROCKCHIP_RK322X_H__ + +#ifndef BIT +#define BIT(nr) (1 << (nr)) +#endif + +/* the suspend mode */ +#define RKPM_CTR_PWR_DMNS BIT(0) +#define RKPM_CTR_GTCLKS BIT(1) +#define RKPM_CTR_PLLS BIT(2) +#define RKPM_CTR_VOLTS BIT(3) +#define RKPM_CTR_GPIOS BIT(4) +#define RKPM_CTR_DDR BIT(5) +#define RKPM_CTR_PMIC BIT(6) + +/* system clk is 24M,and div to min */ +#define RKPM_CTR_SYSCLK_DIV BIT(7) +/* switch sysclk to 32k, need hardwart support, and div to min */ +#define RKPM_CTR_SYSCLK_32K BIT(8) +/* switch sysclk to 32k,disable 24M OSC, + * need hardwart susport. and div to min + */ +#define RKPM_CTR_SYSCLK_OSC_DIS BIT(9) +#define RKPM_CTR_VOL_PWM0 BIT(10) +#define RKPM_CTR_VOL_PWM1 BIT(11) +#define RKPM_CTR_VOL_PWM2 BIT(12) +#define RKPM_CTR_VOL_PWM3 BIT(13) +#define RKPM_CTR_BUS_IDLE BIT(14) +#define RKPM_CTR_SRAM BIT(15) +/*Low Power Function Selection*/ +#define RKPM_CTR_IDLESRAM_MD BIT(16) +#define RKPM_CTR_IDLEAUTO_MD BIT(17) +#define RKPM_CTR_ARMDP_LPMD BIT(18) +#define RKPM_CTR_ARMOFF_LPMD BIT(19) +#define RKPM_CTR_ARMLOGDP_LPMD BIT(20) +#define RKPM_CTR_ARMOFF_LOGDP_LPMD BIT(21) +#define RKPM_CTR_ARMLOGOFF_DLPMD BIT(22) + +#endif diff --git a/include/dt-bindings/suspend/rockchip-rk3288.h b/include/dt-bindings/suspend/rockchip-rk3288.h new file mode 100644 index 000000000000..d07cced43877 --- /dev/null +++ b/include/dt-bindings/suspend/rockchip-rk3288.h @@ -0,0 +1,59 @@ +/* + * Header providing constants for Rockchip suspend bindings. + * + * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd + * Author: Power.xu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3288_H__ +#define __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3288_H__ + +/* the suspend mode */ +#define RKPM_CTR_PWR_DMNS (1 << 0) +#define RKPM_CTR_GTCLKS (1 << 1) +#define RKPM_CTR_PLLS (1 << 2) +#define RKPM_CTR_VOLTS (1 << 3) +#define RKPM_CTR_GPIOS (1 << 4) +#define RKPM_CTR_DDR (1 << 5) +#define RKPM_CTR_PMIC (1 << 6) +/* system clk is 24M,and div to min */ +#define RKPM_CTR_SYSCLK_DIV (1 << 7) +/* switch sysclk to 32k, need hardwart support, and div to min */ +#define RKPM_CTR_SYSCLK_32K (1 << 8) +/* switch sysclk to 32k,disable 24M OSC, + * need hardwart susport. and div to min + */ +#define RKPM_CTR_SYSCLK_OSC_DIS (1 << 9) +#define RKPM_CTR_BUS_IDLE (1 << 14) +#define RKPM_CTR_SRAM (1 << 15) +/*Low Power Function Selection*/ +#define RKPM_CTR_IDLESRAM_MD (1 << 16) +#define RKPM_CTR_IDLEAUTO_MD (1 << 17) +#define RKPM_CTR_ARMDP_LPMD (1 << 18) +#define RKPM_CTR_ARMOFF_LPMD (1 << 19) +#define RKPM_CTR_ARMLOGDP_LPMD (1 << 20) +#define RKPM_CTR_ARMOFF_LOGDP_LPMD (1 << 21) +#define RKPM_CTR_ARMLOGOFF_DLPMD (1 << 22) + +/* the wake up source */ +#define RKPM_ARMINT_WKUP_EN (1 << 0) +#define RKPM_SDMMC_WKUP_EN (1 << 2) +#define RKPM_GPIO_WKUP_EN (1 << 3) + +/* the pwm regulator */ +#define PWM0_REGULATOR_EN (1 << 0) +#define PWM1_REGULATOR_EN (1 << 1) +#define PWM2_REGULATOR_EN (1 << 2) +#define PWM3_REGULATOR_EN (1 << 3) + +#endif diff --git a/include/dt-bindings/suspend/rockchip-rk3308.h b/include/dt-bindings/suspend/rockchip-rk3308.h new file mode 100644 index 000000000000..86ac23b83b48 --- /dev/null +++ b/include/dt-bindings/suspend/rockchip-rk3308.h @@ -0,0 +1,103 @@ +/* + * Header providing constants for Rockchip suspend bindings. + * + * Copyright (C) 2018, Fuzhou Rockchip Electronics Co., Ltd + * Author: Joseph Chen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __DT_BINDINGS_RK3308_PM_H__ +#define __DT_BINDINGS_RK3308_PM_H__ +/******************************bits ops************************************/ + +#ifndef BIT +#define BIT(nr) (1 << (nr)) +#endif + +/* + * RK3308 system suspend mode configure definitions. + * + * Driver: + * These configures are pass to ATF by SMC in: + * drivers/soc/rockchip/rockchip_pm_config.c + * + * DTS: + * rockchip_suspend: rockchip-suspend { + * rockchip,sleep-mode-config = <...>; + * rockchip,wakeup-config = <...>; + * rockchip,apios-suspend = <...>; + * rockchip,pwm-regulator-config = <...>; + * }; + */ + +/* + * Suspend mode: + * rockchip,sleep-mode-config = <...>; + */ +#define RKPM_ARMOFF BIT(0) /* vdd_arm off */ +#define RKPM_VADOFF BIT(1) /* assume vad off, enter lowest system suspend */ +#define RKPM_PMU_HW_PLLS_PD BIT(3) /* disable PLLs by PMU hardware, recommend */ +#define RKPM_PMU_DIS_OSC BIT(4) /* disable 24M osc */ +#define RKPM_PMU_PMUALIVE_32K BIT(5) /* pvtm 32khz */ +#define RKPM_PMU_EXT_32K BIT(6) /* ext 32khz osc */ +#define RKPM_DDR_SREF_HARDWARE BIT(7) /* ddr enter self-refresh by PMU hardware, not recommend */ +#define RKPM_DDR_EXIT_SRPD_IDLE BIT(8) /* ddr exit sr/pd idle by ddr controller, not recommend */ +#define RKPM_PDM_CLK_OFF BIT(9) /* armoff with pdm clk off, not recommend */ + +/* + * Regulator mode: + * rockchip,pwm-regulator-config = <...>; + */ +#define RKPM_PWM_REGULATOR BIT(2) /* support pwm regulator */ + +/* + * Wakeup source: + * rockchip,wakeup-config = <...>; + */ +#define RKPM_ARM_PRE_WAKEUP_EN BIT(11) /* all interrupts can wakeup(gic doesn't filter these) */ +#define RKPM_ARM_GIC_WAKEUP_EN BIT(12) /* all interrupts can wakeup(gic filter these) */ +#define RKPM_SDMMC_WAKEUP_EN BIT(13) /* sdmmc can wakeup */ +#define RKPM_SDMMC_GRF_IRQ_WAKEUP_EN BIT(14) /* sdmmc grf irq can wakeup */ +#define RKPM_TIMER_WAKEUP_EN BIT(15) /* rk timers can wakeup */ +#define RKPM_USBDEV_WAKEUP_EN BIT(16) /* usbdev can wakeup */ +#define RKPM_TIMEOUT_WAKEUP_EN BIT(17) /* PMU timeout can wakeup, for self test */ +#define RKPM_GPIO0_WAKEUP_EN BIT(18) /* gpio0(only) can wakeup */ +#define RKPM_VAD_WAKEUP_EN BIT(19) /* vad can wakeup */ + +/* + * Debug control in system suspend: + * rockchip,sleep-mode-config = <...>; + */ +#define RKPM_DBG_INT_TIMER_TEST BIT(22) /* enable RKPM_TIMEOUT_WAKEUP_EN */ +#define RKPM_DBG_WOARKAROUND BIT(23) /* ignore, useless */ +#define RKPM_DBG_VAD_INT_OFF BIT(24) /* enable RKPM_VADOFF */ +#define RKPM_DBG_CLK_UNGATE BIT(25) /* enable all clks */ +#define RKPM_DBG_CLKOUT BIT(26) /* enable test_out clk output */ +#define RKPM_DBG_FSM_SOUT BIT(27) /* FSM state one pin out */ +#define RKPM_DBG_FSM_STATE BIT(28) /* FSM state multi pins out */ +#define RKPM_DBG_REG BIT(29) /* verbose regs */ +#define RKPM_DBG_VERBOSE BIT(30) /* verbose more message */ +#define RKPM_CONFIG_WAKEUP_END BIT(31) /* ignore, it's a placeholder */ + +/* + * GPIOn/PWMn ignore global 1st reset, usually used for pwr_hold pin: + * rockchip,apios-suspend = <...>; + */ +#define GLB1RST_IGNORE_PWM0 BIT(23) /* pwm0 ignore global 1st reset */ +#define GLB1RST_IGNORE_PWM1 BIT(24) /* pwm1 ignore global 1st reset */ +#define GLB1RST_IGNORE_PWM2 BIT(25) /* pwm2 ignore global 1st reset */ +#define GLB1RST_IGNORE_GPIO0 BIT(26) /* gpio0 ignore global 1st reset */ +#define GLB1RST_IGNORE_GPIO1 BIT(27) /* gpio1 ignore global 1st reset */ +#define GLB1RST_IGNORE_GPIO2 BIT(28) /* gpio2 ignore global 1st reset */ +#define GLB1RST_IGNORE_GPIO3 BIT(29) /* gpio3 ignore global 1st reset */ +#define GLB1RST_IGNORE_GPIO4 BIT(30) /* gpio4 ignore global 1st reset */ + +#endif diff --git a/include/dt-bindings/suspend/rockchip-rk3328.h b/include/dt-bindings/suspend/rockchip-rk3328.h new file mode 100644 index 000000000000..972f8bb5e281 --- /dev/null +++ b/include/dt-bindings/suspend/rockchip-rk3328.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Header providing constants for Rockchip suspend bindings. + * + * Copyright (C) 2018, Fuzhou Rockchip Electronics Co., Ltd + * Author: XiaoDong.Huang + */ +#ifndef __DT_BINDINGS_ROCKCHIP_PM_H__ +#define __DT_BINDINGS_ROCKCHIP_PM_H__ +/******************************bits ops************************************/ + +#ifndef BIT +#define BIT(nr) (1 << (nr)) +#endif + +#define RKPM_SLP_CTR_VOL_PWM0 BIT(10) +#define RKPM_SLP_CTR_VOL_PWM1 BIT(11) + +#endif diff --git a/include/dt-bindings/suspend/rockchip-rk3368.h b/include/dt-bindings/suspend/rockchip-rk3368.h new file mode 100644 index 000000000000..9873f8236a8b --- /dev/null +++ b/include/dt-bindings/suspend/rockchip-rk3368.h @@ -0,0 +1,56 @@ +/* + * Header providing constants for Rockchip suspend bindings. + * + * Copyright (C) 2015, Fuzhou Rockchip Electronics Co., Ltd + * Author: Tony.Xie + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __DT_BINDINGS_ROCKCHIP_PM_H__ +#define __DT_BINDINGS_ROCKCHIP_PM_H__ +/******************************bits ops************************************/ + +#ifndef BIT +#define BIT(nr) (1 << (nr)) +#endif + +#define RKPM_SLP_WFI BIT(0) +#define RKPM_SLP_ARMPD BIT(1) +#define RKPM_SLP_ARMOFF BIT(2) +#define RKPM_SLP_ARMOFF_LOGPD BIT(3) +#define RKPM_SLP_ARMOFF_LOGOFF BIT(4) +#define RKPM_RUNNING_ARMMODE BIT(5) + +/* func ctrl by pmu auto ctr */ +#define RKPM_SLP_PMU_PLLS_PWRDN BIT(8) /* all plls except ddr's pll*/ +#define RKPM_SLP_PMU_PMUALIVE_32K BIT(9) +#define RKPM_SLP_PMU_DIS_OSC BIT(10) + +/* func ctrl by software set */ +#define RKPM_SLP_SFT_PLLS_DEEP BIT(16) /* all plls except ddr's pll*/ +#define RKPM_SLP_SFT_32K_EXT BIT(17) +#define RKPM_SLP_SFT_PD_PERI BIT(18) +#define RKPM_SLP_SFT_PD_NBSCUS BIT(19) /* noboot scus in muti-cluster */ + +/* the wake up source */ +#define RKPM_CLUSTER_L_WKUP_EN BIT(0) +#define RKPM_CLUSTER_B_WKUPB_EN BIT(1) +#define RKPM_GPIO_WKUP_EN BIT(2) +#define RKPM_SDIO_WKUP_EN BIT(3) +#define RKPM_SDMMC_WKUP_EN BIT(4) +#define RKPM_SIM_WKUP_EN BIT(5) +#define RKPM_TIMER_WKUP_EN BIT(6) +#define RKPM_USB_WKUP_EN BIT(7) +#define RKPM_SFT_WKUP_EN BIT(8) +#define RKPM_WDT_M0_WKUP_EN BIT(9) +#define RKPM_TIME_OUT_WKUP_EN BIT(10) + +#endif diff --git a/include/dt-bindings/suspend/rockchip-rk3399.h b/include/dt-bindings/suspend/rockchip-rk3399.h new file mode 100644 index 000000000000..176c7cfcd989 --- /dev/null +++ b/include/dt-bindings/suspend/rockchip-rk3399.h @@ -0,0 +1,61 @@ +/* + * Header providing constants for Rockchip suspend bindings. + * + * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd + * Author: Tony.Xie + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3399_H__ +#define __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3399_H__ + +/* the suspend mode */ +#define RKPM_SLP_WFI (1 << 0) +#define RKPM_SLP_ARMPD (1 << 1) +#define RKPM_SLP_PERILPPD (1 << 2) +#define RKPM_SLP_DDR_RET (1 << 3) +#define RKPM_SLP_PLLPD (1 << 4) +#define RKPM_SLP_OSC_DIS (1 << 5) +#define RKPM_SLP_CENTER_PD (1 << 6) +#define RKPM_SLP_AP_PWROFF (1 << 7) + +/* the wake up source */ +#define RKPM_CLUSTER_L_WKUP_EN (1 << 0) +#define RKPM_CLUSTER_B_WKUPB_EN (1 << 1) +#define RKPM_GPIO_WKUP_EN (1 << 2) +#define RKPM_SDIO_WKUP_EN (1 << 3) +#define RKPM_SDMMC_WKUP_EN (1 << 4) +#define RKPM_TIMER_WKUP_EN (1 << 6) +#define RKPM_USB_WKUP_EN (1 << 7) +#define RKPM_SFT_WKUP_EN (1 << 8) +#define RKPM_WDT_M0_WKUP_EN (1 << 9) +#define RKPM_TIME_OUT_WKUP_EN (1 << 10) +#define RKPM_PWM_WKUP_EN (1 << 11) +#define RKPM_PCIE_WKUP_EN (1 << 13) +#define RKPM_USB_LINESTATE_WKUP_EN (1 << 14) + +/* the pwm regulator */ +#define PWM0_REGULATOR_EN (1 << 0) +#define PWM1_REGULATOR_EN (1 << 1) +#define PWM2_REGULATOR_EN (1 << 2) +#define PWM3A_REGULATOR_EN (1 << 3) +#define PWM3B_REGULATOR_EN (1 << 4) + +/* the APIO voltage domain */ +#define RKPM_APIO0_SUSPEND (1 << 0) +#define RKPM_APIO1_SUSPEND (1 << 1) +#define RKPM_APIO2_SUSPEND (1 << 2) +#define RKPM_APIO3_SUSPEND (1 << 3) +#define RKPM_APIO4_SUSPEND (1 << 4) +#define RKPM_APIO5_SUSPEND (1 << 5) + +#endif |