diff options
Diffstat (limited to 'drivers/clk/rockchip/clk.h')
| -rw-r--r-- | drivers/clk/rockchip/clk.h | 35 |
1 files changed, 12 insertions, 23 deletions
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 7ef87aad40d2..6db1e7a66f19 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -45,12 +45,21 @@ struct clk; #define BOOST_SWITCH_THRESHOLD 0x0024 #define BOOST_FSM_STATUS 0x0028 #define BOOST_PLL_L_CON(x) ((x) * 0x4 + 0x2c) +#define BOOST_PLL_CON_MASK 0xffff +#define BOOST_BACKUP_PLL_MASK 0x3 +#define BOOST_BACKUP_PLL_SHIFT 8 +#define BOOST_BACKUP_PLL_USAGE_MASK 0x1 +#define BOOST_BACKUP_PLL_USAGE_SHIFT 12 +#define BOOST_ENABLE_MASK 0x1 +#define BOOST_ENABLE_SHIFT 0 #define BOOST_RECOVERY_MASK 0x1 #define BOOST_RECOVERY_SHIFT 1 #define BOOST_SW_CTRL_MASK 0x1 #define BOOST_SW_CTRL_SHIFT 2 #define BOOST_LOW_FREQ_EN_MASK 0x1 #define BOOST_LOW_FREQ_EN_SHIFT 3 +#define BOOST_STATIS_ENABLE_MASK 0x1 +#define BOOST_STATIS_ENABLE_SHIFT 4 #define BOOST_BUSY_STATE BIT(8) #define PX30_PLL_CON(x) ((x) * 0x4) @@ -261,7 +270,6 @@ struct rockchip_clk_provider { struct clk_onecell_data clk_data; struct device_node *cru_node; struct regmap *grf; - struct regmap *boost; spinlock_t lock; }; @@ -294,7 +302,6 @@ struct rockchip_pll_rate_table { * @type: Type of PLL to be registered. * @pll_flags: hardware-specific flags * @rate_table: Table of usable pll rates - * @boost_enabled: whether pll supports boost * * Flags: * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the @@ -313,7 +320,6 @@ struct rockchip_pll_clock { enum rockchip_pll_type type; u8 pll_flags; struct rockchip_pll_rate_table *rate_table; - bool boost_enabled; }; #define ROCKCHIP_PLL_SYNC_RATE BIT(0) @@ -335,32 +341,15 @@ struct rockchip_pll_clock { .rate_table = _rtable, \ } -#define PLL_BOOST(_type, _id, _name, _pnames, _flags, _con, _mode, \ - _mshift, _lshift, _pflags, _rtable) \ - { \ - .id = _id, \ - .type = _type, \ - .name = _name, \ - .parent_names = _pnames, \ - .num_parents = ARRAY_SIZE(_pnames), \ - .flags = CLK_GET_RATE_NOCACHE | _flags, \ - .con_offset = _con, \ - .mode_offset = _mode, \ - .mode_shift = _mshift, \ - .lock_shift = _lshift, \ - .pll_flags = _pflags, \ - .rate_table = _rtable, \ - .boost_enabled = true, \ - } - struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, enum rockchip_pll_type pll_type, const char *name, const char *const *parent_names, u8 num_parents, int con_offset, int grf_lock_offset, int lock_shift, int mode_offset, int mode_shift, struct rockchip_pll_rate_table *rate_table, - unsigned long flags, u8 clk_pll_flags, - bool boost_enabled); + unsigned long flags, u8 clk_pll_flags); + +void rockchip_boost_init(struct clk_hw *hw); void rockchip_boost_enable_recovery_sw_low(struct clk_hw *hw); |