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-rw-r--r--arch/arm64/boot/dts/rockchip/Makefile6
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-puma-edp.dts62
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-puma-hdmi+edp.dts44
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-puma-hdmi+mipidsi.dts40
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-puma-mipidsi.dts141
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-puma-spi5.dts18
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-puma.dts1015
-rw-r--r--arch/arm64/configs/puma-rk3399_defconfig598
8 files changed, 1924 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index ff3e97e22eba..a3be431d5fb3 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -92,6 +92,12 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin-r0.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin-r1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-mid-818-android-6.0.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-mid-818-android.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-edp.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-hdmi+edp.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-hdmi+mipidsi.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-mipidsi.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-spi5.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960-ab.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rv1-android.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-edp.dts b/arch/arm64/boot/dts/rockchip/rk3399-puma-edp.dts
new file mode 100644
index 000000000000..9f995fd1c42a
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-edp.dts
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2017 Theobroma Systemd Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+
+/*
+ * Theobroma Systems RK3399-Q7 "Puma" with EDP enabled instead of HDMI
+ */
+#include "rk3399-puma.dts"
+
+/ {
+ edp_panel: edp_panel {
+ // simple-panel does not define any timings - they are read from the monitor EDID.
+ compatible = "simple-panel";
+ // The enable gpio is used to switch the hardware multiplexer (U29) to DisplayPort.
+ enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; // GPIO2_A2 = SEL_EDP_1V8
+ ports {
+ panel_in_edp: endpoint {
+ remote-endpoint = <&edp_out_panel>;
+ };
+ };
+ };
+};
+
+&vopl {
+ status = "okay";
+};
+&vopl_mmu {
+ status = "okay";
+};
+
+&edp {
+ status = "okay";
+ force-hpd;
+ /delete-property/ pinctrl-0;
+ ports {
+ edp_out: port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ edp_out_panel: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&panel_in_edp>;
+ };
+ };
+ };
+};
+
+&hdmi {
+ status = "disabled";
+};
+
+&route_hdmi {
+ status = "disabled";
+};
+
+&route_edp {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-hdmi+edp.dts b/arch/arm64/boot/dts/rockchip/rk3399-puma-hdmi+edp.dts
new file mode 100644
index 000000000000..cc05ed117c35
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-hdmi+edp.dts
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2017 Theobroma Systemd Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/*
+ * Theobroma Systems RK3399-Q7 "Puma" with EDP and HDMI enabled
+ */
+#include "rk3399-puma-edp.dts"
+
+// Bind HDMI<->VOPB and DP<->VOPL by dropping the other paths
+//
+// Drop the HDMI<->VOPL path
+&vopl_out {
+ /delete-node/ endpoint@2; // vopl_out_hdmi
+};
+&hdmi_in {
+ /delete-node/ endpoint@1; // hdmi_in_vopl
+};
+// Drop the DP<->VOPB path
+&vopb_out {
+ /delete-node/ endpoint@0; // vopb_out_edp
+};
+&edp_in {
+ /delete-node/ endpoint@0; // edp_in_vopb
+};
+// Fix display_subsystem routes that refer to nodes that were deleted above
+&route_edp {
+ connect = <&vopl_out_edp>;
+};
+&route_hdmi {
+ connect = <&vopb_out_hdmi>;
+};
+
+// Enable HDMI
+&hdmi {
+ status = "okay";
+};
+
+&route_hdmi {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-hdmi+mipidsi.dts b/arch/arm64/boot/dts/rockchip/rk3399-puma-hdmi+mipidsi.dts
new file mode 100644
index 000000000000..2e10eaf46f24
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-hdmi+mipidsi.dts
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2017 Theobroma Systemd Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/*
+ * Theobroma Systems RK3399-Q7 "Puma" with MIPI-DSI and HDMI enabled
+ */
+#include "rk3399-puma-mipidsi.dts"
+
+// Swap the order so MIPI-DSI gets VOPL, HDMI gets VOPB
+&display_subsystem {
+ ports = <&vopl_out>, <&vopb_out>;
+};
+
+// Enable HDMI on VOPB
+&hdmi {
+ status = "okay";
+ ports { port { /delete-node/ endpoint@1; }; };
+};
+&route_hdmi {
+ // defined in rk3399-puma.dts: connect = <&vopb_out_hdmi>;
+ status = "okay";
+};
+
+// Enable VOPL and move MIPI-DSI there
+&vopl {
+ status = "okay";
+ port { /delete-node/ endpoint@2; };
+};
+&vopl_mmu {
+ status = "okay";
+};
+
+&route_dsi {
+ // default in rk3399-linux.dtsi: connect = <&vopb_out_dsi>;
+ connect = <&vopl_out_dsi>;
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-mipidsi.dts b/arch/arm64/boot/dts/rockchip/rk3399-puma-mipidsi.dts
new file mode 100644
index 000000000000..30621b4a04d4
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-mipidsi.dts
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2017 Theobroma Systemd Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/*
+ * Theobroma Systems RK3399-Q7 "Puma" with MIPI-DSI enabled instead of HDMI
+ */
+#include "rk3399-puma.dts"
+
+/ {
+ backlight: backlight {
+ compatible = "gpio-backlight";
+ // GPIO4_C2 = Q7_LVDS_BLT_CTRL. Set high to enable the backlight. Use PWM to regulate brightness.
+ gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
+ default-on;
+ };
+};
+
+&hdmi {
+ status = "disabled";
+};
+
+&route_hdmi {
+ status = "disabled";
+};
+
+&route_dsi {
+ status = "okay";
+ // default in rk3399-linux.dtsi: connect = <&vopb_out_dsi>;
+};
+
+&dsi {
+ status = "okay";
+ panel {
+ compatible ="simple-panel-dsi";
+ reg = <0>;
+ backlight = <&backlight>;
+ // GPIO2_A2 = SEL_EDP_1V8. Set low to switch the hardware mux from eDP to DSI.
+ enable-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+ // GPIO4_D6 = LVDS_PPEN. Set low to send the panel into reset.
+ reset-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>;
+ // Keep reset low for X milliseconds
+ reset-delay-ms = <10>;
+ // And wait X ms for the panel controller to boot up
+ init-delay-ms = <100>;
+
+ dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+ MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_LPM)>;
+ dsi,format = <MIPI_DSI_FMT_RGB888>;
+ dsi,lanes = <4>;
+ status = "okay";
+
+ panel-init-sequence = [
+ 15 01 02 cd aa
+ 15 01 02 30 00
+ 15 01 02 5e 03
+ 15 01 02 32 00
+ 15 01 02 33 25
+ 15 01 02 65 08
+ 15 01 02 3a 10
+ 15 01 02 36 49
+ 15 01 02 67 82
+ 15 01 02 69 27
+ 15 01 02 6c 27
+ 15 01 02 6d 14
+ 39 01 09 55 09 09 09 09 09 09 09 09
+ 39 01 11 56 09 09 09 09 09 09 09 09 09 09 09 09 09 09 09 09
+ 15 01 02 6b 00
+ 15 01 02 58 08
+ 15 01 02 73 30
+ 15 01 02 74 10
+ 15 01 02 77 00
+ 15 01 02 68 00
+ 15 01 02 28 28
+ 39 01 05 57 00 00 09 09
+ 15 01 02 41 46
+ 15 01 02 4e 50
+ 15 01 02 4f 55
+ 15 01 02 63 04
+ 39 01 14 53 1f 1a 17 13 12 12 14 15 15 10 0d 0b 0b 0c 0d 0a 08 03 00
+ 39 01 14 54 1f 1a 17 13 12 12 14 15 15 10 0d 0b 0b 0c 0d 0a 08 03 00
+ 15 01 02 29 10
+ 15 01 02 2e 03
+ 15 01 02 78 67
+ 15 01 02 76 36
+ 15 01 02 47 18
+ 15 01 02 2d 31
+ 15 01 02 50 d0
+ 15 01 02 48 66
+ 15 01 02 3f 00
+ 15 01 02 31 01
+ 15 01 02 4d 00
+ ];
+
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: timing0 {
+ clock-frequency = <71900000>;
+ hactive = <800>;
+ vactive = <1280>;
+ hback-porch = <24>;
+ hfront-porch = <72>;
+ vback-porch = <10>;
+ vfront-porch = <12>;
+ hsync-len = <24>;
+ vsync-len = <2>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ };
+ };
+ };
+};
+
+&i2c1 {
+ gsl1680 {
+ compatible = "silead,gsl1680";
+ reg = <0x40>;
+ // We don't have an interrupt line available on the dev kit.
+ // So we use 15 = arch_timer interrupt instead, tricking the driver into polling.
+ interrupts = <15 IRQ_TYPE_NONE>;
+ // Must be set but value is arbitrary (?)
+ interrupt-parent = <&gpio2>;
+ // GPIO1_C7 = LVDS_BLEN = gpio1 23
+ power-gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
+ touchscreen-size-x = <1720>;
+ touchscreen-size-y = <1150>;
+ touchscreen-swapped-x-y;
+ touchscreen-inverted-x;
+ touchscreen-inverted-y;
+
+ silead,max-fingers = <5>;
+ // Place into /lib/firmware/silead
+ firmware-name = "ec080.fw";
+ };
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-spi5.dts b/arch/arm64/boot/dts/rockchip/rk3399-puma-spi5.dts
new file mode 100644
index 000000000000..2ce706861f39
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-spi5.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/*
+ * Theobroma Systems RK3399-Q7 "Puma" with HDMI and eDP enabled
+ * and an M25P40 SPI flash connected to SPI5.
+ */
+
+#include "rk3399-puma-hdmi+edp.dts"
+
+&spi5 {
+ status = "okay";
+
+ m25p40@0 {
+ compatible = "m25p40";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dts b/arch/arm64/boot/dts/rockchip/rk3399-puma.dts
new file mode 100644
index 000000000000..de6165978941
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dts
@@ -0,0 +1,1015 @@
+/*
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2017 Theobroma Systemd Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+
+#include "dt-bindings/pwm/pwm.h"
+#include "rk3399.dtsi"
+#include "rk3399-linux.dtsi"
+#include "rk3399-sched-energy.dtsi"
+
+/ {
+ model = "Theobroma Systems RK3399-Q7 SoM";
+ compatible = "tsd,rk3399-q7", "rockchip,rk3399";
+
+ aliases {
+ spi1 = &spi1; // internal bus
+ spi5 = &spi5; // routed to Q7 connector as Q7_SPI_SCK/MOSI/...
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpuinfo {
+ compatible = "rockchip,cpuinfo";
+ nvmem-cells = <&efuse_id>;
+ nvmem-cell-names = "id";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_pins_puma>;
+
+ module_led {
+ label = "module_led";
+ gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ sd_card_led {
+ label = "sd_card_led";
+ gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ };
+ };
+
+ cluster0_opp: opp-table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <850000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp@1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <925000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <1125000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
+ cluster1_opp: opp-table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <830000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp@1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <880000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <1030000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1200000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@1992000000 {
+ opp-hz = /bits/ 64 <1992000000>;
+ opp-microvolt = <1230000>;
+ clock-latency-ns = <40000>;
+ turbo-mode;
+ };
+ };
+
+ gpu_opp_table: opp-table2 {
+ compatible = "operating-points-v2";
+
+ opp@200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <800000>;
+ };
+ opp@297000000 {
+ opp-hz = /bits/ 64 <297000000>;
+ opp-microvolt = <800000>;
+ };
+ opp@400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <830000>;
+ };
+ opp@500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <880000>;
+ };
+ opp@600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <930000>;
+ };
+ opp@800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1100000>;
+ };
+ };
+
+ dmc_opp_table: opp-table3 {
+ compatible = "operating-points-v2";
+
+ opp@200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <825000>;
+ };
+ opp@297000000 {
+ opp-hz = /bits/ 64 <297000000>;
+ opp-microvolt = <850000>;
+ };
+ opp@400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <850000>;
+ };
+ opp@594000000 {
+ opp-hz = /bits/ 64 <594000000>;
+ opp-microvolt = <900000>;
+ };
+ opp@800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <900000>;
+ };
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ sgtl5000_clk: sgtl5000-oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12000000>;
+ };
+
+ sgtl5000-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "Haikou,I2S-codec";
+ // 24.576 MHz oscillator on the baseboard, divided by 512 = 48 kHz
+ simple-audio-card,mclk-fs = <512>;
+ simple-audio-card,cpu {
+ sound-dai = <&i2s0>;
+ frame-master;
+ bitclock-master;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&sgtl5000>;
+ clocks = <&sgtl5000_clk>;
+ };
+ };
+
+ dw_hdmi_audio: dw-hdmi-audio {
+ status = "enabled";
+ compatible = "rockchip,dw-hdmi-audio";
+ #sound-dai-cells = <0>;
+ };
+
+ hdmi_codec: hdmi-codec {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,name = "HDMI-CODEC";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s2>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&hdmi>;
+ };
+ };
+
+ hdmi_sound: hdmi-sound {
+ status = "disabled";
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,name = "rockchip,hdmi";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s2>;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&hdmi>;
+ };
+ };
+
+ vccadc_ref: vccadc-ref {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vdda_codec: vdda-codec {
+ compatible = "regulator-fixed";
+ regulator-name = "vdda_codec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddd_codec: vddd-codec {
+ compatible = "regulator-fixed";
+ regulator-name = "vddd_codec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <1600000>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vcc5v0_otg: vcc5v0-otg-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&otg_vbus_drv>;
+ regulator-name = "vcc5v0_otg";
+ regulator-always-on;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-low;
+ gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&host_vbus_drv>;
+ regulator-name = "vcc5v0_host";
+ regulator-always-on;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&display_subsystem {
+ status = "okay";
+};
+
+&edp {
+ status = "disabled";
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&gmac {
+ phy-supply = <&vcc_phy>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ snps,reset-gpio = <&gpio3 16 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <2 10000 50000>;
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
+ assigned-clock-parents = <&clkin_gmac>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ tx_delay = <0x10>;
+ rx_delay = <0x10>;
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+ mali-supply = <&vdd_gpu>;
+};
+
+&hdmi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
+&route_hdmi {
+ status = "okay";
+ // default in rk3399-linux.dtsi: connect = <&vopl_out_hdmi>;
+ connect = <&vopb_out_hdmi>;
+};
+
+&i2c0 {
+ status = "okay";
+ i2c-scl-rising-time-ns = <168>;
+ i2c-scl-falling-time-ns = <4>;
+ clock-frequency = <400000>;
+
+ vdd_gpu: fan535555@60 {
+ compatible = "fcs,fan53555";
+ reg = <0x60>;
+ vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vcc5v0_sys>;
+ regulator-compatible = "fan53555-reg";
+ regulator-name = "vdd_gpu";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1230000>;
+ regulator-ramp-delay = <1000>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-state = <3>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <22 IRQ_TYPE_LEVEL_LOW>; // TODO check interrupt?
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc5v0_sys>;
+ vcc12-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc1v8_pmu>;
+
+ regulators {
+ vdd_center: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-name = "vdd_center";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_l: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-name = "vdd_cpu_l";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_ddr";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_ldo1: LDO_REG1 {
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_ldo1";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_hdmi: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_hdmi";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_pmu: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_sd: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_sd";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_ldo5: LDO_REG5 {
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc_ldo5";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ldo6: LDO_REG6 {
+ regulator-boot-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc_ldo6";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc0v9_hdmi: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vcc0v9_hdmi";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_efuse: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_efuse";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_s3: SWITCH_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc3v3_s3";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_s0: SWITCH_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc3v3_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2c8 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ vdd_cpu_b: fan53555@60 {
+ compatible = "fcs,fan53555";
+ reg = <0x60>;
+ vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vcc5v0_sys>;
+ regulator-compatible = "fan53555-reg";
+ regulator-name = "vdd_cpu_b";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1230000>;
+ regulator-ramp-delay = <1000>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-state = <3>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+/* Q7_I2S */
+&i2s0 {
+ status = "okay";
+ rockchip,i2s-broken-burst-len;
+ rockchip,playback-channels = <2>;
+ rockchip,capture-channels = <2>;
+ #sound-dai-cells = <0>;
+ pinctrl-0 = <&i2s0_2ch_bus>;
+};
+
+&i2s2 {
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
+&io_domains {
+ status = "okay";
+
+ bt656-supply = <&vcc_1v8>; /* bt656_gpio2ab_ms */
+ audio-supply = <&vcc_1v8>; /* audio_gpio3d4a_ms */
+ sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */
+ gpio1830-supply = <&vcc_1v8>; /* gpio1833_gpio4cd_ms */
+};
+
+&pcie0 {
+ assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
+ assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
+ assigned-clock-rates = <100000000>;
+ ep-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+ num-lanes = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_clkreqn>;
+ status = "okay";
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+&pmu_io_domains {
+ status = "okay";
+ pmu1830-supply = <&vcc_1v8>;
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+/* On-Module eMMC */
+&sdhci {
+ bus-width = <8>;
+ supports-emmc;
+ non-removable;
+ keep-power-in-suspend;
+ status = "okay";
+};
+
+/* Q7_SDIO - External SD Card */
+&sdmmc {
+ // On the AP6255 Wifi module, firmware download fails above 25 MHz. Set to 10 MHz to be safe.
+ //max-frequency = <10000000>;
+ max-frequency = <50000000>; // 50 MHz = High Speed 3.3V
+ supports-sdio;
+ supports-sd;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ num-slots = <1>;
+ vqmmc-supply = <&vcc_sd>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+};
+
+&tcphy0 {
+ status = "okay";
+};
+
+&tcphy1 {
+ status = "okay";
+};
+
+&tsadc {
+ /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-mode = <1>;
+ /* tshut polarity 0:LOW 1:HIGH */
+ rockchip,hw-tshut-polarity = <1>;
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+
+ u2phy0_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy0_host: host-port {
+ phy-supply = <&vcc5v0_otg>;
+ status = "okay";
+ };
+};
+
+&u2phy1 {
+ status = "okay";
+
+ u2phy1_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy1_host: host-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd3_1 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usbdrd_dwc3_1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&rkvdec {
+ status = "okay";
+ /* 0 means ion, 1 means drm */
+ //allocator = <0>;
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vpu {
+ status = "okay";
+ /* 0 means ion, 1 means drm */
+ //allocator = <0>;
+};
+
+&pinctrl {
+ // Pins that are not explicitely used by any devices
+ pinctrl-names = "default";
+ pinctrl-0 = <&puma_pin_hog>;
+ hog {
+ puma_pin_hog: puma_pin_hog {
+ rockchip,pins =
+ <1 26 RK_FUNC_GPIO &pcfg_pull_up>, // Q7_USB_ID
+ // We need pull-ups on Q7 buttons
+ <0 4 RK_FUNC_GPIO &pcfg_pull_up>, // LID_BTN#
+ <0 10 RK_FUNC_GPIO &pcfg_pull_up>, // BATLOW#
+ <0 11 RK_FUNC_GPIO &pcfg_pull_up>, // SLP_BTN#
+ <0 9 RK_FUNC_GPIO &pcfg_pull_up>, // BIOS_DISABLE#
+ <0 3 RK_FUNC_GPIO &pcfg_pull_up>, // THRM#
+ <0 13 RK_FUNC_GPIO &pcfg_pull_up>, // SDIO_WP#
+ <0 12 RK_FUNC_GPIO &pcfg_pull_up>; // SMB_ALERT#
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins =
+ <1 22 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ leds_pins_puma: led_pins@0 {
+ rockchip,pins =
+ <2 25 RK_FUNC_GPIO &pcfg_pull_none>,
+ <1 2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usb2 {
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins =
+ <0 2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins =
+ <0 2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ i2c8 {
+ i2c8_xfer_a: i2c8-xfer {
+ rockchip,pins = <1 21 RK_FUNC_1 &pcfg_pull_up>,
+ <1 20 RK_FUNC_1 &pcfg_pull_up>;
+ };
+ };
+
+ i2s0 {
+ i2s0_2ch_bus: i2s0_2ch_bus {
+ rockchip,pins =
+ <3 24 RK_FUNC_1 &pcfg_pull_none>, // I2S_CLK
+ <3 26 RK_FUNC_1 &pcfg_pull_none>, // I2S_WS
+ <3 27 RK_FUNC_1 &pcfg_pull_none>, // I2S_SDI
+ <3 31 RK_FUNC_1 &pcfg_pull_none>; // I2S_SDO
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+};
+&i2c2 {
+ status = "okay";
+ clock-frequency = <400000>;
+};
+&i2c4 {
+ status = "okay";
+ clock-frequency = <400000>;
+ sgtl5000: codec@0a {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ VDDA-supply = <&vdda_codec>;
+ VDDIO-supply = <&vdda_codec>;
+ VDDD-supply = <&vddd_codec>;
+ clocks = <&sgtl5000_clk>;
+ status = "okay";
+ };
+};
+&i2c6 {
+ status = "okay";
+ clock-frequency = <400000>;
+};
+
+// Enable pull-ups, the pins would float otherwise.
+&i2c6_xfer {
+ rockchip,pins =
+ <2 10 RK_FUNC_2 &pcfg_pull_up>,
+ <2 9 RK_FUNC_2 &pcfg_pull_up>;
+};
+
+&i2c7 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ rtc_twi: rtc@6f {
+ compatible = "isil,isl1208";
+ reg = <0x6f>;
+ };
+ fan: fan@18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
+ cooling-min-state = <0>;
+ cooling-max-state = <9>;
+ #cooling-cells = <2>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vccadc_ref>;
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+
+ flash: w25q32fw@0 {
+ compatible = "winbond,w25q32dw";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&rockchip_suspend {
+ status = "okay";
+ rockchip,sleep-debug-en = <1>;
+ rockchip,sleep-mode-config = <
+ (0
+ | RKPM_SLP_ARMPD
+ | RKPM_SLP_PERILPPD
+ | RKPM_SLP_DDR_RET
+ | RKPM_SLP_PLLPD
+ | RKPM_SLP_CENTER_PD
+ | RKPM_SLP_AP_PWROFF
+ )
+ >;
+ rockchip,wakeup-config = <
+ (0
+ | RKPM_GPIO_WKUP_EN
+ | RKPM_PWM_WKUP_EN
+ )
+ >;
+ rockchip,pwm-regulator-config = <
+ (0
+ | PWM2_REGULATOR_EN
+ )
+ >;
+ rockchip,power-ctrl =
+ <&gpio1 4 GPIO_ACTIVE_HIGH>,
+ <&gpio1 14 GPIO_ACTIVE_HIGH>;
+};
+
+&cpu_l0 {
+ operating-points-v2 = <&cluster0_opp>;
+ sched-energy-costs = <&RK3399_CPU_COST_0 &RK3399_CLUSTER_COST_0>;
+};
+
+&cpu_l1 {
+ operating-points-v2 = <&cluster0_opp>;
+ sched-energy-costs = <&RK3399_CPU_COST_0 &RK3399_CLUSTER_COST_0>;
+};
+
+&cpu_l2 {
+ operating-points-v2 = <&cluster0_opp>;
+ sched-energy-costs = <&RK3399_CPU_COST_0 &RK3399_CLUSTER_COST_0>;
+};
+
+&cpu_l3 {
+ operating-points-v2 = <&cluster0_opp>;
+ sched-energy-costs = <&RK3399_CPU_COST_0 &RK3399_CLUSTER_COST_0>;
+};
+
+&cpu_b0 {
+ operating-points-v2 = <&cluster1_opp>;
+ sched-energy-costs = <&RK3399_CPU_COST_1 &RK3399_CLUSTER_COST_1>;
+};
+
+&cpu_b1 {
+ operating-points-v2 = <&cluster1_opp>;
+ sched-energy-costs = <&RK3399_CPU_COST_1 &RK3399_CLUSTER_COST_1>;
+};
+
+&gpu {
+ operating-points-v2 = <&gpu_opp_table>;
+};
+
+&dmc {
+ operating-points-v2 = <&dmc_opp_table>;
+};
diff --git a/arch/arm64/configs/puma-rk3399_defconfig b/arch/arm64/configs/puma-rk3399_defconfig
new file mode 100644
index 000000000000..9a844fb79152
--- /dev/null
+++ b/arch/arm64/configs/puma-rk3399_defconfig
@@ -0,0 +1,598 @@
+CONFIG_DEFAULT_HOSTNAME="localhost"
+CONFIG_SYSVIPC=y
+CONFIG_FHANDLE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_NAMESPACES=y
+CONFIG_USER_NS=y
+CONFIG_DEFAULT_USE_ENERGY_AWARE=y
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_RD_LZ4 is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_EMBEDDED=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_PROFILING=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCIE_ROCKCHIP=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIEASPM_POWERSAVE=y
+# CONFIG_ARM64_ERRATUM_826319 is not set
+# CONFIG_ARM64_ERRATUM_827319 is not set
+# CONFIG_ARM64_ERRATUM_824069 is not set
+# CONFIG_ARM64_ERRATUM_819472 is not set
+# CONFIG_ARM64_ERRATUM_832075 is not set
+# CONFIG_CAVIUM_ERRATUM_22375 is not set
+# CONFIG_CAVIUM_ERRATUM_23154 is not set
+CONFIG_SCHED_MC=y
+CONFIG_NR_CPUS=8
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_HZ_1000=y
+# CONFIG_COMPACTION is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
+CONFIG_ZSMALLOC=y
+CONFIG_SECCOMP=y
+CONFIG_ARMV8_DEPRECATED=y
+CONFIG_SWP_EMULATION=y
+CONFIG_CP15_BARRIER_EMULATION=y
+CONFIG_SETEND_EMULATION=y
+# CONFIG_EFI is not set
+CONFIG_COMPAT=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_ADVANCED_DEBUG=y
+CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
+CONFIG_CPU_IDLE=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_ARM_ROCKCHIP_CPUFREQ=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+# CONFIG_INET_DIAG is not set
+CONFIG_TCP_CONG_ADVANCED=y
+# CONFIG_TCP_CONG_BIC is not set
+# CONFIG_TCP_CONG_WESTWOOD is not set
+# CONFIG_TCP_CONG_HTCP is not set
+CONFIG_TCP_CONG_LP=y
+CONFIG_TCP_MD5SIG=y
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+# CONFIG_ANDROID_PARANOID_NETWORK is not set
+CONFIG_NETWORK_SECMARK=y
+CONFIG_NETFILTER=y
+CONFIG_BRIDGE_NETFILTER=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XT_MARK=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_DSCP=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_TARGET_SECMARK=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_IP_SET=y
+CONFIG_IP_VS=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_NF_CONNTRACK_IPV6=y
+CONFIG_NF_NAT_IPV6=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_MATCH_IPV6HEADER=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_BRIDGE=y
+CONFIG_VLAN_8021Q=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_CODEL=y
+CONFIG_NET_SCH_FQ_CODEL=y
+CONFIG_NET_CLS_U32=y
+CONFIG_CLS_U32_MARK=y
+CONFIG_CAN=y
+CONFIG_CAN_LEDS=y
+CONFIG_CAN_UCAN=y
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_HIDP=y
+CONFIG_BT_HCIBTUSB=y
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_ATH3K=y
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIBFUSB=y
+CONFIG_BT_HCIVHCI=y
+CONFIG_BT_MRVL=y
+CONFIG_BT_MRVL_SDIO=y
+CONFIG_CFG80211=y
+CONFIG_NL80211_TESTMODE=y
+CONFIG_CFG80211_DEBUGFS=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_MAC80211=y
+CONFIG_MAC80211_LEDS=y
+CONFIG_MAC80211_DEBUGFS=y
+CONFIG_MAC80211_DEBUG_MENU=y
+CONFIG_MAC80211_VERBOSE_DEBUG=y
+CONFIG_RFKILL=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DEBUG_DEVRES=y
+CONFIG_CONNECTOR=y
+CONFIG_MTD=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_BLOCK2MTD=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_ZRAM=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=1
+CONFIG_BLK_DEV_NVME=y
+CONFIG_ROCKCHIP_SCR=y
+CONFIG_SRAM=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_SCSI_SPI_ATTRS=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_CRYPT=y
+CONFIG_DM_THIN_PROVISIONING=y
+CONFIG_DM_VERITY=y
+CONFIG_NETDEVICES=y
+CONFIG_TUN=y
+CONFIG_VETH=y
+CONFIG_VHOST_NET=y
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_AGERE is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+CONFIG_EMAC_ROCKCHIP=y
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_VENDOR_CAVIUM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EXAR is not set
+# CONFIG_NET_VENDOR_HP is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_NET_PACKET_ENGINE is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_REALTEK is not set
+# CONFIG_NET_VENDOR_RDC is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+CONFIG_PPP=y
+CONFIG_PPP_ASYNC=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_RTL8150=y
+CONFIG_USB_RTL8152=y
+CONFIG_USB_NET_CDC_MBIM=y
+CONFIG_USB_NET_DM9601=y
+CONFIG_USB_NET_SMSC75XX=y
+CONFIG_USB_NET_SMSC95XX=y
+CONFIG_USB_NET_MCS7830=y
+# CONFIG_USB_NET_CDC_SUBSET is not set
+# CONFIG_USB_NET_ZAURUS is not set
+CONFIG_LIBERTAS_THINFIRM=y
+CONFIG_USB_NET_RNDIS_WLAN=y
+CONFIG_BRCMFMAC=y
+CONFIG_HOSTAP=y
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+CONFIG_MWIFIEX=y
+CONFIG_MWIFIEX_SDIO=y
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_JOYDEV=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_ADC=y
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_GPIO_POLLED=y
+CONFIG_KEYBOARD_ROCKCHIP=y
+CONFIG_KEYBOARD_CROS_EC=y
+# CONFIG_MOUSE_PS2 is not set
+CONFIG_MOUSE_CYAPA=y
+CONFIG_MOUSE_ELAN_I2C=y
+CONFIG_INPUT_JOYSTICK=y
+CONFIG_JOYSTICK_IFORCE=y
+CONFIG_JOYSTICK_IFORCE_USB=y
+CONFIG_JOYSTICK_XPAD=y
+CONFIG_JOYSTICK_XPAD_FF=y
+CONFIG_JOYSTICK_XPAD_LEDS=y
+CONFIG_INPUT_TABLET=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ATMEL_MXT=y
+CONFIG_TOUCHSCREEN_GSLX680_VR=y
+CONFIG_TOUCHSCREEN_GSL3673=y
+CONFIG_TOUCHSCREEN_GT9XX=y
+CONFIG_TOUCHSCREEN_ELAN=y
+CONFIG_TOUCHSCREEN_USB_COMPOSITE=y
+CONFIG_TOUCHSCREEN_SILEAD=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_INPUT_GPIO=y
+CONFIG_SERIO_RAW=y
+CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_HW_RANDOM=y
+CONFIG_TCG_TPM=y
+CONFIG_TCG_TIS_I2C_INFINEON=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_RK3X=y
+CONFIG_I2C_CROS_EC_TUNNEL=y
+CONFIG_I2C_STUB=m
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_ROCKCHIP=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_BATTERY_SBS=y
+CONFIG_CHARGER_GPIO=y
+CONFIG_CHARGER_BQ24735=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_RESET_GPIO_RESTART=y
+CONFIG_SYSCON_REBOOT_MODE=y
+CONFIG_POWER_AVS=y
+CONFIG_ROCKCHIP_IODOMAIN=y
+CONFIG_SENSORS_AMC6821=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR=y
+CONFIG_THERMAL_GOV_FAIR_SHARE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_CPU_THERMAL=y
+CONFIG_DEVFREQ_THERMAL=y
+CONFIG_ROCKCHIP_THERMAL=y
+CONFIG_MFD_CROS_EC=y
+CONFIG_MFD_CROS_EC_SPI=y
+CONFIG_MFD_RK808=y
+CONFIG_MFD_TPS6586X=y
+CONFIG_FUSB_30X=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_DEBUG=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_ACT8865=y
+CONFIG_REGULATOR_FAN53555=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_LP8752=y
+CONFIG_REGULATOR_MP8865=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK808=y
+CONFIG_REGULATOR_RK818=y
+CONFIG_REGULATOR_TPS6586X=y
+CONFIG_REGULATOR_XZ3216=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_RC_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=y
+# CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV is not set
+# CONFIG_USB_GSPCA is not set
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_VIDEO_ROCKCHIP_RGA=y
+CONFIG_V4L_TEST_DRIVERS=y
+# CONFIG_VGA_ARB is not set
+CONFIG_DRM=y
+CONFIG_DRM_LOAD_EDID_FIRMWARE=y
+CONFIG_DRM_DMA_SYNC=y
+CONFIG_DRM_ROCKCHIP=y
+CONFIG_ROCKCHIP_DW_HDMI=y
+CONFIG_ROCKCHIP_DW_MIPI_DSI=y
+CONFIG_ROCKCHIP_ANALOGIX_DP=y
+CONFIG_ROCKCHIP_INNO_HDMI=y
+CONFIG_ROCKCHIP_LVDS=y
+CONFIG_DRM_UDL=y
+CONFIG_DRM_PANEL_SIMPLE=y
+CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
+CONFIG_MALI_DEVFREQ=y
+CONFIG_MALI_MIDGARD=y
+CONFIG_MALI_EXPERT=y
+CONFIG_MALI_PLATFORM_THIRDPARTY=y
+CONFIG_MALI_PLATFORM_THIRDPARTY_NAME="rk"
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_RK_VCODEC=y
+CONFIG_ROCKCHIP_MPP_SERVICE=y
+CONFIG_ROCKCHIP_MPP_DEVICE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SEQUENCER=y
+CONFIG_SND_SEQ_DUMMY=y
+CONFIG_SND_HRTIMER=y
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_PCI is not set
+# CONFIG_SND_SPI is not set
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_ROCKCHIP=y
+CONFIG_SND_SOC_ROCKCHIP_SPDIF=y
+CONFIG_SND_SOC_ROCKCHIP_MAX98090=y
+CONFIG_SND_SOC_ROCKCHIP_RT5645=y
+CONFIG_SND_SOC_ES8316=y
+CONFIG_SND_SOC_RT5616=y
+CONFIG_SND_SOC_RT5640=y
+CONFIG_SND_SOC_RT5651=y
+CONFIG_SND_SOC_SGTL5000=y
+CONFIG_SND_SOC_SPDIF=y
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_SOUND_PRIME=y
+CONFIG_HID_BATTERY_STRENGTH=y
+CONFIG_HIDRAW=y
+CONFIG_UHID=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_KENSINGTON=y
+CONFIG_HID_LOGITECH=y
+CONFIG_HID_LOGITECH_DJ=y
+CONFIG_HID_MAGICMOUSE=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MULTITOUCH=y
+CONFIG_HID_PLANTRONICS=y
+CONFIG_HID_PRIMAX=y
+CONFIG_HID_SONY=y
+CONFIG_HID_RMI=y
+CONFIG_HID_WIIMOTE=y
+CONFIG_USB_HIDDEV=y
+CONFIG_I2C_HID=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+# CONFIG_USB_DEFAULT_PERSIST is not set
+CONFIG_USB_OTG=y
+CONFIG_USB_MON=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_HCD_PCI is not set
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_ACM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_UAS=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_PCI is not set
+CONFIG_USB_DWC2=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_CP210X=y
+CONFIG_USB_SERIAL_FTDI_SIO=y
+CONFIG_USB_SERIAL_KEYSPAN=y
+CONFIG_USB_SERIAL_PL2303=y
+CONFIG_USB_SERIAL_OTI6858=y
+CONFIG_USB_SERIAL_QUALCOMM=y
+CONFIG_USB_SERIAL_SIERRAWIRELESS=y
+CONFIG_USB_SERIAL_OPTION=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_VBUS_DRAW=500
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_UEVENT=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_TEST=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_HYM8563=y
+CONFIG_RTC_DRV_ISL1208=y
+CONFIG_DMADEVICES=y
+CONFIG_PL330_DMA=y
+CONFIG_STAGING=y
+CONFIG_SENSORS_ISL29018=y
+CONFIG_TSL2583=y
+CONFIG_ASHMEM=y
+# CONFIG_ANDROID_TIMED_OUTPUT is not set
+CONFIG_FIQ_DEBUGGER=y
+CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
+CONFIG_FIQ_DEBUGGER_CONSOLE=y
+CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
+CONFIG_COMMON_CLK_RK808=y
+CONFIG_MAILBOX=y
+CONFIG_ROCKCHIP_IOMMU=y
+CONFIG_ROCKCHIP_PM_DOMAINS=y
+CONFIG_PM_DEVFREQ=y
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_DEVFREQ_GOV_USERSPACE=y
+CONFIG_PM_DEVFREQ_EVENT=y
+CONFIG_MEMORY=y
+CONFIG_IIO=y
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_KFIFO_BUF=y
+CONFIG_IIO_TRIGGER=y
+CONFIG_ROCKCHIP_SARADC=y
+CONFIG_SENSORS_TSL2563=y
+CONFIG_IIO_SYSFS_TRIGGER=y
+CONFIG_PWM=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_USB=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_INNO_USB3=y
+CONFIG_PHY_ROCKCHIP_EMMC=y
+CONFIG_PHY_ROCKCHIP_DP=y
+CONFIG_PHY_ROCKCHIP_INNO_HDMI_PHY=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
+CONFIG_PHY_ROCKCHIP_PCIE=y
+CONFIG_ANDROID=y
+CONFIG_NVMEM=y
+CONFIG_ROCKCHIP_EFUSE=y
+CONFIG_ROCKCHIP_SIP=y
+# CONFIG_ACPI is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_PSTORE=y
+CONFIG_PSTORE_CONSOLE=y
+CONFIG_PSTORE_RAM=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_SWAP=y
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+CONFIG_CIFS=y
+# CONFIG_CIFS_DEBUG is not set
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_KVM=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_INFO=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_CREDENTIALS=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_FUNCTION_TRACER=y
+CONFIG_BLK_DEV_IO_TRACE=y
+CONFIG_LKDTM=y
+CONFIG_TEST_UDELAY=y
+CONFIG_STRICT_DEVMEM=y
+CONFIG_DEBUG_SET_MODULE_RONX=y
+CONFIG_SECURITY=y
+CONFIG_SECURITY_NETWORK=y
+CONFIG_SECURITY_PATH=y
+CONFIG_SECURITY_YAMA=y
+CONFIG_CRYPTO_ECHAINIV=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_CRYPTO_USER_API_SKCIPHER=y
+CONFIG_ASYMMETRIC_KEY_TYPE=y
+CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
+CONFIG_X509_CERTIFICATE_PARSER=y
+CONFIG_PKCS7_MESSAGE_PARSER=y
+CONFIG_SYSTEM_TRUSTED_KEYRING=y
+CONFIG_ARM64_CRYPTO=y
+CONFIG_CRYPTO_SHA1_ARM64_CE=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC7=y
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_IA64 is not set
+# CONFIG_XZ_DEC_SPARC is not set
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-23 15:06:05 +0000