diff options
| author | huang lin <hl@rock-chips.com> | 2018-05-15 11:22:39 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-08-15 17:28:40 +0800 |
| commit | eedd1893c99597f7229cf81ec65e68c36ceab16d (patch) | |
| tree | 1752f3c6287c74857dc7f286734d44cc76135c81 /include/soc | |
| parent | 707ec089ca32a9e69da448a37b8c2ad3248e0457 (diff) | |
BACKPORT: FROMLIST: phy: rockchip-typec: support variable phy config value
the phy config values used to fix in dp firmware, but some boards
need change these values to do training and get the better eye diagram
result. So support that in phy driver.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Lin Huang <hl@rock-chips.com>
(am from https://patchwork.kernel.org/patch/10420473/)
Conflicts:
drivers/phy/phy-rockchip-typec.c
[phy-rockchip-typec.c is different path in upstream code]
BUG=b:72006974
TEST=DP can display on Dru
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1032713
Change-Id: I8a63307ad5cb690d819779662d70ae1c232842a5
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Diffstat (limited to 'include/soc')
| -rw-r--r-- | include/soc/rockchip/rockchip_phy_typec.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/soc/rockchip/rockchip_phy_typec.h b/include/soc/rockchip/rockchip_phy_typec.h index b13d01368b76..51270e4f85d7 100644 --- a/include/soc/rockchip/rockchip_phy_typec.h +++ b/include/soc/rockchip/rockchip_phy_typec.h @@ -23,6 +23,11 @@ struct rockchip_usb3phy_port_cfg { struct usb3phy_reg uphy_dp_sel; }; +struct phy_config { + int swing; + int pe; +}; + struct rockchip_typec_phy { struct device *dev; void __iomem *base; @@ -39,6 +44,9 @@ struct rockchip_typec_phy { bool flip; u8 mode; + struct phy_config config[3][4]; + int (*typec_phy_config)(struct phy *phy, int link_rate, + int lanes, u8 swing, u8 pre_emp); }; #endif |