diff options
| author | Zheng Yang <zhengyang@rock-chips.com> | 2017-06-21 15:18:04 +0800 |
|---|---|---|
| committer | Jianqun Xu <jay.xu@rock-chips.com> | 2017-06-29 14:20:49 +0800 |
| commit | 572c46535894f9b7d54ff717865ba3fa63fe6355 (patch) | |
| tree | 788f2268d1c976b4566aec83dddbe40ce458654a /drivers | |
| parent | e68ba0f6ddabe9e51f275d7399b5b900f3fb11e4 (diff) | |
drm: rockchip: hdmi: check sink max_tmds_clock in mode_valid
If sink max TMDS clock < 340MHz, we think the mode pixel clock
greater than 340MHz should support YCbCr420, or it is a bad mode.
Change-Id: I9f53fa4f9875977ae0355b65d9ccd8a304558c5d
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 104f8771bd31..fafdd94fd2ba 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -888,6 +888,14 @@ dw_hdmi_rockchip_mode_valid(struct drm_connector *connector, */ if (mode->clock > INT_MAX / 1000) return MODE_BAD; + /* + * If sink max TMDS clock < 340MHz, we should check the mode pixel + * clock > 340MHz is YCbCr420 or not. + */ + if (mode->clock > 340000 && + connector->display_info.max_tmds_clock < 340000 && + !(mode->flags & DRM_MODE_FLAG_420_MASK)) + return MODE_BAD; if (!encoder) { const struct drm_connector_helper_funcs *funcs; |