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authorHuibin Hong <huibin.hong@rock-chips.com>2016-09-26 16:09:10 +0800
committerHuang, Tao <huangtao@rock-chips.com>2016-09-26 18:33:23 +0800
commit087633170d51f3b5307c145c3681968bfedbc8e6 (patch)
tree9e2cd7e3206c44f18794cd5e5a27a8be3b471d32 /drivers
parent97ff73ffbcef885e0b74b48088e95340664085db (diff)
rk_fiq_debugger: Reset and set uart to loopback mode before init
The uart may be reinitialized when resume, if uart is in busy state, which would fail to configure the baud rate. So reset and set uart to loopback mode can make sure uart is in idle state. Change-Id: I54d9ac8de1531cd06da8c223583cd2e330178eff Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Diffstat (limited to 'drivers')
-rwxr-xr-xdrivers/soc/rockchip/rk_fiq_debugger.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/soc/rockchip/rk_fiq_debugger.c b/drivers/soc/rockchip/rk_fiq_debugger.c
index e6f960894b89..d9d798f0d3c1 100755
--- a/drivers/soc/rockchip/rk_fiq_debugger.c
+++ b/drivers/soc/rockchip/rk_fiq_debugger.c
@@ -36,6 +36,7 @@
#include <../drivers/staging/android/fiq_debugger/fiq_debugger.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/clk.h>
+#include <linux/delay.h>
#include <linux/soc/rockchip/rk_fiq_debugger.h>
#ifdef CONFIG_FIQ_DEBUGGER_EL3_TO_EL1
@@ -48,6 +49,7 @@
#define UART_USR_TX_FIFO_EMPTY 0x04 /* Transmit FIFO empty */
#define UART_USR_TX_FIFO_NOT_FULL 0x02 /* Transmit FIFO not full */
#define UART_USR_BUSY 0x01 /* UART busy indicator */
+#define UART_SRR 0x22 /* software reset register */
struct rk_fiq_debugger {
int irq;
@@ -102,6 +104,11 @@ static int debug_port_init(struct platform_device *pdev)
dll = 0xd;
break;
}
+ /* reset uart */
+ rk_fiq_write(t, 0x07, UART_SRR);
+ udelay(10);
+ /* set uart to loop back mode */
+ rk_fiq_write(t, 0x10, UART_MCR);
rk_fiq_write(t, 0x83, UART_LCR);
/* set baud rate */
@@ -118,6 +125,7 @@ static int debug_port_init(struct platform_device *pdev)
found unregistered, so it is disable.
hhb@rock-chips.com */
rk_fiq_write(t, 0xc1, UART_FCR);
+ rk_fiq_write(t, 0x0, UART_MCR);
return 0;
}