diff options
| author | Wenlong Zhuang <daisen.zhuang@rock-chips.com> | 2019-01-10 21:21:14 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2019-01-21 09:13:36 +0800 |
| commit | c0bad62acdf9517e6f06173c7db9dac9630bd5a7 (patch) | |
| tree | d4be1490ae26c1b10baea883cd9dc3a04b521ebf /drivers | |
| parent | 1dcc7058e820e64d89a20d2a2d81d526635ebe63 (diff) | |
phy/rockchip: mipi-rx: add support maximum clock frequency
Also fix configure settle count failed for rk1808.
Change-Id: I61be26eb322901c66ccfd358ef18fbe4f48947ef
Signed-off-by: Wenlong Zhuang <daisen.zhuang@rock-chips.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/phy/rockchip/phy-rockchip-mipi-rx.c | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/drivers/phy/rockchip/phy-rockchip-mipi-rx.c b/drivers/phy/rockchip/phy-rockchip-mipi-rx.c index 000423fba452..7bc219942765 100644 --- a/drivers/phy/rockchip/phy-rockchip-mipi-rx.c +++ b/drivers/phy/rockchip/phy-rockchip-mipi-rx.c @@ -582,7 +582,7 @@ static void csi_mipidphy_wr_ths_settle(struct mipidphy_priv *priv, int hsfreq, } read_csiphy_reg(priv, offset, &val); - val = (val & ~0xf) | hsfreq; + val = (val & ~0x7f) | hsfreq; write_csiphy_reg(priv, offset, val); } @@ -889,6 +889,13 @@ static int mipidphy_rx_stream_on(struct mipidphy_priv *priv, } } + if (i == num_hsfreq_ranges) { + i = num_hsfreq_ranges - 1; + dev_warn(priv->dev, "data rate: %lld mbps, max support %d mbps", + priv->data_rate_mbps, hsfreq_ranges[i].range_h + 1); + hsfreq = hsfreq_ranges[i].cfg_bit; + } + /* RK3288 isp connected to phy0-rx */ write_grf_reg(priv, GRF_CON_ISP_DPHY_SEL, 0); @@ -973,6 +980,13 @@ static int mipidphy_txrx_stream_on(struct mipidphy_priv *priv, } } + if (i == num_hsfreq_ranges) { + i = num_hsfreq_ranges - 1; + dev_warn(priv->dev, "data rate: %lld mbps, max support %d mbps", + priv->data_rate_mbps, hsfreq_ranges[i].range_h + 1); + hsfreq = hsfreq_ranges[i].cfg_bit; + } + /* *Config rk3288: *step1:rk3288 isp connected to phy1-rx @@ -1119,6 +1133,14 @@ static int csi_mipidphy_stream_on(struct mipidphy_priv *priv, break; } } + + if (i == num_hsfreq_ranges) { + i = num_hsfreq_ranges - 1; + dev_warn(priv->dev, "data rate: %lld mbps, max support %d mbps", + priv->data_rate_mbps, hsfreq_ranges[i].range_h + 1); + hsfreq = hsfreq_ranges[i].cfg_bit; + } + csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_CLOCK); if (sensor->lanes > 0x00) csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_DATA0); |