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authorSandy Huang <hjc@rock-chips.com>2018-04-18 15:42:10 +0800
committerTao Huang <huangtao@rock-chips.com>2018-04-19 18:39:34 +0800
commit04e6e5c7a0bf11fabc5472c0666d30c1b2799583 (patch)
tree7ca02025c3fdfe449a0083b5fd79061521820944 /drivers
parent27e0c547c220f41e5be9f24ec33e089573c5b98f (diff)
drm/rockchip: vop: add support dclk invert config
Since some special hardware or panel need to invert dclk, so we add dclk invert config at dts display timing node: dts sample: display-timings { timing0: timing0 { ... pixelclk-active = <1>; ... } } Change-Id: I64f053ecda0f607bdd6fd392a0922489502ac274 Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/drm_modes.c3
-rw-r--r--drivers/gpu/drm/rockchip/rockchip_drm_vop.c13
2 files changed, 11 insertions, 5 deletions
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 4a7614d6575e..d2d04615be0e 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -611,6 +611,9 @@ void drm_display_mode_from_videomode(const struct videomode *vm,
dmode->flags |= DRM_MODE_FLAG_DBLSCAN;
if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
dmode->flags |= DRM_MODE_FLAG_DBLCLK;
+ if (vm->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
+ dmode->flags |= DRM_MODE_FLAG_PPIXDATA;
+
drm_mode_set_name(dmode);
}
EXPORT_SYMBOL_GPL(drm_display_mode_from_videomode);
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 6f5fd511e85f..3e7e4ef6032e 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -2475,6 +2475,7 @@ static void vop_crtc_enable(struct drm_crtc *crtc)
int act_end;
bool interlaced = !!(adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);
int for_ddr_freq = 0;
+ bool dclk_inv;
rockchip_set_system_status(sys_status);
mutex_lock(&vop->vop_lock);
@@ -2492,7 +2493,9 @@ static void vop_crtc_enable(struct drm_crtc *crtc)
*/
if (vop->lut_active)
vop_crtc_load_lut(crtc);
- VOP_CTRL_SET(vop, dclk_pol, 1);
+ dclk_inv = (adjusted_mode->flags & DRM_MODE_FLAG_PPIXDATA) ? 0 : 1;
+
+ VOP_CTRL_SET(vop, dclk_pol, dclk_inv);
val = (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
0 : BIT(HSYNC_POSITIVE);
val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ?
@@ -2509,15 +2512,15 @@ static void vop_crtc_enable(struct drm_crtc *crtc)
case DRM_MODE_CONNECTOR_LVDS:
VOP_CTRL_SET(vop, rgb_en, 1);
VOP_CTRL_SET(vop, rgb_pin_pol, val);
- VOP_CTRL_SET(vop, rgb_dclk_pol, 1);
+ VOP_CTRL_SET(vop, rgb_dclk_pol, dclk_inv);
VOP_CTRL_SET(vop, lvds_en, 1);
VOP_CTRL_SET(vop, lvds_pin_pol, val);
- VOP_CTRL_SET(vop, lvds_dclk_pol, 1);
+ VOP_CTRL_SET(vop, lvds_dclk_pol, dclk_inv);
break;
case DRM_MODE_CONNECTOR_eDP:
VOP_CTRL_SET(vop, edp_en, 1);
VOP_CTRL_SET(vop, edp_pin_pol, val);
- VOP_CTRL_SET(vop, edp_dclk_pol, 1);
+ VOP_CTRL_SET(vop, edp_dclk_pol, dclk_inv);
break;
case DRM_MODE_CONNECTOR_HDMIA:
VOP_CTRL_SET(vop, hdmi_en, 1);
@@ -2527,7 +2530,7 @@ static void vop_crtc_enable(struct drm_crtc *crtc)
case DRM_MODE_CONNECTOR_DSI:
VOP_CTRL_SET(vop, mipi_en, 1);
VOP_CTRL_SET(vop, mipi_pin_pol, val);
- VOP_CTRL_SET(vop, mipi_dclk_pol, 1);
+ VOP_CTRL_SET(vop, mipi_dclk_pol, dclk_inv);
VOP_CTRL_SET(vop, mipi_dual_channel_en,
!!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL));
VOP_CTRL_SET(vop, data01_swap,