diff options
| author | Finley Xiao <finley.xiao@rock-chips.com> | 2018-01-05 15:04:59 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-01-08 09:59:42 +0800 |
| commit | a1b416e8deffcd5b465205ae0ce7024f5fad26d7 (patch) | |
| tree | a00f2e9dbb07e61a8b04db2d89c4dc5bad260e48 /drivers | |
| parent | 32c581e78e6e1da07845931a61d0deb8f6e54b01 (diff) | |
clk: rockchip: px30: Add CLK_IGNORE_UNUSED for ddr clk
Change-Id: Ib53b8b8c24edeb4e1046808ae9ae2736d2fb8df9
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/rockchip/clk-px30.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/clk/rockchip/clk-px30.c b/drivers/clk/rockchip/clk-px30.c index 5d61cda9b3fb..4897872b8291 100644 --- a/drivers/clk/rockchip/clk-px30.c +++ b/drivers/clk/rockchip/clk-px30.c @@ -580,11 +580,11 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = { COMPOSITE(0, "clk_ddr_src", mux_ddrphy_p, CLK_IGNORE_UNUSED, PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, PX30_CLKGATE_CON(0), 14, GFLAGS), - FACTOR(SCLK_DDRC, "clk_ddr", "clk_ddr_src", 0, 1, 2), - FACTOR_GATE(0, "clk_ddrphy1x", "clk_ddr_src", 0, 1, 4, + FACTOR(SCLK_DDRC, "clk_ddr", "clk_ddr_src", CLK_IGNORE_UNUSED, 1, 2), + FACTOR_GATE(0, "clk_ddrphy1x", "clk_ddr_src", CLK_IGNORE_UNUSED, 1, 4, PX30_CLKGATE_CON(0), 14, GFLAGS), - FACTOR(0, "clk_stdby_2wrap", "clk_ddr_src", 0, 1, 4), - COMPOSITE_NODIV(0, "clk_ddrstdby", mux_ddrstdby_p, 0, + FACTOR(0, "clk_stdby_2wrap", "clk_ddr_src", CLK_IGNORE_UNUSED, 1, 4), + COMPOSITE_NODIV(0, "clk_ddrstdby", mux_ddrstdby_p, CLK_IGNORE_UNUSED, PX30_CLKSEL_CON(2), 4, 1, MFLAGS, PX30_CLKGATE_CON(1), 13, GFLAGS), GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED, @@ -596,7 +596,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = { GATE(0, "clk_ddrmon", "xin24m", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(0), 15, GFLAGS), - COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "gpll", 0, + COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "gpll", CLK_IGNORE_UNUSED, PX30_CLKSEL_CON(2), 8, 5, DFLAGS, PX30_CLKGATE_CON(1), 1, GFLAGS), GATE(0, "pclk_ddrupctl", "pclk_ddr", CLK_IGNORE_UNUSED, |