diff options
| author | Finley Xiao <finley.xiao@rock-chips.com> | 2018-10-30 21:05:38 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-11-01 16:44:26 +0800 |
| commit | ee8302dd5919a87e10794d2a54621c4f87cc53e7 (patch) | |
| tree | 853371a92f2c25d49bc641cd372f0f95abb6686d /drivers/thermal | |
| parent | 8aa4184e0b59d31a961be3e87ec129c2fb50c0ee (diff) | |
thermal: rockchip: Add a new initialize function for rk1808
As clock frequency should be between 500KHz and 800KHz, inter_pd_soc
should be no less than 90us and bandgap chopper function should be
enabled, add a new initialize function to handle the power sequence
for rk1808 SoCs.
Change-Id: Ia1ad81783ccc34bc4218dbbd62f7710ee0773b0a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Diffstat (limited to 'drivers/thermal')
| -rw-r--r-- | drivers/thermal/rockchip_thermal.c | 33 |
1 files changed, 32 insertions, 1 deletions
diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c index 4c930ce06a8b..d5825c09ba6f 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -215,8 +215,11 @@ struct rockchip_thermal_data { #define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* 50ms */ #define TSADCV3_AUTO_PERIOD_TIME 1875 /* 2.5ms */ #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 /* 2.5ms */ +#define TSADCV5_AUTO_PERIOD_TIME 1622 /* 2.5ms */ +#define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */ #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ +#define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */ #define GRF_SARADC_TESTBIT 0x0e644 #define GRF_TSADC_TESTBIT_L 0x0e648 @@ -224,8 +227,11 @@ struct rockchip_thermal_data { #define PX30_GRF_SOC_CON2 0x0408 +#define RK1808_BUS_GRF_SOC_CON0 0x0400 + #define GRF_SARADC_TESTBIT_ON (0x10001 << 2) #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2) +#define GRF_TSADC_BANDGAP_CHOPPER_EN (0x10001 << 2) #define GRF_TSADC_VCM_EN_L (0x10001 << 7) #define GRF_TSADC_VCM_EN_H (0x10001 << 7) @@ -727,6 +733,31 @@ static void rk_tsadcv4_initialize(struct regmap *grf, void __iomem *regs, regmap_write(grf, PX30_GRF_SOC_CON2, GRF_CON_TSADC_CH_INV); } +static void rk_tsadcv5_initialize(struct regmap *grf, void __iomem *regs, + enum tshut_polarity tshut_polarity) +{ + if (tshut_polarity == TSHUT_HIGH_ACTIVE) + writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, + regs + TSADCV2_AUTO_CON); + else + writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, + regs + TSADCV2_AUTO_CON); + + writel_relaxed(TSADCV5_USER_INTER_PD_SOC, regs + TSADCV2_USER_CON); + + writel_relaxed(TSADCV5_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD); + writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, + regs + TSADCV2_HIGHT_INT_DEBOUNCE); + writel_relaxed(TSADCV5_AUTO_PERIOD_HT_TIME, + regs + TSADCV2_AUTO_PERIOD_HT); + writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, + regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); + + if (!IS_ERR(grf)) + regmap_write(grf, RK1808_BUS_GRF_SOC_CON0, + GRF_TSADC_BANDGAP_CHOPPER_EN); +} + static void rk_tsadcv2_irq_ack(void __iomem *regs) { u32 val; @@ -931,7 +962,7 @@ static const struct rockchip_tsadc_chip rk1808_tsadc_data = { .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ .tshut_temp = 95000, - .initialize = rk_tsadcv2_initialize, + .initialize = rk_tsadcv5_initialize, .irq_ack = rk_tsadcv3_irq_ack, .control = rk_tsadcv3_control, .get_temp = rk_tsadcv2_get_temp, |