phy: rockchip-inno-combphy: disable lane 1 for usb3 to save power

The PHY lane 1isn't used for USB 3.0, we can
disable it to reduce power consumption.

I test the 0.8V and 1.8V power consumption for
USB 3.0 mode while the PHY is in P2 state which
controlled by USB 3.0 controller on RK1808-EVB.

Without this patch:
- 0.8V : 35mA
- 1.8V : 56mA

With this patch:
- 0.8V : 16.6mA
- 1.8V : 16.4mA

Change-Id: I24e57faa8a862053c2492fe4e7df9e5de25b757f
Signed-off-by: William Wu <william.wu@rock-chips.com>

1 files changed, 27 insertions, 0 deletions

diff --git a/drivers/phy/rockchip/phy-rockchip-inno-combphy.c b/drivers/phy/rockchip/phy-rockchip-inno-combphy.c
index 4ed7f5d24e0d..40b5df15c1f4 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-combphy.c
@@ -575,6 +575,33 @@ static int rk1808_combphy_cfg(struct rockchip_combphy_priv *priv)
 		writel(0x8b, priv->mmio + 0x21b8);
 		writel(0x8b, priv->mmio + 0x31b8);
 	} else if (priv->phy_type == PHY_TYPE_USB3) {
+		/*
+		 * Disable PHY Lane 1 which isn't needed
+		 * for USB3 to reduce power consumption.
+		 */
+		/* Lane 1 cdr power down */
+		writel(0x09, priv->mmio + 0x3148);
+
+		/* Lane 1 rx bias disable */
+		writel(0x01, priv->mmio + 0x21cc);
+
+		/* Lane 1 cdr disable */
+		writel(0x08, priv->mmio + 0x30c4);
+		writel(0x08, priv->mmio + 0x20f4);
+
+		/* Lane 1 rx lock disable and tx bias disable */
+		writel(0x12, priv->mmio + 0x3150);
+
+		/* Lane 1 rx termination disable */
+		writel(0x00, priv->mmio + 0x3080);
+
+		/* Lane 1 tx termination disable */
+		writel(0x1d, priv->mmio + 0x3090);
+
+		/* Lane 1 tx driver disable */
+		writel(0x50, priv->mmio + 0x21c4);
+		writel(0x10, priv->mmio + 0x2050);
+
 		/* Adjust Lane 0 Rx interface timing */
 		writel(0x20, priv->mmio + 0x20ac);