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authorHu Kejun <william.hu@rock-chips.com>2019-01-22 19:58:36 +0800
committerTao Huang <huangtao@rock-chips.com>2019-02-25 10:33:05 +0800
commite577dc03658686a9e646d6eb5a3ec1c78ed62423 (patch)
tree046a664eb19b2e6791e2c987001f2c039f450fa7 /drivers/media/platform/rockchip
parent312701d21955b4ea9b0e3867c8ec06b39108ded2 (diff)
media: rockchip: isp1: add macro to switch between old mipi and new mipi
Change-Id: I878099d6a38f00a255a7b99ff9f2a3c5770226e5 Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
Diffstat (limited to 'drivers/media/platform/rockchip')
-rw-r--r--drivers/media/platform/rockchip/isp1/capture.c15
-rw-r--r--drivers/media/platform/rockchip/isp1/common.h1
-rw-r--r--drivers/media/platform/rockchip/isp1/dev.c28
-rw-r--r--drivers/media/platform/rockchip/isp1/rkisp1.c95
4 files changed, 128 insertions, 11 deletions
diff --git a/drivers/media/platform/rockchip/isp1/capture.c b/drivers/media/platform/rockchip/isp1/capture.c
index 0f4e9904c141..b8b445a0cfad 100644
--- a/drivers/media/platform/rockchip/isp1/capture.c
+++ b/drivers/media/platform/rockchip/isp1/capture.c
@@ -1223,8 +1223,13 @@ static int rkisp1_start(struct rkisp1_stream *stream)
"stream raw only support to open after stream mp/sp");
return -EINVAL;
}
+
+#if RKISP1_RK3326_USE_OLDMIPI
+ if (dev->isp_ver == ISP_V13)
+#else
if (dev->isp_ver == ISP_V12 ||
dev->isp_ver == ISP_V13)
+#endif
raw_config_mi(stream);
if (stream->ops->set_data_path)
@@ -2000,10 +2005,16 @@ void rkisp1_unregister_stream_vdevs(struct rkisp1_device *dev)
struct rkisp1_stream *raw_stream = &dev->stream[RKISP1_STREAM_RAW];
rkisp1_unregister_stream_vdev(mp_stream);
+
if (dev->isp_ver != ISP_V10_1)
rkisp1_unregister_stream_vdev(sp_stream);
+
+#if RKISP1_RK3326_USE_OLDMIPI
+ if (dev->isp_ver == ISP_V13)
+#else
if (dev->isp_ver == ISP_V12 ||
dev->isp_ver == ISP_V13)
+#endif
rkisp1_unregister_stream_vdev(raw_stream);
}
@@ -2027,8 +2038,12 @@ static int rkisp1_register_stream_vdev(struct rkisp1_stream *stream)
break;
case RKISP1_STREAM_RAW:
vdev_name = RAW_VDEV_NAME;
+#if RKISP1_RK3326_USE_OLDMIPI
+ if (dev->isp_ver != ISP_V13)
+#else
if (dev->isp_ver != ISP_V12 &&
dev->isp_ver != ISP_V13)
+#endif
return 0;
break;
default:
diff --git a/drivers/media/platform/rockchip/isp1/common.h b/drivers/media/platform/rockchip/isp1/common.h
index d2c606461886..7a41e40a8bcb 100644
--- a/drivers/media/platform/rockchip/isp1/common.h
+++ b/drivers/media/platform/rockchip/isp1/common.h
@@ -56,6 +56,7 @@
#define RKISP1_EMDDATA_FIFO_MAX 4
#define RKISP1_DMATX_CHECK 0xA5A5A5A5
+#define RKISP1_RK3326_USE_OLDMIPI 0
enum rkisp1_sd_type {
RKISP1_SD_SENSOR,
diff --git a/drivers/media/platform/rockchip/isp1/dev.c b/drivers/media/platform/rockchip/isp1/dev.c
index 770c2d4de7a3..c576cea609a2 100644
--- a/drivers/media/platform/rockchip/isp1/dev.c
+++ b/drivers/media/platform/rockchip/isp1/dev.c
@@ -358,8 +358,12 @@ static int rkisp1_create_links(struct rkisp1_device *dev)
if (ret < 0)
return ret;
+#if RKISP1_RK3326_USE_OLDMIPI
+ if (dev->isp_ver == ISP_V13) {
+#else
if (dev->isp_ver == ISP_V12 ||
dev->isp_ver == ISP_V13) {
+#endif
/* MIPI RAW links */
source = &dev->isp_sdev.sd.entity;
sink = &dev->stream[RKISP1_STREAM_RAW].vnode.vdev.entity;
@@ -662,8 +666,12 @@ static irqreturn_t rkisp1_mipi_irq_hdl(int irq, void *ctx)
unsigned int mis_val;
unsigned int err1, err2, err3;
+#if RKISP1_RK3326_USE_OLDMIPI
+ if (rkisp1_dev->isp_ver == ISP_V13) {
+#else
if (rkisp1_dev->isp_ver == ISP_V13 ||
rkisp1_dev->isp_ver == ISP_V12) {
+#endif
err1 = readl(rkisp1_dev->base_addr + CIF_ISP_CSI0_ERR1);
err2 = readl(rkisp1_dev->base_addr + CIF_ISP_CSI0_ERR2);
err3 = readl(rkisp1_dev->base_addr + CIF_ISP_CSI0_ERR3);
@@ -676,6 +684,20 @@ static irqreturn_t rkisp1_mipi_irq_hdl(int irq, void *ctx)
mis_val = readl(rkisp1_dev->base_addr + CIF_MIPI_MIS);
if (mis_val)
rkisp1_mipi_isr(mis_val, rkisp1_dev);
+
+ /*
+ * As default interrupt mask for csi_rx are on,
+ * when resetting isp, interrupt from csi_rx maybe arise,
+ * we should clear them.
+ */
+#if RKISP1_RK3326_USE_OLDMIPI
+ if (rkisp1_dev->isp_ver == ISP_V12) {
+ /* read error state register to clear interrupt state */
+ readl(rkisp1_dev->base_addr + CIF_ISP_CSI0_ERR1);
+ readl(rkisp1_dev->base_addr + CIF_ISP_CSI0_ERR2);
+ readl(rkisp1_dev->base_addr + CIF_ISP_CSI0_ERR3);
+ }
+#endif
}
return IRQ_HANDLED;
@@ -1087,6 +1109,12 @@ static int rkisp1_plat_probe(struct platform_device *pdev)
if (ret)
goto err_runtime_disable;
+ if (isp_dev->isp_ver == ISP_V12 || isp_dev->isp_ver == ISP_V13) {
+ writel(0, isp_dev->base_addr + CIF_ISP_CSI0_CTRL0);
+ writel(0, isp_dev->base_addr + CIF_ISP_CSI0_MASK1);
+ writel(0, isp_dev->base_addr + CIF_ISP_CSI0_MASK2);
+ writel(0, isp_dev->base_addr + CIF_ISP_CSI0_MASK3);
+ }
return 0;
err_runtime_disable:
diff --git a/drivers/media/platform/rockchip/isp1/rkisp1.c b/drivers/media/platform/rockchip/isp1/rkisp1.c
index 6b46d229673d..429b9780536f 100644
--- a/drivers/media/platform/rockchip/isp1/rkisp1.c
+++ b/drivers/media/platform/rockchip/isp1/rkisp1.c
@@ -411,11 +411,12 @@ static int rkisp1_config_mipi(struct rkisp1_device *dev)
}
}
+#if RKISP1_RK3326_USE_OLDMIPI
+ if (dev->isp_ver == ISP_V13) {
+#else
if (dev->isp_ver == ISP_V13 ||
dev->isp_ver == ISP_V12) {
- /* csi2host enable */
- writel(1, base + CIF_ISP_CSI0_CTRL0);
-
+#endif
/* lanes */
writel(lanes - 1, base + CIF_ISP_CSI0_CTRL1);
@@ -426,19 +427,36 @@ static int rkisp1_config_mipi(struct rkisp1_device *dev)
writel(CIF_MIPI_DATA_SEL_DT(in_fmt->mipi_dt) | CIF_MIPI_DATA_SEL_VC(0),
base + CIF_ISP_CSI0_DATA_IDS_1);
- /* interrupts */
+ /* clear interrupts state */
+ readl(base + CIF_ISP_CSI0_ERR1);
+ readl(base + CIF_ISP_CSI0_ERR2);
+ readl(base + CIF_ISP_CSI0_ERR3);
+ /* set interrupts mask */
+ writel(0x1FFFFFF0, base + CIF_ISP_CSI0_MASK1);
+ writel(0x03FFFFFF, base + CIF_ISP_CSI0_MASK2);
writel(CIF_ISP_CSI0_IMASK_FRAME_END(0x3F) |
CIF_ISP_CSI0_IMASK_RAW0_OUT_V_END |
CIF_ISP_CSI0_IMASK_RAW1_OUT_V_END |
CIF_ISP_CSI0_IMASK_LINECNT,
base + CIF_ISP_CSI0_MASK3);
-
} else {
mipi_ctrl = CIF_MIPI_CTRL_NUM_LANES(lanes - 1) |
CIF_MIPI_CTRL_SHUTDOWNLANES(0xf) |
CIF_MIPI_CTRL_ERR_SOT_SYNC_HS_SKIP |
CIF_MIPI_CTRL_CLOCKLANE_ENA;
+#if RKISP1_RK3326_USE_OLDMIPI
+ if (dev->isp_ver == ISP_V12) {
+ writel(0, base + CIF_ISP_CSI0_CTRL0);
+ writel(0, base + CIF_ISP_CSI0_MASK1);
+ writel(0, base + CIF_ISP_CSI0_MASK2);
+ writel(0, base + CIF_ISP_CSI0_MASK3);
+ /* clear interrupts state */
+ readl(base + CIF_ISP_CSI0_ERR1);
+ readl(base + CIF_ISP_CSI0_ERR2);
+ readl(base + CIF_ISP_CSI0_ERR3);
+ }
+#endif
writel(mipi_ctrl, base + CIF_MIPI_CTRL);
/* Configure Data Type and Virtual Channel */
@@ -540,16 +558,37 @@ static int rkisp1_isp_stop(struct rkisp1_device *dev)
* Stop ISP(isp) ->wait for ISP isp off
*/
/* stop and clear MI, MIPI, and ISP interrupts */
- writel(0, base + CIF_MIPI_IMSC);
- writel(~0, base + CIF_MIPI_ICR);
+#if RKISP1_RK3326_USE_OLDMIPI
+ if (dev->isp_ver == ISP_V13) {
+#else
+ if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
+#endif
+ writel(0, base + CIF_ISP_CSI0_MASK1);
+ writel(0, base + CIF_ISP_CSI0_MASK2);
+ writel(0, base + CIF_ISP_CSI0_MASK3);
+ readl(base + CIF_ISP_CSI0_ERR1);
+ readl(base + CIF_ISP_CSI0_ERR2);
+ readl(base + CIF_ISP_CSI0_ERR3);
+ } else {
+ writel(0, base + CIF_MIPI_IMSC);
+ writel(~0, base + CIF_MIPI_ICR);
+ }
writel(0, base + CIF_ISP_IMSC);
writel(~0, base + CIF_ISP_ICR);
writel(0, base + CIF_MI_IMSC);
writel(~0, base + CIF_MI_ICR);
- val = readl(base + CIF_MIPI_CTRL);
- writel(val & (~CIF_MIPI_CTRL_OUTPUT_ENA), base + CIF_MIPI_CTRL);
+#if RKISP1_RK3326_USE_OLDMIPI
+ if (dev->isp_ver == ISP_V13) {
+#else
+ if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
+#endif
+ writel(0, base + CIF_ISP_CSI0_CTRL0);
+ } else {
+ val = readl(base + CIF_MIPI_CTRL);
+ writel(val & (~CIF_MIPI_CTRL_OUTPUT_ENA), base + CIF_MIPI_CTRL);
+ }
/* stop ISP */
val = readl(base + CIF_ISP_CTRL);
val &= ~(CIF_ISP_CTRL_ISP_INFORM_ENABLE | CIF_ISP_CTRL_ISP_ENABLE);
@@ -569,6 +608,13 @@ static int rkisp1_isp_stop(struct rkisp1_device *dev)
readl(base + CIF_MIPI_CTRL));
writel(CIF_IRCL_CIF_SW_RST, base + CIF_IRCL);
+ if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
+ writel(0, base + CIF_ISP_CSI0_CSI2_RESETN);
+ writel(0, base + CIF_ISP_CSI0_CTRL0);
+ writel(0, base + CIF_ISP_CSI0_MASK1);
+ writel(0, base + CIF_ISP_CSI0_MASK2);
+ writel(0, base + CIF_ISP_CSI0_MASK3);
+ }
if (dev->emd_vc <= CIF_ISP_ADD_DATA_VC_MAX) {
for (i = 0; i < RKISP1_EMDDATA_FIFO_MAX; i++)
@@ -598,8 +644,22 @@ static int rkisp1_isp_start(struct rkisp1_device *dev)
/* Activate MIPI */
if (sensor->mbus.type == V4L2_MBUS_CSI2) {
- val = readl(base + CIF_MIPI_CTRL);
- writel(val | CIF_MIPI_CTRL_OUTPUT_ENA, base + CIF_MIPI_CTRL);
+#if RKISP1_RK3326_USE_OLDMIPI
+ if (dev->isp_ver == ISP_V13) {
+#else
+ if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
+#endif
+ /* clear interrupts state */
+ readl(base + CIF_ISP_CSI0_ERR1);
+ readl(base + CIF_ISP_CSI0_ERR2);
+ readl(base + CIF_ISP_CSI0_ERR3);
+ /* csi2host enable */
+ writel(1, base + CIF_ISP_CSI0_CTRL0);
+ } else {
+ val = readl(base + CIF_MIPI_CTRL);
+ writel(val | CIF_MIPI_CTRL_OUTPUT_ENA,
+ base + CIF_MIPI_CTRL);
+ }
}
/* Activate ISP */
val = readl(base + CIF_ISP_CTRL);
@@ -633,7 +693,11 @@ static void rkisp1_config_clk(struct rkisp1_device *dev)
writel(val, dev->base_addr + CIF_ICCL);
+#if RKISP1_RK3326_USE_OLDMIPI
+ if (dev->isp_ver == ISP_V13) {
+#else
if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
+#endif
val = CIF_CLK_CTRL_MI_Y12 | CIF_CLK_CTRL_MI_SP |
CIF_CLK_CTRL_MI_RAW0 | CIF_CLK_CTRL_MI_RAW1 |
CIF_CLK_CTRL_MI_READ | CIF_CLK_CTRL_MI_RAWRD |
@@ -1205,6 +1269,7 @@ static int rkisp1_isp_sd_s_stream(struct v4l2_subdev *sd, int on)
static int rkisp1_isp_sd_s_power(struct v4l2_subdev *sd, int on)
{
struct rkisp1_device *isp_dev = sd_to_isp_dev(sd);
+ void __iomem *base = isp_dev->base_addr;
int ret;
v4l2_dbg(1, rkisp1_debug, &isp_dev->v4l2_dev, "s_power: %d\n", on);
@@ -1215,6 +1280,14 @@ static int rkisp1_isp_sd_s_power(struct v4l2_subdev *sd, int on)
return ret;
rkisp1_config_clk(isp_dev);
+ if (isp_dev->isp_ver == ISP_V12 ||
+ isp_dev->isp_ver == ISP_V13) {
+ /* disable csi_rx interrupt */
+ writel(0, base + CIF_ISP_CSI0_CTRL0);
+ writel(0, base + CIF_ISP_CSI0_MASK1);
+ writel(0, base + CIF_ISP_CSI0_MASK2);
+ writel(0, base + CIF_ISP_CSI0_MASK3);
+ }
} else {
ret = pm_runtime_put(isp_dev->dev);
if (ret < 0)