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authorTang Yun ping <typ@rock-chips.com>2015-08-21 17:14:10 +0800
committerTang Yun ping <typ@rock-chips.com>2015-08-25 11:05:11 +0800
commite0f1b4b3f45d84eb9e25ad0acedb93600ff5add6 (patch)
tree809060ab6ef0d941f027e3796405b14becf6237f /drivers/mailbox
parent7643ffa0e67d57b067c778b95b0c8cd1e69f3f1d (diff)
RK3368 DDR: new ddr change freq method
Using fiq to notify trust to stop cpu when ddr changing freq. 1.bl30 must update to rk3368bl30_v2.10.bin and bl31 must update to rk3368bl31_v1.5.bin. 2.Insure kernel commit 7643ffa0e67d5 and cc6e554e54fe1 were merged. Change-Id: I2449613221c49a49ba14dab54e77714e961dcd16 Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Diffstat (limited to 'drivers/mailbox')
-rw-r--r--drivers/mailbox/scpi_protocol.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/mailbox/scpi_protocol.c b/drivers/mailbox/scpi_protocol.c
index 673437a5deea..efcc92721c20 100644
--- a/drivers/mailbox/scpi_protocol.c
+++ b/drivers/mailbox/scpi_protocol.c
@@ -492,7 +492,7 @@ int scpi_sys_set_mcu_state_resume(void)
}
EXPORT_SYMBOL_GPL(scpi_sys_set_mcu_state_resume);
-int scpi_ddr_init(u32 dram_speed_bin, u32 freq, u32 lcdc_type)
+int scpi_ddr_init(u32 dram_speed_bin, u32 freq, u32 lcdc_type, u32 addr_mcu_el3)
{
struct scpi_data_buf sdata;
struct rockchip_mbox_msg mdata;
@@ -500,6 +500,7 @@ int scpi_ddr_init(u32 dram_speed_bin, u32 freq, u32 lcdc_type)
u32 dram_speed_bin;
u32 freq;
u32 lcdc_type;
+ u32 addr_mcu_el3;
} tx_buf;
struct __packed2 {
u32 status;
@@ -508,7 +509,7 @@ int scpi_ddr_init(u32 dram_speed_bin, u32 freq, u32 lcdc_type)
tx_buf.dram_speed_bin = (u32)dram_speed_bin;
tx_buf.freq = (u32)freq;
tx_buf.lcdc_type = (u32)lcdc_type;
-
+ tx_buf.addr_mcu_el3 = addr_mcu_el3;
SCPI_SETUP_DBUF(sdata, mdata, SCPI_CL_DDR,
SCPI_DDR_INIT, tx_buf, rx_buf);
return scpi_execute_cmd(&sdata);