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authorLiang Chen <cl@rock-chips.com>2018-03-15 15:07:21 +0800
committerTao Huang <huangtao@rock-chips.com>2018-03-16 17:49:29 +0800
commitf31ed416e5064502d7538e6e223a4012de36ffab (patch)
tree121cc0516d57a10c2c658060e5f0a5ec14986ab4 /drivers/clk
parent5790f6182b4ca2411e71f46b063125b8542484b6 (diff)
soc: rockchip: add support for adjust opp-table by board IR-Drop
The IR-Drop is always different between different boards, so we need know the IR-Drop to adjust opp-table to guarantee stably for the board. Change-Id: I8ad05d30e15a7e62910a952cc6fa199d70129660 Signed-off-by: Liang Chen <cl@rock-chips.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/rockchip/clk-pll.c25
-rw-r--r--drivers/clk/rockchip/clk.h1
2 files changed, 26 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 56be4249d6c1..3d6a241bca8b 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -103,6 +103,31 @@ int rockchip_pll_clk_adaptive_scaling(struct clk *clk, int sel)
return 0;
}
+int rockchip_pll_clk_adaptive_rate(struct clk *clk, unsigned long rate)
+{
+ const struct rockchip_pll_rate_table *rate_table;
+ struct clk *parent = clk_get_parent(clk);
+ struct rockchip_clk_pll *pll;
+ int i;
+
+ if (IS_ERR_OR_NULL(parent))
+ return -EINVAL;
+
+ pll = to_rockchip_clk_pll(__clk_get_hw(parent));
+ if (!pll)
+ return -EINVAL;
+
+ rate_table = pll->rate_table;
+ for (i = 0; i < pll->rate_count; i++) {
+ if (rate >= rate_table[i].rate) {
+ pll->sel = i;
+ break;
+ }
+ }
+
+ return 0;
+}
+
static struct rockchip_pll_rate_table *rk_pll_rate_table_get(void)
{
return &auto_table;
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 420b5f846e80..a423dc080e2f 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -756,6 +756,7 @@ void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
int nrates);
void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
int rockchip_pll_clk_adaptive_scaling(struct clk *clk, int sel);
+int rockchip_pll_clk_adaptive_rate(struct clk *clk, unsigned long rate);
void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
unsigned int reg, void (*cb)(void));