diff options
| author | Elaine Zhang <zhangqing@rock-chips.com> | 2018-10-09 11:53:44 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-10-09 14:59:04 +0800 |
| commit | 1c450a80824496dc9cf23c79044267fc53ee5706 (patch) | |
| tree | e25506daf5238c68dbcef1bf1155c055baade622 /drivers/clk | |
| parent | c7f27e053c9f8b4094bac7786ef25920c96a8c55 (diff) | |
clk: rockchip: rk1808: rename SCLK_GPIO to DBCLK_GPIO
Change-Id: I1ed6fe175fb2e640a7a61e1a2e799e94e76b435f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk1808.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/clk/rockchip/clk-rk1808.c b/drivers/clk/rockchip/clk-rk1808.c index ca64588a2bf0..7d27b5fb313f 100644 --- a/drivers/clk/rockchip/clk-rk1808.c +++ b/drivers/clk/rockchip/clk-rk1808.c @@ -940,16 +940,16 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = { RK1808_CLKSEL_CON(64), 14, 2, MFLAGS, 8, 6, DFLAGS, RK1808_CLKGATE_CON(14), 1, GFLAGS), - COMPOSITE(SCLK_GPIO1, "dbclk_gpio1", mux_xin24m_32k_p, 0, + COMPOSITE(DBCLK_GPIO1, "dbclk_gpio1", mux_xin24m_32k_p, 0, RK1808_CLKSEL_CON(65), 15, 1, MFLAGS, 0, 11, DFLAGS, RK1808_CLKGATE_CON(14), 2, GFLAGS), - COMPOSITE(SCLK_GPIO2, "dbclk_gpio2", mux_xin24m_32k_p, 0, + COMPOSITE(DBCLK_GPIO2, "dbclk_gpio2", mux_xin24m_32k_p, 0, RK1808_CLKSEL_CON(66), 15, 1, MFLAGS, 0, 11, DFLAGS, RK1808_CLKGATE_CON(14), 3, GFLAGS), - COMPOSITE(SCLK_GPIO3, "dbclk_gpio3", mux_xin24m_32k_p, 0, + COMPOSITE(DBCLK_GPIO3, "dbclk_gpio3", mux_xin24m_32k_p, 0, RK1808_CLKSEL_CON(67), 15, 1, MFLAGS, 0, 11, DFLAGS, RK1808_CLKGATE_CON(14), 4, GFLAGS), - COMPOSITE(SCLK_GPIO4, "dbclk_gpio4", mux_xin24m_32k_p, 0, + COMPOSITE(DBCLK_GPIO4, "dbclk_gpio4", mux_xin24m_32k_p, 0, RK1808_CLKSEL_CON(68), 15, 1, MFLAGS, 0, 11, DFLAGS, RK1808_CLKGATE_CON(14), 5, GFLAGS), @@ -1102,7 +1102,7 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = { RK1808_PMU_CLKSEL_CON(7), 15, 1, MFLAGS, 8, 7, DFLAGS, RK1808_PMU_CLKGATE_CON(1), 5, GFLAGS), - COMPOSITE(SCLK_PMU_GPIO0, "dbclk_gpio0", mux_xin24m_32k_p, 0, + COMPOSITE(DBCLK_PMU_GPIO0, "dbclk_gpio0", mux_xin24m_32k_p, 0, RK1808_PMU_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 11, DFLAGS, RK1808_PMU_CLKGATE_CON(1), 6, GFLAGS), |