clk: rockchip: Separate boost address from cru

Change-Id: I3e632b7f6769568ade18aad2fa000bc3f6ff8c2f
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

4 files changed, 58 insertions, 55 deletions

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 16b3eef50554..0818ed89e70e 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -359,54 +359,60 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
 void rockchip_boost_enable_recovery_sw_low(struct clk_hw *hw)
 {
 	struct rockchip_clk_pll *pll;
-	int ret;
+	struct regmap *boost;
+	unsigned int val;
 
 	if (!hw)
 		return;
 	pll = to_rockchip_clk_pll(hw);
+	if (!pll->boost_enabled || IS_ERR(pll->ctx->boost))
+		return;
 
-	if (pll->type == pll_px30) {
-		writel_relaxed(HIWORD_UPDATE(1, PX30_BOOST_RECOVERY_MASK,
-					     PX30_BOOST_RECOVERY_SHIFT),
-			       pll->reg_base + PX30_BOOST_BOOST_CON);
-		do {
-			ret = readl_relaxed(pll->reg_base +
-					    PX30_BOOST_FSM_STATUS);
-		} while (!(ret & PX30_BOOST_BUSY_STATE));
-
-		writel_relaxed(HIWORD_UPDATE(1, PX30_BOOST_SW_CTRL_MASK,
-					     PX30_BOOST_SW_CTRL_SHIFT) |
-			       HIWORD_UPDATE(1, PX30_BOOST_LOW_FREQ_EN_MASK,
-					     PX30_BOOST_LOW_FREQ_EN_SHIFT),
-			       pll->reg_base + PX30_BOOST_BOOST_CON);
-	}
+	boost = pll->ctx->boost;
+	regmap_write(boost, BOOST_BOOST_CON,
+		     HIWORD_UPDATE(1, BOOST_RECOVERY_MASK,
+				   BOOST_RECOVERY_SHIFT));
+	do {
+		regmap_read(boost, BOOST_FSM_STATUS, &val);
+	} while (!(val & BOOST_BUSY_STATE));
+
+	regmap_write(boost, BOOST_BOOST_CON,
+		     HIWORD_UPDATE(1, BOOST_SW_CTRL_MASK,
+				   BOOST_SW_CTRL_SHIFT) |
+		     HIWORD_UPDATE(1, BOOST_LOW_FREQ_EN_MASK,
+				   BOOST_LOW_FREQ_EN_SHIFT));
 }
 
 void rockchip_boost_disable_low(struct rockchip_clk_pll *pll)
 {
-	if (pll->type == pll_px30) {
-		writel_relaxed(HIWORD_UPDATE(0, PX30_BOOST_LOW_FREQ_EN_MASK,
-					     PX30_BOOST_LOW_FREQ_EN_SHIFT),
-			       pll->reg_base + PX30_BOOST_BOOST_CON);
-	}
+	struct regmap *boost = pll->ctx->boost;
+
+	if (!pll->boost_enabled || IS_ERR(boost))
+		return;
+
+	regmap_write(boost, BOOST_BOOST_CON,
+		     HIWORD_UPDATE(0, BOOST_LOW_FREQ_EN_MASK,
+				   BOOST_LOW_FREQ_EN_SHIFT));
 }
 
 void rockchip_boost_disable_recovery_sw(struct clk_hw *hw)
 {
 	struct rockchip_clk_pll *pll;
+	struct regmap *boost;
 
 	if (!hw)
 		return;
 	pll = to_rockchip_clk_pll(hw);
+	if (!pll->boost_enabled || IS_ERR(pll->ctx->boost))
+		return;
 
-	if (pll->type == pll_px30) {
-		writel_relaxed(HIWORD_UPDATE(0, PX30_BOOST_RECOVERY_MASK,
-					     PX30_BOOST_RECOVERY_SHIFT),
-			       pll->reg_base + PX30_BOOST_BOOST_CON);
-		writel_relaxed(HIWORD_UPDATE(0, PX30_BOOST_SW_CTRL_MASK,
-					     PX30_BOOST_SW_CTRL_SHIFT),
-			       pll->reg_base + PX30_BOOST_BOOST_CON);
-	}
+	boost = pll->ctx->boost;
+	regmap_write(boost, BOOST_BOOST_CON,
+		     HIWORD_UPDATE(0, BOOST_RECOVERY_MASK,
+				   BOOST_RECOVERY_SHIFT));
+	regmap_write(boost, BOOST_BOOST_CON,
+		     HIWORD_UPDATE(0, BOOST_SW_CTRL_MASK,
+				   BOOST_SW_CTRL_SHIFT));
 }
 
 /**
diff --git a/drivers/clk/rockchip/clk-px30.c b/drivers/clk/rockchip/clk-px30.c
index 0487657a1e7a..ed35e3ea2aea 100644
--- a/drivers/clk/rockchip/clk-px30.c
+++ b/drivers/clk/rockchip/clk-px30.c
@@ -186,7 +186,7 @@ PNAME(mux_usbphy_ref_p)		= { "xin24m", "clk_ref24m_pmu" };
 PNAME(mux_mipidsiphy_ref_p)	= { "xin24m", "clk_ref24m_pmu" };
 
 static struct rockchip_pll_clock px30_pll_clks[] __initdata = {
-	[apll] = PLL(pll_px30, PLL_APLL, "apll", mux_pll_p,
+	[apll] = PLL_BOOST(pll_rk3036, PLL_APLL, "apll", mux_pll_p,
 		     0, PX30_PLL_CON(0),
 		     PX30_MODE_CON, 0, 0, 0, px30_pll_rates),
 	[dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p,
@@ -198,12 +198,6 @@ static struct rockchip_pll_clock px30_pll_clks[] __initdata = {
 	[npll] = PLL(pll_rk3036, PLL_NPLL, "npll", mux_pll_p,
 		     0, PX30_PLL_CON(24),
 		     PX30_MODE_CON, 6, 4, 0, px30_pll_rates),
-	[apll_b_h] = PLL(pll_rk3036, APLL_BOOST_H, "apll_b_h", mux_pll_p,
-		     0, PX30_BOOST_PLL_H_CON(0),
-		     PX30_MODE_CON, 0, 0, 0, px30_pll_rates),
-	[apll_b_l] = PLL(pll_rk3036, APLL_BOOST_L, "apll_b_l", mux_pll_p,
-		     0, PX30_BOOST_PLL_L_CON(0),
-		     PX30_MODE_CON, 0, 0, 0, px30_pll_rates),
 };
 
 static struct rockchip_pll_clock px30_pmu_pll_clks[] __initdata = {
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index f26c77c40631..981264fb8200 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -402,6 +402,8 @@ struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
 	spin_lock_init(&ctx->lock);
 	ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
 						   "rockchip,grf");
+	ctx->boost = syscon_regmap_lookup_by_phandle(ctx->cru_node,
+						   "rockchip,boost");
 
 	return ctx;
 
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 6ad4253c5da1..862e405a6275 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -34,6 +34,25 @@ struct clk;
 #define HIWORD_UPDATE(val, mask, shift) \
 		((val) << (shift) | (mask) << ((shift) + 16))
 
+#define BOOST_PLL_H_CON(x)		((x) * 0x4)
+#define BOOST_CLK_CON			0x0008
+#define BOOST_BOOST_CON			0x000c
+#define BOOST_SWITCH_CNT		0x0010
+#define BOOST_HIGH_PERF_CNT0		0x0014
+#define BOOST_HIGH_PERF_CNT1		0x0018
+#define BOOST_STATIS_THRESHOLD		0x001c
+#define BOOST_SHORT_SWITCH_CNT		0x0020
+#define BOOST_SWITCH_THRESHOLD		0x0024
+#define BOOST_FSM_STATUS		0x0028
+#define BOOST_PLL_L_CON(x)		((x) * 0x4 + 0x2c)
+#define BOOST_RECOVERY_MASK		0x1
+#define BOOST_RECOVERY_SHIFT		1
+#define BOOST_SW_CTRL_MASK		0x1
+#define BOOST_SW_CTRL_SHIFT		2
+#define BOOST_LOW_FREQ_EN_MASK		0x1
+#define BOOST_LOW_FREQ_EN_SHIFT		3
+#define BOOST_BUSY_STATE		BIT(8)
+
 #define PX30_PLL_CON(x)			((x) * 0x4)
 #define PX30_CLKSEL_CON(x)		((x) * 0x4 + 0x100)
 #define PX30_CLKGATE_CON(x)		((x) * 0x4 + 0x200)
@@ -54,25 +73,6 @@ struct clk;
 #define PX30_PMU_CLKGATE_CON(x)		((x) * 0x4 + 0x80)
 #define PX30_PMU_MODE			0x0020
 
-#define PX30_BOOST_PLL_H_CON(x)		((x) * 0x4 + 0x8000)
-#define PX30_BOOST_CLK_CON		0x8008
-#define PX30_BOOST_BOOST_CON		0x800c
-#define PX30_BOOST_SWITCH_CNT		0x8010
-#define PX30_BOOST_HIGH_PERF_CNT0	0x8014
-#define PX30_BOOST_HIGH_PERF_CNT1	0x8018
-#define PX30_BOOST_STATIS_THRESHOLD	0x801c
-#define PX30_BOOST_SHORT_SWITCH_CNT	0x8020
-#define PX30_BOOST_SWITCH_THRESHOLD	0x8024
-#define PX30_BOOST_FSM_STATUS		0x8028
-#define PX30_BOOST_PLL_L_CON(x)		((x) * 0x4 + 0x802c)
-#define PX30_BOOST_RECOVERY_MASK	0x1
-#define PX30_BOOST_RECOVERY_SHIFT	1
-#define PX30_BOOST_SW_CTRL_MASK		0x1
-#define PX30_BOOST_SW_CTRL_SHIFT	2
-#define PX30_BOOST_LOW_FREQ_EN_MASK	0x1
-#define PX30_BOOST_LOW_FREQ_EN_SHIFT	3
-#define PX30_BOOST_BUSY_STATE		BIT(8)
-
 /* register positions shared by RK2928, RK3036, RK3066, RK3188 and RK3228 */
 #define RK2928_PLL_CON(x)		((x) * 0x4)
 #define RK2928_MODE_CON		0x40
@@ -237,6 +237,7 @@ struct rockchip_clk_provider {
 	struct clk_onecell_data clk_data;
 	struct device_node *cru_node;
 	struct regmap *grf;
+	struct regmap *boost;
 	spinlock_t lock;
 };