diff options
| author | Elaine Zhang <zhangqing@rock-chips.com> | 2018-10-19 16:03:06 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-10-22 11:09:26 +0800 |
| commit | 739318806434020dd1b7fbc90f5eaecff01c4268 (patch) | |
| tree | d10050447df6db8179cc45ff646529d4a4571fc2 /drivers/clk/rockchip | |
| parent | 4202ab5440c9a1930e311bb8b792cad7813efafd (diff) | |
clk: rockchip: rk1808: remove the apll from parents clk for npu
apll is always change,
not allowed apll as npu parent clk.
Change-Id: Ia354b7ac533c2c7537d2d25894f956b855db9bc6
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk1808.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/rockchip/clk-rk1808.c b/drivers/clk/rockchip/clk-rk1808.c index 50a26d4097d3..107149c57389 100644 --- a/drivers/clk/rockchip/clk-rk1808.c +++ b/drivers/clk/rockchip/clk-rk1808.c @@ -334,9 +334,9 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = { /* * Clock-Architecture Diagram 4 */ - COMPOSITE_NOGATE(0, "clk_npu_div", mux_gpll_cpll_apll_p, 0, + COMPOSITE_NOGATE(0, "clk_npu_div", mux_gpll_cpll_p, CLK_KEEP_REQ_RATE, RK1808_CLKSEL_CON(1), 8, 2, MFLAGS, 0, 4, DFLAGS), - COMPOSITE_NOGATE_HALFDIV(0, "clk_npu_np5", mux_gpll_cpll_apll_p, 0, + COMPOSITE_NOGATE_HALFDIV(0, "clk_npu_np5", mux_gpll_cpll_p, CLK_KEEP_REQ_RATE, RK1808_CLKSEL_CON(1), 10, 2, MFLAGS, 4, 4, DFLAGS), MUX(0, "clk_npu_pre", mux_npu_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(1), 15, 1, MFLAGS), |