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authorChen Lei <lei.chen@rock-chips.com>2018-12-25 18:29:04 +0800
committerTao Huang <huangtao@rock-chips.com>2018-12-26 18:38:02 +0800
commit6aacd99ecf717fb2a020f503bc8ffc3fd67facc7 (patch)
tree6533215feb402a18556ba958017ccaa54224b4be /drivers/clk/rockchip
parenta1ed5f4f104df70788849cd274544ad88c27ffe6 (diff)
clk: rockchip: rk322x: fix wrong mmc phase shift for rk3228
mmc sample shift should be 1 for rk3228, or it will fail if we enable mmc tuning for rk3228. Change-Id: I301c2a7d33de8d519d7c288aef03a82531016373 Signed-off-by: Chen Lei <lei.chen@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip')
-rw-r--r--drivers/clk/rockchip/clk-rk3228.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
index eb7dd7406944..b9948dfd43d0 100644
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -629,13 +629,13 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
/* PD_MMC */
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
- MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 0),
+ MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 1),
MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3228_SDIO_CON0, 1),
- MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 0),
+ MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 1),
MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3228_EMMC_CON0, 1),
- MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 0),
+ MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 1),
};
static const char *const rk3228_critical_clocks[] __initconst = {