diff options
| author | Xing Zheng <zhengxing@rock-chips.com> | 2016-10-21 12:03:40 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-07-25 14:43:59 +0800 |
| commit | 49d2f9f2a7fdaedf4b213a553e0db888b83324f6 (patch) | |
| tree | f1573697548b29e8f4a5c1e2f855784ec0d25304 /drivers/clk/rockchip | |
| parent | 25c7cb783d96434dea91af8a12da1b6becb7c291 (diff) | |
UPSTREAM: clk: rockchip: add 533.25MHz to rk3399 clock rates table
We need to get the accurate 533.25MHz for the DP display.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 5c1c63f6345b9e1600875f3122166c0af434158e)
Change-Id: Ib945c80451d52081683488fe410c5200622fb1c3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3399.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index 40855164622c..6aabccb6cc24 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -94,6 +94,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = { RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0), RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0), + RK3036_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0), RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), |