diff options
| author | Tao Huang <huangtao@rock-chips.com> | 2018-10-06 16:46:46 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-10-06 16:48:58 +0800 |
| commit | 3e9d3367b9300edfdd022026627510de5700e50b (patch) | |
| tree | f5995e2872619943f7a493f0f0ff3bd29b8e9d2b /drivers/clk/rockchip | |
| parent | fefd0db56d2458886a43765bda59256b36e64c59 (diff) | |
clk: rockchip: rk1808: fix PMU_CRU offset
from 0x4000 to 0xc000
Change-Id: I32f8eb124c3c0621f5001473529bbae418789309
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip')
| -rw-r--r-- | drivers/clk/rockchip/clk.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 3056082c37ba..61d7a5aedcfd 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -107,10 +107,10 @@ struct clk; #define RK1808_EMMC_CON0 0x390 #define RK1808_EMMC_CON1 0x394 -#define RK1808_PMU_PLL_CON(x) ((x) * 0x4 + 0x4000) -#define RK1808_PMU_MODE_CON 0x4020 -#define RK1808_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x4040) -#define RK1808_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x4080) +#define RK1808_PMU_PLL_CON(x) ((x) * 0x4 + 0xc000) +#define RK1808_PMU_MODE_CON 0xc020 +#define RK1808_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0xc040) +#define RK1808_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0xc080) #define RK2928_PLL_CON(x) ((x) * 0x4) #define RK2928_MODE_CON 0x40 |