diff options
| author | huang lin <hl@rock-chips.com> | 2016-08-22 11:36:17 +0800 |
|---|---|---|
| committer | Jianqun Xu <jay.xu@rock-chips.com> | 2016-08-25 19:04:37 +0800 |
| commit | 00fed37569b977b313ca2064d5c293f040ac90ab (patch) | |
| tree | 6004bbb0c4bd2b59c406772a299fe506d23cb8b9 /drivers/clk/rockchip/clk.h | |
| parent | 8f8121632183f20bd6002961c361d2448198a03b (diff) | |
FROMLIST: clk: rockchip: add new clock-type for the ddrclk
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Change-Id: I9e15dd9e01ab1c51a639a6a59391cd5e0de383b7
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip/clk.h')
| -rw-r--r-- | drivers/clk/rockchip/clk.h | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 12616a788172..a2867bb79bc2 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -285,6 +285,22 @@ struct clk *rockchip_clk_register_mmc(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *reg, int shift); +/* + * for COMPOSITE_DDRCLK div_flag, + * there may have serval ways to set ddr clock, use + * this flag to distinguish them. + * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate. + */ +#define ROCKCHIP_DDRCLK_SIP 0x01 + +struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, + const char *const *parent_names, + u8 num_parents, int mux_offset, + int mux_shift, int mux_width, + int div_shift, int div_width, + int ddr_flags, void __iomem *reg_base, + spinlock_t *lock); + #define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0) struct clk *rockchip_clk_register_inverter(const char *name, @@ -303,6 +319,7 @@ enum rockchip_clk_branch_type { branch_mmc, branch_inverter, branch_factor, + branch_ddrc, }; struct rockchip_clk_branch { @@ -492,6 +509,24 @@ struct rockchip_clk_branch { .child = ch, \ } +#define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw, \ + ds, dw, df) \ + { \ + .id = _id, \ + .branch_type = branch_ddrc, \ + .name = cname, \ + .parent_names = pnames, \ + .num_parents = ARRAY_SIZE(pnames), \ + .flags = f, \ + .muxdiv_offset = mo, \ + .mux_shift = ms, \ + .mux_width = mw, \ + .div_shift = ds, \ + .div_width = dw, \ + .div_flags = df, \ + .gate_offset = -1, \ + } + #define MUX(_id, cname, pnames, f, o, s, w, mf) \ { \ .id = _id, \ |