summaryrefslogtreecommitdiff
path: root/drivers/clk/rockchip/clk.c
diff options
context:
space:
mode:
authorElaine Zhang <zhangqing@rock-chips.com>2019-03-07 14:46:17 +0800
committerTao Huang <huangtao@rock-chips.com>2019-03-08 17:37:05 +0800
commitda355404b3ddfb9be352d62f67a22ad408db4ef4 (patch)
treecd70ce591606240a51f41fd744511d00f0da6c02 /drivers/clk/rockchip/clk.c
parent1deb7f8c26f1a330dd948215a2d412542e533720 (diff)
clk: rockchip: add a clock-type for muxes based in the pmugrf
Rockchip socs often have some tiny number of muxes not controlled from the core clock controller but through bits set in the pmugrf. Use MUXPMUGRF() to cover this special clock-type. Change-Id: Iac962a27a3c88ce188d03c416cb4b3b45a462c0a Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip/clk.c')
-rw-r--r--drivers/clk/rockchip/clk.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index a2cf1d39e450..d5e130263c05 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -421,9 +421,12 @@ struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
ctx->clk_data.clk_num = nr_clks;
ctx->cru_node = np;
ctx->grf = ERR_PTR(-EPROBE_DEFER);
+ ctx->pmugrf = ERR_PTR(-EPROBE_DEFER);
spin_lock_init(&ctx->lock);
ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
"rockchip,grf");
+ ctx->pmugrf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
+ "rockchip,pmugrf");
return ctx;
@@ -506,6 +509,13 @@ void __init rockchip_clk_register_branches(
list->mux_shift, list->mux_width,
list->mux_flags);
break;
+ case branch_muxpmugrf:
+ clk = rockchip_clk_register_muxgrf(list->name,
+ list->parent_names, list->num_parents,
+ flags, ctx->pmugrf, list->muxdiv_offset,
+ list->mux_shift, list->mux_width,
+ list->mux_flags);
+ break;
case branch_divider:
if (list->div_table)
clk = clk_register_divider_table(NULL,