diff options
author | Elaine Zhang <zhangqing@rock-chips.com> | 2018-05-23 10:51:30 +0800 |
---|---|---|
committer | Tao Huang <huangtao@rock-chips.com> | 2018-06-15 09:41:09 +0800 |
commit | cd4d3065afbf38411762e2a5f65b751b5594b351 (patch) | |
tree | ea77df5074cbadf1d2b3cee934a492fb6008c2a7 /drivers/clk/rockchip/clk.c | |
parent | e6dda0b9d970f06f9e7b54c4a7d6fedefa13cb1c (diff) |
clk: rockchip: add support for half divider
The new Rockchip socs have optional half divider,
so we use "branch_half_divider" + "COMPOSITE_NOMUX_HALFDIV \
DIV_HALF \ COMPOSITE_HALFDIV \ CMPOSITE_NOGATE_HALFDIV"
to hook that special divider clock-type into our clock-tree.
Change-Id: I79e3f0e8265ccb6a9839cd83a7a3ee0ca825a020
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip/clk.c')
-rw-r--r-- | drivers/clk/rockchip/clk.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index a1c25a4f61ae..9fbcc8bc861b 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -515,6 +515,16 @@ void __init rockchip_clk_register_branches( list->gate_flags, flags, list->child, list->max_prate, &ctx->lock); break; + case branch_half_divider: + clk = rockchip_clk_register_halfdiv(list->name, + list->parent_names, list->num_parents, + ctx->reg_base, list->muxdiv_offset, + list->mux_shift, list->mux_width, + list->mux_flags, list->div_shift, + list->div_width, list->div_flags, + list->gate_offset, list->gate_shift, + list->gate_flags, flags, &ctx->lock); + break; case branch_gate: flags |= CLK_SET_RATE_PARENT; |