diff options
| author | Alexandru M Stan <amstan@chromium.org> | 2014-11-26 17:30:27 -0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2014-11-28 00:44:24 +0100 |
| commit | 89bf26cbc1a09476c4c4740d16a0ffdfa2192b9c (patch) | |
| tree | 954a8753ce27fbd5ee9b0cc9fe4adeaa4d9d15bc /drivers/clk/rockchip/clk.c | |
| parent | c1c9f2cced4e3ba22b3fc25603dd3bd2ec7dc173 (diff) | |
clk: rockchip: Add support for the mmc clock phases using the framework
This patch adds the 2 physical clocks for the mmc (drive and sample). They're
mostly there for the phase properties, but they also show the true clock
(by dividing by RK3288_MMC_CLKGEN_DIV).
The drive and sample phases are generated by dividing an upstream parent clock
by 2, this allows us to adjust the phase by 90 deg.
There's also an option to have up to 255 delay elements (40-80 picoseconds long).
This driver uses those elements (under the assumption that they're 60 ps long)
to generate approximate 22.5 degrees options. 67.5 (22.5*3) might be as high as
90 deg if the delay elements are as big as 80 ps, so a finer division (smaller
than 22.5) was not picked because the phase might not be monotonic anymore.
Suggested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk.c')
| -rw-r--r-- | drivers/clk/rockchip/clk.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 3b8f26e2cd1a..f6150da97e8b 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -271,6 +271,14 @@ void __init rockchip_clk_register_branches( list->gate_offset, list->gate_shift, list->gate_flags, flags, &clk_lock); break; + case branch_mmc: + clk = rockchip_clk_register_mmc( + list->name, + list->parent_names, list->num_parents, + reg_base + list->muxdiv_offset, + list->div_shift + ); + break; } /* none of the cases above matched */ |