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authorElaine Zhang <zhangqing@rock-chips.com>2018-05-28 16:56:50 +0800
committerTao Huang <huangtao@rock-chips.com>2018-05-29 19:54:32 +0800
commit88ec34820f793bc1026aac2c35e41a23f71a2957 (patch)
tree6614455368fe34433d46ad6cee60f68f7f084be7 /drivers/clk/rockchip/clk.c
parentc64eb759a8e21c7a7c6980ee8f50e9f644c956fe (diff)
clk: rockchip: fix up the frac clk get rate error
support fractional divider with only one level parent clock Change-Id: I6593f908edf4454ef03255080bf9ac1d72c6f64e Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip/clk.c')
-rw-r--r--drivers/clk/rockchip/clk.c15
1 files changed, 10 insertions, 5 deletions
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index c9052c4f8606..15419bbb0ccb 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -166,11 +166,16 @@ static void rockchip_fractional_approximation(struct clk_hw *hw,
if (((rate * 20 > p_rate) && (p_rate % rate != 0)) ||
(fd->max_prate && fd->max_prate < p_rate)) {
p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
- p_parent_rate = clk_hw_get_rate(p_parent);
- *parent_rate = p_parent_rate;
- if (fd->max_prate && p_parent_rate > fd->max_prate) {
- div = DIV_ROUND_UP(p_parent_rate, fd->max_prate);
- *parent_rate = p_parent_rate / div;
+ if (!p_parent) {
+ *parent_rate = p_rate;
+ } else {
+ p_parent_rate = clk_hw_get_rate(p_parent);
+ *parent_rate = p_parent_rate;
+ if (fd->max_prate && p_parent_rate > fd->max_prate) {
+ div = DIV_ROUND_UP(p_parent_rate,
+ fd->max_prate);
+ *parent_rate = p_parent_rate / div;
+ }
}
if (*parent_rate < rate * 20) {